1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
7 /* These structures define the layouts for the TLV items stored in static and
8 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
10 * They contain the same sort of information that was kept in the
11 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
12 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
15 * These are used directly by the MC and should also be usable directly on host
16 * systems which are little-endian and do not do strange things with structure
17 * padding. (Big-endian host systems will require some byte-swapping.)
21 * Please refer to SF-108797-SW for a general overview of the TLV partition
26 * The current tag IDs have a general structure: with the exception of the
27 * special values defined in the document, they are of the form 0xLTTTNNNN,
30 * - L is a location, indicating where this tag is expected to be found:
31 * 0: static configuration
32 * 1: dynamic configuration
33 * 2: firmware internal use
34 * 3: license partition
35 * 4: tsa configuration
37 * - TTT is a type, which is just a unique value. The same type value
38 * might appear in both locations, indicating a relationship between
39 * the items (e.g. static and dynamic VPD below).
41 * - NNNN is an index of some form. Some item types are per-port, some
42 * are per-PF, some are per-partition-type.
46 * As with the previous Siena structures, each structure here is laid out
47 * carefully: values are aligned to their natural boundary, with explicit
48 * padding fields added where necessary. (No, technically this does not
49 * absolutely guarantee portability. But, in practice, compilers are generally
50 * sensible enough not to introduce completely pointless padding, and it works
55 #ifndef CI_MGMT_TLV_LAYOUT_H
56 #define CI_MGMT_TLV_LAYOUT_H
59 /* ----------------------------------------------------------------------------
60 * General structure (defined by SF-108797-SW)
61 * ----------------------------------------------------------------------------
67 * (Note that this is *not* followed by length or value fields: anything after
68 * the tag itself is irrelevant.)
71 #define TLV_TAG_END (0xEEEEEEEE)
74 /* Other special reserved tag values.
77 #define TLV_TAG_SKIP (0x00000000)
78 #define TLV_TAG_INVALID (0xFFFFFFFF)
81 /* TLV partition header.
83 * In a TLV partition, this must be the first item in the sequence, at offset
87 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
89 struct tlv_partition_header {
93 /* 0 indicates the default segment (always located at offset 0), while other values
94 * are for RFID-selectable presets that should immediately follow the default segment.
95 * The default segment may also have preset > 0, which means that it is a preset
96 * selected through an RFID command and copied by FW to the location at offset 0. */
99 uint32_t total_length;
103 /* TLV partition trailer.
105 * In a TLV partition, this must be the last item in the sequence, immediately
106 * preceding the TLV_TAG_END word.
109 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
111 struct tlv_partition_trailer {
119 /* Appendable TLV partition header.
121 * In an appendable TLV partition, this must be the first item in the sequence,
122 * at offset 0. (Note that, unlike the configuration partitions, there is no
123 * trailer before the TLV_TAG_END word.)
126 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
128 struct tlv_appendable_partition_header {
136 /* ----------------------------------------------------------------------------
137 * Configuration items
138 * ----------------------------------------------------------------------------
142 /* NIC global capabilities.
145 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
147 struct tlv_global_capabilities {
154 /* Siena-style per-port MAC address allocation.
156 * There are <count> addresses, starting at <base_address> and incrementing
157 * by adding <stride> to the low-order byte(s).
159 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
160 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
163 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
165 struct tlv_port_mac {
168 uint8_t base_address[6];
177 * This is the portion of VPD which is set at manufacturing time and not
178 * expected to change. It is formatted as a standard PCI VPD block. There are
179 * global and per-pf TLVs for this, the global TLV is new for Medford and is
180 * used in preference to the per-pf TLV.
183 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
185 struct tlv_pf_static_vpd {
191 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
193 struct tlv_global_static_vpd {
202 * This is the portion of VPD which may be changed (e.g. by firmware updates).
203 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
204 * for this, the global TLV is new for Medford and is used in preference to the
208 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
210 struct tlv_pf_dynamic_vpd {
216 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
218 struct tlv_global_dynamic_vpd {
225 /* "DBI" PCI config space changes.
227 * This is a set of edits made to the default PCI config space values before
228 * the device is allowed to enumerate. There are global and per-pf TLVs for
229 * this, the global TLV is new for Medford and is used in preference to the
233 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
240 uint16_t byte_enables;
246 #define TLV_TAG_GLOBAL_DBI (0x00210000)
248 struct tlv_global_dbi {
253 uint16_t byte_enables;
259 /* Partition subtype codes.
261 * A subtype may optionally be stored for each type of partition present in
262 * the NVRAM. For example, this may be used to allow a generic firmware update
263 * utility to select a specific variant of firmware for a specific variant of
266 * The description[] field is an optional string which is returned in the
267 * MC_CMD_NVRAM_METADATA response if present.
270 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
272 struct tlv_partition_subtype {
276 uint8_t description[];
280 /* Partition version codes.
282 * A version may optionally be stored for each type of partition present in
283 * the NVRAM. This provides a standard way of tracking the currently stored
284 * version of each of the various component images.
287 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
289 struct tlv_partition_version {
298 /* Global PCIe configuration */
300 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
302 struct tlv_pcie_config {
305 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
306 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
307 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
308 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
309 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
310 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
313 /* Per-PF configuration. Note that not all these fields are necessarily useful
314 * as the apertures are constrained by the BIU settings (the one case we do
315 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
316 * tidy things up later */
318 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
320 struct tlv_per_pf_pcie_config {
324 uint8_t port_allocation;
325 uint16_t vectors_per_pf;
326 uint16_t vectors_per_vf;
327 uint8_t pf_bar0_aperture;
328 uint8_t pf_bar2_aperture;
329 uint8_t vf_bar0_aperture;
331 uint16_t supp_pagesz;
332 uint16_t msix_vec_base;
336 /* Development ONLY. This is a single TLV tag for all the gubbins
337 * that can be set through the MC command-line other than the PCIe
338 * settings. This is a temporary measure. */
339 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
340 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
342 struct tlv_tmp_gubbins {
345 /* Consumed by dpcpu.c */
346 uint64_t tx0_tags; /* Bitmap */
347 uint64_t tx1_tags; /* Bitmap */
348 uint64_t dl_tags; /* Bitmap */
350 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
351 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
352 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
353 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
354 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
355 /* Consumed by features.c */
356 uint32_t dut_features; /* All 1s -> leave alone */
357 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
358 /* Consumed by clocks_hunt.c */
359 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
360 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
361 int8_t rx_dc_size; /* -1 -> leave alone */
363 int16_t num_q_allocs;
366 /* Global port configuration
368 * This is now deprecated in favour of a platform-provided default
369 * and dynamic config override via tlv_global_port_options.
371 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
373 struct tlv_global_port_config {
376 uint32_t ports_per_core;
377 uint32_t max_port_speed;
383 * This is intended for user-configurable selection of optional firmware
384 * features and variants.
386 * Initially, this consists only of the satellite CPU firmware variant
387 * selection, but this tag could be extended in the future (using the
388 * tag length to determine whether additional fields are present).
391 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
393 struct tlv_firmware_options {
396 uint32_t firmware_variant;
397 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
399 /* These are the values for overriding the driver's choice; the definitions
400 * are taken from MCDI so that they don't get out of step. Include
401 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
402 * you need to use these constants.
404 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
405 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
406 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
407 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
408 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
409 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
410 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
411 #define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK
416 * Intended for boards with A0 silicon where the core voltage may
417 * need tweaking. Most likely set once when the pass voltage is
420 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
422 struct tlv_0v9_settings {
425 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
426 #define TLV_TAG_0V9_REQUIRES_FAN (1)
427 uint16_t target_voltage; /* In millivolts */
428 /* Since the limits are meant to be centred to the target (and must at least
429 * contain it) they need setting as well. */
430 uint16_t warn_low; /* In millivolts */
431 uint16_t warn_high; /* In millivolts */
432 uint16_t panic_low; /* In millivolts */
433 uint16_t panic_high; /* In millivolts */
437 /* Clock configuration */
439 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
440 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
442 struct tlv_clock_config {
445 uint16_t clk_sys; /* MHz */
446 uint16_t clk_dpcpu; /* MHz */
447 uint16_t clk_icore; /* MHz */
448 uint16_t clk_pcs; /* MHz */
451 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
453 struct tlv_clock_config_medford {
456 uint16_t clk_sys; /* MHz */
457 uint16_t clk_mc; /* MHz */
458 uint16_t clk_rmon; /* MHz */
459 uint16_t clk_vswitch; /* MHz */
460 uint16_t clk_dpcpu; /* MHz */
461 uint16_t clk_pcs; /* MHz */
465 /* EF10-style global pool of MAC addresses.
467 * There are <count> addresses, starting at <base_address>, which are
468 * contiguous. Firmware is responsible for allocating addresses from this
469 * pool to ports / PFs as appropriate.
472 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
474 struct tlv_global_mac {
477 uint8_t base_address[6];
483 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
484 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
486 /* The target value for the 0v9 power rail measured on-chip at the
487 * analogue test bus */
488 struct tlv_0v9_atb_target {
495 /* Factory settings for amplitude calibration of the PCIE TX serdes */
496 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000)
497 struct tlv_pcie_tx_amp_config {
500 uint8_t quad_tx_imp2k[4];
501 uint8_t quad_tx_imp50[4];
502 uint8_t lane_amp[16];
506 /* Global PCIe configuration, second revision. This represents the visible PFs
507 * by a bitmap rather than having the number of the highest visible one. As such
508 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
509 * can and it should be used in place of that tag in future (but compatibility with
510 * the old tag will be left in the firmware indefinitely). */
512 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
514 struct tlv_pcie_config_r2 {
517 uint16_t visible_pfs; /**< Bitmap of visible PFs */
518 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
519 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
520 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
523 /* Dynamic port mode.
525 * Allows selecting alternate port configuration for platforms that support it
526 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
527 * number of externally visible ports (and, hence, PF to port mapping), so must
528 * be done at boot time.
530 * Port mode naming convention is
532 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]
534 * Port lane width determines the capabilities (speeds) of the ports, subject
535 * to architecture capabilities (e.g. 25G support) and switch bandwidth
537 * - single lane ports can do 25G/10G/1G
538 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
539 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
541 * This tag supercedes tlv_global_port_config.
544 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
546 struct tlv_global_port_mode {
550 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
552 /* Huntington port modes */
553 #define TLV_PORT_MODE_10G (0)
554 #define TLV_PORT_MODE_40G (1)
555 #define TLV_PORT_MODE_10G_10G (2)
556 #define TLV_PORT_MODE_40G_40G (3)
557 #define TLV_PORT_MODE_10G_10G_10G_10G (4)
558 #define TLV_PORT_MODE_40G_10G_10G (6)
559 #define TLV_PORT_MODE_10G_10G_40G (7)
561 /* Medford (and later) port modes */
562 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
563 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
564 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
565 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */
566 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
567 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
568 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
569 #define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */
570 #define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */
571 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
572 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
573 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
574 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */
575 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */
576 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */
577 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */
578 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
579 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
580 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
582 /* Snapper-only Medford2 port modes.
583 * These modes are eftest only, to allow snapper explicit
584 * selection between multi-channel and LLPCS. In production,
585 * this selection is automatic and outside world should not
588 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
589 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
590 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
591 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
592 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
593 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
594 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
596 /* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
597 #define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)
598 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4)
599 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)
600 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)
602 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
605 /* Type of the v-switch created implicitly by the firmware */
607 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
609 struct tlv_vswitch_type {
612 uint32_t vswitch_type;
613 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
614 #define TLV_VSWITCH_TYPE_NONE (0)
615 #define TLV_VSWITCH_TYPE_VLAN (1)
616 #define TLV_VSWITCH_TYPE_VEB (2)
617 #define TLV_VSWITCH_TYPE_VEPA (3)
618 #define TLV_VSWITCH_TYPE_MUX (4)
619 #define TLV_VSWITCH_TYPE_TEST (5)
622 /* A VLAN tag for the v-port created implicitly by the firmware */
624 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
626 struct tlv_vport_vlan_tag {
630 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
633 /* Offset to be applied to the 0v9 setting, wherever it came from */
635 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
637 struct tlv_0v9_atb_offset {
640 int16_t offset_millivolts;
644 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
645 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
646 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
647 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
648 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
650 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
652 struct tlv_privilege_mask { /* legacy structure - do not use */
655 uint32_t privilege_mask;
658 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
660 struct tlv_privilege_mask_add {
663 uint32_t privilege_mask_add;
666 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
668 struct tlv_privilege_mask_rem {
671 uint32_t privilege_mask_rem;
674 /* Additional privileges given to all PFs.
675 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
677 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
679 struct tlv_privilege_mask_add_all_pfs {
682 uint32_t privilege_mask_add;
685 /* Additional privileges given to a selected PF.
686 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
688 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
690 struct tlv_privilege_mask_add_single_pf {
693 uint32_t privilege_mask_add;
696 /* Turning on/off the PFIOV mode.
697 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
699 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
705 #define TLV_PFIOV_OFF (0) /* Default */
706 #define TLV_PFIOV_ON (1)
709 /* Multicast filter chaining mode selection.
711 * When enabled, multicast packets are delivered to all recipients of all
712 * matching multicast filters, with the exception that IP multicast filters
713 * will steal traffic from MAC multicast filters on a per-function basis.
716 * When disabled, multicast packets will always be delivered only to the
717 * recipients of the highest priority matching multicast filter.
718 * (Legacy behaviour.)
720 * The DEFAULT mode (which is the same as the tag not being present at all)
721 * is equivalent to ENABLED in production builds, and DISABLED in eftest
724 * This option is intended to provide run-time control over this feature
725 * while it is being stabilised and may be withdrawn at some point in the
726 * future; the new behaviour is intended to become the standard behaviour.
729 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
731 struct tlv_mcast_filter_chaining {
735 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
736 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
737 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
740 /* Pacer rate limit per PF */
741 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
743 struct tlv_rate_limit {
749 /* OCSD Enable/Disable
751 * This setting allows OCSD to be disabled. This is a requirement for HP
752 * servers to support PCI passthrough for virtualization.
754 * The DEFAULT mode (which is the same as the tag not being present) is
755 * equivalent to ENABLED.
757 * This option is not used by the MCFW, and is entirely handled by the various
758 * drivers that support OCSD, by reading the setting before they attempt
761 * bit0: OCSD Disabled/Enabled
764 #define TLV_TAG_OCSD (0x101C0000)
770 #define TLV_OCSD_DISABLED 0
771 #define TLV_OCSD_ENABLED 1 /* Default */
774 /* Descriptor cache config.
776 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
777 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
778 * away from the highest numbered port first, so a vi_count of 1024 means 1024
779 * VIs on the first port and 0 on the second (on a Torino).
782 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
784 struct tlv_descriptor_cache_config {
787 uint8_t rx_desc_cache_size;
788 uint8_t tx_desc_cache_size;
791 #define TLV_DESC_CACHE_DEFAULT (0xff)
792 #define TLV_VI_COUNT_DEFAULT (0xffff)
794 /* RX event merging config (read batching).
796 * Sets the global maximum number of events for the merging bins, and the
797 * global timeout configuration for the bins.
800 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
802 struct tlv_rx_event_merging_config {
806 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
809 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
810 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
812 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
813 struct tlv_pcie_link_settings {
816 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
817 uint16_t width; /* Number of lanes */
820 /* TX event merging config.
822 * Sets the global maximum number of events for the merging bins, and the
823 * global timeout configuration for the bins, and the global timeout for
826 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
827 struct tlv_tx_event_merging_config {
831 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
833 uint32_t qempty_timeout_ns; /* Medford only */
835 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
836 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
837 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
839 #define TLV_TAG_LICENSE (0x30800000)
841 typedef struct tlv_license {
847 /* TSA NIC IP address configuration (DEPRECATED)
849 * Sets the TSA NIC IP address statically via configuration tool or dynamically
850 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
852 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
853 * be moved to a private partition during TSA development. It is not used in any
857 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */
859 #define TLV_TSAN_IP_MODE_STATIC (0)
860 #define TLV_TSAN_IP_MODE_DHCP (1)
861 #define TLV_TSAN_IP_MODE_SNOOP (2)
862 typedef struct tlv_tsan_config {
870 uint32_t bind_retry; /* DEPRECATED */
871 uint32_t bind_bkout; /* DEPRECATED */
874 /* TSA Controller IP address configuration (DEPRECATED)
876 * Sets the TSA Controller IP address statically via configuration tool
878 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
879 * be moved to a private partition during TSA development. It is not used in any
883 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */
885 #define TLV_MAX_TSACS (4)
886 typedef struct tlv_tsac_config {
890 uint32_t ip[TLV_MAX_TSACS];
891 uint32_t port[TLV_MAX_TSACS];
894 /* Binding ticket (DEPRECATED)
896 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
897 * and the TSA Controller
899 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
900 * be moved to a private partition during TSA development. It is not used in any
904 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */
906 typedef struct tlv_binding_ticket {
910 } tlv_binding_ticket_t;
912 /* Solarflare private key (DEPRECATED)
914 * Sets the Solareflare private key used for signing during the binding process
916 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
917 * be moved to a private partition during TSA development. It is not used in any
921 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
923 typedef struct tlv_pik_sf {
929 /* CA root certificate (DEPRECATED)
931 * Sets the CA root certificate used for TSA Controller verfication during
932 * TLS connection setup between the TSA NIC and the TSA Controller
934 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
935 * be moved to a private partition during TSA development. It is not used in any
939 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */
941 typedef struct tlv_ca_root_cert {
945 } tlv_ca_root_cert_t;
947 /* Tx vFIFO Low latency configuration
949 * To keep the desired booting behaviour for the switch, it just requires to
950 * know if the low latency mode is enabled.
953 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
954 struct tlv_tx_vfifo_ull_mode {
958 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
963 * Medford2 tag for selecting VI window decode (see values below)
965 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
966 struct tlv_biu_vi_window_mode {
970 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
971 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
972 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
977 * Medford2 tag for configuring the FastPD mode (see values below)
979 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port))
980 struct tlv_fastpd_mode {
984 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */
985 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */
986 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
989 #endif /* CI_MGMT_TLV_LAYOUT_H */