1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
7 /* These structures define the layouts for the TLV items stored in static and
8 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
10 * They contain the same sort of information that was kept in the
11 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
12 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
15 * These are used directly by the MC and should also be usable directly on host
16 * systems which are little-endian and do not do strange things with structure
17 * padding. (Big-endian host systems will require some byte-swapping.)
21 * Please refer to SF-108797-SW for a general overview of the TLV partition
26 * The current tag IDs have a general structure: with the exception of the
27 * special values defined in the document, they are of the form 0xLTTTNNNN,
30 * - L is a location, indicating where this tag is expected to be found:
31 * 0: static configuration
32 * 1: dynamic configuration
33 * 2: firmware internal use
34 * 3: license partition
36 * - TTT is a type, which is just a unique value. The same type value
37 * might appear in both locations, indicating a relationship between
38 * the items (e.g. static and dynamic VPD below).
40 * - NNNN is an index of some form. Some item types are per-port, some
41 * are per-PF, some are per-partition-type.
45 * As with the previous Siena structures, each structure here is laid out
46 * carefully: values are aligned to their natural boundary, with explicit
47 * padding fields added where necessary. (No, technically this does not
48 * absolutely guarantee portability. But, in practice, compilers are generally
49 * sensible enough not to introduce completely pointless padding, and it works
54 #ifndef CI_MGMT_TLV_LAYOUT_H
55 #define CI_MGMT_TLV_LAYOUT_H
58 /* ----------------------------------------------------------------------------
59 * General structure (defined by SF-108797-SW)
60 * ----------------------------------------------------------------------------
66 * (Note that this is *not* followed by length or value fields: anything after
67 * the tag itself is irrelevant.)
70 #define TLV_TAG_END (0xEEEEEEEE)
73 /* Other special reserved tag values.
76 #define TLV_TAG_SKIP (0x00000000)
77 #define TLV_TAG_INVALID (0xFFFFFFFF)
80 /* TLV partition header.
82 * In a TLV partition, this must be the first item in the sequence, at offset
86 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
88 struct tlv_partition_header {
92 /* 0 indicates the default segment (always located at offset 0), while other values
93 * are for RFID-selectable presets that should immediately follow the default segment.
94 * The default segment may also have preset > 0, which means that it is a preset
95 * selected through an RFID command and copied by FW to the location at offset 0. */
98 uint32_t total_length;
102 /* TLV partition trailer.
104 * In a TLV partition, this must be the last item in the sequence, immediately
105 * preceding the TLV_TAG_END word.
108 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
110 struct tlv_partition_trailer {
118 /* Appendable TLV partition header.
120 * In an appendable TLV partition, this must be the first item in the sequence,
121 * at offset 0. (Note that, unlike the configuration partitions, there is no
122 * trailer before the TLV_TAG_END word.)
125 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
127 struct tlv_appendable_partition_header {
135 /* ----------------------------------------------------------------------------
136 * Configuration items
137 * ----------------------------------------------------------------------------
141 /* NIC global capabilities.
144 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
146 struct tlv_global_capabilities {
153 /* Siena-style per-port MAC address allocation.
155 * There are <count> addresses, starting at <base_address> and incrementing
156 * by adding <stride> to the low-order byte(s).
158 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
159 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
162 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
164 struct tlv_port_mac {
167 uint8_t base_address[6];
176 * This is the portion of VPD which is set at manufacturing time and not
177 * expected to change. It is formatted as a standard PCI VPD block. There are
178 * global and per-pf TLVs for this, the global TLV is new for Medford and is
179 * used in preference to the per-pf TLV.
182 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
184 struct tlv_pf_static_vpd {
190 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
192 struct tlv_global_static_vpd {
201 * This is the portion of VPD which may be changed (e.g. by firmware updates).
202 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
203 * for this, the global TLV is new for Medford and is used in preference to the
207 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
209 struct tlv_pf_dynamic_vpd {
215 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
217 struct tlv_global_dynamic_vpd {
224 /* "DBI" PCI config space changes.
226 * This is a set of edits made to the default PCI config space values before
227 * the device is allowed to enumerate. There are global and per-pf TLVs for
228 * this, the global TLV is new for Medford and is used in preference to the
232 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
239 uint16_t byte_enables;
245 #define TLV_TAG_GLOBAL_DBI (0x00210000)
247 struct tlv_global_dbi {
252 uint16_t byte_enables;
258 /* Partition subtype codes.
260 * A subtype may optionally be stored for each type of partition present in
261 * the NVRAM. For example, this may be used to allow a generic firmware update
262 * utility to select a specific variant of firmware for a specific variant of
265 * The description[] field is an optional string which is returned in the
266 * MC_CMD_NVRAM_METADATA response if present.
269 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
271 struct tlv_partition_subtype {
275 uint8_t description[];
279 /* Partition version codes.
281 * A version may optionally be stored for each type of partition present in
282 * the NVRAM. This provides a standard way of tracking the currently stored
283 * version of each of the various component images.
286 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
288 struct tlv_partition_version {
297 /* Global PCIe configuration */
299 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
301 struct tlv_pcie_config {
304 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
305 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
306 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
307 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
308 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
309 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
312 /* Per-PF configuration. Note that not all these fields are necessarily useful
313 * as the apertures are constrained by the BIU settings (the one case we do
314 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
315 * tidy things up later */
317 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
319 struct tlv_per_pf_pcie_config {
323 uint8_t port_allocation;
324 uint16_t vectors_per_pf;
325 uint16_t vectors_per_vf;
326 uint8_t pf_bar0_aperture;
327 uint8_t pf_bar2_aperture;
328 uint8_t vf_bar0_aperture;
330 uint16_t supp_pagesz;
331 uint16_t msix_vec_base;
335 /* Development ONLY. This is a single TLV tag for all the gubbins
336 * that can be set through the MC command-line other than the PCIe
337 * settings. This is a temporary measure. */
338 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
339 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
341 struct tlv_tmp_gubbins {
344 /* Consumed by dpcpu.c */
345 uint64_t tx0_tags; /* Bitmap */
346 uint64_t tx1_tags; /* Bitmap */
347 uint64_t dl_tags; /* Bitmap */
349 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
350 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
351 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
352 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
353 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
354 /* Consumed by features.c */
355 uint32_t dut_features; /* All 1s -> leave alone */
356 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
357 /* Consumed by clocks_hunt.c */
358 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
359 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
360 int8_t rx_dc_size; /* -1 -> leave alone */
362 int16_t num_q_allocs;
365 /* Global port configuration
367 * This is now deprecated in favour of a platform-provided default
368 * and dynamic config override via tlv_global_port_options.
370 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
372 struct tlv_global_port_config {
375 uint32_t ports_per_core;
376 uint32_t max_port_speed;
382 * This is intended for user-configurable selection of optional firmware
383 * features and variants.
385 * Initially, this consists only of the satellite CPU firmware variant
386 * selection, but this tag could be extended in the future (using the
387 * tag length to determine whether additional fields are present).
390 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
392 struct tlv_firmware_options {
395 uint32_t firmware_variant;
396 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
398 /* These are the values for overriding the driver's choice; the definitions
399 * are taken from MCDI so that they don't get out of step. Include
400 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
401 * you need to use these constants.
403 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
404 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
405 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
406 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
407 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
408 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
409 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
414 * Intended for boards with A0 silicon where the core voltage may
415 * need tweaking. Most likely set once when the pass voltage is
418 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
420 struct tlv_0v9_settings {
423 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
424 #define TLV_TAG_0V9_REQUIRES_FAN (1)
425 uint16_t target_voltage; /* In millivolts */
426 /* Since the limits are meant to be centred to the target (and must at least
427 * contain it) they need setting as well. */
428 uint16_t warn_low; /* In millivolts */
429 uint16_t warn_high; /* In millivolts */
430 uint16_t panic_low; /* In millivolts */
431 uint16_t panic_high; /* In millivolts */
435 /* Clock configuration */
437 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
438 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
440 struct tlv_clock_config {
443 uint16_t clk_sys; /* MHz */
444 uint16_t clk_dpcpu; /* MHz */
445 uint16_t clk_icore; /* MHz */
446 uint16_t clk_pcs; /* MHz */
449 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
451 struct tlv_clock_config_medford {
454 uint16_t clk_sys; /* MHz */
455 uint16_t clk_mc; /* MHz */
456 uint16_t clk_rmon; /* MHz */
457 uint16_t clk_vswitch; /* MHz */
458 uint16_t clk_dpcpu; /* MHz */
459 uint16_t clk_pcs; /* MHz */
463 /* EF10-style global pool of MAC addresses.
465 * There are <count> addresses, starting at <base_address>, which are
466 * contiguous. Firmware is responsible for allocating addresses from this
467 * pool to ports / PFs as appropriate.
470 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
472 struct tlv_global_mac {
475 uint8_t base_address[6];
481 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
482 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
484 /* The target value for the 0v9 power rail measured on-chip at the
485 * analogue test bus */
486 struct tlv_0v9_atb_target {
493 /* Factory settings for amplitude calibration of the PCIE TX serdes */
494 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000)
495 struct tlv_pcie_tx_amp_config {
498 uint8_t quad_tx_imp2k[4];
499 uint8_t quad_tx_imp50[4];
500 uint8_t lane_amp[16];
504 /* Global PCIe configuration, second revision. This represents the visible PFs
505 * by a bitmap rather than having the number of the highest visible one. As such
506 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
507 * can and it should be used in place of that tag in future (but compatibility with
508 * the old tag will be left in the firmware indefinitely). */
510 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
512 struct tlv_pcie_config_r2 {
515 uint16_t visible_pfs; /**< Bitmap of visible PFs */
516 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
517 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
518 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
521 /* Dynamic port mode.
523 * Allows selecting alternate port configuration for platforms that support it
524 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
525 * number of externally visible ports (and, hence, PF to port mapping), so must
526 * be done at boot time.
528 * Port mode naming convention is
530 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]
532 * Port lane width determines the capabilities (speeds) of the ports, subject
533 * to architecture capabilities (e.g. 25G support) and switch bandwidth
535 * - single lane ports can do 25G/10G/1G
536 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
537 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
539 * This tag supercedes tlv_global_port_config.
542 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
544 struct tlv_global_port_mode {
548 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
549 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
550 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
551 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
552 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */
553 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
554 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
555 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
556 #define TLV_PORT_MODE_2x1_2x1 (4) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 - WARNING: bug3720: On Newport only, this is actually Quad 10G on mdi0 */
557 #define TLV_PORT_MODE_4x1_NA (5) /* Quad 10G/25G on mdi0 */
558 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
559 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
560 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
561 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */
562 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */
563 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */
564 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */
565 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
566 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
567 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
568 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
569 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
570 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
571 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
572 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
573 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
574 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
576 /* Deprecated aliases */
577 #define TLV_PORT_MODE_10G TLV_PORT_MODE_1x1_NA
578 #define TLV_PORT_MODE_40G TLV_PORT_MODE_1x4_NA
579 #define TLV_PORT_MODE_10G_10G TLV_PORT_MODE_1x1_1x1
580 #define TLV_PORT_MODE_40G_40G TLV_PORT_MODE_1x4_1x4
581 #define TLV_PORT_MODE_10G_10G_10G_10G TLV_PORT_MODE_2x1_2x1
582 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 TLV_PORT_MODE_2x1_2x1 /* bug63720: Do not use */
583 #define TLV_PORT_MODE_10G_10G_10G_10G_Q TLV_PORT_MODE_4x1_NA
584 #define TLV_PORT_MODE_40G_10G_10G TLV_PORT_MODE_1x4_2x1
585 #define TLV_PORT_MODE_10G_10G_40G TLV_PORT_MODE_2x1_1x4
586 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 TLV_PORT_MODE_NA_4x1
587 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 TLV_PORT_MODE_BUG63720_DO_NOT_USE /* bug63720: Do not use */
588 #define TLV_PORT_MODE_25G TLV_PORT_MODE_1x1_NA /* Single 25G on mdi0 */
589 #define TLV_PORT_MODE_100G_Q1 TLV_PORT_MODE_1x4_NA /* Single 100G on mdi0 */
590 #define TLV_PORT_MODE_100G_Q2 TLV_PORT_MODE_NA_1x4 /* Single 100G on mdi1 */
591 #define TLV_PORT_MODE_50G_Q1 TLV_PORT_MODE_1x2_NA /* Single 50G on mdi0 */
592 #define TLV_PORT_MODE_50G_Q2 TLV_PORT_MODE_NA_1x2 /* Single 50G on mdi1 */
593 #define TLV_PORT_MODE_25G_25G TLV_PORT_MODE_1x1_1x1 /* Single 25G on mdi0, single 25G on mdi1 */
594 #define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2 TLV_PORT_MODE_2x1_2x1 /* Dual 25G on mdi0, dual 25G on mdi1 */
595 #define TLV_PORT_MODE_25G_25G_25G_25G_Q1 TLV_PORT_MODE_4x1_NA /* Quad 25G on mdi0 */
596 #define TLV_PORT_MODE_25G_25G_25G_25G_Q2 TLV_PORT_MODE_NA_4x1 /* Quad 25G on mdi1 */
597 #define TLV_PORT_MODE_40G_25G_25G TLV_PORT_MODE_1x4_2x1 /* Single 40G on mdi0, dual 25G on mdi1 */
598 #define TLV_PORT_MODE_25G_25G_40G TLV_PORT_MODE_2x1_1x4 /* Dual 25G on mdi0, single 40G on mdi1 */
599 #define TLV_PORT_MODE_50G_50G_Q1_Q2 TLV_PORT_MODE_1x2_1x2 /* Single 50G on mdi0, single 50G on mdi1 */
600 #define TLV_PORT_MODE_50G_50G_Q1 TLV_PORT_MODE_2x2_NA /* Dual 50G on mdi0 */
601 #define TLV_PORT_MODE_50G_50G_Q2 TLV_PORT_MODE_NA_2x2 /* Dual 50G on mdi1 */
602 #define TLV_PORT_MODE_40G_50G TLV_PORT_MODE_1x4_1x2 /* Single 40G on mdi0, single 50G on mdi1 */
603 #define TLV_PORT_MODE_50G_40G TLV_PORT_MODE_1x2_1x4 /* Single 50G on mdi0, single 40G on mdi1 */
604 #define TLV_PORT_MODE_50G_25G_25G TLV_PORT_MODE_1x2_2x1 /* Single 50G on mdi0, dual 25G on mdi1 */
605 #define TLV_PORT_MODE_25G_25G_50G TLV_PORT_MODE_2x1_1x2 /* Dual 25G on mdi0, single 50G on mdi1 */
606 #define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2_LL TLV_PORT_MODE_2x1_2x1_LL /* Dual 25G on mdi0, dual 25G on mdi1, low-latency PCS */
607 #define TLV_PORT_MODE_25G_25G_25G_25G_Q1_LL TLV_PORT_MODE_4x1_NA_LL /* Quad 25G on mdi0, low-latency PCS */
608 #define TLV_PORT_MODE_25G_25G_25G_25G_Q2_LL TLV_PORT_MODE_NA_4x1_LL /* Quad 25G on mdi1, low-latency PCS */
609 #define TLV_PORT_MODE_25G_LL TLV_PORT_MODE_1x1_NA_LL /* Single 10G/25G on mdi0, low-latency PCS */
610 #define TLV_PORT_MODE_25G_25G_LL TLV_PORT_MODE_1x1_1x1_LL /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
613 /* Type of the v-switch created implicitly by the firmware */
615 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
617 struct tlv_vswitch_type {
620 uint32_t vswitch_type;
621 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
622 #define TLV_VSWITCH_TYPE_NONE (0)
623 #define TLV_VSWITCH_TYPE_VLAN (1)
624 #define TLV_VSWITCH_TYPE_VEB (2)
625 #define TLV_VSWITCH_TYPE_VEPA (3)
626 #define TLV_VSWITCH_TYPE_MUX (4)
627 #define TLV_VSWITCH_TYPE_TEST (5)
630 /* A VLAN tag for the v-port created implicitly by the firmware */
632 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
634 struct tlv_vport_vlan_tag {
638 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
641 /* Offset to be applied to the 0v9 setting, wherever it came from */
643 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
645 struct tlv_0v9_atb_offset {
648 int16_t offset_millivolts;
652 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
653 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
654 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
655 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
656 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
658 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
660 struct tlv_privilege_mask { /* legacy structure - do not use */
663 uint32_t privilege_mask;
666 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
668 struct tlv_privilege_mask_add {
671 uint32_t privilege_mask_add;
674 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
676 struct tlv_privilege_mask_rem {
679 uint32_t privilege_mask_rem;
682 /* Additional privileges given to all PFs.
683 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
685 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
687 struct tlv_privilege_mask_add_all_pfs {
690 uint32_t privilege_mask_add;
693 /* Additional privileges given to a selected PF.
694 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
696 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
698 struct tlv_privilege_mask_add_single_pf {
701 uint32_t privilege_mask_add;
704 /* Turning on/off the PFIOV mode.
705 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
707 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
713 #define TLV_PFIOV_OFF (0) /* Default */
714 #define TLV_PFIOV_ON (1)
717 /* Multicast filter chaining mode selection.
719 * When enabled, multicast packets are delivered to all recipients of all
720 * matching multicast filters, with the exception that IP multicast filters
721 * will steal traffic from MAC multicast filters on a per-function basis.
724 * When disabled, multicast packets will always be delivered only to the
725 * recipients of the highest priority matching multicast filter.
726 * (Legacy behaviour.)
728 * The DEFAULT mode (which is the same as the tag not being present at all)
729 * is equivalent to ENABLED in production builds, and DISABLED in eftest
732 * This option is intended to provide run-time control over this feature
733 * while it is being stabilised and may be withdrawn at some point in the
734 * future; the new behaviour is intended to become the standard behaviour.
737 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
739 struct tlv_mcast_filter_chaining {
743 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
744 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
745 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
748 /* Pacer rate limit per PF */
749 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
751 struct tlv_rate_limit {
757 /* OCSD Enable/Disable
759 * This setting allows OCSD to be disabled. This is a requirement for HP
760 * servers to support PCI passthrough for virtualization.
762 * The DEFAULT mode (which is the same as the tag not being present) is
763 * equivalent to ENABLED.
765 * This option is not used by the MCFW, and is entirely handled by the various
766 * drivers that support OCSD, by reading the setting before they attempt
769 * bit0: OCSD Disabled/Enabled
772 #define TLV_TAG_OCSD (0x101C0000)
778 #define TLV_OCSD_DISABLED 0
779 #define TLV_OCSD_ENABLED 1 /* Default */
782 /* Descriptor cache config.
784 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
785 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
786 * away from the highest numbered port first, so a vi_count of 1024 means 1024
787 * VIs on the first port and 0 on the second (on a Torino).
790 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
792 struct tlv_descriptor_cache_config {
795 uint8_t rx_desc_cache_size;
796 uint8_t tx_desc_cache_size;
799 #define TLV_DESC_CACHE_DEFAULT (0xff)
800 #define TLV_VI_COUNT_DEFAULT (0xffff)
802 /* RX event merging config (read batching).
804 * Sets the global maximum number of events for the merging bins, and the
805 * global timeout configuration for the bins.
808 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
810 struct tlv_rx_event_merging_config {
814 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
817 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
818 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
820 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
821 struct tlv_pcie_link_settings {
824 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
825 uint16_t width; /* Number of lanes */
828 /* TX event merging config.
830 * Sets the global maximum number of events for the merging bins, and the
831 * global timeout configuration for the bins, and the global timeout for
834 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
835 struct tlv_tx_event_merging_config {
839 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
841 uint32_t qempty_timeout_ns; /* Medford only */
843 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
844 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
845 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
847 #define TLV_TAG_LICENSE (0x30800000)
849 typedef struct tlv_license {
855 /* TSA NIC IP address configuration
857 * Sets the TSA NIC IP address statically via configuration tool or dynamically
858 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
860 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
861 * be moved to a private partition during TSA development. It is not used in any
865 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000)
867 #define TLV_TSAN_IP_MODE_STATIC (0)
868 #define TLV_TSAN_IP_MODE_DHCP (1)
869 #define TLV_TSAN_IP_MODE_SNOOP (2)
870 typedef struct tlv_tsan_config {
878 uint32_t bind_retry; /* DEPRECATED */
879 uint32_t bind_bkout; /* DEPRECATED */
882 /* TSA Controller IP address configuration
884 * Sets the TSA Controller IP address statically via configuration tool
886 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
887 * be moved to a private partition during TSA development. It is not used in any
891 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000)
893 #define TLV_MAX_TSACS (4)
894 typedef struct tlv_tsac_config {
898 uint32_t ip[TLV_MAX_TSACS];
899 uint32_t port[TLV_MAX_TSACS];
904 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
905 * and the TSA Controller
907 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
908 * be moved to a private partition during TSA development. It is not used in any
912 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000)
914 typedef struct tlv_binding_ticket {
918 } tlv_binding_ticket_t;
920 /* Solarflare private key (DEPRECATED)
922 * Sets the Solareflare private key used for signing during the binding process
924 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
925 * be moved to a private partition during TSA development. It is not used in any
929 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
931 typedef struct tlv_pik_sf {
937 /* CA root certificate
939 * Sets the CA root certificate used for TSA Controller verfication during
940 * TLS connection setup between the TSA NIC and the TSA Controller
942 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
943 * be moved to a private partition during TSA development. It is not used in any
947 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000)
949 typedef struct tlv_ca_root_cert {
953 } tlv_ca_root_cert_t;
955 /* Tx vFIFO Low latency configuration
957 * To keep the desired booting behaviour for the switch, it just requires to
958 * know if the low latency mode is enabled.
961 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
962 struct tlv_tx_vfifo_ull_mode {
966 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
971 * Medford2 tag for selecting VI window decode (see values below)
973 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
974 struct tlv_biu_vi_window_mode {
978 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
979 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
980 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
985 * Medford2 tag for configuring the FastPD mode (see values below)
987 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port))
988 struct tlv_fastpd_mode {
992 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */
993 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */
994 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
997 #endif /* CI_MGMT_TLV_LAYOUT_H */