1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
7 /* These structures define the layouts for the TLV items stored in static and
8 * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
10 * They contain the same sort of information that was kept in the
11 * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
12 * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
15 * These are used directly by the MC and should also be usable directly on host
16 * systems which are little-endian and do not do strange things with structure
17 * padding. (Big-endian host systems will require some byte-swapping.)
21 * Please refer to SF-108797-SW for a general overview of the TLV partition
26 * The current tag IDs have a general structure: with the exception of the
27 * special values defined in the document, they are of the form 0xLTTTNNNN,
30 * - L is a location, indicating where this tag is expected to be found:
31 * 0: static configuration
32 * 1: dynamic configuration
33 * 2: firmware internal use
34 * 3: license partition
35 * 4: tsa configuration
37 * - TTT is a type, which is just a unique value. The same type value
38 * might appear in both locations, indicating a relationship between
39 * the items (e.g. static and dynamic VPD below).
41 * - NNNN is an index of some form. Some item types are per-port, some
42 * are per-PF, some are per-partition-type.
46 * As with the previous Siena structures, each structure here is laid out
47 * carefully: values are aligned to their natural boundary, with explicit
48 * padding fields added where necessary. (No, technically this does not
49 * absolutely guarantee portability. But, in practice, compilers are generally
50 * sensible enough not to introduce completely pointless padding, and it works
55 #ifndef CI_MGMT_TLV_LAYOUT_H
56 #define CI_MGMT_TLV_LAYOUT_H
59 /* ----------------------------------------------------------------------------
60 * General structure (defined by SF-108797-SW)
61 * ----------------------------------------------------------------------------
67 * (Note that this is *not* followed by length or value fields: anything after
68 * the tag itself is irrelevant.)
71 #define TLV_TAG_END (0xEEEEEEEE)
74 /* Other special reserved tag values.
77 #define TLV_TAG_SKIP (0x00000000)
78 #define TLV_TAG_INVALID (0xFFFFFFFF)
81 /* TLV partition header.
83 * In a TLV partition, this must be the first item in the sequence, at offset
87 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
89 struct tlv_partition_header {
93 /* 0 indicates the default segment (always located at offset 0), while other values
94 * are for RFID-selectable presets that should immediately follow the default segment.
95 * The default segment may also have preset > 0, which means that it is a preset
96 * selected through an RFID command and copied by FW to the location at offset 0. */
99 uint32_t total_length;
103 /* TLV partition trailer.
105 * In a TLV partition, this must be the last item in the sequence, immediately
106 * preceding the TLV_TAG_END word.
109 #define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
111 struct tlv_partition_trailer {
119 /* Appendable TLV partition header.
121 * In an appendable TLV partition, this must be the first item in the sequence,
122 * at offset 0. (Note that, unlike the configuration partitions, there is no
123 * trailer before the TLV_TAG_END word.)
126 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
128 struct tlv_appendable_partition_header {
136 /* ----------------------------------------------------------------------------
137 * Configuration items
138 * ----------------------------------------------------------------------------
142 /* NIC global capabilities.
145 #define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
147 struct tlv_global_capabilities {
154 /* Siena-style per-port MAC address allocation.
156 * There are <count> addresses, starting at <base_address> and incrementing
157 * by adding <stride> to the low-order byte(s).
159 * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
160 * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
163 #define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
165 struct tlv_port_mac {
168 uint8_t base_address[6];
177 * This is the portion of VPD which is set at manufacturing time and not
178 * expected to change. It is formatted as a standard PCI VPD block. There are
179 * global and per-pf TLVs for this, the global TLV is new for Medford and is
180 * used in preference to the per-pf TLV.
183 #define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
185 struct tlv_pf_static_vpd {
191 #define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
193 struct tlv_global_static_vpd {
202 * This is the portion of VPD which may be changed (e.g. by firmware updates).
203 * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
204 * for this, the global TLV is new for Medford and is used in preference to the
208 #define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
210 struct tlv_pf_dynamic_vpd {
216 #define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
218 struct tlv_global_dynamic_vpd {
225 /* "DBI" PCI config space changes.
227 * This is a set of edits made to the default PCI config space values before
228 * the device is allowed to enumerate. There are global and per-pf TLVs for
229 * this, the global TLV is new for Medford and is used in preference to the
233 #define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
240 uint16_t byte_enables;
246 #define TLV_TAG_GLOBAL_DBI (0x00210000)
248 struct tlv_global_dbi {
253 uint16_t byte_enables;
259 /* Partition subtype codes.
261 * A subtype may optionally be stored for each type of partition present in
262 * the NVRAM. For example, this may be used to allow a generic firmware update
263 * utility to select a specific variant of firmware for a specific variant of
266 * The description[] field is an optional string which is returned in the
267 * MC_CMD_NVRAM_METADATA response if present.
270 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
272 struct tlv_partition_subtype {
276 uint8_t description[];
280 /* Partition version codes.
282 * A version may optionally be stored for each type of partition present in
283 * the NVRAM. This provides a standard way of tracking the currently stored
284 * version of each of the various component images.
287 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
289 struct tlv_partition_version {
298 /* Global PCIe configuration */
300 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
302 struct tlv_pcie_config {
305 int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
306 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
307 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
308 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
309 #define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
310 #define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
313 /* Per-PF configuration. Note that not all these fields are necessarily useful
314 * as the apertures are constrained by the BIU settings (the one case we do
315 * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
316 * tidy things up later */
318 #define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
320 struct tlv_per_pf_pcie_config {
324 uint8_t port_allocation;
325 uint16_t vectors_per_pf;
326 uint16_t vectors_per_vf;
327 uint8_t pf_bar0_aperture;
328 uint8_t pf_bar2_aperture;
329 uint8_t vf_bar0_aperture;
331 uint16_t supp_pagesz;
332 uint16_t msix_vec_base;
336 /* Development ONLY. This is a single TLV tag for all the gubbins
337 * that can be set through the MC command-line other than the PCIe
338 * settings. This is a temporary measure. */
339 #define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
340 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
342 struct tlv_tmp_gubbins {
345 /* Consumed by dpcpu.c */
346 uint64_t tx0_tags; /* Bitmap */
347 uint64_t tx1_tags; /* Bitmap */
348 uint64_t dl_tags; /* Bitmap */
350 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
351 #define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
352 #define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
353 #define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
354 #define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
355 /* Consumed by features.c */
356 uint32_t dut_features; /* All 1s -> leave alone */
357 int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
358 /* Consumed by clocks_hunt.c */
359 int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
360 /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
361 int8_t rx_dc_size; /* -1 -> leave alone */
363 int16_t num_q_allocs;
366 /* Global port configuration
368 * This is now deprecated in favour of a platform-provided default
369 * and dynamic config override via tlv_global_port_options.
371 #define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
373 struct tlv_global_port_config {
376 uint32_t ports_per_core;
377 uint32_t max_port_speed;
383 * This is intended for user-configurable selection of optional firmware
384 * features and variants.
386 * Initially, this consists only of the satellite CPU firmware variant
387 * selection, but this tag could be extended in the future (using the
388 * tag length to determine whether additional fields are present).
391 #define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
393 struct tlv_firmware_options {
396 uint32_t firmware_variant;
397 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
399 /* These are the values for overriding the driver's choice; the definitions
400 * are taken from MCDI so that they don't get out of step. Include
401 * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
402 * you need to use these constants.
404 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
405 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
406 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
407 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
408 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
409 MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
410 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
415 * Intended for boards with A0 silicon where the core voltage may
416 * need tweaking. Most likely set once when the pass voltage is
419 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
421 struct tlv_0v9_settings {
424 uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
425 #define TLV_TAG_0V9_REQUIRES_FAN (1)
426 uint16_t target_voltage; /* In millivolts */
427 /* Since the limits are meant to be centred to the target (and must at least
428 * contain it) they need setting as well. */
429 uint16_t warn_low; /* In millivolts */
430 uint16_t warn_high; /* In millivolts */
431 uint16_t panic_low; /* In millivolts */
432 uint16_t panic_high; /* In millivolts */
436 /* Clock configuration */
438 #define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
439 #define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
441 struct tlv_clock_config {
444 uint16_t clk_sys; /* MHz */
445 uint16_t clk_dpcpu; /* MHz */
446 uint16_t clk_icore; /* MHz */
447 uint16_t clk_pcs; /* MHz */
450 #define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
452 struct tlv_clock_config_medford {
455 uint16_t clk_sys; /* MHz */
456 uint16_t clk_mc; /* MHz */
457 uint16_t clk_rmon; /* MHz */
458 uint16_t clk_vswitch; /* MHz */
459 uint16_t clk_dpcpu; /* MHz */
460 uint16_t clk_pcs; /* MHz */
464 /* EF10-style global pool of MAC addresses.
466 * There are <count> addresses, starting at <base_address>, which are
467 * contiguous. Firmware is responsible for allocating addresses from this
468 * pool to ports / PFs as appropriate.
471 #define TLV_TAG_GLOBAL_MAC (0x000e0000)
473 struct tlv_global_mac {
476 uint8_t base_address[6];
482 #define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
483 #define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
485 /* The target value for the 0v9 power rail measured on-chip at the
486 * analogue test bus */
487 struct tlv_0v9_atb_target {
494 /* Factory settings for amplitude calibration of the PCIE TX serdes */
495 #define TLV_TAG_TX_PCIE_AMP_CONFIG (0x00220000)
496 struct tlv_pcie_tx_amp_config {
499 uint8_t quad_tx_imp2k[4];
500 uint8_t quad_tx_imp50[4];
501 uint8_t lane_amp[16];
505 /* Global PCIe configuration, second revision. This represents the visible PFs
506 * by a bitmap rather than having the number of the highest visible one. As such
507 * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
508 * can and it should be used in place of that tag in future (but compatibility with
509 * the old tag will be left in the firmware indefinitely). */
511 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
513 struct tlv_pcie_config_r2 {
516 uint16_t visible_pfs; /**< Bitmap of visible PFs */
517 uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
518 uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
519 uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
522 /* Dynamic port mode.
524 * Allows selecting alternate port configuration for platforms that support it
525 * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
526 * number of externally visible ports (and, hence, PF to port mapping), so must
527 * be done at boot time.
529 * Port mode naming convention is
531 * [nports_on_cage0]x[port_lane_width]_[nports_on_cage1]x[port_lane_width]
533 * Port lane width determines the capabilities (speeds) of the ports, subject
534 * to architecture capabilities (e.g. 25G support) and switch bandwidth
536 * - single lane ports can do 25G/10G/1G
537 * - dual lane ports can do 50G/25G/10G/1G (with fallback to 1 lane)
538 * - quad lane ports can do 100G/40G/50G/25G/10G/1G (with fallback to 2 or 1 lanes)
540 * This tag supercedes tlv_global_port_config.
543 #define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
545 struct tlv_global_port_mode {
549 #define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
550 #define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
551 #define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
552 #define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
553 #define TLV_PORT_MODE_1x2_NA (10) /* Single 50G on mdi0 */
554 #define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
555 #define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
556 #define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
557 #define TLV_PORT_MODE_2x1_2x1 (4) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 - WARNING: bug3720: On Newport only, this is actually Quad 10G on mdi0 */
558 #define TLV_PORT_MODE_4x1_NA (5) /* Quad 10G/25G on mdi0 */
559 #define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
560 #define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
561 #define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
562 #define TLV_PORT_MODE_1x2_1x2 (12) /* Single 50G on mdi0, single 50G on mdi1 */
563 #define TLV_PORT_MODE_2x2_NA (13) /* Dual 50G on mdi0 */
564 #define TLV_PORT_MODE_NA_2x2 (14) /* Dual 50G on mdi1 */
565 #define TLV_PORT_MODE_1x4_1x2 (15) /* Single 40G on mdi0, single 50G on mdi1 */
566 #define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
567 #define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
568 #define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
569 /* Below modes are eftest only, to allow snapper explicit selection between multi-channel and LLPCS. In production, this selection is automatic and outside world should not care about LLPCS */
570 #define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
571 #define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
572 #define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
573 #define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on mdi0, low-latency PCS */
574 #define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
575 #define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
576 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
578 /* Deprecated aliases */
579 #define TLV_PORT_MODE_10G TLV_PORT_MODE_1x1_NA
580 #define TLV_PORT_MODE_40G TLV_PORT_MODE_1x4_NA
581 #define TLV_PORT_MODE_10G_10G TLV_PORT_MODE_1x1_1x1
582 #define TLV_PORT_MODE_40G_40G TLV_PORT_MODE_1x4_1x4
583 #define TLV_PORT_MODE_10G_10G_10G_10G TLV_PORT_MODE_2x1_2x1
584 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1 TLV_PORT_MODE_2x1_2x1 /* bug63720: Do not use */
585 #define TLV_PORT_MODE_10G_10G_10G_10G_Q TLV_PORT_MODE_4x1_NA
586 #define TLV_PORT_MODE_40G_10G_10G TLV_PORT_MODE_1x4_2x1
587 #define TLV_PORT_MODE_10G_10G_40G TLV_PORT_MODE_2x1_1x4
588 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2 TLV_PORT_MODE_NA_4x1
589 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 TLV_PORT_MODE_BUG63720_DO_NOT_USE /* bug63720: Do not use */
590 #define TLV_PORT_MODE_25G TLV_PORT_MODE_1x1_NA /* Single 25G on mdi0 */
591 #define TLV_PORT_MODE_100G_Q1 TLV_PORT_MODE_1x4_NA /* Single 100G on mdi0 */
592 #define TLV_PORT_MODE_100G_Q2 TLV_PORT_MODE_NA_1x4 /* Single 100G on mdi1 */
593 #define TLV_PORT_MODE_50G_Q1 TLV_PORT_MODE_1x2_NA /* Single 50G on mdi0 */
594 #define TLV_PORT_MODE_50G_Q2 TLV_PORT_MODE_NA_1x2 /* Single 50G on mdi1 */
595 #define TLV_PORT_MODE_25G_25G TLV_PORT_MODE_1x1_1x1 /* Single 25G on mdi0, single 25G on mdi1 */
596 #define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2 TLV_PORT_MODE_2x1_2x1 /* Dual 25G on mdi0, dual 25G on mdi1 */
597 #define TLV_PORT_MODE_25G_25G_25G_25G_Q1 TLV_PORT_MODE_4x1_NA /* Quad 25G on mdi0 */
598 #define TLV_PORT_MODE_25G_25G_25G_25G_Q2 TLV_PORT_MODE_NA_4x1 /* Quad 25G on mdi1 */
599 #define TLV_PORT_MODE_40G_25G_25G TLV_PORT_MODE_1x4_2x1 /* Single 40G on mdi0, dual 25G on mdi1 */
600 #define TLV_PORT_MODE_25G_25G_40G TLV_PORT_MODE_2x1_1x4 /* Dual 25G on mdi0, single 40G on mdi1 */
601 #define TLV_PORT_MODE_50G_50G_Q1_Q2 TLV_PORT_MODE_1x2_1x2 /* Single 50G on mdi0, single 50G on mdi1 */
602 #define TLV_PORT_MODE_50G_50G_Q1 TLV_PORT_MODE_2x2_NA /* Dual 50G on mdi0 */
603 #define TLV_PORT_MODE_50G_50G_Q2 TLV_PORT_MODE_NA_2x2 /* Dual 50G on mdi1 */
604 #define TLV_PORT_MODE_40G_50G TLV_PORT_MODE_1x4_1x2 /* Single 40G on mdi0, single 50G on mdi1 */
605 #define TLV_PORT_MODE_50G_40G TLV_PORT_MODE_1x2_1x4 /* Single 50G on mdi0, single 40G on mdi1 */
606 #define TLV_PORT_MODE_50G_25G_25G TLV_PORT_MODE_1x2_2x1 /* Single 50G on mdi0, dual 25G on mdi1 */
607 #define TLV_PORT_MODE_25G_25G_50G TLV_PORT_MODE_2x1_1x2 /* Dual 25G on mdi0, single 50G on mdi1 */
608 /* eftest only, see comments for _LL modes above */
609 #define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2_LL TLV_PORT_MODE_2x1_2x1_LL /* Dual 25G on mdi0, dual 25G on mdi1, low-latency PCS */
610 #define TLV_PORT_MODE_25G_25G_25G_25G_Q1_LL TLV_PORT_MODE_4x1_NA_LL /* Quad 25G on mdi0, low-latency PCS */
611 #define TLV_PORT_MODE_25G_25G_25G_25G_Q2_LL TLV_PORT_MODE_NA_4x1_LL /* Quad 25G on mdi1, low-latency PCS */
612 #define TLV_PORT_MODE_25G_LL TLV_PORT_MODE_1x1_NA_LL /* Single 10G/25G on mdi0, low-latency PCS */
613 #define TLV_PORT_MODE_25G_25G_LL TLV_PORT_MODE_1x1_1x1_LL /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
616 /* Type of the v-switch created implicitly by the firmware */
618 #define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
620 struct tlv_vswitch_type {
623 uint32_t vswitch_type;
624 #define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
625 #define TLV_VSWITCH_TYPE_NONE (0)
626 #define TLV_VSWITCH_TYPE_VLAN (1)
627 #define TLV_VSWITCH_TYPE_VEB (2)
628 #define TLV_VSWITCH_TYPE_VEPA (3)
629 #define TLV_VSWITCH_TYPE_MUX (4)
630 #define TLV_VSWITCH_TYPE_TEST (5)
633 /* A VLAN tag for the v-port created implicitly by the firmware */
635 #define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
637 struct tlv_vport_vlan_tag {
641 #define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
644 /* Offset to be applied to the 0v9 setting, wherever it came from */
646 #define TLV_TAG_ATB_0V9_OFFSET (0x10140000)
648 struct tlv_0v9_atb_offset {
651 int16_t offset_millivolts;
655 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
656 * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
657 * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
658 * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
659 * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
661 #define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
663 struct tlv_privilege_mask { /* legacy structure - do not use */
666 uint32_t privilege_mask;
669 #define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
671 struct tlv_privilege_mask_add {
674 uint32_t privilege_mask_add;
677 #define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
679 struct tlv_privilege_mask_rem {
682 uint32_t privilege_mask_rem;
685 /* Additional privileges given to all PFs.
686 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
688 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
690 struct tlv_privilege_mask_add_all_pfs {
693 uint32_t privilege_mask_add;
696 /* Additional privileges given to a selected PF.
697 * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
699 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
701 struct tlv_privilege_mask_add_single_pf {
704 uint32_t privilege_mask_add;
707 /* Turning on/off the PFIOV mode.
708 * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
710 #define TLV_TAG_PFIOV(port) (0x10170000 + (port))
716 #define TLV_PFIOV_OFF (0) /* Default */
717 #define TLV_PFIOV_ON (1)
720 /* Multicast filter chaining mode selection.
722 * When enabled, multicast packets are delivered to all recipients of all
723 * matching multicast filters, with the exception that IP multicast filters
724 * will steal traffic from MAC multicast filters on a per-function basis.
727 * When disabled, multicast packets will always be delivered only to the
728 * recipients of the highest priority matching multicast filter.
729 * (Legacy behaviour.)
731 * The DEFAULT mode (which is the same as the tag not being present at all)
732 * is equivalent to ENABLED in production builds, and DISABLED in eftest
735 * This option is intended to provide run-time control over this feature
736 * while it is being stabilised and may be withdrawn at some point in the
737 * future; the new behaviour is intended to become the standard behaviour.
740 #define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
742 struct tlv_mcast_filter_chaining {
746 #define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
747 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
748 #define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
751 /* Pacer rate limit per PF */
752 #define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
754 struct tlv_rate_limit {
760 /* OCSD Enable/Disable
762 * This setting allows OCSD to be disabled. This is a requirement for HP
763 * servers to support PCI passthrough for virtualization.
765 * The DEFAULT mode (which is the same as the tag not being present) is
766 * equivalent to ENABLED.
768 * This option is not used by the MCFW, and is entirely handled by the various
769 * drivers that support OCSD, by reading the setting before they attempt
772 * bit0: OCSD Disabled/Enabled
775 #define TLV_TAG_OCSD (0x101C0000)
781 #define TLV_OCSD_DISABLED 0
782 #define TLV_OCSD_ENABLED 1 /* Default */
785 /* Descriptor cache config.
787 * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
788 * sets the total number of VIs. When the number of VIs is reduced VIs are taken
789 * away from the highest numbered port first, so a vi_count of 1024 means 1024
790 * VIs on the first port and 0 on the second (on a Torino).
793 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
795 struct tlv_descriptor_cache_config {
798 uint8_t rx_desc_cache_size;
799 uint8_t tx_desc_cache_size;
802 #define TLV_DESC_CACHE_DEFAULT (0xff)
803 #define TLV_VI_COUNT_DEFAULT (0xffff)
805 /* RX event merging config (read batching).
807 * Sets the global maximum number of events for the merging bins, and the
808 * global timeout configuration for the bins.
811 #define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
813 struct tlv_rx_event_merging_config {
817 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
820 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
821 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
823 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
824 struct tlv_pcie_link_settings {
827 uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
828 uint16_t width; /* Number of lanes */
831 /* TX event merging config.
833 * Sets the global maximum number of events for the merging bins, and the
834 * global timeout configuration for the bins, and the global timeout for
837 #define TLV_TAG_TX_EVENT_MERGING_CONFIG (0x10210000)
838 struct tlv_tx_event_merging_config {
842 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
844 uint32_t qempty_timeout_ns; /* Medford only */
846 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
847 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
848 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
850 #define TLV_TAG_LICENSE (0x30800000)
852 typedef struct tlv_license {
858 /* TSA NIC IP address configuration (DEPRECATED)
860 * Sets the TSA NIC IP address statically via configuration tool or dynamically
861 * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
863 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
864 * be moved to a private partition during TSA development. It is not used in any
868 #define TLV_TAG_TMP_TSAN_CONFIG (0x10220000) /* DEPRECATED */
870 #define TLV_TSAN_IP_MODE_STATIC (0)
871 #define TLV_TSAN_IP_MODE_DHCP (1)
872 #define TLV_TSAN_IP_MODE_SNOOP (2)
873 typedef struct tlv_tsan_config {
881 uint32_t bind_retry; /* DEPRECATED */
882 uint32_t bind_bkout; /* DEPRECATED */
885 /* TSA Controller IP address configuration (DEPRECATED)
887 * Sets the TSA Controller IP address statically via configuration tool
889 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
890 * be moved to a private partition during TSA development. It is not used in any
894 #define TLV_TAG_TMP_TSAC_CONFIG (0x10230000) /* DEPRECATED */
896 #define TLV_MAX_TSACS (4)
897 typedef struct tlv_tsac_config {
901 uint32_t ip[TLV_MAX_TSACS];
902 uint32_t port[TLV_MAX_TSACS];
905 /* Binding ticket (DEPRECATED)
907 * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
908 * and the TSA Controller
910 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
911 * be moved to a private partition during TSA development. It is not used in any
915 #define TLV_TAG_TMP_BINDING_TICKET (0x10240000) /* DEPRECATED */
917 typedef struct tlv_binding_ticket {
921 } tlv_binding_ticket_t;
923 /* Solarflare private key (DEPRECATED)
925 * Sets the Solareflare private key used for signing during the binding process
927 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
928 * be moved to a private partition during TSA development. It is not used in any
932 #define TLV_TAG_TMP_PIK_SF (0x10250000) /* DEPRECATED */
934 typedef struct tlv_pik_sf {
940 /* CA root certificate (DEPRECATED)
942 * Sets the CA root certificate used for TSA Controller verfication during
943 * TLS connection setup between the TSA NIC and the TSA Controller
945 * NOTE: This TAG is temporarily placed in the dynamic config partition and will
946 * be moved to a private partition during TSA development. It is not used in any
950 #define TLV_TAG_TMP_CA_ROOT_CERT (0x10260000) /* DEPRECATED */
952 typedef struct tlv_ca_root_cert {
956 } tlv_ca_root_cert_t;
958 /* Tx vFIFO Low latency configuration
960 * To keep the desired booting behaviour for the switch, it just requires to
961 * know if the low latency mode is enabled.
964 #define TLV_TAG_TX_VFIFO_ULL_MODE (0x10270000)
965 struct tlv_tx_vfifo_ull_mode {
969 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT 0
974 * Medford2 tag for selecting VI window decode (see values below)
976 #define TLV_TAG_BIU_VI_WINDOW_MODE (0x10280000)
977 struct tlv_biu_vi_window_mode {
981 #define TLV_BIU_VI_WINDOW_MODE_8K 0 /* 8k per VI, CTPIO not mapped, medford/hunt compatible */
982 #define TLV_BIU_VI_WINDOW_MODE_16K 1 /* 16k per VI, CTPIO mapped */
983 #define TLV_BIU_VI_WINDOW_MODE_64K 2 /* 64k per VI, CTPIO mapped, POWER-friendly */
988 * Medford2 tag for configuring the FastPD mode (see values below)
990 #define TLV_TAG_FASTPD_MODE(port) (0x10290000 + (port))
991 struct tlv_fastpd_mode {
995 #define TLV_FASTPD_MODE_SOFT_ALL 0 /* All packets to the SoftPD */
996 #define TLV_FASTPD_MODE_FAST_ALL 1 /* All packets to the FastPD */
997 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
1000 #endif /* CI_MGMT_TLV_LAYOUT_H */