2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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28 * policies, either expressed or implied, of the FreeBSD Project.
35 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
38 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
40 (_etp)->et_stat[_stat]++; \
41 _NOTE(CONSTANTCONDITION) \
44 #define EFX_TX_QSTAT_INCR(_etp, _stat)
47 static __checkReturn efx_rc_t
51 __in uint32_t target_evq,
53 __in uint32_t instance,
55 __in efsys_mem_t *esmp)
58 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
59 MC_CMD_INIT_TXQ_OUT_LEN)];
60 efx_qword_t *dma_addr;
66 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
67 EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
69 npages = EFX_TXQ_NBUFS(size);
70 if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
75 (void) memset(payload, 0, sizeof (payload));
76 req.emr_cmd = MC_CMD_INIT_TXQ;
77 req.emr_in_buf = payload;
78 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
79 req.emr_out_buf = payload;
80 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
82 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
83 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
84 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
85 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
87 MCDI_IN_POPULATE_DWORD_7(req, INIT_TXQ_IN_FLAGS,
88 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
89 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
90 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
91 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
92 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
93 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
94 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
95 INIT_TXQ_IN_CRC_MODE, 0,
96 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
98 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
99 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
101 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
102 addr = EFSYS_MEM_ADDR(esmp);
104 for (i = 0; i < npages; i++) {
105 EFX_POPULATE_QWORD_2(*dma_addr,
106 EFX_DWORD_1, (uint32_t)(addr >> 32),
107 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
110 addr += EFX_BUF_SIZE;
113 efx_mcdi_execute(enp, &req);
115 if (req.emr_rc != 0) {
125 EFSYS_PROBE1(fail1, efx_rc_t, rc);
130 static __checkReturn efx_rc_t
133 __in uint32_t instance)
136 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
137 MC_CMD_FINI_TXQ_OUT_LEN)];
140 (void) memset(payload, 0, sizeof (payload));
141 req.emr_cmd = MC_CMD_FINI_TXQ;
142 req.emr_in_buf = payload;
143 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
144 req.emr_out_buf = payload;
145 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
147 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
149 efx_mcdi_execute_quiet(enp, &req);
151 if (req.emr_rc != 0) {
160 * EALREADY is not an error, but indicates that the MC has rebooted and
161 * that the TXQ has already been destroyed.
164 EFSYS_PROBE1(fail1, efx_rc_t, rc);
169 __checkReturn efx_rc_t
173 _NOTE(ARGUNUSED(enp))
181 _NOTE(ARGUNUSED(enp))
184 __checkReturn efx_rc_t
187 __in unsigned int index,
188 __in unsigned int label,
189 __in efsys_mem_t *esmp,
195 __out unsigned int *addedp)
202 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
207 * A previous user of this TX queue may have written a descriptor to the
208 * TX push collector, but not pushed the doorbell (e.g. after a crash).
209 * The next doorbell write would then push the stale descriptor.
211 * Ensure the (per network port) TX push collector is cleared by writing
212 * a no-op TX option descriptor. See bug29981 for details.
215 EFX_POPULATE_QWORD_4(desc,
216 ESF_DZ_TX_DESC_IS_OPT, 1,
217 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
218 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
219 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
220 ESF_DZ_TX_OPTION_IP_CSUM,
221 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0);
223 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
224 ef10_tx_qpush(etp, *addedp, 0);
229 EFSYS_PROBE1(fail1, efx_rc_t, rc);
239 _NOTE(ARGUNUSED(etp))
243 __checkReturn efx_rc_t
247 efx_nic_t *enp = etp->et_enp;
248 efx_piobuf_handle_t handle;
251 if (etp->et_pio_size != 0) {
256 /* Sub-allocate a PIO block from a piobuf */
257 if ((rc = ef10_nic_pio_alloc(enp,
262 &etp->et_pio_size)) != 0) {
265 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
267 /* Link the piobuf to this TXQ */
268 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
273 * et_pio_offset is the offset of the sub-allocated block within the
274 * hardware PIO buffer. It is used as the buffer address in the PIO
277 * et_pio_write_offset is the offset of the sub-allocated block from the
278 * start of the write-combined memory mapping, and is used for writing
279 * data into the PIO buffer.
281 etp->et_pio_write_offset =
282 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
283 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
289 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
292 etp->et_pio_size = 0;
294 EFSYS_PROBE1(fail1, efx_rc_t, rc);
300 ef10_tx_qpio_disable(
303 efx_nic_t *enp = etp->et_enp;
305 if (etp->et_pio_size != 0) {
306 /* Unlink the piobuf from this TXQ */
307 ef10_nic_pio_unlink(enp, etp->et_index);
309 /* Free the sub-allocated PIO block */
310 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
311 etp->et_pio_size = 0;
312 etp->et_pio_write_offset = 0;
316 __checkReturn efx_rc_t
319 __in_ecount(length) uint8_t *buffer,
323 efx_nic_t *enp = etp->et_enp;
324 efsys_bar_t *esbp = enp->en_esbp;
325 uint32_t write_offset;
326 uint32_t write_offset_limit;
330 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
332 if (etp->et_pio_size == 0) {
336 if (offset + length > etp->et_pio_size) {
342 * Writes to PIO buffers must be 64 bit aligned, and multiples of
345 write_offset = etp->et_pio_write_offset + offset;
346 write_offset_limit = write_offset + length;
347 eqp = (efx_qword_t *)buffer;
348 while (write_offset < write_offset_limit) {
349 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
351 write_offset += sizeof (efx_qword_t);
359 EFSYS_PROBE1(fail1, efx_rc_t, rc);
364 __checkReturn efx_rc_t
367 __in size_t pkt_length,
368 __in unsigned int completed,
369 __inout unsigned int *addedp)
371 efx_qword_t pio_desc;
374 unsigned int added = *addedp;
378 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
383 if (etp->et_pio_size == 0) {
388 id = added++ & etp->et_mask;
389 offset = id * sizeof (efx_qword_t);
391 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
392 unsigned int, id, uint32_t, etp->et_pio_offset,
395 EFX_POPULATE_QWORD_5(pio_desc,
396 ESF_DZ_TX_DESC_IS_OPT, 1,
397 ESF_DZ_TX_OPTION_TYPE, 1,
398 ESF_DZ_TX_PIO_CONT, 0,
399 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
400 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
402 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
404 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
412 EFSYS_PROBE1(fail1, efx_rc_t, rc);
417 __checkReturn efx_rc_t
420 __in_ecount(n) efx_buffer_t *eb,
422 __in unsigned int completed,
423 __inout unsigned int *addedp)
425 unsigned int added = *addedp;
429 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
434 for (i = 0; i < n; i++) {
435 efx_buffer_t *ebp = &eb[i];
436 efsys_dma_addr_t addr = ebp->eb_addr;
437 size_t size = ebp->eb_size;
438 boolean_t eop = ebp->eb_eop;
443 /* No limitations on boundary crossing */
445 etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
447 id = added++ & etp->et_mask;
448 offset = id * sizeof (efx_qword_t);
450 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
451 unsigned int, id, efsys_dma_addr_t, addr,
452 size_t, size, boolean_t, eop);
454 EFX_POPULATE_QWORD_5(qword,
455 ESF_DZ_TX_KER_TYPE, 0,
456 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
457 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
458 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
459 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
461 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
464 EFX_TX_QSTAT_INCR(etp, TX_POST);
470 EFSYS_PROBE1(fail1, efx_rc_t, rc);
476 * This improves performance by, when possible, pushing a TX descriptor at the
477 * same time as the doorbell. The descriptor must be added to the TXQ, so that
478 * can be used if the hardware decides not to use the pushed descriptor.
483 __in unsigned int added,
484 __in unsigned int pushed)
486 efx_nic_t *enp = etp->et_enp;
493 wptr = added & etp->et_mask;
494 id = pushed & etp->et_mask;
495 offset = id * sizeof (efx_qword_t);
497 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
500 * Bug 65776: TSO option descriptors cannot be pushed if pacer bypass is
501 * enabled on the event queue this transmit queue is attached to.
503 * To ensure the code is safe, it is easiest to simply test the type of
504 * the descriptor to push, and only push it is if it not a TSO option
507 if ((EFX_QWORD_FIELD(desc, ESF_DZ_TX_DESC_IS_OPT) != 1) ||
508 (EFX_QWORD_FIELD(desc, ESF_DZ_TX_OPTION_TYPE) !=
509 ESE_DZ_TX_OPTION_DESC_TSO)) {
510 /* Push the descriptor and update the wptr. */
511 EFX_POPULATE_OWORD_3(oword, ERF_DZ_TX_DESC_WPTR, wptr,
512 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
513 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
515 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
516 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
518 EFSYS_PIO_WRITE_BARRIER();
519 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
520 etp->et_index, &oword);
525 * Only update the wptr. This is signalled to the hardware by
526 * only writing one DWORD of the doorbell register.
528 EFX_POPULATE_OWORD_1(oword, ERF_DZ_TX_DESC_WPTR, wptr);
529 dword = oword.eo_dword[2];
531 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
532 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
534 EFSYS_PIO_WRITE_BARRIER();
535 EFX_BAR_TBL_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
536 etp->et_index, &dword, B_FALSE);
540 __checkReturn efx_rc_t
543 __in_ecount(n) efx_desc_t *ed,
545 __in unsigned int completed,
546 __inout unsigned int *addedp)
548 unsigned int added = *addedp;
552 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
557 for (i = 0; i < n; i++) {
558 efx_desc_t *edp = &ed[i];
562 id = added++ & etp->et_mask;
563 offset = id * sizeof (efx_desc_t);
565 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
568 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
569 unsigned int, added, unsigned int, n);
571 EFX_TX_QSTAT_INCR(etp, TX_POST);
577 EFSYS_PROBE1(fail1, efx_rc_t, rc);
583 ef10_tx_qdesc_dma_create(
585 __in efsys_dma_addr_t addr,
588 __out efx_desc_t *edp)
590 /* No limitations on boundary crossing */
591 EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
593 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
594 efsys_dma_addr_t, addr,
595 size_t, size, boolean_t, eop);
597 EFX_POPULATE_QWORD_5(edp->ed_eq,
598 ESF_DZ_TX_KER_TYPE, 0,
599 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
600 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
601 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
602 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
606 ef10_tx_qdesc_tso_create(
608 __in uint16_t ipv4_id,
609 __in uint32_t tcp_seq,
610 __in uint8_t tcp_flags,
611 __out efx_desc_t *edp)
613 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
614 uint16_t, ipv4_id, uint32_t, tcp_seq,
617 EFX_POPULATE_QWORD_5(edp->ed_eq,
618 ESF_DZ_TX_DESC_IS_OPT, 1,
619 ESF_DZ_TX_OPTION_TYPE,
620 ESE_DZ_TX_OPTION_DESC_TSO,
621 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
622 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
623 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
627 ef10_tx_qdesc_tso2_create(
629 __in uint16_t ipv4_id,
630 __in uint32_t tcp_seq,
631 __in uint16_t tcp_mss,
632 __out_ecount(count) efx_desc_t *edp,
635 EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
636 uint16_t, ipv4_id, uint32_t, tcp_seq,
639 EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
641 EFX_POPULATE_QWORD_5(edp[0].ed_eq,
642 ESF_DZ_TX_DESC_IS_OPT, 1,
643 ESF_DZ_TX_OPTION_TYPE,
644 ESE_DZ_TX_OPTION_DESC_TSO,
645 ESF_DZ_TX_TSO_OPTION_TYPE,
646 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
647 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
648 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
649 EFX_POPULATE_QWORD_4(edp[1].ed_eq,
650 ESF_DZ_TX_DESC_IS_OPT, 1,
651 ESF_DZ_TX_OPTION_TYPE,
652 ESE_DZ_TX_OPTION_DESC_TSO,
653 ESF_DZ_TX_TSO_OPTION_TYPE,
654 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
655 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
659 ef10_tx_qdesc_vlantci_create(
662 __out efx_desc_t *edp)
664 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
667 EFX_POPULATE_QWORD_4(edp->ed_eq,
668 ESF_DZ_TX_DESC_IS_OPT, 1,
669 ESF_DZ_TX_OPTION_TYPE,
670 ESE_DZ_TX_OPTION_DESC_VLAN,
671 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
672 ESF_DZ_TX_VLAN_TAG1, tci);
676 __checkReturn efx_rc_t
679 __in unsigned int ns)
684 _NOTE(ARGUNUSED(etp, ns))
685 _NOTE(CONSTANTCONDITION)
695 EFSYS_PROBE1(fail1, efx_rc_t, rc);
700 __checkReturn efx_rc_t
704 efx_nic_t *enp = etp->et_enp;
707 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
714 * EALREADY is not an error, but indicates that the MC has rebooted and
715 * that the TXQ has already been destroyed. Callers need to know that
716 * the TXQ flush has completed to avoid waiting until timeout for a
717 * flush done event that will not be delivered.
720 EFSYS_PROBE1(fail1, efx_rc_t, rc);
730 _NOTE(ARGUNUSED(etp))
736 ef10_tx_qstats_update(
738 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
742 for (id = 0; id < TX_NQSTATS; id++) {
743 efsys_stat_t *essp = &stat[id];
745 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
746 etp->et_stat[id] = 0;
750 #endif /* EFSYS_OPT_QSTATS */
752 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */