1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2012-2018 Solarflare Communications Inc.
11 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
14 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
16 (_etp)->et_stat[_stat]++; \
17 _NOTE(CONSTANTCONDITION) \
20 #define EFX_TX_QSTAT_INCR(_etp, _stat)
23 static __checkReturn efx_rc_t
27 __in uint32_t target_evq,
29 __in uint32_t instance,
31 __in efsys_mem_t *esmp)
34 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
35 MC_CMD_INIT_TXQ_OUT_LEN)];
36 efx_qword_t *dma_addr;
42 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
43 EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
45 npages = EFX_TXQ_NBUFS(ndescs);
46 if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
51 (void) memset(payload, 0, sizeof (payload));
52 req.emr_cmd = MC_CMD_INIT_TXQ;
53 req.emr_in_buf = payload;
54 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
55 req.emr_out_buf = payload;
56 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
58 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, ndescs);
59 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
60 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
61 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
63 MCDI_IN_POPULATE_DWORD_9(req, INIT_TXQ_IN_FLAGS,
64 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
65 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
66 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
67 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
68 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
69 INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN,
70 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0,
71 INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN,
72 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
73 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
74 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
75 INIT_TXQ_IN_CRC_MODE, 0,
76 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
78 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
79 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
81 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
82 addr = EFSYS_MEM_ADDR(esmp);
84 for (i = 0; i < npages; i++) {
85 EFX_POPULATE_QWORD_2(*dma_addr,
86 EFX_DWORD_1, (uint32_t)(addr >> 32),
87 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
93 efx_mcdi_execute(enp, &req);
95 if (req.emr_rc != 0) {
105 EFSYS_PROBE1(fail1, efx_rc_t, rc);
110 static __checkReturn efx_rc_t
113 __in uint32_t instance)
116 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
117 MC_CMD_FINI_TXQ_OUT_LEN)];
120 (void) memset(payload, 0, sizeof (payload));
121 req.emr_cmd = MC_CMD_FINI_TXQ;
122 req.emr_in_buf = payload;
123 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
124 req.emr_out_buf = payload;
125 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
127 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
129 efx_mcdi_execute_quiet(enp, &req);
131 if (req.emr_rc != 0) {
140 * EALREADY is not an error, but indicates that the MC has rebooted and
141 * that the TXQ has already been destroyed.
144 EFSYS_PROBE1(fail1, efx_rc_t, rc);
149 __checkReturn efx_rc_t
153 _NOTE(ARGUNUSED(enp))
161 _NOTE(ARGUNUSED(enp))
164 __checkReturn efx_rc_t
167 __in unsigned int index,
168 __in unsigned int label,
169 __in efsys_mem_t *esmp,
175 __out unsigned int *addedp)
177 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
184 inner_csum = EFX_TXQ_CKSUM_INNER_IPV4 | EFX_TXQ_CKSUM_INNER_TCPUDP;
185 if (((flags & inner_csum) != 0) &&
186 (encp->enc_tunnel_encapsulations_supported == 0)) {
191 if ((rc = efx_mcdi_init_txq(enp, ndescs, eep->ee_index, label, index,
196 * A previous user of this TX queue may have written a descriptor to the
197 * TX push collector, but not pushed the doorbell (e.g. after a crash).
198 * The next doorbell write would then push the stale descriptor.
200 * Ensure the (per network port) TX push collector is cleared by writing
201 * a no-op TX option descriptor. See bug29981 for details.
204 EFX_POPULATE_QWORD_6(desc,
205 ESF_DZ_TX_DESC_IS_OPT, 1,
206 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
207 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
208 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
209 ESF_DZ_TX_OPTION_IP_CSUM,
210 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0,
211 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM,
212 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
213 ESF_DZ_TX_OPTION_INNER_IP_CSUM,
214 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0);
216 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
217 ef10_tx_qpush(etp, *addedp, 0);
224 EFSYS_PROBE1(fail1, efx_rc_t, rc);
234 _NOTE(ARGUNUSED(etp))
238 __checkReturn efx_rc_t
242 efx_nic_t *enp = etp->et_enp;
243 efx_piobuf_handle_t handle;
246 if (etp->et_pio_size != 0) {
251 /* Sub-allocate a PIO block from a piobuf */
252 if ((rc = ef10_nic_pio_alloc(enp,
257 &etp->et_pio_size)) != 0) {
260 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
262 /* Link the piobuf to this TXQ */
263 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
268 * et_pio_offset is the offset of the sub-allocated block within the
269 * hardware PIO buffer. It is used as the buffer address in the PIO
272 * et_pio_write_offset is the offset of the sub-allocated block from the
273 * start of the write-combined memory mapping, and is used for writing
274 * data into the PIO buffer.
276 etp->et_pio_write_offset =
277 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
278 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
284 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
287 etp->et_pio_size = 0;
289 EFSYS_PROBE1(fail1, efx_rc_t, rc);
295 ef10_tx_qpio_disable(
298 efx_nic_t *enp = etp->et_enp;
300 if (etp->et_pio_size != 0) {
301 /* Unlink the piobuf from this TXQ */
302 ef10_nic_pio_unlink(enp, etp->et_index);
304 /* Free the sub-allocated PIO block */
305 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
306 etp->et_pio_size = 0;
307 etp->et_pio_write_offset = 0;
311 __checkReturn efx_rc_t
314 __in_ecount(length) uint8_t *buffer,
318 efx_nic_t *enp = etp->et_enp;
319 efsys_bar_t *esbp = enp->en_esbp;
320 uint32_t write_offset;
321 uint32_t write_offset_limit;
325 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
327 if (etp->et_pio_size == 0) {
331 if (offset + length > etp->et_pio_size) {
337 * Writes to PIO buffers must be 64 bit aligned, and multiples of
340 write_offset = etp->et_pio_write_offset + offset;
341 write_offset_limit = write_offset + length;
342 eqp = (efx_qword_t *)buffer;
343 while (write_offset < write_offset_limit) {
344 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
346 write_offset += sizeof (efx_qword_t);
354 EFSYS_PROBE1(fail1, efx_rc_t, rc);
359 __checkReturn efx_rc_t
362 __in size_t pkt_length,
363 __in unsigned int completed,
364 __inout unsigned int *addedp)
366 efx_qword_t pio_desc;
369 unsigned int added = *addedp;
373 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
378 if (etp->et_pio_size == 0) {
383 id = added++ & etp->et_mask;
384 offset = id * sizeof (efx_qword_t);
386 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
387 unsigned int, id, uint32_t, etp->et_pio_offset,
390 EFX_POPULATE_QWORD_5(pio_desc,
391 ESF_DZ_TX_DESC_IS_OPT, 1,
392 ESF_DZ_TX_OPTION_TYPE, 1,
393 ESF_DZ_TX_PIO_CONT, 0,
394 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
395 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
397 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
399 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
407 EFSYS_PROBE1(fail1, efx_rc_t, rc);
412 __checkReturn efx_rc_t
415 __in_ecount(ndescs) efx_buffer_t *eb,
416 __in unsigned int ndescs,
417 __in unsigned int completed,
418 __inout unsigned int *addedp)
420 unsigned int added = *addedp;
424 if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
429 for (i = 0; i < ndescs; i++) {
430 efx_buffer_t *ebp = &eb[i];
431 efsys_dma_addr_t addr = ebp->eb_addr;
432 size_t size = ebp->eb_size;
433 boolean_t eop = ebp->eb_eop;
438 /* No limitations on boundary crossing */
440 etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
442 id = added++ & etp->et_mask;
443 offset = id * sizeof (efx_qword_t);
445 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
446 unsigned int, id, efsys_dma_addr_t, addr,
447 size_t, size, boolean_t, eop);
449 EFX_POPULATE_QWORD_5(qword,
450 ESF_DZ_TX_KER_TYPE, 0,
451 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
452 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
453 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
454 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
456 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
459 EFX_TX_QSTAT_INCR(etp, TX_POST);
465 EFSYS_PROBE1(fail1, efx_rc_t, rc);
471 * This improves performance by, when possible, pushing a TX descriptor at the
472 * same time as the doorbell. The descriptor must be added to the TXQ, so that
473 * can be used if the hardware decides not to use the pushed descriptor.
478 __in unsigned int added,
479 __in unsigned int pushed)
481 efx_nic_t *enp = etp->et_enp;
488 wptr = added & etp->et_mask;
489 id = pushed & etp->et_mask;
490 offset = id * sizeof (efx_qword_t);
492 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
495 * Bug 65776: TSO option descriptors cannot be pushed if pacer bypass is
496 * enabled on the event queue this transmit queue is attached to.
498 * To ensure the code is safe, it is easiest to simply test the type of
499 * the descriptor to push, and only push it is if it not a TSO option
502 if ((EFX_QWORD_FIELD(desc, ESF_DZ_TX_DESC_IS_OPT) != 1) ||
503 (EFX_QWORD_FIELD(desc, ESF_DZ_TX_OPTION_TYPE) !=
504 ESE_DZ_TX_OPTION_DESC_TSO)) {
505 /* Push the descriptor and update the wptr. */
506 EFX_POPULATE_OWORD_3(oword, ERF_DZ_TX_DESC_WPTR, wptr,
507 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
508 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
510 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
511 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
513 EFSYS_PIO_WRITE_BARRIER();
514 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
515 etp->et_index, &oword);
520 * Only update the wptr. This is signalled to the hardware by
521 * only writing one DWORD of the doorbell register.
523 EFX_POPULATE_OWORD_1(oword, ERF_DZ_TX_DESC_WPTR, wptr);
524 dword = oword.eo_dword[2];
526 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
527 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
529 EFSYS_PIO_WRITE_BARRIER();
530 EFX_BAR_TBL_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
531 etp->et_index, &dword, B_FALSE);
535 __checkReturn efx_rc_t
538 __in_ecount(ndescs) efx_desc_t *ed,
539 __in unsigned int ndescs,
540 __in unsigned int completed,
541 __inout unsigned int *addedp)
543 unsigned int added = *addedp;
547 if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
552 for (i = 0; i < ndescs; i++) {
553 efx_desc_t *edp = &ed[i];
557 id = added++ & etp->et_mask;
558 offset = id * sizeof (efx_desc_t);
560 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
563 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
564 unsigned int, added, unsigned int, ndescs);
566 EFX_TX_QSTAT_INCR(etp, TX_POST);
572 EFSYS_PROBE1(fail1, efx_rc_t, rc);
578 ef10_tx_qdesc_dma_create(
580 __in efsys_dma_addr_t addr,
583 __out efx_desc_t *edp)
585 _NOTE(ARGUNUSED(etp))
587 /* No limitations on boundary crossing */
588 EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
590 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
591 efsys_dma_addr_t, addr,
592 size_t, size, boolean_t, eop);
594 EFX_POPULATE_QWORD_5(edp->ed_eq,
595 ESF_DZ_TX_KER_TYPE, 0,
596 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
597 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
598 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
599 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
603 ef10_tx_qdesc_tso_create(
605 __in uint16_t ipv4_id,
606 __in uint32_t tcp_seq,
607 __in uint8_t tcp_flags,
608 __out efx_desc_t *edp)
610 _NOTE(ARGUNUSED(etp))
612 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
613 uint16_t, ipv4_id, uint32_t, tcp_seq,
616 EFX_POPULATE_QWORD_5(edp->ed_eq,
617 ESF_DZ_TX_DESC_IS_OPT, 1,
618 ESF_DZ_TX_OPTION_TYPE,
619 ESE_DZ_TX_OPTION_DESC_TSO,
620 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
621 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
622 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
626 ef10_tx_qdesc_tso2_create(
628 __in uint16_t ipv4_id,
629 __in uint32_t tcp_seq,
630 __in uint16_t tcp_mss,
631 __out_ecount(count) efx_desc_t *edp,
634 _NOTE(ARGUNUSED(etp, count))
636 EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
637 uint16_t, ipv4_id, uint32_t, tcp_seq,
640 EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
642 EFX_POPULATE_QWORD_5(edp[0].ed_eq,
643 ESF_DZ_TX_DESC_IS_OPT, 1,
644 ESF_DZ_TX_OPTION_TYPE,
645 ESE_DZ_TX_OPTION_DESC_TSO,
646 ESF_DZ_TX_TSO_OPTION_TYPE,
647 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
648 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
649 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
650 EFX_POPULATE_QWORD_4(edp[1].ed_eq,
651 ESF_DZ_TX_DESC_IS_OPT, 1,
652 ESF_DZ_TX_OPTION_TYPE,
653 ESE_DZ_TX_OPTION_DESC_TSO,
654 ESF_DZ_TX_TSO_OPTION_TYPE,
655 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
656 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
660 ef10_tx_qdesc_vlantci_create(
663 __out efx_desc_t *edp)
665 _NOTE(ARGUNUSED(etp))
667 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
670 EFX_POPULATE_QWORD_4(edp->ed_eq,
671 ESF_DZ_TX_DESC_IS_OPT, 1,
672 ESF_DZ_TX_OPTION_TYPE,
673 ESE_DZ_TX_OPTION_DESC_VLAN,
674 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
675 ESF_DZ_TX_VLAN_TAG1, tci);
679 __checkReturn efx_rc_t
682 __in unsigned int ns)
687 _NOTE(ARGUNUSED(etp, ns))
688 _NOTE(CONSTANTCONDITION)
698 EFSYS_PROBE1(fail1, efx_rc_t, rc);
703 __checkReturn efx_rc_t
707 efx_nic_t *enp = etp->et_enp;
710 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
717 * EALREADY is not an error, but indicates that the MC has rebooted and
718 * that the TXQ has already been destroyed. Callers need to know that
719 * the TXQ flush has completed to avoid waiting until timeout for a
720 * flush done event that will not be delivered.
723 EFSYS_PROBE1(fail1, efx_rc_t, rc);
733 _NOTE(ARGUNUSED(etp))
739 ef10_tx_qstats_update(
741 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
745 for (id = 0; id < TX_NQSTATS; id++) {
746 efsys_stat_t *essp = &stat[id];
748 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
749 etp->et_stat[id] = 0;
753 #endif /* EFSYS_OPT_QSTATS */
755 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */