2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
38 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
40 (_etp)->et_stat[_stat]++; \
41 _NOTE(CONSTANTCONDITION) \
44 #define EFX_TX_QSTAT_INCR(_etp, _stat)
47 static __checkReturn efx_rc_t
51 __in uint32_t target_evq,
53 __in uint32_t instance,
55 __in efsys_mem_t *esmp)
58 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
59 MC_CMD_INIT_TXQ_OUT_LEN)];
60 efx_qword_t *dma_addr;
66 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
67 EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
69 npages = EFX_TXQ_NBUFS(size);
70 if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
75 (void) memset(payload, 0, sizeof (payload));
76 req.emr_cmd = MC_CMD_INIT_TXQ;
77 req.emr_in_buf = payload;
78 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
79 req.emr_out_buf = payload;
80 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
82 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
83 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
84 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
85 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
87 MCDI_IN_POPULATE_DWORD_9(req, INIT_TXQ_IN_FLAGS,
88 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
89 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
90 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
91 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
92 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
93 INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN,
94 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0,
95 INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN,
96 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
97 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
98 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
99 INIT_TXQ_IN_CRC_MODE, 0,
100 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
102 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
103 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
105 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
106 addr = EFSYS_MEM_ADDR(esmp);
108 for (i = 0; i < npages; i++) {
109 EFX_POPULATE_QWORD_2(*dma_addr,
110 EFX_DWORD_1, (uint32_t)(addr >> 32),
111 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
114 addr += EFX_BUF_SIZE;
117 efx_mcdi_execute(enp, &req);
119 if (req.emr_rc != 0) {
129 EFSYS_PROBE1(fail1, efx_rc_t, rc);
134 static __checkReturn efx_rc_t
137 __in uint32_t instance)
140 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
141 MC_CMD_FINI_TXQ_OUT_LEN)];
144 (void) memset(payload, 0, sizeof (payload));
145 req.emr_cmd = MC_CMD_FINI_TXQ;
146 req.emr_in_buf = payload;
147 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
148 req.emr_out_buf = payload;
149 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
151 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
153 efx_mcdi_execute_quiet(enp, &req);
155 if (req.emr_rc != 0) {
164 * EALREADY is not an error, but indicates that the MC has rebooted and
165 * that the TXQ has already been destroyed.
168 EFSYS_PROBE1(fail1, efx_rc_t, rc);
173 __checkReturn efx_rc_t
177 _NOTE(ARGUNUSED(enp))
185 _NOTE(ARGUNUSED(enp))
188 __checkReturn efx_rc_t
191 __in unsigned int index,
192 __in unsigned int label,
193 __in efsys_mem_t *esmp,
199 __out unsigned int *addedp)
201 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
208 inner_csum = EFX_TXQ_CKSUM_INNER_IPV4 | EFX_TXQ_CKSUM_INNER_TCPUDP;
209 if (((flags & inner_csum) != 0) &&
210 (encp->enc_tunnel_encapsulations_supported == 0)) {
215 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
220 * A previous user of this TX queue may have written a descriptor to the
221 * TX push collector, but not pushed the doorbell (e.g. after a crash).
222 * The next doorbell write would then push the stale descriptor.
224 * Ensure the (per network port) TX push collector is cleared by writing
225 * a no-op TX option descriptor. See bug29981 for details.
228 EFX_POPULATE_QWORD_6(desc,
229 ESF_DZ_TX_DESC_IS_OPT, 1,
230 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
231 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
232 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
233 ESF_DZ_TX_OPTION_IP_CSUM,
234 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0,
235 ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM,
236 (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
237 ESF_DZ_TX_OPTION_INNER_IP_CSUM,
238 (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0);
240 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
241 ef10_tx_qpush(etp, *addedp, 0);
248 EFSYS_PROBE1(fail1, efx_rc_t, rc);
258 _NOTE(ARGUNUSED(etp))
262 __checkReturn efx_rc_t
266 efx_nic_t *enp = etp->et_enp;
267 efx_piobuf_handle_t handle;
270 if (etp->et_pio_size != 0) {
275 /* Sub-allocate a PIO block from a piobuf */
276 if ((rc = ef10_nic_pio_alloc(enp,
281 &etp->et_pio_size)) != 0) {
284 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
286 /* Link the piobuf to this TXQ */
287 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
292 * et_pio_offset is the offset of the sub-allocated block within the
293 * hardware PIO buffer. It is used as the buffer address in the PIO
296 * et_pio_write_offset is the offset of the sub-allocated block from the
297 * start of the write-combined memory mapping, and is used for writing
298 * data into the PIO buffer.
300 etp->et_pio_write_offset =
301 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
302 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
308 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
311 etp->et_pio_size = 0;
313 EFSYS_PROBE1(fail1, efx_rc_t, rc);
319 ef10_tx_qpio_disable(
322 efx_nic_t *enp = etp->et_enp;
324 if (etp->et_pio_size != 0) {
325 /* Unlink the piobuf from this TXQ */
326 ef10_nic_pio_unlink(enp, etp->et_index);
328 /* Free the sub-allocated PIO block */
329 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
330 etp->et_pio_size = 0;
331 etp->et_pio_write_offset = 0;
335 __checkReturn efx_rc_t
338 __in_ecount(length) uint8_t *buffer,
342 efx_nic_t *enp = etp->et_enp;
343 efsys_bar_t *esbp = enp->en_esbp;
344 uint32_t write_offset;
345 uint32_t write_offset_limit;
349 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
351 if (etp->et_pio_size == 0) {
355 if (offset + length > etp->et_pio_size) {
361 * Writes to PIO buffers must be 64 bit aligned, and multiples of
364 write_offset = etp->et_pio_write_offset + offset;
365 write_offset_limit = write_offset + length;
366 eqp = (efx_qword_t *)buffer;
367 while (write_offset < write_offset_limit) {
368 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
370 write_offset += sizeof (efx_qword_t);
378 EFSYS_PROBE1(fail1, efx_rc_t, rc);
383 __checkReturn efx_rc_t
386 __in size_t pkt_length,
387 __in unsigned int completed,
388 __inout unsigned int *addedp)
390 efx_qword_t pio_desc;
393 unsigned int added = *addedp;
397 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
402 if (etp->et_pio_size == 0) {
407 id = added++ & etp->et_mask;
408 offset = id * sizeof (efx_qword_t);
410 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
411 unsigned int, id, uint32_t, etp->et_pio_offset,
414 EFX_POPULATE_QWORD_5(pio_desc,
415 ESF_DZ_TX_DESC_IS_OPT, 1,
416 ESF_DZ_TX_OPTION_TYPE, 1,
417 ESF_DZ_TX_PIO_CONT, 0,
418 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
419 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
421 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
423 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
431 EFSYS_PROBE1(fail1, efx_rc_t, rc);
436 __checkReturn efx_rc_t
439 __in_ecount(n) efx_buffer_t *eb,
441 __in unsigned int completed,
442 __inout unsigned int *addedp)
444 unsigned int added = *addedp;
448 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
453 for (i = 0; i < n; i++) {
454 efx_buffer_t *ebp = &eb[i];
455 efsys_dma_addr_t addr = ebp->eb_addr;
456 size_t size = ebp->eb_size;
457 boolean_t eop = ebp->eb_eop;
462 /* No limitations on boundary crossing */
464 etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
466 id = added++ & etp->et_mask;
467 offset = id * sizeof (efx_qword_t);
469 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
470 unsigned int, id, efsys_dma_addr_t, addr,
471 size_t, size, boolean_t, eop);
473 EFX_POPULATE_QWORD_5(qword,
474 ESF_DZ_TX_KER_TYPE, 0,
475 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
476 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
477 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
478 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
480 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
483 EFX_TX_QSTAT_INCR(etp, TX_POST);
489 EFSYS_PROBE1(fail1, efx_rc_t, rc);
495 * This improves performance by, when possible, pushing a TX descriptor at the
496 * same time as the doorbell. The descriptor must be added to the TXQ, so that
497 * can be used if the hardware decides not to use the pushed descriptor.
502 __in unsigned int added,
503 __in unsigned int pushed)
505 efx_nic_t *enp = etp->et_enp;
512 wptr = added & etp->et_mask;
513 id = pushed & etp->et_mask;
514 offset = id * sizeof (efx_qword_t);
516 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
519 * Bug 65776: TSO option descriptors cannot be pushed if pacer bypass is
520 * enabled on the event queue this transmit queue is attached to.
522 * To ensure the code is safe, it is easiest to simply test the type of
523 * the descriptor to push, and only push it is if it not a TSO option
526 if ((EFX_QWORD_FIELD(desc, ESF_DZ_TX_DESC_IS_OPT) != 1) ||
527 (EFX_QWORD_FIELD(desc, ESF_DZ_TX_OPTION_TYPE) !=
528 ESE_DZ_TX_OPTION_DESC_TSO)) {
529 /* Push the descriptor and update the wptr. */
530 EFX_POPULATE_OWORD_3(oword, ERF_DZ_TX_DESC_WPTR, wptr,
531 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
532 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
534 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
535 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
537 EFSYS_PIO_WRITE_BARRIER();
538 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
539 etp->et_index, &oword);
544 * Only update the wptr. This is signalled to the hardware by
545 * only writing one DWORD of the doorbell register.
547 EFX_POPULATE_OWORD_1(oword, ERF_DZ_TX_DESC_WPTR, wptr);
548 dword = oword.eo_dword[2];
550 /* Ensure ordering of memory (descriptors) and PIO (doorbell) */
551 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
553 EFSYS_PIO_WRITE_BARRIER();
554 EFX_BAR_TBL_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
555 etp->et_index, &dword, B_FALSE);
559 __checkReturn efx_rc_t
562 __in_ecount(n) efx_desc_t *ed,
564 __in unsigned int completed,
565 __inout unsigned int *addedp)
567 unsigned int added = *addedp;
571 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
576 for (i = 0; i < n; i++) {
577 efx_desc_t *edp = &ed[i];
581 id = added++ & etp->et_mask;
582 offset = id * sizeof (efx_desc_t);
584 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
587 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
588 unsigned int, added, unsigned int, n);
590 EFX_TX_QSTAT_INCR(etp, TX_POST);
596 EFSYS_PROBE1(fail1, efx_rc_t, rc);
602 ef10_tx_qdesc_dma_create(
604 __in efsys_dma_addr_t addr,
607 __out efx_desc_t *edp)
609 /* No limitations on boundary crossing */
610 EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
612 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
613 efsys_dma_addr_t, addr,
614 size_t, size, boolean_t, eop);
616 EFX_POPULATE_QWORD_5(edp->ed_eq,
617 ESF_DZ_TX_KER_TYPE, 0,
618 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
619 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
620 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
621 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
625 ef10_tx_qdesc_tso_create(
627 __in uint16_t ipv4_id,
628 __in uint32_t tcp_seq,
629 __in uint8_t tcp_flags,
630 __out efx_desc_t *edp)
632 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
633 uint16_t, ipv4_id, uint32_t, tcp_seq,
636 EFX_POPULATE_QWORD_5(edp->ed_eq,
637 ESF_DZ_TX_DESC_IS_OPT, 1,
638 ESF_DZ_TX_OPTION_TYPE,
639 ESE_DZ_TX_OPTION_DESC_TSO,
640 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
641 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
642 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
646 ef10_tx_qdesc_tso2_create(
648 __in uint16_t ipv4_id,
649 __in uint32_t tcp_seq,
650 __in uint16_t tcp_mss,
651 __out_ecount(count) efx_desc_t *edp,
654 EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
655 uint16_t, ipv4_id, uint32_t, tcp_seq,
658 EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
660 EFX_POPULATE_QWORD_5(edp[0].ed_eq,
661 ESF_DZ_TX_DESC_IS_OPT, 1,
662 ESF_DZ_TX_OPTION_TYPE,
663 ESE_DZ_TX_OPTION_DESC_TSO,
664 ESF_DZ_TX_TSO_OPTION_TYPE,
665 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
666 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
667 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
668 EFX_POPULATE_QWORD_4(edp[1].ed_eq,
669 ESF_DZ_TX_DESC_IS_OPT, 1,
670 ESF_DZ_TX_OPTION_TYPE,
671 ESE_DZ_TX_OPTION_DESC_TSO,
672 ESF_DZ_TX_TSO_OPTION_TYPE,
673 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
674 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
678 ef10_tx_qdesc_vlantci_create(
681 __out efx_desc_t *edp)
683 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
686 EFX_POPULATE_QWORD_4(edp->ed_eq,
687 ESF_DZ_TX_DESC_IS_OPT, 1,
688 ESF_DZ_TX_OPTION_TYPE,
689 ESE_DZ_TX_OPTION_DESC_VLAN,
690 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
691 ESF_DZ_TX_VLAN_TAG1, tci);
695 __checkReturn efx_rc_t
698 __in unsigned int ns)
703 _NOTE(ARGUNUSED(etp, ns))
704 _NOTE(CONSTANTCONDITION)
714 EFSYS_PROBE1(fail1, efx_rc_t, rc);
719 __checkReturn efx_rc_t
723 efx_nic_t *enp = etp->et_enp;
726 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
733 * EALREADY is not an error, but indicates that the MC has rebooted and
734 * that the TXQ has already been destroyed. Callers need to know that
735 * the TXQ flush has completed to avoid waiting until timeout for a
736 * flush done event that will not be delivered.
739 EFSYS_PROBE1(fail1, efx_rc_t, rc);
749 _NOTE(ARGUNUSED(etp))
755 ef10_tx_qstats_update(
757 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
761 for (id = 0; id < TX_NQSTATS; id++) {
762 efsys_stat_t *essp = &stat[id];
764 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
765 etp->et_stat[id] = 0;
769 #endif /* EFSYS_OPT_QSTATS */
771 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */