2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
38 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
40 (_etp)->et_stat[_stat]++; \
41 _NOTE(CONSTANTCONDITION) \
44 #define EFX_TX_QSTAT_INCR(_etp, _stat)
47 static __checkReturn efx_rc_t
51 __in uint32_t target_evq,
53 __in uint32_t instance,
55 __in efsys_mem_t *esmp)
58 uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
59 MC_CMD_INIT_TXQ_OUT_LEN)];
60 efx_qword_t *dma_addr;
66 EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
67 EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
69 npages = EFX_TXQ_NBUFS(size);
70 if (npages > MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM) {
75 (void) memset(payload, 0, sizeof (payload));
76 req.emr_cmd = MC_CMD_INIT_TXQ;
77 req.emr_in_buf = payload;
78 req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
79 req.emr_out_buf = payload;
80 req.emr_out_length = MC_CMD_INIT_TXQ_OUT_LEN;
82 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_SIZE, size);
83 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_TARGET_EVQ, target_evq);
84 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_LABEL, label);
85 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_INSTANCE, instance);
87 MCDI_IN_POPULATE_DWORD_7(req, INIT_TXQ_IN_FLAGS,
88 INIT_TXQ_IN_FLAG_BUFF_MODE, 0,
89 INIT_TXQ_IN_FLAG_IP_CSUM_DIS,
90 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1,
91 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS,
92 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1,
93 INIT_TXQ_EXT_IN_FLAG_TSOV2_EN, (flags & EFX_TXQ_FATSOV2) ? 1 : 0,
94 INIT_TXQ_IN_FLAG_TCP_UDP_ONLY, 0,
95 INIT_TXQ_IN_CRC_MODE, 0,
96 INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
98 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
99 MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
101 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
102 addr = EFSYS_MEM_ADDR(esmp);
104 for (i = 0; i < npages; i++) {
105 EFX_POPULATE_QWORD_2(*dma_addr,
106 EFX_DWORD_1, (uint32_t)(addr >> 32),
107 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
110 addr += EFX_BUF_SIZE;
113 efx_mcdi_execute(enp, &req);
115 if (req.emr_rc != 0) {
125 EFSYS_PROBE1(fail1, efx_rc_t, rc);
130 static __checkReturn efx_rc_t
133 __in uint32_t instance)
136 uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
137 MC_CMD_FINI_TXQ_OUT_LEN)];
140 (void) memset(payload, 0, sizeof (payload));
141 req.emr_cmd = MC_CMD_FINI_TXQ;
142 req.emr_in_buf = payload;
143 req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
144 req.emr_out_buf = payload;
145 req.emr_out_length = MC_CMD_FINI_TXQ_OUT_LEN;
147 MCDI_IN_SET_DWORD(req, FINI_TXQ_IN_INSTANCE, instance);
149 efx_mcdi_execute_quiet(enp, &req);
151 if ((req.emr_rc != 0) && (req.emr_rc != MC_CMD_ERR_EALREADY)) {
159 EFSYS_PROBE1(fail1, efx_rc_t, rc);
164 __checkReturn efx_rc_t
168 _NOTE(ARGUNUSED(enp))
176 _NOTE(ARGUNUSED(enp))
179 __checkReturn efx_rc_t
182 __in unsigned int index,
183 __in unsigned int label,
184 __in efsys_mem_t *esmp,
190 __out unsigned int *addedp)
197 if ((rc = efx_mcdi_init_txq(enp, n, eep->ee_index, label, index, flags,
202 * A previous user of this TX queue may have written a descriptor to the
203 * TX push collector, but not pushed the doorbell (e.g. after a crash).
204 * The next doorbell write would then push the stale descriptor.
206 * Ensure the (per network port) TX push collector is cleared by writing
207 * a no-op TX option descriptor. See bug29981 for details.
210 EFX_POPULATE_QWORD_4(desc,
211 ESF_DZ_TX_DESC_IS_OPT, 1,
212 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
213 ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
214 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
215 ESF_DZ_TX_OPTION_IP_CSUM,
216 (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0);
218 EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
219 ef10_tx_qpush(etp, *addedp, 0);
224 EFSYS_PROBE1(fail1, efx_rc_t, rc);
234 _NOTE(ARGUNUSED(etp))
238 __checkReturn efx_rc_t
242 efx_nic_t *enp = etp->et_enp;
243 efx_piobuf_handle_t handle;
246 if (etp->et_pio_size != 0) {
251 /* Sub-allocate a PIO block from a piobuf */
252 if ((rc = ef10_nic_pio_alloc(enp,
257 &etp->et_pio_size)) != 0) {
260 EFSYS_ASSERT3U(etp->et_pio_size, !=, 0);
262 /* Link the piobuf to this TXQ */
263 if ((rc = ef10_nic_pio_link(enp, etp->et_index, handle)) != 0) {
268 * et_pio_offset is the offset of the sub-allocated block within the
269 * hardware PIO buffer. It is used as the buffer address in the PIO
272 * et_pio_write_offset is the offset of the sub-allocated block from the
273 * start of the write-combined memory mapping, and is used for writing
274 * data into the PIO buffer.
276 etp->et_pio_write_offset =
277 (etp->et_pio_bufnum * ER_DZ_TX_PIOBUF_STEP) +
278 ER_DZ_TX_PIOBUF_OFST + etp->et_pio_offset;
284 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
285 etp->et_pio_size = 0;
289 EFSYS_PROBE1(fail1, efx_rc_t, rc);
295 ef10_tx_qpio_disable(
298 efx_nic_t *enp = etp->et_enp;
300 if (etp->et_pio_size != 0) {
301 /* Unlink the piobuf from this TXQ */
302 ef10_nic_pio_unlink(enp, etp->et_index);
304 /* Free the sub-allocated PIO block */
305 ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
306 etp->et_pio_size = 0;
307 etp->et_pio_write_offset = 0;
311 __checkReturn efx_rc_t
314 __in_ecount(length) uint8_t *buffer,
318 efx_nic_t *enp = etp->et_enp;
319 efsys_bar_t *esbp = enp->en_esbp;
320 uint32_t write_offset;
321 uint32_t write_offset_limit;
325 EFSYS_ASSERT(length % sizeof (efx_qword_t) == 0);
327 if (etp->et_pio_size == 0) {
331 if (offset + length > etp->et_pio_size) {
337 * Writes to PIO buffers must be 64 bit aligned, and multiples of
340 write_offset = etp->et_pio_write_offset + offset;
341 write_offset_limit = write_offset + length;
342 eqp = (efx_qword_t *)buffer;
343 while (write_offset < write_offset_limit) {
344 EFSYS_BAR_WC_WRITEQ(esbp, write_offset, eqp);
346 write_offset += sizeof (efx_qword_t);
354 EFSYS_PROBE1(fail1, efx_rc_t, rc);
359 __checkReturn efx_rc_t
362 __in size_t pkt_length,
363 __in unsigned int completed,
364 __inout unsigned int *addedp)
366 efx_qword_t pio_desc;
369 unsigned int added = *addedp;
373 if (added - completed + 1 > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
378 if (etp->et_pio_size == 0) {
383 id = added++ & etp->et_mask;
384 offset = id * sizeof (efx_qword_t);
386 EFSYS_PROBE4(tx_pio_post, unsigned int, etp->et_index,
387 unsigned int, id, uint32_t, etp->et_pio_offset,
390 EFX_POPULATE_QWORD_5(pio_desc,
391 ESF_DZ_TX_DESC_IS_OPT, 1,
392 ESF_DZ_TX_OPTION_TYPE, 1,
393 ESF_DZ_TX_PIO_CONT, 0,
394 ESF_DZ_TX_PIO_BYTE_CNT, pkt_length,
395 ESF_DZ_TX_PIO_BUF_ADDR, etp->et_pio_offset);
397 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &pio_desc);
399 EFX_TX_QSTAT_INCR(etp, TX_POST_PIO);
407 EFSYS_PROBE1(fail1, efx_rc_t, rc);
412 __checkReturn efx_rc_t
415 __in_ecount(n) efx_buffer_t *eb,
417 __in unsigned int completed,
418 __inout unsigned int *addedp)
420 unsigned int added = *addedp;
424 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
429 for (i = 0; i < n; i++) {
430 efx_buffer_t *ebp = &eb[i];
431 efsys_dma_addr_t addr = ebp->eb_addr;
432 size_t size = ebp->eb_size;
433 boolean_t eop = ebp->eb_eop;
438 /* Fragments must not span 4k boundaries. */
439 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size));
441 id = added++ & etp->et_mask;
442 offset = id * sizeof (efx_qword_t);
444 EFSYS_PROBE5(tx_post, unsigned int, etp->et_index,
445 unsigned int, id, efsys_dma_addr_t, addr,
446 size_t, size, boolean_t, eop);
448 EFX_POPULATE_QWORD_5(qword,
449 ESF_DZ_TX_KER_TYPE, 0,
450 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
451 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
452 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
453 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
455 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &qword);
458 EFX_TX_QSTAT_INCR(etp, TX_POST);
464 EFSYS_PROBE1(fail1, efx_rc_t, rc);
470 * This improves performance by pushing a TX descriptor at the same time as the
471 * doorbell. The descriptor must be added to the TXQ, so that can be used if the
472 * hardware decides not to use the pushed descriptor.
477 __in unsigned int added,
478 __in unsigned int pushed)
480 efx_nic_t *enp = etp->et_enp;
487 wptr = added & etp->et_mask;
488 id = pushed & etp->et_mask;
489 offset = id * sizeof (efx_qword_t);
491 EFSYS_MEM_READQ(etp->et_esmp, offset, &desc);
492 EFX_POPULATE_OWORD_3(oword,
493 ERF_DZ_TX_DESC_WPTR, wptr,
494 ERF_DZ_TX_DESC_HWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_1),
495 ERF_DZ_TX_DESC_LWORD, EFX_QWORD_FIELD(desc, EFX_DWORD_0));
497 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
498 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1, wptr, id);
499 EFSYS_PIO_WRITE_BARRIER();
500 EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG, etp->et_index,
504 __checkReturn efx_rc_t
507 __in_ecount(n) efx_desc_t *ed,
509 __in unsigned int completed,
510 __inout unsigned int *addedp)
512 unsigned int added = *addedp;
516 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
521 for (i = 0; i < n; i++) {
522 efx_desc_t *edp = &ed[i];
526 id = added++ & etp->et_mask;
527 offset = id * sizeof (efx_desc_t);
529 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
532 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
533 unsigned int, added, unsigned int, n);
535 EFX_TX_QSTAT_INCR(etp, TX_POST);
541 EFSYS_PROBE1(fail1, efx_rc_t, rc);
547 ef10_tx_qdesc_dma_create(
549 __in efsys_dma_addr_t addr,
552 __out efx_desc_t *edp)
554 /* Fragments must not span 4k boundaries. */
555 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
557 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
558 efsys_dma_addr_t, addr,
559 size_t, size, boolean_t, eop);
561 EFX_POPULATE_QWORD_5(edp->ed_eq,
562 ESF_DZ_TX_KER_TYPE, 0,
563 ESF_DZ_TX_KER_CONT, (eop) ? 0 : 1,
564 ESF_DZ_TX_KER_BYTE_CNT, (uint32_t)(size),
565 ESF_DZ_TX_KER_BUF_ADDR_DW0, (uint32_t)(addr & 0xffffffff),
566 ESF_DZ_TX_KER_BUF_ADDR_DW1, (uint32_t)(addr >> 32));
570 ef10_tx_qdesc_tso_create(
572 __in uint16_t ipv4_id,
573 __in uint32_t tcp_seq,
574 __in uint8_t tcp_flags,
575 __out efx_desc_t *edp)
577 EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
578 uint16_t, ipv4_id, uint32_t, tcp_seq,
581 EFX_POPULATE_QWORD_5(edp->ed_eq,
582 ESF_DZ_TX_DESC_IS_OPT, 1,
583 ESF_DZ_TX_OPTION_TYPE,
584 ESE_DZ_TX_OPTION_DESC_TSO,
585 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
586 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
587 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
591 ef10_tx_qdesc_tso2_create(
593 __in uint16_t ipv4_id,
594 __in uint32_t tcp_seq,
595 __in uint16_t tcp_mss,
596 __out_ecount(count) efx_desc_t *edp,
599 EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
600 uint16_t, ipv4_id, uint32_t, tcp_seq,
603 EFSYS_ASSERT(count >= EFX_TX_FATSOV2_OPT_NDESCS);
605 EFX_POPULATE_QWORD_5(edp[0].ed_eq,
606 ESF_DZ_TX_DESC_IS_OPT, 1,
607 ESF_DZ_TX_OPTION_TYPE,
608 ESE_DZ_TX_OPTION_DESC_TSO,
609 ESF_DZ_TX_TSO_OPTION_TYPE,
610 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
611 ESF_DZ_TX_TSO_IP_ID, ipv4_id,
612 ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
613 EFX_POPULATE_QWORD_4(edp[1].ed_eq,
614 ESF_DZ_TX_DESC_IS_OPT, 1,
615 ESF_DZ_TX_OPTION_TYPE,
616 ESE_DZ_TX_OPTION_DESC_TSO,
617 ESF_DZ_TX_TSO_OPTION_TYPE,
618 ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
619 ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
623 ef10_tx_qdesc_vlantci_create(
626 __out efx_desc_t *edp)
628 EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
631 EFX_POPULATE_QWORD_4(edp->ed_eq,
632 ESF_DZ_TX_DESC_IS_OPT, 1,
633 ESF_DZ_TX_OPTION_TYPE,
634 ESE_DZ_TX_OPTION_DESC_VLAN,
635 ESF_DZ_TX_VLAN_OP, tci ? 1 : 0,
636 ESF_DZ_TX_VLAN_TAG1, tci);
640 __checkReturn efx_rc_t
643 __in unsigned int ns)
648 _NOTE(ARGUNUSED(etp, ns))
649 _NOTE(CONSTANTCONDITION)
659 EFSYS_PROBE1(fail1, efx_rc_t, rc);
664 __checkReturn efx_rc_t
668 efx_nic_t *enp = etp->et_enp;
671 if ((rc = efx_mcdi_fini_txq(enp, etp->et_index)) != 0)
677 EFSYS_PROBE1(fail1, efx_rc_t, rc);
687 _NOTE(ARGUNUSED(etp))
693 ef10_tx_qstats_update(
695 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
699 for (id = 0; id < TX_NQSTATS; id++) {
700 efsys_stat_t *essp = &stat[id];
702 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
703 etp->et_stat[id] = 0;
707 #endif /* EFSYS_OPT_QSTATS */
709 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */