2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 __in efx_nic_t *enp);
155 __in efx_nic_t *enp);
159 __in efx_nic_t *enp);
161 #define EFX_PCIE_LINK_SPEED_GEN1 1
162 #define EFX_PCIE_LINK_SPEED_GEN2 2
163 #define EFX_PCIE_LINK_SPEED_GEN3 3
165 typedef enum efx_pcie_link_performance_e {
166 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
167 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
168 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
169 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
170 } efx_pcie_link_performance_t;
172 extern __checkReturn efx_rc_t
173 efx_nic_calculate_pcie_link_bandwidth(
174 __in uint32_t pcie_link_width,
175 __in uint32_t pcie_link_gen,
176 __out uint32_t *bandwidth_mbpsp);
178 extern __checkReturn efx_rc_t
179 efx_nic_check_pcie_link_speed(
181 __in uint32_t pcie_link_width,
182 __in uint32_t pcie_link_gen,
183 __out efx_pcie_link_performance_t *resultp);
187 #define EFX_NINTR_SIENA 1024
189 typedef enum efx_intr_type_e {
190 EFX_INTR_INVALID = 0,
196 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
198 extern __checkReturn efx_rc_t
201 __in efx_intr_type_t type,
202 __in efsys_mem_t *esmp);
206 __in efx_nic_t *enp);
210 __in efx_nic_t *enp);
213 efx_intr_disable_unlocked(
214 __in efx_nic_t *enp);
216 #define EFX_INTR_NEVQS 32
218 extern __checkReturn efx_rc_t
221 __in unsigned int level);
224 efx_intr_status_line(
226 __out boolean_t *fatalp,
227 __out uint32_t *maskp);
230 efx_intr_status_message(
232 __in unsigned int message,
233 __out boolean_t *fatalp);
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
245 typedef enum efx_link_mode_e {
246 EFX_LINK_UNKNOWN = 0,
259 #define EFX_MAC_ADDR_LEN 6
261 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
263 #define EFX_MAC_MULTICAST_LIST_MAX 256
265 #define EFX_MAC_SDU_MAX 9202
267 #define EFX_MAC_PDU_ADJUSTMENT \
271 + /* bug16011 */ 16) \
273 #define EFX_MAC_PDU(_sdu) \
274 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
277 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
278 * the SDU rounded up slightly.
280 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
282 #define EFX_MAC_PDU_MIN 60
283 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
285 extern __checkReturn efx_rc_t
290 extern __checkReturn efx_rc_t
295 extern __checkReturn efx_rc_t
300 extern __checkReturn efx_rc_t
303 __in boolean_t all_unicst,
304 __in boolean_t mulcst,
305 __in boolean_t all_mulcst,
306 __in boolean_t brdcst);
308 extern __checkReturn efx_rc_t
309 efx_mac_multicast_list_set(
311 __in_ecount(6*count) uint8_t const *addrs,
314 extern __checkReturn efx_rc_t
315 efx_mac_filter_default_rxq_set(
318 __in boolean_t using_rss);
321 efx_mac_filter_default_rxq_clear(
322 __in efx_nic_t *enp);
324 extern __checkReturn efx_rc_t
327 __in boolean_t enabled);
329 extern __checkReturn efx_rc_t
332 __out boolean_t *mac_upp);
334 #define EFX_FCNTL_RESPOND 0x00000001
335 #define EFX_FCNTL_GENERATE 0x00000002
337 extern __checkReturn efx_rc_t
340 __in unsigned int fcntl,
341 __in boolean_t autoneg);
346 __out unsigned int *fcntl_wantedp,
347 __out unsigned int *fcntl_linkp);
352 typedef enum efx_mon_type_e {
364 __in efx_nic_t *enp);
366 #endif /* EFSYS_OPT_NAMES */
368 extern __checkReturn efx_rc_t
370 __in efx_nic_t *enp);
374 __in efx_nic_t *enp);
378 extern __checkReturn efx_rc_t
380 __in efx_nic_t *enp);
382 extern __checkReturn efx_rc_t
384 __in efx_nic_t *enp);
386 extern __checkReturn efx_rc_t
389 __out_opt efx_link_mode_t *link_modep);
393 __in efx_nic_t *enp);
395 typedef enum efx_phy_cap_type_e {
396 EFX_PHY_CAP_INVALID = 0,
403 EFX_PHY_CAP_10000FDX,
407 EFX_PHY_CAP_40000FDX,
409 } efx_phy_cap_type_t;
412 #define EFX_PHY_CAP_CURRENT 0x00000000
413 #define EFX_PHY_CAP_DEFAULT 0x00000001
414 #define EFX_PHY_CAP_PERM 0x00000002
420 __out uint32_t *maskp);
422 extern __checkReturn efx_rc_t
430 __out uint32_t *maskp);
432 extern __checkReturn efx_rc_t
435 __out uint32_t *ouip);
437 typedef enum efx_phy_media_type_e {
438 EFX_PHY_MEDIA_INVALID = 0,
443 EFX_PHY_MEDIA_SFP_PLUS,
444 EFX_PHY_MEDIA_BASE_T,
445 EFX_PHY_MEDIA_QSFP_PLUS,
447 } efx_phy_media_type_t;
449 /* Get the type of medium currently used. If the board has ports for
450 * modules, a module is present, and we recognise the media type of
451 * the module, then this will be the media type of the module.
452 * Otherwise it will be the media type of the port.
455 efx_phy_media_type_get(
457 __out efx_phy_media_type_t *typep);
460 efx_phy_module_get_info(
462 __in uint8_t dev_addr,
465 __out_bcount(len) uint8_t *data);
468 #define EFX_FEATURE_IPV6 0x00000001
469 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
470 #define EFX_FEATURE_LINK_EVENTS 0x00000004
471 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
472 #define EFX_FEATURE_MCDI 0x00000020
473 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
474 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
475 #define EFX_FEATURE_TURBO 0x00000100
476 #define EFX_FEATURE_MCDI_DMA 0x00000200
477 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
478 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
479 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
480 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
481 #define EFX_FEATURE_PACKED_STREAM 0x00004000
483 typedef struct efx_nic_cfg_s {
484 uint32_t enc_board_type;
485 uint32_t enc_phy_type;
487 char enc_phy_name[21];
489 char enc_phy_revision[21];
490 efx_mon_type_t enc_mon_type;
491 unsigned int enc_features;
492 uint8_t enc_mac_addr[6];
493 uint8_t enc_port; /* PHY port number */
494 uint32_t enc_intr_vec_base;
495 uint32_t enc_intr_limit;
496 uint32_t enc_evq_limit;
497 uint32_t enc_txq_limit;
498 uint32_t enc_rxq_limit;
499 uint32_t enc_txq_max_ndescs;
500 uint32_t enc_buftbl_limit;
501 uint32_t enc_piobuf_limit;
502 uint32_t enc_piobuf_size;
503 uint32_t enc_piobuf_min_alloc_size;
504 uint32_t enc_evq_timer_quantum_ns;
505 uint32_t enc_evq_timer_max_us;
506 uint32_t enc_clk_mult;
507 uint32_t enc_rx_prefix_size;
508 uint32_t enc_rx_buf_align_start;
509 uint32_t enc_rx_buf_align_end;
510 boolean_t enc_bug26807_workaround;
511 boolean_t enc_bug35388_workaround;
512 boolean_t enc_bug41750_workaround;
513 boolean_t enc_bug61265_workaround;
514 boolean_t enc_rx_batching_enabled;
515 /* Maximum number of descriptors completed in an rx event. */
516 uint32_t enc_rx_batch_max;
517 /* Number of rx descriptors the hardware requires for a push. */
518 uint32_t enc_rx_push_align;
520 * Maximum number of bytes into the packet the TCP header can start for
521 * the hardware to apply TSO packet edits.
523 uint32_t enc_tx_tso_tcp_header_offset_limit;
524 boolean_t enc_fw_assisted_tso_enabled;
525 boolean_t enc_fw_assisted_tso_v2_enabled;
526 /* Number of TSO contexts on the NIC (FATSOv2) */
527 uint32_t enc_fw_assisted_tso_v2_n_contexts;
528 boolean_t enc_hw_tx_insert_vlan_enabled;
529 /* Number of PFs on the NIC */
530 uint32_t enc_hw_pf_count;
531 /* Datapath firmware vadapter/vport/vswitch support */
532 boolean_t enc_datapath_cap_evb;
533 boolean_t enc_rx_disable_scatter_supported;
534 boolean_t enc_allow_set_mac_with_installed_filters;
535 boolean_t enc_enhanced_set_mac_supported;
536 boolean_t enc_init_evq_v2_supported;
537 boolean_t enc_rx_packed_stream_supported;
538 boolean_t enc_rx_var_packed_stream_supported;
539 boolean_t enc_pm_and_rxdp_counters;
540 boolean_t enc_mac_stats_40g_tx_size_bins;
541 /* External port identifier */
542 uint8_t enc_external_port;
543 uint32_t enc_mcdi_max_payload_length;
544 /* VPD may be per-PF or global */
545 boolean_t enc_vpd_is_global;
546 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
547 uint32_t enc_required_pcie_bandwidth_mbps;
548 uint32_t enc_max_pcie_link_gen;
549 /* Firmware verifies integrity of NVRAM updates */
550 uint32_t enc_fw_verified_nvram_update_required;
553 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
554 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
556 #define EFX_PCI_FUNCTION(_encp) \
557 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
559 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
561 extern const efx_nic_cfg_t *
563 __in efx_nic_t *enp);
565 /* Driver resource limits (minimum required/maximum usable). */
566 typedef struct efx_drv_limits_s {
567 uint32_t edl_min_evq_count;
568 uint32_t edl_max_evq_count;
570 uint32_t edl_min_rxq_count;
571 uint32_t edl_max_rxq_count;
573 uint32_t edl_min_txq_count;
574 uint32_t edl_max_txq_count;
576 /* PIO blocks (sub-allocated from piobuf) */
577 uint32_t edl_min_pio_alloc_size;
578 uint32_t edl_max_pio_alloc_count;
581 extern __checkReturn efx_rc_t
582 efx_nic_set_drv_limits(
583 __inout efx_nic_t *enp,
584 __in efx_drv_limits_t *edlp);
586 typedef enum efx_nic_region_e {
587 EFX_REGION_VI, /* Memory BAR UC mapping */
588 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
591 extern __checkReturn efx_rc_t
592 efx_nic_get_bar_region(
594 __in efx_nic_region_t region,
595 __out uint32_t *offsetp,
596 __out size_t *sizep);
598 extern __checkReturn efx_rc_t
601 __out uint32_t *evq_countp,
602 __out uint32_t *rxq_countp,
603 __out uint32_t *txq_countp);
608 extern __checkReturn efx_rc_t
609 efx_sram_buf_tbl_set(
612 __in efsys_mem_t *esmp,
616 efx_sram_buf_tbl_clear(
621 #define EFX_BUF_TBL_SIZE 0x20000
623 #define EFX_BUF_SIZE 4096
627 typedef struct efx_evq_s efx_evq_t;
629 extern __checkReturn efx_rc_t
631 __in efx_nic_t *enp);
635 __in efx_nic_t *enp);
637 #define EFX_EVQ_MAXNEVS 32768
638 #define EFX_EVQ_MINNEVS 512
640 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
641 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
643 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
644 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
645 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
646 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
648 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
649 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
650 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
652 extern __checkReturn efx_rc_t
655 __in unsigned int index,
656 __in efsys_mem_t *esmp,
661 __deref_out efx_evq_t **eepp);
668 typedef __checkReturn boolean_t
669 (*efx_initialized_ev_t)(
672 #define EFX_PKT_UNICAST 0x0004
673 #define EFX_PKT_START 0x0008
675 #define EFX_PKT_VLAN_TAGGED 0x0010
676 #define EFX_CKSUM_TCPUDP 0x0020
677 #define EFX_CKSUM_IPV4 0x0040
678 #define EFX_PKT_CONT 0x0080
680 #define EFX_CHECK_VLAN 0x0100
681 #define EFX_PKT_TCP 0x0200
682 #define EFX_PKT_UDP 0x0400
683 #define EFX_PKT_IPV4 0x0800
685 #define EFX_PKT_IPV6 0x1000
686 #define EFX_PKT_PREFIX_LEN 0x2000
687 #define EFX_ADDR_MISMATCH 0x4000
688 #define EFX_DISCARD 0x8000
691 * The following flags are used only for packed stream
692 * mode. The values for the flags are reused to fit into 16 bit,
693 * since EFX_PKT_START and EFX_PKT_CONT are never used in
696 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
697 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
700 #define EFX_EV_RX_NLABELS 32
701 #define EFX_EV_TX_NLABELS 32
703 typedef __checkReturn boolean_t
709 __in uint16_t flags);
711 typedef __checkReturn boolean_t
717 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
718 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
719 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
720 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
721 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
722 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
723 #define EFX_EXCEPTION_RX_ERROR 0x00000007
724 #define EFX_EXCEPTION_TX_ERROR 0x00000008
725 #define EFX_EXCEPTION_EV_ERROR 0x00000009
727 typedef __checkReturn boolean_t
728 (*efx_exception_ev_t)(
733 typedef __checkReturn boolean_t
734 (*efx_rxq_flush_done_ev_t)(
736 __in uint32_t rxq_index);
738 typedef __checkReturn boolean_t
739 (*efx_rxq_flush_failed_ev_t)(
741 __in uint32_t rxq_index);
743 typedef __checkReturn boolean_t
744 (*efx_txq_flush_done_ev_t)(
746 __in uint32_t txq_index);
748 typedef __checkReturn boolean_t
749 (*efx_software_ev_t)(
751 __in uint16_t magic);
753 typedef __checkReturn boolean_t
758 #define EFX_SRAM_CLEAR 0
759 #define EFX_SRAM_UPDATE 1
760 #define EFX_SRAM_ILLEGAL_CLEAR 2
762 typedef __checkReturn boolean_t
765 __in uint32_t label);
767 typedef __checkReturn boolean_t
770 __in uint32_t label);
772 typedef __checkReturn boolean_t
773 (*efx_link_change_ev_t)(
775 __in efx_link_mode_t link_mode);
777 typedef struct efx_ev_callbacks_s {
778 efx_initialized_ev_t eec_initialized;
781 efx_exception_ev_t eec_exception;
782 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
783 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
784 efx_txq_flush_done_ev_t eec_txq_flush_done;
785 efx_software_ev_t eec_software;
786 efx_sram_ev_t eec_sram;
787 efx_wake_up_ev_t eec_wake_up;
788 efx_timer_ev_t eec_timer;
789 efx_link_change_ev_t eec_link_change;
790 } efx_ev_callbacks_t;
792 extern __checkReturn boolean_t
795 __in unsigned int count);
800 __inout unsigned int *countp,
801 __in const efx_ev_callbacks_t *eecp,
804 extern __checkReturn efx_rc_t
805 efx_ev_usecs_to_ticks(
807 __in unsigned int usecs,
808 __out unsigned int *ticksp);
810 extern __checkReturn efx_rc_t
813 __in unsigned int us);
815 extern __checkReturn efx_rc_t
818 __in unsigned int count);
822 __in efx_evq_t *eep);
826 extern __checkReturn efx_rc_t
828 __inout efx_nic_t *enp);
832 __in efx_nic_t *enp);
834 extern __checkReturn efx_rc_t
835 efx_pseudo_hdr_pkt_length_get(
837 __in uint8_t *buffer,
838 __out uint16_t *pkt_lengthp);
840 #define EFX_RXQ_MAXNDESCS 4096
841 #define EFX_RXQ_MINNDESCS 512
843 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
844 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
845 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
846 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
848 typedef enum efx_rxq_type_e {
849 EFX_RXQ_TYPE_DEFAULT,
850 EFX_RXQ_TYPE_SCATTER,
851 EFX_RXQ_TYPE_PACKED_STREAM_1M,
852 EFX_RXQ_TYPE_PACKED_STREAM_512K,
853 EFX_RXQ_TYPE_PACKED_STREAM_256K,
854 EFX_RXQ_TYPE_PACKED_STREAM_128K,
855 EFX_RXQ_TYPE_PACKED_STREAM_64K,
859 extern __checkReturn efx_rc_t
862 __in unsigned int index,
863 __in unsigned int label,
864 __in efx_rxq_type_t type,
865 __in efsys_mem_t *esmp,
869 __deref_out efx_rxq_t **erpp);
871 typedef struct efx_buffer_s {
872 efsys_dma_addr_t eb_addr;
877 typedef struct efx_desc_s {
884 __in_ecount(n) efsys_dma_addr_t *addrp,
887 __in unsigned int completed,
888 __in unsigned int added);
893 __in unsigned int added,
894 __inout unsigned int *pushedp);
896 extern __checkReturn efx_rc_t
898 __in efx_rxq_t *erp);
902 __in efx_rxq_t *erp);
906 __in efx_rxq_t *erp);
910 typedef struct efx_txq_s efx_txq_t;
912 extern __checkReturn efx_rc_t
914 __in efx_nic_t *enp);
918 __in efx_nic_t *enp);
920 #define EFX_TXQ_MINNDESCS 512
922 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
923 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
924 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
925 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
927 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
929 #define EFX_TXQ_CKSUM_IPV4 0x0001
930 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
931 #define EFX_TXQ_FATSOV2 0x0004
933 extern __checkReturn efx_rc_t
936 __in unsigned int index,
937 __in unsigned int label,
938 __in efsys_mem_t *esmp,
943 __deref_out efx_txq_t **etpp,
944 __out unsigned int *addedp);
946 extern __checkReturn efx_rc_t
949 __in_ecount(n) efx_buffer_t *eb,
951 __in unsigned int completed,
952 __inout unsigned int *addedp);
954 extern __checkReturn efx_rc_t
957 __in unsigned int ns);
962 __in unsigned int added,
963 __in unsigned int pushed);
965 extern __checkReturn efx_rc_t
967 __in efx_txq_t *etp);
971 __in efx_txq_t *etp);
973 extern __checkReturn efx_rc_t
975 __in efx_txq_t *etp);
979 __in efx_txq_t *etp);
981 extern __checkReturn efx_rc_t
984 __in_ecount(buf_length) uint8_t *buffer,
985 __in size_t buf_length,
986 __in size_t pio_buf_offset);
988 extern __checkReturn efx_rc_t
991 __in size_t pkt_length,
992 __in unsigned int completed,
993 __inout unsigned int *addedp);
995 extern __checkReturn efx_rc_t
998 __in_ecount(n) efx_desc_t *ed,
1000 __in unsigned int completed,
1001 __inout unsigned int *addedp);
1004 efx_tx_qdesc_dma_create(
1005 __in efx_txq_t *etp,
1006 __in efsys_dma_addr_t addr,
1009 __out efx_desc_t *edp);
1012 efx_tx_qdesc_tso_create(
1013 __in efx_txq_t *etp,
1014 __in uint16_t ipv4_id,
1015 __in uint32_t tcp_seq,
1016 __in uint8_t tcp_flags,
1017 __out efx_desc_t *edp);
1019 /* Number of FATSOv2 option descriptors */
1020 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1022 /* Maximum number of DMA segments per TSO packet (not superframe) */
1023 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1026 efx_tx_qdesc_tso2_create(
1027 __in efx_txq_t *etp,
1028 __in uint16_t ipv4_id,
1029 __in uint32_t tcp_seq,
1030 __in uint16_t tcp_mss,
1031 __out_ecount(count) efx_desc_t *edp,
1035 efx_tx_qdesc_vlantci_create(
1036 __in efx_txq_t *etp,
1038 __out efx_desc_t *edp);
1042 __in efx_txq_t *etp);
1047 #if EFSYS_OPT_FILTER
1049 #define EFX_ETHER_TYPE_IPV4 0x0800
1050 #define EFX_ETHER_TYPE_IPV6 0x86DD
1052 #define EFX_IPPROTO_TCP 6
1053 #define EFX_IPPROTO_UDP 17
1055 /* Use RSS to spread across multiple queues */
1056 #define EFX_FILTER_FLAG_RX_RSS 0x01
1057 /* Enable RX scatter */
1058 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1060 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1061 * May only be set by the filter implementation for each type.
1062 * A removal request will restore the automatic filter in its place.
1064 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1065 /* Filter is for RX */
1066 #define EFX_FILTER_FLAG_RX 0x08
1067 /* Filter is for TX */
1068 #define EFX_FILTER_FLAG_TX 0x10
1070 typedef unsigned int efx_filter_flags_t;
1072 typedef enum efx_filter_match_flags_e {
1073 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1075 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1077 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1078 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1079 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1080 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1081 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1082 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1083 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1084 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1086 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1087 * I/G bit. Used for RX default
1088 * unicast and multicast/
1089 * broadcast filters. */
1090 } efx_filter_match_flags_t;
1092 typedef enum efx_filter_priority_s {
1093 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1094 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1095 * address list or hardware
1096 * requirements. This may only be used
1097 * by the filter implementation for
1099 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1100 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1101 * client (e.g. SR-IOV, HyperV VMQ etc.)
1103 } efx_filter_priority_t;
1106 * FIXME: All these fields are assumed to be in little-endian byte order.
1107 * It may be better for some to be big-endian. See bug42804.
1110 typedef struct efx_filter_spec_s {
1111 uint32_t efs_match_flags:12;
1112 uint32_t efs_priority:2;
1113 uint32_t efs_flags:6;
1114 uint32_t efs_dmaq_id:12;
1115 uint32_t efs_rss_context;
1116 uint16_t efs_outer_vid;
1117 uint16_t efs_inner_vid;
1118 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1119 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1120 uint16_t efs_ether_type;
1121 uint8_t efs_ip_proto;
1122 uint16_t efs_loc_port;
1123 uint16_t efs_rem_port;
1124 efx_oword_t efs_rem_host;
1125 efx_oword_t efs_loc_host;
1126 } efx_filter_spec_t;
1129 /* Default values for use in filter specifications */
1130 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1131 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1132 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1134 extern __checkReturn efx_rc_t
1136 __in efx_nic_t *enp);
1140 __in efx_nic_t *enp);
1142 extern __checkReturn efx_rc_t
1144 __in efx_nic_t *enp,
1145 __inout efx_filter_spec_t *spec);
1147 extern __checkReturn efx_rc_t
1149 __in efx_nic_t *enp,
1150 __inout efx_filter_spec_t *spec);
1152 extern __checkReturn efx_rc_t
1154 __in efx_nic_t *enp);
1156 extern __checkReturn efx_rc_t
1157 efx_filter_supported_filters(
1158 __in efx_nic_t *enp,
1159 __out uint32_t *list,
1160 __out size_t *length);
1163 efx_filter_spec_init_rx(
1164 __out efx_filter_spec_t *spec,
1165 __in efx_filter_priority_t priority,
1166 __in efx_filter_flags_t flags,
1167 __in efx_rxq_t *erp);
1170 efx_filter_spec_init_tx(
1171 __out efx_filter_spec_t *spec,
1172 __in efx_txq_t *etp);
1174 extern __checkReturn efx_rc_t
1175 efx_filter_spec_set_ipv4_local(
1176 __inout efx_filter_spec_t *spec,
1179 __in uint16_t port);
1181 extern __checkReturn efx_rc_t
1182 efx_filter_spec_set_ipv4_full(
1183 __inout efx_filter_spec_t *spec,
1185 __in uint32_t lhost,
1186 __in uint16_t lport,
1187 __in uint32_t rhost,
1188 __in uint16_t rport);
1190 extern __checkReturn efx_rc_t
1191 efx_filter_spec_set_eth_local(
1192 __inout efx_filter_spec_t *spec,
1194 __in const uint8_t *addr);
1196 extern __checkReturn efx_rc_t
1197 efx_filter_spec_set_uc_def(
1198 __inout efx_filter_spec_t *spec);
1200 extern __checkReturn efx_rc_t
1201 efx_filter_spec_set_mc_def(
1202 __inout efx_filter_spec_t *spec);
1204 #endif /* EFSYS_OPT_FILTER */
1208 extern __checkReturn uint32_t
1210 __in_ecount(count) uint32_t const *input,
1212 __in uint32_t init);
1214 extern __checkReturn uint32_t
1216 __in_ecount(length) uint8_t const *input,
1218 __in uint32_t init);
1226 #endif /* _SYS_EFX_H */