1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 extern __checkReturn efx_rc_t
134 __in efx_nic_t *enp);
136 extern __checkReturn efx_rc_t
138 __in efx_nic_t *enp);
140 extern __checkReturn efx_rc_t
142 __in efx_nic_t *enp);
146 extern __checkReturn efx_rc_t
147 efx_nic_register_test(
148 __in efx_nic_t *enp);
150 #endif /* EFSYS_OPT_DIAG */
154 __in efx_nic_t *enp);
158 __in efx_nic_t *enp);
162 __in efx_nic_t *enp);
164 #define EFX_PCIE_LINK_SPEED_GEN1 1
165 #define EFX_PCIE_LINK_SPEED_GEN2 2
166 #define EFX_PCIE_LINK_SPEED_GEN3 3
168 typedef enum efx_pcie_link_performance_e {
169 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
170 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
171 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
172 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
173 } efx_pcie_link_performance_t;
175 extern __checkReturn efx_rc_t
176 efx_nic_calculate_pcie_link_bandwidth(
177 __in uint32_t pcie_link_width,
178 __in uint32_t pcie_link_gen,
179 __out uint32_t *bandwidth_mbpsp);
181 extern __checkReturn efx_rc_t
182 efx_nic_check_pcie_link_speed(
184 __in uint32_t pcie_link_width,
185 __in uint32_t pcie_link_gen,
186 __out efx_pcie_link_performance_t *resultp);
190 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
191 /* Huntington and Medford require MCDIv2 commands */
192 #define WITH_MCDI_V2 1
195 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
197 typedef enum efx_mcdi_exception_e {
198 EFX_MCDI_EXCEPTION_MC_REBOOT,
199 EFX_MCDI_EXCEPTION_MC_BADASSERT,
200 } efx_mcdi_exception_t;
202 #if EFSYS_OPT_MCDI_LOGGING
203 typedef enum efx_log_msg_e {
205 EFX_LOG_MCDI_REQUEST,
206 EFX_LOG_MCDI_RESPONSE,
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
210 typedef struct efx_mcdi_transport_s {
212 efsys_mem_t *emt_dma_mem;
213 void (*emt_execute)(void *, efx_mcdi_req_t *);
214 void (*emt_ev_cpl)(void *);
215 void (*emt_exception)(void *, efx_mcdi_exception_t);
216 #if EFSYS_OPT_MCDI_LOGGING
217 void (*emt_logger)(void *, efx_log_msg_t,
218 void *, size_t, void *, size_t);
219 #endif /* EFSYS_OPT_MCDI_LOGGING */
220 #if EFSYS_OPT_MCDI_PROXY_AUTH
221 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
222 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
223 } efx_mcdi_transport_t;
225 extern __checkReturn efx_rc_t
228 __in const efx_mcdi_transport_t *mtp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
236 __in efx_nic_t *enp);
239 efx_mcdi_get_timeout(
241 __in efx_mcdi_req_t *emrp,
242 __out uint32_t *usec_timeoutp);
245 efx_mcdi_request_start(
247 __in efx_mcdi_req_t *emrp,
248 __in boolean_t ev_cpl);
250 extern __checkReturn boolean_t
251 efx_mcdi_request_poll(
252 __in efx_nic_t *enp);
254 extern __checkReturn boolean_t
255 efx_mcdi_request_abort(
256 __in efx_nic_t *enp);
260 __in efx_nic_t *enp);
262 #endif /* EFSYS_OPT_MCDI */
266 #define EFX_NINTR_SIENA 1024
268 typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
275 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
277 extern __checkReturn efx_rc_t
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
285 __in efx_nic_t *enp);
289 __in efx_nic_t *enp);
292 efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
295 #define EFX_INTR_NEVQS 32
297 extern __checkReturn efx_rc_t
300 __in unsigned int level);
303 efx_intr_status_line(
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
309 efx_intr_status_message(
311 __in unsigned int message,
312 __out boolean_t *fatalp);
316 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
324 #if EFSYS_OPT_MAC_STATS
326 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
327 typedef enum efx_mac_stat_e {
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
412 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
414 #endif /* EFSYS_OPT_MAC_STATS */
416 typedef enum efx_link_mode_e {
417 EFX_LINK_UNKNOWN = 0,
433 #define EFX_MAC_ADDR_LEN 6
435 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
437 #define EFX_MAC_MULTICAST_LIST_MAX 256
439 #define EFX_MAC_SDU_MAX 9202
441 #define EFX_MAC_PDU_ADJUSTMENT \
445 + /* bug16011 */ 16) \
447 #define EFX_MAC_PDU(_sdu) \
448 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
451 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
452 * the SDU rounded up slightly.
454 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
456 #define EFX_MAC_PDU_MIN 60
457 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
459 extern __checkReturn efx_rc_t
464 extern __checkReturn efx_rc_t
469 extern __checkReturn efx_rc_t
474 extern __checkReturn efx_rc_t
477 __in boolean_t all_unicst,
478 __in boolean_t mulcst,
479 __in boolean_t all_mulcst,
480 __in boolean_t brdcst);
482 extern __checkReturn efx_rc_t
483 efx_mac_multicast_list_set(
485 __in_ecount(6*count) uint8_t const *addrs,
488 extern __checkReturn efx_rc_t
489 efx_mac_filter_default_rxq_set(
492 __in boolean_t using_rss);
495 efx_mac_filter_default_rxq_clear(
496 __in efx_nic_t *enp);
498 extern __checkReturn efx_rc_t
501 __in boolean_t enabled);
503 extern __checkReturn efx_rc_t
506 __out boolean_t *mac_upp);
508 #define EFX_FCNTL_RESPOND 0x00000001
509 #define EFX_FCNTL_GENERATE 0x00000002
511 extern __checkReturn efx_rc_t
514 __in unsigned int fcntl,
515 __in boolean_t autoneg);
520 __out unsigned int *fcntl_wantedp,
521 __out unsigned int *fcntl_linkp);
524 #if EFSYS_OPT_MAC_STATS
528 extern __checkReturn const char *
531 __in unsigned int id);
533 #endif /* EFSYS_OPT_NAMES */
535 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
537 #define EFX_MAC_STATS_MASK_NPAGES \
538 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
539 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
542 * Get mask of MAC statistics supported by the hardware.
544 * If mask_size is insufficient to return the mask, EINVAL error is
545 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
546 * (which is sizeof (uint32_t)) is sufficient.
548 extern __checkReturn efx_rc_t
549 efx_mac_stats_get_mask(
551 __out_bcount(mask_size) uint32_t *maskp,
552 __in size_t mask_size);
554 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
555 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
556 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
558 #define EFX_MAC_STATS_SIZE 0x400
560 extern __checkReturn efx_rc_t
562 __in efx_nic_t *enp);
565 * Upload mac statistics supported by the hardware into the given buffer.
567 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
570 * The hardware will only DMA statistics that it understands (of course).
571 * Drivers should not make any assumptions about which statistics are
572 * supported, especially when the statistics are generated by firmware.
574 * Thus, drivers should zero this buffer before use, so that not-understood
575 * statistics read back as zero.
577 extern __checkReturn efx_rc_t
578 efx_mac_stats_upload(
580 __in efsys_mem_t *esmp);
582 extern __checkReturn efx_rc_t
583 efx_mac_stats_periodic(
585 __in efsys_mem_t *esmp,
586 __in uint16_t period_ms,
587 __in boolean_t events);
589 extern __checkReturn efx_rc_t
590 efx_mac_stats_update(
592 __in efsys_mem_t *esmp,
593 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
594 __inout_opt uint32_t *generationp);
596 #endif /* EFSYS_OPT_MAC_STATS */
600 typedef enum efx_mon_type_e {
612 __in efx_nic_t *enp);
614 #endif /* EFSYS_OPT_NAMES */
616 extern __checkReturn efx_rc_t
618 __in efx_nic_t *enp);
620 #if EFSYS_OPT_MON_STATS
622 #define EFX_MON_STATS_PAGE_SIZE 0x100
623 #define EFX_MON_MASK_ELEMENT_SIZE 32
625 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock fcc1b6748432e1ac */
626 typedef enum efx_mon_stat_e {
633 EFX_MON_STAT_EXT_TEMP,
634 EFX_MON_STAT_INT_TEMP,
637 EFX_MON_STAT_INT_COOLING,
638 EFX_MON_STAT_EXT_COOLING,
646 EFX_MON_STAT_AOE_TEMP,
647 EFX_MON_STAT_PSU_AOE_TEMP,
648 EFX_MON_STAT_PSU_TEMP,
654 EFX_MON_STAT_VAOE_IN,
656 EFX_MON_STAT_IAOE_IN,
657 EFX_MON_STAT_NIC_POWER,
661 EFX_MON_STAT_0_9V_ADC,
662 EFX_MON_STAT_INT_TEMP2,
663 EFX_MON_STAT_VREG_TEMP,
664 EFX_MON_STAT_VREG_0_9V_TEMP,
665 EFX_MON_STAT_VREG_1_2V_TEMP,
666 EFX_MON_STAT_INT_VPTAT,
667 EFX_MON_STAT_INT_ADC_TEMP,
668 EFX_MON_STAT_EXT_VPTAT,
669 EFX_MON_STAT_EXT_ADC_TEMP,
670 EFX_MON_STAT_AMBIENT_TEMP,
671 EFX_MON_STAT_AIRFLOW,
672 EFX_MON_STAT_VDD08D_VSS08D_CSR,
673 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
674 EFX_MON_STAT_HOTPOINT_TEMP,
675 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
676 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
677 EFX_MON_STAT_MUM_VCC,
680 EFX_MON_STAT_0V9_A_TEMP,
683 EFX_MON_STAT_0V9_B_TEMP,
684 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
685 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
686 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
687 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
688 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
689 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
690 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
691 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
692 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
693 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
694 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
695 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
696 EFX_MON_STAT_SODIMM_VOUT,
697 EFX_MON_STAT_SODIMM_0_TEMP,
698 EFX_MON_STAT_SODIMM_1_TEMP,
699 EFX_MON_STAT_PHY0_VCC,
700 EFX_MON_STAT_PHY1_VCC,
701 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
702 EFX_MON_STAT_BOARD_FRONT_TEMP,
703 EFX_MON_STAT_BOARD_BACK_TEMP,
711 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
713 typedef enum efx_mon_stat_state_e {
714 EFX_MON_STAT_STATE_OK = 0,
715 EFX_MON_STAT_STATE_WARNING = 1,
716 EFX_MON_STAT_STATE_FATAL = 2,
717 EFX_MON_STAT_STATE_BROKEN = 3,
718 EFX_MON_STAT_STATE_NO_READING = 4,
719 } efx_mon_stat_state_t;
721 typedef struct efx_mon_stat_value_s {
724 } efx_mon_stat_value_t;
731 __in efx_mon_stat_t id);
733 #endif /* EFSYS_OPT_NAMES */
735 extern __checkReturn efx_rc_t
736 efx_mon_stats_update(
738 __in efsys_mem_t *esmp,
739 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
741 #endif /* EFSYS_OPT_MON_STATS */
745 __in efx_nic_t *enp);
749 extern __checkReturn efx_rc_t
751 __in efx_nic_t *enp);
753 #if EFSYS_OPT_PHY_LED_CONTROL
755 typedef enum efx_phy_led_mode_e {
756 EFX_PHY_LED_DEFAULT = 0,
761 } efx_phy_led_mode_t;
763 extern __checkReturn efx_rc_t
766 __in efx_phy_led_mode_t mode);
768 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
770 extern __checkReturn efx_rc_t
772 __in efx_nic_t *enp);
774 #if EFSYS_OPT_LOOPBACK
776 typedef enum efx_loopback_type_e {
777 EFX_LOOPBACK_OFF = 0,
778 EFX_LOOPBACK_DATA = 1,
779 EFX_LOOPBACK_GMAC = 2,
780 EFX_LOOPBACK_XGMII = 3,
781 EFX_LOOPBACK_XGXS = 4,
782 EFX_LOOPBACK_XAUI = 5,
783 EFX_LOOPBACK_GMII = 6,
784 EFX_LOOPBACK_SGMII = 7,
785 EFX_LOOPBACK_XGBR = 8,
786 EFX_LOOPBACK_XFI = 9,
787 EFX_LOOPBACK_XAUI_FAR = 10,
788 EFX_LOOPBACK_GMII_FAR = 11,
789 EFX_LOOPBACK_SGMII_FAR = 12,
790 EFX_LOOPBACK_XFI_FAR = 13,
791 EFX_LOOPBACK_GPHY = 14,
792 EFX_LOOPBACK_PHY_XS = 15,
793 EFX_LOOPBACK_PCS = 16,
794 EFX_LOOPBACK_PMA_PMD = 17,
795 EFX_LOOPBACK_XPORT = 18,
796 EFX_LOOPBACK_XGMII_WS = 19,
797 EFX_LOOPBACK_XAUI_WS = 20,
798 EFX_LOOPBACK_XAUI_WS_FAR = 21,
799 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
800 EFX_LOOPBACK_GMII_WS = 23,
801 EFX_LOOPBACK_XFI_WS = 24,
802 EFX_LOOPBACK_XFI_WS_FAR = 25,
803 EFX_LOOPBACK_PHYXS_WS = 26,
804 EFX_LOOPBACK_PMA_INT = 27,
805 EFX_LOOPBACK_SD_NEAR = 28,
806 EFX_LOOPBACK_SD_FAR = 29,
807 EFX_LOOPBACK_PMA_INT_WS = 30,
808 EFX_LOOPBACK_SD_FEP2_WS = 31,
809 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
810 EFX_LOOPBACK_SD_FEP_WS = 33,
811 EFX_LOOPBACK_SD_FES_WS = 34,
813 } efx_loopback_type_t;
815 typedef enum efx_loopback_kind_e {
816 EFX_LOOPBACK_KIND_OFF = 0,
817 EFX_LOOPBACK_KIND_ALL,
818 EFX_LOOPBACK_KIND_MAC,
819 EFX_LOOPBACK_KIND_PHY,
821 } efx_loopback_kind_t;
825 __in efx_loopback_kind_t loopback_kind,
826 __out efx_qword_t *maskp);
828 extern __checkReturn efx_rc_t
829 efx_port_loopback_set(
831 __in efx_link_mode_t link_mode,
832 __in efx_loopback_type_t type);
836 extern __checkReturn const char *
837 efx_loopback_type_name(
839 __in efx_loopback_type_t type);
841 #endif /* EFSYS_OPT_NAMES */
843 #endif /* EFSYS_OPT_LOOPBACK */
845 extern __checkReturn efx_rc_t
848 __out_opt efx_link_mode_t *link_modep);
852 __in efx_nic_t *enp);
854 typedef enum efx_phy_cap_type_e {
855 EFX_PHY_CAP_INVALID = 0,
862 EFX_PHY_CAP_10000FDX,
866 EFX_PHY_CAP_40000FDX,
868 EFX_PHY_CAP_100000FDX,
869 EFX_PHY_CAP_25000FDX,
870 EFX_PHY_CAP_50000FDX,
872 } efx_phy_cap_type_t;
875 #define EFX_PHY_CAP_CURRENT 0x00000000
876 #define EFX_PHY_CAP_DEFAULT 0x00000001
877 #define EFX_PHY_CAP_PERM 0x00000002
883 __out uint32_t *maskp);
885 extern __checkReturn efx_rc_t
893 __out uint32_t *maskp);
895 extern __checkReturn efx_rc_t
898 __out uint32_t *ouip);
900 typedef enum efx_phy_media_type_e {
901 EFX_PHY_MEDIA_INVALID = 0,
906 EFX_PHY_MEDIA_SFP_PLUS,
907 EFX_PHY_MEDIA_BASE_T,
908 EFX_PHY_MEDIA_QSFP_PLUS,
910 } efx_phy_media_type_t;
913 * Get the type of medium currently used. If the board has ports for
914 * modules, a module is present, and we recognise the media type of
915 * the module, then this will be the media type of the module.
916 * Otherwise it will be the media type of the port.
919 efx_phy_media_type_get(
921 __out efx_phy_media_type_t *typep);
923 extern __checkReturn efx_rc_t
924 efx_phy_module_get_info(
926 __in uint8_t dev_addr,
929 __out_bcount(len) uint8_t *data);
931 #if EFSYS_OPT_PHY_STATS
933 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
934 typedef enum efx_phy_stat_e {
936 EFX_PHY_STAT_PMA_PMD_LINK_UP,
937 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
938 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
939 EFX_PHY_STAT_PMA_PMD_REV_A,
940 EFX_PHY_STAT_PMA_PMD_REV_B,
941 EFX_PHY_STAT_PMA_PMD_REV_C,
942 EFX_PHY_STAT_PMA_PMD_REV_D,
943 EFX_PHY_STAT_PCS_LINK_UP,
944 EFX_PHY_STAT_PCS_RX_FAULT,
945 EFX_PHY_STAT_PCS_TX_FAULT,
946 EFX_PHY_STAT_PCS_BER,
947 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
948 EFX_PHY_STAT_PHY_XS_LINK_UP,
949 EFX_PHY_STAT_PHY_XS_RX_FAULT,
950 EFX_PHY_STAT_PHY_XS_TX_FAULT,
951 EFX_PHY_STAT_PHY_XS_ALIGN,
952 EFX_PHY_STAT_PHY_XS_SYNC_A,
953 EFX_PHY_STAT_PHY_XS_SYNC_B,
954 EFX_PHY_STAT_PHY_XS_SYNC_C,
955 EFX_PHY_STAT_PHY_XS_SYNC_D,
956 EFX_PHY_STAT_AN_LINK_UP,
957 EFX_PHY_STAT_AN_MASTER,
958 EFX_PHY_STAT_AN_LOCAL_RX_OK,
959 EFX_PHY_STAT_AN_REMOTE_RX_OK,
960 EFX_PHY_STAT_CL22EXT_LINK_UP,
965 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
966 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
967 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
968 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
969 EFX_PHY_STAT_AN_COMPLETE,
970 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
971 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
972 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
973 EFX_PHY_STAT_PCS_FW_VERSION_0,
974 EFX_PHY_STAT_PCS_FW_VERSION_1,
975 EFX_PHY_STAT_PCS_FW_VERSION_2,
976 EFX_PHY_STAT_PCS_FW_VERSION_3,
977 EFX_PHY_STAT_PCS_FW_BUILD_YY,
978 EFX_PHY_STAT_PCS_FW_BUILD_MM,
979 EFX_PHY_STAT_PCS_FW_BUILD_DD,
980 EFX_PHY_STAT_PCS_OP_MODE,
984 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
991 __in efx_phy_stat_t stat);
993 #endif /* EFSYS_OPT_NAMES */
995 #define EFX_PHY_STATS_SIZE 0x100
997 extern __checkReturn efx_rc_t
998 efx_phy_stats_update(
1000 __in efsys_mem_t *esmp,
1001 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1003 #endif /* EFSYS_OPT_PHY_STATS */
1008 typedef enum efx_bist_type_e {
1009 EFX_BIST_TYPE_UNKNOWN,
1010 EFX_BIST_TYPE_PHY_NORMAL,
1011 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1012 EFX_BIST_TYPE_PHY_CABLE_LONG,
1013 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1014 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1015 EFX_BIST_TYPE_REG, /* Test the register memories */
1016 EFX_BIST_TYPE_NTYPES,
1019 typedef enum efx_bist_result_e {
1020 EFX_BIST_RESULT_UNKNOWN,
1021 EFX_BIST_RESULT_RUNNING,
1022 EFX_BIST_RESULT_PASSED,
1023 EFX_BIST_RESULT_FAILED,
1024 } efx_bist_result_t;
1026 typedef enum efx_phy_cable_status_e {
1027 EFX_PHY_CABLE_STATUS_OK,
1028 EFX_PHY_CABLE_STATUS_INVALID,
1029 EFX_PHY_CABLE_STATUS_OPEN,
1030 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1031 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1032 EFX_PHY_CABLE_STATUS_BUSY,
1033 } efx_phy_cable_status_t;
1035 typedef enum efx_bist_value_e {
1036 EFX_BIST_PHY_CABLE_LENGTH_A,
1037 EFX_BIST_PHY_CABLE_LENGTH_B,
1038 EFX_BIST_PHY_CABLE_LENGTH_C,
1039 EFX_BIST_PHY_CABLE_LENGTH_D,
1040 EFX_BIST_PHY_CABLE_STATUS_A,
1041 EFX_BIST_PHY_CABLE_STATUS_B,
1042 EFX_BIST_PHY_CABLE_STATUS_C,
1043 EFX_BIST_PHY_CABLE_STATUS_D,
1044 EFX_BIST_FAULT_CODE,
1046 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1052 EFX_BIST_MEM_EXPECT,
1053 EFX_BIST_MEM_ACTUAL,
1055 EFX_BIST_MEM_ECC_PARITY,
1056 EFX_BIST_MEM_ECC_FATAL,
1060 extern __checkReturn efx_rc_t
1061 efx_bist_enable_offline(
1062 __in efx_nic_t *enp);
1064 extern __checkReturn efx_rc_t
1066 __in efx_nic_t *enp,
1067 __in efx_bist_type_t type);
1069 extern __checkReturn efx_rc_t
1071 __in efx_nic_t *enp,
1072 __in efx_bist_type_t type,
1073 __out efx_bist_result_t *resultp,
1074 __out_opt uint32_t *value_maskp,
1075 __out_ecount_opt(count) unsigned long *valuesp,
1080 __in efx_nic_t *enp,
1081 __in efx_bist_type_t type);
1083 #endif /* EFSYS_OPT_BIST */
1085 #define EFX_FEATURE_IPV6 0x00000001
1086 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1087 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1088 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1089 #define EFX_FEATURE_MCDI 0x00000020
1090 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1091 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1092 #define EFX_FEATURE_TURBO 0x00000100
1093 #define EFX_FEATURE_MCDI_DMA 0x00000200
1094 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1095 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1096 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1097 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1098 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1100 typedef enum efx_tunnel_protocol_e {
1101 EFX_TUNNEL_PROTOCOL_NONE = 0,
1102 EFX_TUNNEL_PROTOCOL_VXLAN,
1103 EFX_TUNNEL_PROTOCOL_GENEVE,
1104 EFX_TUNNEL_PROTOCOL_NVGRE,
1106 } efx_tunnel_protocol_t;
1108 typedef enum efx_vi_window_shift_e {
1109 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1110 EFX_VI_WINDOW_SHIFT_8K = 13,
1111 EFX_VI_WINDOW_SHIFT_16K = 14,
1112 EFX_VI_WINDOW_SHIFT_64K = 16,
1113 } efx_vi_window_shift_t;
1115 typedef struct efx_nic_cfg_s {
1116 uint32_t enc_board_type;
1117 uint32_t enc_phy_type;
1119 char enc_phy_name[21];
1121 char enc_phy_revision[21];
1122 efx_mon_type_t enc_mon_type;
1123 #if EFSYS_OPT_MON_STATS
1124 uint32_t enc_mon_stat_dma_buf_size;
1125 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1127 unsigned int enc_features;
1128 efx_vi_window_shift_t enc_vi_window_shift;
1129 uint8_t enc_mac_addr[6];
1130 uint8_t enc_port; /* PHY port number */
1131 uint32_t enc_intr_vec_base;
1132 uint32_t enc_intr_limit;
1133 uint32_t enc_evq_limit;
1134 uint32_t enc_txq_limit;
1135 uint32_t enc_rxq_limit;
1136 uint32_t enc_txq_max_ndescs;
1137 uint32_t enc_buftbl_limit;
1138 uint32_t enc_piobuf_limit;
1139 uint32_t enc_piobuf_size;
1140 uint32_t enc_piobuf_min_alloc_size;
1141 uint32_t enc_evq_timer_quantum_ns;
1142 uint32_t enc_evq_timer_max_us;
1143 uint32_t enc_clk_mult;
1144 uint32_t enc_rx_prefix_size;
1145 uint32_t enc_rx_buf_align_start;
1146 uint32_t enc_rx_buf_align_end;
1147 uint32_t enc_rx_scale_max_exclusive_contexts;
1148 #if EFSYS_OPT_LOOPBACK
1149 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1150 #endif /* EFSYS_OPT_LOOPBACK */
1151 #if EFSYS_OPT_PHY_FLAGS
1152 uint32_t enc_phy_flags_mask;
1153 #endif /* EFSYS_OPT_PHY_FLAGS */
1154 #if EFSYS_OPT_PHY_LED_CONTROL
1155 uint32_t enc_led_mask;
1156 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1157 #if EFSYS_OPT_PHY_STATS
1158 uint64_t enc_phy_stat_mask;
1159 #endif /* EFSYS_OPT_PHY_STATS */
1161 uint8_t enc_mcdi_mdio_channel;
1162 #if EFSYS_OPT_PHY_STATS
1163 uint32_t enc_mcdi_phy_stat_mask;
1164 #endif /* EFSYS_OPT_PHY_STATS */
1165 #if EFSYS_OPT_MON_STATS
1166 uint32_t *enc_mcdi_sensor_maskp;
1167 uint32_t enc_mcdi_sensor_mask_size;
1168 #endif /* EFSYS_OPT_MON_STATS */
1169 #endif /* EFSYS_OPT_MCDI */
1171 uint32_t enc_bist_mask;
1172 #endif /* EFSYS_OPT_BIST */
1173 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1176 uint32_t enc_privilege_mask;
1177 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1178 boolean_t enc_bug26807_workaround;
1179 boolean_t enc_bug35388_workaround;
1180 boolean_t enc_bug41750_workaround;
1181 boolean_t enc_bug61265_workaround;
1182 boolean_t enc_rx_batching_enabled;
1183 /* Maximum number of descriptors completed in an rx event. */
1184 uint32_t enc_rx_batch_max;
1185 /* Number of rx descriptors the hardware requires for a push. */
1186 uint32_t enc_rx_push_align;
1187 /* Maximum amount of data in DMA descriptor */
1188 uint32_t enc_tx_dma_desc_size_max;
1190 * Boundary which DMA descriptor data must not cross or 0 if no
1193 uint32_t enc_tx_dma_desc_boundary;
1195 * Maximum number of bytes into the packet the TCP header can start for
1196 * the hardware to apply TSO packet edits.
1198 uint32_t enc_tx_tso_tcp_header_offset_limit;
1199 boolean_t enc_fw_assisted_tso_enabled;
1200 boolean_t enc_fw_assisted_tso_v2_enabled;
1201 /* Number of TSO contexts on the NIC (FATSOv2) */
1202 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1203 boolean_t enc_hw_tx_insert_vlan_enabled;
1204 /* Number of PFs on the NIC */
1205 uint32_t enc_hw_pf_count;
1206 /* Datapath firmware vadapter/vport/vswitch support */
1207 boolean_t enc_datapath_cap_evb;
1208 boolean_t enc_rx_disable_scatter_supported;
1209 boolean_t enc_allow_set_mac_with_installed_filters;
1210 boolean_t enc_enhanced_set_mac_supported;
1211 boolean_t enc_init_evq_v2_supported;
1212 boolean_t enc_rx_packed_stream_supported;
1213 boolean_t enc_rx_var_packed_stream_supported;
1214 boolean_t enc_pm_and_rxdp_counters;
1215 boolean_t enc_mac_stats_40g_tx_size_bins;
1216 uint32_t enc_tunnel_encapsulations_supported;
1218 * NIC global maximum for unique UDP tunnel ports shared by all
1221 uint32_t enc_tunnel_config_udp_entries_max;
1222 /* External port identifier */
1223 uint8_t enc_external_port;
1224 uint32_t enc_mcdi_max_payload_length;
1225 /* VPD may be per-PF or global */
1226 boolean_t enc_vpd_is_global;
1227 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1228 uint32_t enc_required_pcie_bandwidth_mbps;
1229 uint32_t enc_max_pcie_link_gen;
1230 /* Firmware verifies integrity of NVRAM updates */
1231 uint32_t enc_nvram_update_verify_result_supported;
1234 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1235 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1237 #define EFX_PCI_FUNCTION(_encp) \
1238 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1240 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1242 extern const efx_nic_cfg_t *
1244 __in efx_nic_t *enp);
1246 typedef struct efx_nic_fw_info_s {
1247 /* Basic FW version information */
1248 uint16_t enfi_mc_fw_version[4];
1250 * If datapath capabilities can be detected,
1251 * additional FW information is to be shown
1253 boolean_t enfi_dpcpu_fw_ids_valid;
1254 /* Rx and Tx datapath CPU FW IDs */
1255 uint16_t enfi_rx_dpcpu_fw_id;
1256 uint16_t enfi_tx_dpcpu_fw_id;
1257 } efx_nic_fw_info_t;
1259 extern __checkReturn efx_rc_t
1260 efx_nic_get_fw_version(
1261 __in efx_nic_t *enp,
1262 __out efx_nic_fw_info_t *enfip);
1264 /* Driver resource limits (minimum required/maximum usable). */
1265 typedef struct efx_drv_limits_s {
1266 uint32_t edl_min_evq_count;
1267 uint32_t edl_max_evq_count;
1269 uint32_t edl_min_rxq_count;
1270 uint32_t edl_max_rxq_count;
1272 uint32_t edl_min_txq_count;
1273 uint32_t edl_max_txq_count;
1275 /* PIO blocks (sub-allocated from piobuf) */
1276 uint32_t edl_min_pio_alloc_size;
1277 uint32_t edl_max_pio_alloc_count;
1280 extern __checkReturn efx_rc_t
1281 efx_nic_set_drv_limits(
1282 __inout efx_nic_t *enp,
1283 __in efx_drv_limits_t *edlp);
1285 typedef enum efx_nic_region_e {
1286 EFX_REGION_VI, /* Memory BAR UC mapping */
1287 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1290 extern __checkReturn efx_rc_t
1291 efx_nic_get_bar_region(
1292 __in efx_nic_t *enp,
1293 __in efx_nic_region_t region,
1294 __out uint32_t *offsetp,
1295 __out size_t *sizep);
1297 extern __checkReturn efx_rc_t
1298 efx_nic_get_vi_pool(
1299 __in efx_nic_t *enp,
1300 __out uint32_t *evq_countp,
1301 __out uint32_t *rxq_countp,
1302 __out uint32_t *txq_countp);
1307 typedef enum efx_vpd_tag_e {
1314 typedef uint16_t efx_vpd_keyword_t;
1316 typedef struct efx_vpd_value_s {
1317 efx_vpd_tag_t evv_tag;
1318 efx_vpd_keyword_t evv_keyword;
1320 uint8_t evv_value[0x100];
1324 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1326 extern __checkReturn efx_rc_t
1328 __in efx_nic_t *enp);
1330 extern __checkReturn efx_rc_t
1332 __in efx_nic_t *enp,
1333 __out size_t *sizep);
1335 extern __checkReturn efx_rc_t
1337 __in efx_nic_t *enp,
1338 __out_bcount(size) caddr_t data,
1341 extern __checkReturn efx_rc_t
1343 __in efx_nic_t *enp,
1344 __in_bcount(size) caddr_t data,
1347 extern __checkReturn efx_rc_t
1349 __in efx_nic_t *enp,
1350 __in_bcount(size) caddr_t data,
1353 extern __checkReturn efx_rc_t
1355 __in efx_nic_t *enp,
1356 __in_bcount(size) caddr_t data,
1358 __inout efx_vpd_value_t *evvp);
1360 extern __checkReturn efx_rc_t
1362 __in efx_nic_t *enp,
1363 __inout_bcount(size) caddr_t data,
1365 __in efx_vpd_value_t *evvp);
1367 extern __checkReturn efx_rc_t
1369 __in efx_nic_t *enp,
1370 __inout_bcount(size) caddr_t data,
1372 __out efx_vpd_value_t *evvp,
1373 __inout unsigned int *contp);
1375 extern __checkReturn efx_rc_t
1377 __in efx_nic_t *enp,
1378 __in_bcount(size) caddr_t data,
1383 __in efx_nic_t *enp);
1385 #endif /* EFSYS_OPT_VPD */
1391 typedef enum efx_nvram_type_e {
1392 EFX_NVRAM_INVALID = 0,
1394 EFX_NVRAM_BOOTROM_CFG,
1395 EFX_NVRAM_MC_FIRMWARE,
1396 EFX_NVRAM_MC_GOLDEN,
1402 EFX_NVRAM_FPGA_BACKUP,
1403 EFX_NVRAM_DYNAMIC_CFG,
1406 EFX_NVRAM_MUM_FIRMWARE,
1410 extern __checkReturn efx_rc_t
1412 __in efx_nic_t *enp);
1416 extern __checkReturn efx_rc_t
1418 __in efx_nic_t *enp);
1420 #endif /* EFSYS_OPT_DIAG */
1422 extern __checkReturn efx_rc_t
1424 __in efx_nic_t *enp,
1425 __in efx_nvram_type_t type,
1426 __out size_t *sizep);
1428 extern __checkReturn efx_rc_t
1430 __in efx_nic_t *enp,
1431 __in efx_nvram_type_t type,
1432 __out_opt size_t *pref_chunkp);
1434 extern __checkReturn efx_rc_t
1435 efx_nvram_rw_finish(
1436 __in efx_nic_t *enp,
1437 __in efx_nvram_type_t type,
1438 __out_opt uint32_t *verify_resultp);
1440 extern __checkReturn efx_rc_t
1441 efx_nvram_get_version(
1442 __in efx_nic_t *enp,
1443 __in efx_nvram_type_t type,
1444 __out uint32_t *subtypep,
1445 __out_ecount(4) uint16_t version[4]);
1447 extern __checkReturn efx_rc_t
1448 efx_nvram_read_chunk(
1449 __in efx_nic_t *enp,
1450 __in efx_nvram_type_t type,
1451 __in unsigned int offset,
1452 __out_bcount(size) caddr_t data,
1455 extern __checkReturn efx_rc_t
1456 efx_nvram_read_backup(
1457 __in efx_nic_t *enp,
1458 __in efx_nvram_type_t type,
1459 __in unsigned int offset,
1460 __out_bcount(size) caddr_t data,
1463 extern __checkReturn efx_rc_t
1464 efx_nvram_set_version(
1465 __in efx_nic_t *enp,
1466 __in efx_nvram_type_t type,
1467 __in_ecount(4) uint16_t version[4]);
1469 extern __checkReturn efx_rc_t
1471 __in efx_nic_t *enp,
1472 __in efx_nvram_type_t type,
1473 __in_bcount(partn_size) caddr_t partn_data,
1474 __in size_t partn_size);
1476 extern __checkReturn efx_rc_t
1478 __in efx_nic_t *enp,
1479 __in efx_nvram_type_t type);
1481 extern __checkReturn efx_rc_t
1482 efx_nvram_write_chunk(
1483 __in efx_nic_t *enp,
1484 __in efx_nvram_type_t type,
1485 __in unsigned int offset,
1486 __in_bcount(size) caddr_t data,
1491 __in efx_nic_t *enp);
1493 #endif /* EFSYS_OPT_NVRAM */
1495 #if EFSYS_OPT_BOOTCFG
1497 /* Report size and offset of bootcfg sector in NVRAM partition. */
1498 extern __checkReturn efx_rc_t
1499 efx_bootcfg_sector_info(
1500 __in efx_nic_t *enp,
1502 __out_opt uint32_t *sector_countp,
1503 __out size_t *offsetp,
1504 __out size_t *max_sizep);
1507 * Copy bootcfg sector data to a target buffer which may differ in size.
1508 * Optionally corrects format errors in source buffer.
1511 efx_bootcfg_copy_sector(
1512 __in efx_nic_t *enp,
1513 __inout_bcount(sector_length)
1515 __in size_t sector_length,
1516 __out_bcount(data_size) uint8_t *data,
1517 __in size_t data_size,
1518 __in boolean_t handle_format_errors);
1522 __in efx_nic_t *enp,
1523 __out_bcount(size) uint8_t *data,
1528 __in efx_nic_t *enp,
1529 __in_bcount(size) uint8_t *data,
1532 #endif /* EFSYS_OPT_BOOTCFG */
1536 typedef enum efx_pattern_type_t {
1537 EFX_PATTERN_BYTE_INCREMENT = 0,
1538 EFX_PATTERN_ALL_THE_SAME,
1539 EFX_PATTERN_BIT_ALTERNATE,
1540 EFX_PATTERN_BYTE_ALTERNATE,
1541 EFX_PATTERN_BYTE_CHANGING,
1542 EFX_PATTERN_BIT_SWEEP,
1544 } efx_pattern_type_t;
1547 (*efx_sram_pattern_fn_t)(
1549 __in boolean_t negate,
1550 __out efx_qword_t *eqp);
1552 extern __checkReturn efx_rc_t
1554 __in efx_nic_t *enp,
1555 __in efx_pattern_type_t type);
1557 #endif /* EFSYS_OPT_DIAG */
1559 extern __checkReturn efx_rc_t
1560 efx_sram_buf_tbl_set(
1561 __in efx_nic_t *enp,
1563 __in efsys_mem_t *esmp,
1567 efx_sram_buf_tbl_clear(
1568 __in efx_nic_t *enp,
1572 #define EFX_BUF_TBL_SIZE 0x20000
1574 #define EFX_BUF_SIZE 4096
1578 typedef struct efx_evq_s efx_evq_t;
1580 #if EFSYS_OPT_QSTATS
1582 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1583 typedef enum efx_ev_qstat_e {
1589 EV_RX_PAUSE_FRM_ERR,
1590 EV_RX_BUF_OWNER_ID_ERR,
1591 EV_RX_IPV4_HDR_CHKSUM_ERR,
1592 EV_RX_TCP_UDP_CHKSUM_ERR,
1596 EV_RX_MCAST_HASH_MATCH,
1613 EV_DRIVER_SRM_UPD_DONE,
1614 EV_DRIVER_TX_DESCQ_FLS_DONE,
1615 EV_DRIVER_RX_DESCQ_FLS_DONE,
1616 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1617 EV_DRIVER_RX_DSC_ERROR,
1618 EV_DRIVER_TX_DSC_ERROR,
1624 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1626 #endif /* EFSYS_OPT_QSTATS */
1628 extern __checkReturn efx_rc_t
1630 __in efx_nic_t *enp);
1634 __in efx_nic_t *enp);
1636 #define EFX_EVQ_MAXNEVS 32768
1637 #define EFX_EVQ_MINNEVS 512
1639 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1640 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1642 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1643 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1644 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1645 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1647 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1648 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1649 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1651 extern __checkReturn efx_rc_t
1653 __in efx_nic_t *enp,
1654 __in unsigned int index,
1655 __in efsys_mem_t *esmp,
1659 __in uint32_t flags,
1660 __deref_out efx_evq_t **eepp);
1664 __in efx_evq_t *eep,
1665 __in uint16_t data);
1667 typedef __checkReturn boolean_t
1668 (*efx_initialized_ev_t)(
1669 __in_opt void *arg);
1671 #define EFX_PKT_UNICAST 0x0004
1672 #define EFX_PKT_START 0x0008
1674 #define EFX_PKT_VLAN_TAGGED 0x0010
1675 #define EFX_CKSUM_TCPUDP 0x0020
1676 #define EFX_CKSUM_IPV4 0x0040
1677 #define EFX_PKT_CONT 0x0080
1679 #define EFX_CHECK_VLAN 0x0100
1680 #define EFX_PKT_TCP 0x0200
1681 #define EFX_PKT_UDP 0x0400
1682 #define EFX_PKT_IPV4 0x0800
1684 #define EFX_PKT_IPV6 0x1000
1685 #define EFX_PKT_PREFIX_LEN 0x2000
1686 #define EFX_ADDR_MISMATCH 0x4000
1687 #define EFX_DISCARD 0x8000
1690 * The following flags are used only for packed stream
1691 * mode. The values for the flags are reused to fit into 16 bit,
1692 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1693 * packed stream mode
1695 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1696 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1699 #define EFX_EV_RX_NLABELS 32
1700 #define EFX_EV_TX_NLABELS 32
1702 typedef __checkReturn boolean_t
1705 __in uint32_t label,
1708 __in uint16_t flags);
1710 #if EFSYS_OPT_RX_PACKED_STREAM
1713 * Packed stream mode is documented in SF-112241-TC.
1714 * The general idea is that, instead of putting each incoming
1715 * packet into a separate buffer which is specified in a RX
1716 * descriptor, a large buffer is provided to the hardware and
1717 * packets are put there in a continuous stream.
1718 * The main advantage of such an approach is that RX queue refilling
1719 * happens much less frequently.
1722 typedef __checkReturn boolean_t
1725 __in uint32_t label,
1727 __in uint32_t pkt_count,
1728 __in uint16_t flags);
1732 typedef __checkReturn boolean_t
1735 __in uint32_t label,
1738 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1739 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1740 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1741 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1742 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1743 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1744 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1745 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1746 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1748 typedef __checkReturn boolean_t
1749 (*efx_exception_ev_t)(
1751 __in uint32_t label,
1752 __in uint32_t data);
1754 typedef __checkReturn boolean_t
1755 (*efx_rxq_flush_done_ev_t)(
1757 __in uint32_t rxq_index);
1759 typedef __checkReturn boolean_t
1760 (*efx_rxq_flush_failed_ev_t)(
1762 __in uint32_t rxq_index);
1764 typedef __checkReturn boolean_t
1765 (*efx_txq_flush_done_ev_t)(
1767 __in uint32_t txq_index);
1769 typedef __checkReturn boolean_t
1770 (*efx_software_ev_t)(
1772 __in uint16_t magic);
1774 typedef __checkReturn boolean_t
1777 __in uint32_t code);
1779 #define EFX_SRAM_CLEAR 0
1780 #define EFX_SRAM_UPDATE 1
1781 #define EFX_SRAM_ILLEGAL_CLEAR 2
1783 typedef __checkReturn boolean_t
1784 (*efx_wake_up_ev_t)(
1786 __in uint32_t label);
1788 typedef __checkReturn boolean_t
1791 __in uint32_t label);
1793 typedef __checkReturn boolean_t
1794 (*efx_link_change_ev_t)(
1796 __in efx_link_mode_t link_mode);
1798 #if EFSYS_OPT_MON_STATS
1800 typedef __checkReturn boolean_t
1801 (*efx_monitor_ev_t)(
1803 __in efx_mon_stat_t id,
1804 __in efx_mon_stat_value_t value);
1806 #endif /* EFSYS_OPT_MON_STATS */
1808 #if EFSYS_OPT_MAC_STATS
1810 typedef __checkReturn boolean_t
1811 (*efx_mac_stats_ev_t)(
1813 __in uint32_t generation);
1815 #endif /* EFSYS_OPT_MAC_STATS */
1817 typedef struct efx_ev_callbacks_s {
1818 efx_initialized_ev_t eec_initialized;
1820 #if EFSYS_OPT_RX_PACKED_STREAM
1821 efx_rx_ps_ev_t eec_rx_ps;
1824 efx_exception_ev_t eec_exception;
1825 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1826 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1827 efx_txq_flush_done_ev_t eec_txq_flush_done;
1828 efx_software_ev_t eec_software;
1829 efx_sram_ev_t eec_sram;
1830 efx_wake_up_ev_t eec_wake_up;
1831 efx_timer_ev_t eec_timer;
1832 efx_link_change_ev_t eec_link_change;
1833 #if EFSYS_OPT_MON_STATS
1834 efx_monitor_ev_t eec_monitor;
1835 #endif /* EFSYS_OPT_MON_STATS */
1836 #if EFSYS_OPT_MAC_STATS
1837 efx_mac_stats_ev_t eec_mac_stats;
1838 #endif /* EFSYS_OPT_MAC_STATS */
1839 } efx_ev_callbacks_t;
1841 extern __checkReturn boolean_t
1843 __in efx_evq_t *eep,
1844 __in unsigned int count);
1846 #if EFSYS_OPT_EV_PREFETCH
1850 __in efx_evq_t *eep,
1851 __in unsigned int count);
1853 #endif /* EFSYS_OPT_EV_PREFETCH */
1857 __in efx_evq_t *eep,
1858 __inout unsigned int *countp,
1859 __in const efx_ev_callbacks_t *eecp,
1860 __in_opt void *arg);
1862 extern __checkReturn efx_rc_t
1863 efx_ev_usecs_to_ticks(
1864 __in efx_nic_t *enp,
1865 __in unsigned int usecs,
1866 __out unsigned int *ticksp);
1868 extern __checkReturn efx_rc_t
1870 __in efx_evq_t *eep,
1871 __in unsigned int us);
1873 extern __checkReturn efx_rc_t
1875 __in efx_evq_t *eep,
1876 __in unsigned int count);
1878 #if EFSYS_OPT_QSTATS
1884 __in efx_nic_t *enp,
1885 __in unsigned int id);
1887 #endif /* EFSYS_OPT_NAMES */
1890 efx_ev_qstats_update(
1891 __in efx_evq_t *eep,
1892 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1894 #endif /* EFSYS_OPT_QSTATS */
1898 __in efx_evq_t *eep);
1902 extern __checkReturn efx_rc_t
1904 __inout efx_nic_t *enp);
1908 __in efx_nic_t *enp);
1910 #if EFSYS_OPT_RX_SCATTER
1911 __checkReturn efx_rc_t
1912 efx_rx_scatter_enable(
1913 __in efx_nic_t *enp,
1914 __in unsigned int buf_size);
1915 #endif /* EFSYS_OPT_RX_SCATTER */
1917 /* Handle to represent use of the default RSS context. */
1918 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1920 #if EFSYS_OPT_RX_SCALE
1922 typedef enum efx_rx_hash_alg_e {
1923 EFX_RX_HASHALG_LFSR = 0,
1924 EFX_RX_HASHALG_TOEPLITZ
1925 } efx_rx_hash_alg_t;
1927 #define EFX_RX_HASH_IPV4 (1U << 0)
1928 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1929 #define EFX_RX_HASH_IPV6 (1U << 2)
1930 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1932 typedef unsigned int efx_rx_hash_type_t;
1934 typedef enum efx_rx_hash_support_e {
1935 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1936 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1937 } efx_rx_hash_support_t;
1939 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1940 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1941 #define EFX_MAXRSS 64 /* RX indirection entry range */
1942 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1944 typedef enum efx_rx_scale_context_type_e {
1945 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1946 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1947 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1948 } efx_rx_scale_context_type_t;
1950 extern __checkReturn efx_rc_t
1951 efx_rx_hash_default_support_get(
1952 __in efx_nic_t *enp,
1953 __out efx_rx_hash_support_t *supportp);
1956 extern __checkReturn efx_rc_t
1957 efx_rx_scale_default_support_get(
1958 __in efx_nic_t *enp,
1959 __out efx_rx_scale_context_type_t *typep);
1961 extern __checkReturn efx_rc_t
1962 efx_rx_scale_context_alloc(
1963 __in efx_nic_t *enp,
1964 __in efx_rx_scale_context_type_t type,
1965 __in uint32_t num_queues,
1966 __out uint32_t *rss_contextp);
1968 extern __checkReturn efx_rc_t
1969 efx_rx_scale_context_free(
1970 __in efx_nic_t *enp,
1971 __in uint32_t rss_context);
1973 extern __checkReturn efx_rc_t
1974 efx_rx_scale_mode_set(
1975 __in efx_nic_t *enp,
1976 __in uint32_t rss_context,
1977 __in efx_rx_hash_alg_t alg,
1978 __in efx_rx_hash_type_t type,
1979 __in boolean_t insert);
1981 extern __checkReturn efx_rc_t
1982 efx_rx_scale_tbl_set(
1983 __in efx_nic_t *enp,
1984 __in uint32_t rss_context,
1985 __in_ecount(n) unsigned int *table,
1988 extern __checkReturn efx_rc_t
1989 efx_rx_scale_key_set(
1990 __in efx_nic_t *enp,
1991 __in uint32_t rss_context,
1992 __in_ecount(n) uint8_t *key,
1995 extern __checkReturn uint32_t
1996 efx_pseudo_hdr_hash_get(
1997 __in efx_rxq_t *erp,
1998 __in efx_rx_hash_alg_t func,
1999 __in uint8_t *buffer);
2001 #endif /* EFSYS_OPT_RX_SCALE */
2003 extern __checkReturn efx_rc_t
2004 efx_pseudo_hdr_pkt_length_get(
2005 __in efx_rxq_t *erp,
2006 __in uint8_t *buffer,
2007 __out uint16_t *pkt_lengthp);
2009 #define EFX_RXQ_MAXNDESCS 4096
2010 #define EFX_RXQ_MINNDESCS 512
2012 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2013 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2014 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2015 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2017 typedef enum efx_rxq_type_e {
2018 EFX_RXQ_TYPE_DEFAULT,
2019 EFX_RXQ_TYPE_PACKED_STREAM,
2024 * Dummy flag to be used instead of 0 to make it clear that the argument
2025 * is receive queue flags.
2027 #define EFX_RXQ_FLAG_NONE 0x0
2028 #define EFX_RXQ_FLAG_SCATTER 0x1
2030 * If tunnels are supported and Rx event can provide information about
2031 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2032 * full-feature firmware variant running), outer classes are requested by
2033 * default. However, if the driver supports tunnels, the flag allows to
2034 * request inner classes which are required to be able to interpret inner
2035 * Rx checksum offload results.
2037 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2039 extern __checkReturn efx_rc_t
2041 __in efx_nic_t *enp,
2042 __in unsigned int index,
2043 __in unsigned int label,
2044 __in efx_rxq_type_t type,
2045 __in efsys_mem_t *esmp,
2048 __in unsigned int flags,
2049 __in efx_evq_t *eep,
2050 __deref_out efx_rxq_t **erpp);
2052 #if EFSYS_OPT_RX_PACKED_STREAM
2054 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2055 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2056 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2057 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2058 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2060 extern __checkReturn efx_rc_t
2061 efx_rx_qcreate_packed_stream(
2062 __in efx_nic_t *enp,
2063 __in unsigned int index,
2064 __in unsigned int label,
2065 __in uint32_t ps_buf_size,
2066 __in efsys_mem_t *esmp,
2068 __in efx_evq_t *eep,
2069 __deref_out efx_rxq_t **erpp);
2073 typedef struct efx_buffer_s {
2074 efsys_dma_addr_t eb_addr;
2079 typedef struct efx_desc_s {
2085 __in efx_rxq_t *erp,
2086 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2088 __in unsigned int ndescs,
2089 __in unsigned int completed,
2090 __in unsigned int added);
2094 __in efx_rxq_t *erp,
2095 __in unsigned int added,
2096 __inout unsigned int *pushedp);
2098 #if EFSYS_OPT_RX_PACKED_STREAM
2101 efx_rx_qpush_ps_credits(
2102 __in efx_rxq_t *erp);
2104 extern __checkReturn uint8_t *
2105 efx_rx_qps_packet_info(
2106 __in efx_rxq_t *erp,
2107 __in uint8_t *buffer,
2108 __in uint32_t buffer_length,
2109 __in uint32_t current_offset,
2110 __out uint16_t *lengthp,
2111 __out uint32_t *next_offsetp,
2112 __out uint32_t *timestamp);
2115 extern __checkReturn efx_rc_t
2117 __in efx_rxq_t *erp);
2121 __in efx_rxq_t *erp);
2125 __in efx_rxq_t *erp);
2129 typedef struct efx_txq_s efx_txq_t;
2131 #if EFSYS_OPT_QSTATS
2133 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2134 typedef enum efx_tx_qstat_e {
2140 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2142 #endif /* EFSYS_OPT_QSTATS */
2144 extern __checkReturn efx_rc_t
2146 __in efx_nic_t *enp);
2150 __in efx_nic_t *enp);
2152 #define EFX_TXQ_MINNDESCS 512
2154 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2155 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2156 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2158 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2160 #define EFX_TXQ_CKSUM_IPV4 0x0001
2161 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2162 #define EFX_TXQ_FATSOV2 0x0004
2163 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2164 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2166 extern __checkReturn efx_rc_t
2168 __in efx_nic_t *enp,
2169 __in unsigned int index,
2170 __in unsigned int label,
2171 __in efsys_mem_t *esmp,
2174 __in uint16_t flags,
2175 __in efx_evq_t *eep,
2176 __deref_out efx_txq_t **etpp,
2177 __out unsigned int *addedp);
2179 extern __checkReturn efx_rc_t
2181 __in efx_txq_t *etp,
2182 __in_ecount(ndescs) efx_buffer_t *eb,
2183 __in unsigned int ndescs,
2184 __in unsigned int completed,
2185 __inout unsigned int *addedp);
2187 extern __checkReturn efx_rc_t
2189 __in efx_txq_t *etp,
2190 __in unsigned int ns);
2194 __in efx_txq_t *etp,
2195 __in unsigned int added,
2196 __in unsigned int pushed);
2198 extern __checkReturn efx_rc_t
2200 __in efx_txq_t *etp);
2204 __in efx_txq_t *etp);
2206 extern __checkReturn efx_rc_t
2208 __in efx_txq_t *etp);
2211 efx_tx_qpio_disable(
2212 __in efx_txq_t *etp);
2214 extern __checkReturn efx_rc_t
2216 __in efx_txq_t *etp,
2217 __in_ecount(buf_length) uint8_t *buffer,
2218 __in size_t buf_length,
2219 __in size_t pio_buf_offset);
2221 extern __checkReturn efx_rc_t
2223 __in efx_txq_t *etp,
2224 __in size_t pkt_length,
2225 __in unsigned int completed,
2226 __inout unsigned int *addedp);
2228 extern __checkReturn efx_rc_t
2230 __in efx_txq_t *etp,
2231 __in_ecount(n) efx_desc_t *ed,
2232 __in unsigned int n,
2233 __in unsigned int completed,
2234 __inout unsigned int *addedp);
2237 efx_tx_qdesc_dma_create(
2238 __in efx_txq_t *etp,
2239 __in efsys_dma_addr_t addr,
2242 __out efx_desc_t *edp);
2245 efx_tx_qdesc_tso_create(
2246 __in efx_txq_t *etp,
2247 __in uint16_t ipv4_id,
2248 __in uint32_t tcp_seq,
2249 __in uint8_t tcp_flags,
2250 __out efx_desc_t *edp);
2252 /* Number of FATSOv2 option descriptors */
2253 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2255 /* Maximum number of DMA segments per TSO packet (not superframe) */
2256 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2259 efx_tx_qdesc_tso2_create(
2260 __in efx_txq_t *etp,
2261 __in uint16_t ipv4_id,
2262 __in uint32_t tcp_seq,
2263 __in uint16_t tcp_mss,
2264 __out_ecount(count) efx_desc_t *edp,
2268 efx_tx_qdesc_vlantci_create(
2269 __in efx_txq_t *etp,
2271 __out efx_desc_t *edp);
2274 efx_tx_qdesc_checksum_create(
2275 __in efx_txq_t *etp,
2276 __in uint16_t flags,
2277 __out efx_desc_t *edp);
2279 #if EFSYS_OPT_QSTATS
2285 __in efx_nic_t *etp,
2286 __in unsigned int id);
2288 #endif /* EFSYS_OPT_NAMES */
2291 efx_tx_qstats_update(
2292 __in efx_txq_t *etp,
2293 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2295 #endif /* EFSYS_OPT_QSTATS */
2299 __in efx_txq_t *etp);
2304 #if EFSYS_OPT_FILTER
2306 #define EFX_ETHER_TYPE_IPV4 0x0800
2307 #define EFX_ETHER_TYPE_IPV6 0x86DD
2309 #define EFX_IPPROTO_TCP 6
2310 #define EFX_IPPROTO_UDP 17
2311 #define EFX_IPPROTO_GRE 47
2313 /* Use RSS to spread across multiple queues */
2314 #define EFX_FILTER_FLAG_RX_RSS 0x01
2315 /* Enable RX scatter */
2316 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2318 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2319 * May only be set by the filter implementation for each type.
2320 * A removal request will restore the automatic filter in its place.
2322 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2323 /* Filter is for RX */
2324 #define EFX_FILTER_FLAG_RX 0x08
2325 /* Filter is for TX */
2326 #define EFX_FILTER_FLAG_TX 0x10
2328 typedef uint8_t efx_filter_flags_t;
2331 * Flags which specify the fields to match on. The values are the same as in the
2332 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2335 /* Match by remote IP host address */
2336 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2337 /* Match by local IP host address */
2338 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2339 /* Match by remote MAC address */
2340 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2341 /* Match by remote TCP/UDP port */
2342 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2343 /* Match by remote TCP/UDP port */
2344 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2345 /* Match by local TCP/UDP port */
2346 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2347 /* Match by Ether-type */
2348 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2349 /* Match by inner VLAN ID */
2350 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2351 /* Match by outer VLAN ID */
2352 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2353 /* Match by IP transport protocol */
2354 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2355 /* For encapsulated packets, match all multicast inner frames */
2356 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2357 /* For encapsulated packets, match all unicast inner frames */
2358 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2359 /* Match otherwise-unmatched multicast and broadcast packets */
2360 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2361 /* Match otherwise-unmatched unicast packets */
2362 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2364 typedef uint32_t efx_filter_match_flags_t;
2366 typedef enum efx_filter_priority_s {
2367 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2368 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2369 * address list or hardware
2370 * requirements. This may only be used
2371 * by the filter implementation for
2373 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2374 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2375 * client (e.g. SR-IOV, HyperV VMQ etc.)
2377 } efx_filter_priority_t;
2380 * FIXME: All these fields are assumed to be in little-endian byte order.
2381 * It may be better for some to be big-endian. See bug42804.
2384 typedef struct efx_filter_spec_s {
2385 efx_filter_match_flags_t efs_match_flags;
2386 uint8_t efs_priority;
2387 efx_filter_flags_t efs_flags;
2388 uint16_t efs_dmaq_id;
2389 uint32_t efs_rss_context;
2390 uint16_t efs_outer_vid;
2391 uint16_t efs_inner_vid;
2392 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2393 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2394 uint16_t efs_ether_type;
2395 uint8_t efs_ip_proto;
2396 efx_tunnel_protocol_t efs_encap_type;
2397 uint16_t efs_loc_port;
2398 uint16_t efs_rem_port;
2399 efx_oword_t efs_rem_host;
2400 efx_oword_t efs_loc_host;
2401 } efx_filter_spec_t;
2404 /* Default values for use in filter specifications */
2405 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2406 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2408 extern __checkReturn efx_rc_t
2410 __in efx_nic_t *enp);
2414 __in efx_nic_t *enp);
2416 extern __checkReturn efx_rc_t
2418 __in efx_nic_t *enp,
2419 __inout efx_filter_spec_t *spec);
2421 extern __checkReturn efx_rc_t
2423 __in efx_nic_t *enp,
2424 __inout efx_filter_spec_t *spec);
2426 extern __checkReturn efx_rc_t
2428 __in efx_nic_t *enp);
2430 extern __checkReturn efx_rc_t
2431 efx_filter_supported_filters(
2432 __in efx_nic_t *enp,
2433 __out_ecount(buffer_length) uint32_t *buffer,
2434 __in size_t buffer_length,
2435 __out size_t *list_lengthp);
2438 efx_filter_spec_init_rx(
2439 __out efx_filter_spec_t *spec,
2440 __in efx_filter_priority_t priority,
2441 __in efx_filter_flags_t flags,
2442 __in efx_rxq_t *erp);
2445 efx_filter_spec_init_tx(
2446 __out efx_filter_spec_t *spec,
2447 __in efx_txq_t *etp);
2449 extern __checkReturn efx_rc_t
2450 efx_filter_spec_set_ipv4_local(
2451 __inout efx_filter_spec_t *spec,
2454 __in uint16_t port);
2456 extern __checkReturn efx_rc_t
2457 efx_filter_spec_set_ipv4_full(
2458 __inout efx_filter_spec_t *spec,
2460 __in uint32_t lhost,
2461 __in uint16_t lport,
2462 __in uint32_t rhost,
2463 __in uint16_t rport);
2465 extern __checkReturn efx_rc_t
2466 efx_filter_spec_set_eth_local(
2467 __inout efx_filter_spec_t *spec,
2469 __in const uint8_t *addr);
2472 efx_filter_spec_set_ether_type(
2473 __inout efx_filter_spec_t *spec,
2474 __in uint16_t ether_type);
2476 extern __checkReturn efx_rc_t
2477 efx_filter_spec_set_uc_def(
2478 __inout efx_filter_spec_t *spec);
2480 extern __checkReturn efx_rc_t
2481 efx_filter_spec_set_mc_def(
2482 __inout efx_filter_spec_t *spec);
2484 typedef enum efx_filter_inner_frame_match_e {
2485 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2486 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2487 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2488 } efx_filter_inner_frame_match_t;
2490 extern __checkReturn efx_rc_t
2491 efx_filter_spec_set_encap_type(
2492 __inout efx_filter_spec_t *spec,
2493 __in efx_tunnel_protocol_t encap_type,
2494 __in efx_filter_inner_frame_match_t inner_frame_match);
2496 #if EFSYS_OPT_RX_SCALE
2497 extern __checkReturn efx_rc_t
2498 efx_filter_spec_set_rss_context(
2499 __inout efx_filter_spec_t *spec,
2500 __in uint32_t rss_context);
2502 #endif /* EFSYS_OPT_FILTER */
2506 extern __checkReturn uint32_t
2508 __in_ecount(count) uint32_t const *input,
2510 __in uint32_t init);
2512 extern __checkReturn uint32_t
2514 __in_ecount(length) uint8_t const *input,
2516 __in uint32_t init);
2518 #if EFSYS_OPT_LICENSING
2522 typedef struct efx_key_stats_s {
2524 uint32_t eks_invalid;
2525 uint32_t eks_blacklisted;
2526 uint32_t eks_unverifiable;
2527 uint32_t eks_wrong_node;
2528 uint32_t eks_licensed_apps_lo;
2529 uint32_t eks_licensed_apps_hi;
2530 uint32_t eks_licensed_features_lo;
2531 uint32_t eks_licensed_features_hi;
2534 extern __checkReturn efx_rc_t
2536 __in efx_nic_t *enp);
2540 __in efx_nic_t *enp);
2542 extern __checkReturn boolean_t
2543 efx_lic_check_support(
2544 __in efx_nic_t *enp);
2546 extern __checkReturn efx_rc_t
2547 efx_lic_update_licenses(
2548 __in efx_nic_t *enp);
2550 extern __checkReturn efx_rc_t
2551 efx_lic_get_key_stats(
2552 __in efx_nic_t *enp,
2553 __out efx_key_stats_t *ksp);
2555 extern __checkReturn efx_rc_t
2557 __in efx_nic_t *enp,
2558 __in uint64_t app_id,
2559 __out boolean_t *licensedp);
2561 extern __checkReturn efx_rc_t
2563 __in efx_nic_t *enp,
2564 __in size_t buffer_size,
2565 __out uint32_t *typep,
2566 __out size_t *lengthp,
2567 __out_opt uint8_t *bufferp);
2570 extern __checkReturn efx_rc_t
2572 __in efx_nic_t *enp,
2573 __in_bcount(buffer_size)
2575 __in size_t buffer_size,
2576 __out uint32_t *startp);
2578 extern __checkReturn efx_rc_t
2580 __in efx_nic_t *enp,
2581 __in_bcount(buffer_size)
2583 __in size_t buffer_size,
2584 __in uint32_t offset,
2585 __out uint32_t *endp);
2587 extern __checkReturn __success(return != B_FALSE) boolean_t
2589 __in efx_nic_t *enp,
2590 __in_bcount(buffer_size)
2592 __in size_t buffer_size,
2593 __in uint32_t offset,
2594 __out uint32_t *startp,
2595 __out uint32_t *lengthp);
2597 extern __checkReturn __success(return != B_FALSE) boolean_t
2598 efx_lic_validate_key(
2599 __in efx_nic_t *enp,
2600 __in_bcount(length) caddr_t keyp,
2601 __in uint32_t length);
2603 extern __checkReturn efx_rc_t
2605 __in efx_nic_t *enp,
2606 __in_bcount(buffer_size)
2608 __in size_t buffer_size,
2609 __in uint32_t offset,
2610 __in uint32_t length,
2611 __out_bcount_part(key_max_size, *lengthp)
2613 __in size_t key_max_size,
2614 __out uint32_t *lengthp);
2616 extern __checkReturn efx_rc_t
2618 __in efx_nic_t *enp,
2619 __in_bcount(buffer_size)
2621 __in size_t buffer_size,
2622 __in uint32_t offset,
2623 __in_bcount(length) caddr_t keyp,
2624 __in uint32_t length,
2625 __out uint32_t *lengthp);
2627 __checkReturn efx_rc_t
2629 __in efx_nic_t *enp,
2630 __in_bcount(buffer_size)
2632 __in size_t buffer_size,
2633 __in uint32_t offset,
2634 __in uint32_t length,
2636 __out uint32_t *deltap);
2638 extern __checkReturn efx_rc_t
2639 efx_lic_create_partition(
2640 __in efx_nic_t *enp,
2641 __in_bcount(buffer_size)
2643 __in size_t buffer_size);
2645 extern __checkReturn efx_rc_t
2646 efx_lic_finish_partition(
2647 __in efx_nic_t *enp,
2648 __in_bcount(buffer_size)
2650 __in size_t buffer_size);
2652 #endif /* EFSYS_OPT_LICENSING */
2656 #if EFSYS_OPT_TUNNEL
2658 extern __checkReturn efx_rc_t
2660 __in efx_nic_t *enp);
2664 __in efx_nic_t *enp);
2667 * For overlay network encapsulation using UDP, the firmware needs to know
2668 * the configured UDP port for the overlay so it can decode encapsulated
2670 * The UDP port/protocol list is global.
2673 extern __checkReturn efx_rc_t
2674 efx_tunnel_config_udp_add(
2675 __in efx_nic_t *enp,
2676 __in uint16_t port /* host/cpu-endian */,
2677 __in efx_tunnel_protocol_t protocol);
2679 extern __checkReturn efx_rc_t
2680 efx_tunnel_config_udp_remove(
2681 __in efx_nic_t *enp,
2682 __in uint16_t port /* host/cpu-endian */,
2683 __in efx_tunnel_protocol_t protocol);
2686 efx_tunnel_config_clear(
2687 __in efx_nic_t *enp);
2690 * Apply tunnel UDP ports configuration to hardware.
2692 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2695 extern __checkReturn efx_rc_t
2696 efx_tunnel_reconfigure(
2697 __in efx_nic_t *enp);
2699 #endif /* EFSYS_OPT_TUNNEL */
2706 #endif /* _SYS_EFX_H */