1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp);
54 #define EFX_PCI_VENID_SFC 0x1924
56 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
58 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
59 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
60 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
62 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
63 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
64 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
66 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
67 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
69 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
70 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
71 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
73 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
74 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
75 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
97 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
98 extern __checkReturn uint32_t
100 __in uint32_t crc_init,
101 __in_ecount(length) uint8_t const *input,
105 /* Type prototypes */
107 typedef struct efx_rxq_s efx_rxq_t;
111 typedef struct efx_nic_s efx_nic_t;
113 extern __checkReturn efx_rc_t
115 __in efx_family_t family,
116 __in efsys_identifier_t *esip,
117 __in efsys_bar_t *esbp,
118 __in efsys_lock_t *eslp,
119 __deref_out efx_nic_t **enpp);
121 extern __checkReturn efx_rc_t
123 __in efx_nic_t *enp);
125 extern __checkReturn efx_rc_t
127 __in efx_nic_t *enp);
129 extern __checkReturn efx_rc_t
131 __in efx_nic_t *enp);
135 extern __checkReturn efx_rc_t
136 efx_nic_register_test(
137 __in efx_nic_t *enp);
139 #endif /* EFSYS_OPT_DIAG */
143 __in efx_nic_t *enp);
147 __in efx_nic_t *enp);
151 __in efx_nic_t *enp);
153 #define EFX_PCIE_LINK_SPEED_GEN1 1
154 #define EFX_PCIE_LINK_SPEED_GEN2 2
155 #define EFX_PCIE_LINK_SPEED_GEN3 3
157 typedef enum efx_pcie_link_performance_e {
158 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
159 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
160 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
161 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
162 } efx_pcie_link_performance_t;
164 extern __checkReturn efx_rc_t
165 efx_nic_calculate_pcie_link_bandwidth(
166 __in uint32_t pcie_link_width,
167 __in uint32_t pcie_link_gen,
168 __out uint32_t *bandwidth_mbpsp);
170 extern __checkReturn efx_rc_t
171 efx_nic_check_pcie_link_speed(
173 __in uint32_t pcie_link_width,
174 __in uint32_t pcie_link_gen,
175 __out efx_pcie_link_performance_t *resultp);
179 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
180 /* Huntington and Medford require MCDIv2 commands */
181 #define WITH_MCDI_V2 1
184 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
186 typedef enum efx_mcdi_exception_e {
187 EFX_MCDI_EXCEPTION_MC_REBOOT,
188 EFX_MCDI_EXCEPTION_MC_BADASSERT,
189 } efx_mcdi_exception_t;
191 #if EFSYS_OPT_MCDI_LOGGING
192 typedef enum efx_log_msg_e {
194 EFX_LOG_MCDI_REQUEST,
195 EFX_LOG_MCDI_RESPONSE,
197 #endif /* EFSYS_OPT_MCDI_LOGGING */
199 typedef struct efx_mcdi_transport_s {
201 efsys_mem_t *emt_dma_mem;
202 void (*emt_execute)(void *, efx_mcdi_req_t *);
203 void (*emt_ev_cpl)(void *);
204 void (*emt_exception)(void *, efx_mcdi_exception_t);
205 #if EFSYS_OPT_MCDI_LOGGING
206 void (*emt_logger)(void *, efx_log_msg_t,
207 void *, size_t, void *, size_t);
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
209 #if EFSYS_OPT_MCDI_PROXY_AUTH
210 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
211 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
212 } efx_mcdi_transport_t;
214 extern __checkReturn efx_rc_t
217 __in const efx_mcdi_transport_t *mtp);
219 extern __checkReturn efx_rc_t
221 __in efx_nic_t *enp);
225 __in efx_nic_t *enp);
228 efx_mcdi_get_timeout(
230 __in efx_mcdi_req_t *emrp,
231 __out uint32_t *usec_timeoutp);
234 efx_mcdi_request_start(
236 __in efx_mcdi_req_t *emrp,
237 __in boolean_t ev_cpl);
239 extern __checkReturn boolean_t
240 efx_mcdi_request_poll(
241 __in efx_nic_t *enp);
243 extern __checkReturn boolean_t
244 efx_mcdi_request_abort(
245 __in efx_nic_t *enp);
249 __in efx_nic_t *enp);
251 #endif /* EFSYS_OPT_MCDI */
255 #define EFX_NINTR_SIENA 1024
257 typedef enum efx_intr_type_e {
258 EFX_INTR_INVALID = 0,
264 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
266 extern __checkReturn efx_rc_t
269 __in efx_intr_type_t type,
270 __in efsys_mem_t *esmp);
274 __in efx_nic_t *enp);
278 __in efx_nic_t *enp);
281 efx_intr_disable_unlocked(
282 __in efx_nic_t *enp);
284 #define EFX_INTR_NEVQS 32
286 extern __checkReturn efx_rc_t
289 __in unsigned int level);
292 efx_intr_status_line(
294 __out boolean_t *fatalp,
295 __out uint32_t *maskp);
298 efx_intr_status_message(
300 __in unsigned int message,
301 __out boolean_t *fatalp);
305 __in efx_nic_t *enp);
309 __in efx_nic_t *enp);
313 #if EFSYS_OPT_MAC_STATS
315 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
316 typedef enum efx_mac_stat_e {
319 EFX_MAC_RX_UNICST_PKTS,
320 EFX_MAC_RX_MULTICST_PKTS,
321 EFX_MAC_RX_BRDCST_PKTS,
322 EFX_MAC_RX_PAUSE_PKTS,
323 EFX_MAC_RX_LE_64_PKTS,
324 EFX_MAC_RX_65_TO_127_PKTS,
325 EFX_MAC_RX_128_TO_255_PKTS,
326 EFX_MAC_RX_256_TO_511_PKTS,
327 EFX_MAC_RX_512_TO_1023_PKTS,
328 EFX_MAC_RX_1024_TO_15XX_PKTS,
329 EFX_MAC_RX_GE_15XX_PKTS,
331 EFX_MAC_RX_FCS_ERRORS,
332 EFX_MAC_RX_DROP_EVENTS,
333 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
334 EFX_MAC_RX_SYMBOL_ERRORS,
335 EFX_MAC_RX_ALIGN_ERRORS,
336 EFX_MAC_RX_INTERNAL_ERRORS,
337 EFX_MAC_RX_JABBER_PKTS,
338 EFX_MAC_RX_LANE0_CHAR_ERR,
339 EFX_MAC_RX_LANE1_CHAR_ERR,
340 EFX_MAC_RX_LANE2_CHAR_ERR,
341 EFX_MAC_RX_LANE3_CHAR_ERR,
342 EFX_MAC_RX_LANE0_DISP_ERR,
343 EFX_MAC_RX_LANE1_DISP_ERR,
344 EFX_MAC_RX_LANE2_DISP_ERR,
345 EFX_MAC_RX_LANE3_DISP_ERR,
346 EFX_MAC_RX_MATCH_FAULT,
347 EFX_MAC_RX_NODESC_DROP_CNT,
350 EFX_MAC_TX_UNICST_PKTS,
351 EFX_MAC_TX_MULTICST_PKTS,
352 EFX_MAC_TX_BRDCST_PKTS,
353 EFX_MAC_TX_PAUSE_PKTS,
354 EFX_MAC_TX_LE_64_PKTS,
355 EFX_MAC_TX_65_TO_127_PKTS,
356 EFX_MAC_TX_128_TO_255_PKTS,
357 EFX_MAC_TX_256_TO_511_PKTS,
358 EFX_MAC_TX_512_TO_1023_PKTS,
359 EFX_MAC_TX_1024_TO_15XX_PKTS,
360 EFX_MAC_TX_GE_15XX_PKTS,
362 EFX_MAC_TX_SGL_COL_PKTS,
363 EFX_MAC_TX_MULT_COL_PKTS,
364 EFX_MAC_TX_EX_COL_PKTS,
365 EFX_MAC_TX_LATE_COL_PKTS,
367 EFX_MAC_TX_EX_DEF_PKTS,
368 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
369 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
370 EFX_MAC_PM_TRUNC_VFIFO_FULL,
371 EFX_MAC_PM_DISCARD_VFIFO_FULL,
372 EFX_MAC_PM_TRUNC_QBB,
373 EFX_MAC_PM_DISCARD_QBB,
374 EFX_MAC_PM_DISCARD_MAPPING,
375 EFX_MAC_RXDP_Q_DISABLED_PKTS,
376 EFX_MAC_RXDP_DI_DROPPED_PKTS,
377 EFX_MAC_RXDP_STREAMING_PKTS,
378 EFX_MAC_RXDP_HLB_FETCH,
379 EFX_MAC_RXDP_HLB_WAIT,
380 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
381 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
382 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
383 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
384 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
385 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
386 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
387 EFX_MAC_VADAPTER_RX_BAD_BYTES,
388 EFX_MAC_VADAPTER_RX_OVERFLOW,
389 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
390 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
391 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
392 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
393 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
394 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
395 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
396 EFX_MAC_VADAPTER_TX_BAD_BYTES,
397 EFX_MAC_VADAPTER_TX_OVERFLOW,
401 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
403 #endif /* EFSYS_OPT_MAC_STATS */
405 typedef enum efx_link_mode_e {
406 EFX_LINK_UNKNOWN = 0,
419 #define EFX_MAC_ADDR_LEN 6
421 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
423 #define EFX_MAC_MULTICAST_LIST_MAX 256
425 #define EFX_MAC_SDU_MAX 9202
427 #define EFX_MAC_PDU_ADJUSTMENT \
431 + /* bug16011 */ 16) \
433 #define EFX_MAC_PDU(_sdu) \
434 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
437 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
438 * the SDU rounded up slightly.
440 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
442 #define EFX_MAC_PDU_MIN 60
443 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
445 extern __checkReturn efx_rc_t
450 extern __checkReturn efx_rc_t
455 extern __checkReturn efx_rc_t
460 extern __checkReturn efx_rc_t
463 __in boolean_t all_unicst,
464 __in boolean_t mulcst,
465 __in boolean_t all_mulcst,
466 __in boolean_t brdcst);
468 extern __checkReturn efx_rc_t
469 efx_mac_multicast_list_set(
471 __in_ecount(6*count) uint8_t const *addrs,
474 extern __checkReturn efx_rc_t
475 efx_mac_filter_default_rxq_set(
478 __in boolean_t using_rss);
481 efx_mac_filter_default_rxq_clear(
482 __in efx_nic_t *enp);
484 extern __checkReturn efx_rc_t
487 __in boolean_t enabled);
489 extern __checkReturn efx_rc_t
492 __out boolean_t *mac_upp);
494 #define EFX_FCNTL_RESPOND 0x00000001
495 #define EFX_FCNTL_GENERATE 0x00000002
497 extern __checkReturn efx_rc_t
500 __in unsigned int fcntl,
501 __in boolean_t autoneg);
506 __out unsigned int *fcntl_wantedp,
507 __out unsigned int *fcntl_linkp);
510 #if EFSYS_OPT_MAC_STATS
514 extern __checkReturn const char *
517 __in unsigned int id);
519 #endif /* EFSYS_OPT_NAMES */
521 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
523 #define EFX_MAC_STATS_MASK_NPAGES \
524 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
525 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
528 * Get mask of MAC statistics supported by the hardware.
530 * If mask_size is insufficient to return the mask, EINVAL error is
531 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
532 * (which is sizeof (uint32_t)) is sufficient.
534 extern __checkReturn efx_rc_t
535 efx_mac_stats_get_mask(
537 __out_bcount(mask_size) uint32_t *maskp,
538 __in size_t mask_size);
540 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
541 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
542 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
544 #define EFX_MAC_STATS_SIZE 0x400
546 extern __checkReturn efx_rc_t
548 __in efx_nic_t *enp);
551 * Upload mac statistics supported by the hardware into the given buffer.
553 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
556 * The hardware will only DMA statistics that it understands (of course).
557 * Drivers should not make any assumptions about which statistics are
558 * supported, especially when the statistics are generated by firmware.
560 * Thus, drivers should zero this buffer before use, so that not-understood
561 * statistics read back as zero.
563 extern __checkReturn efx_rc_t
564 efx_mac_stats_upload(
566 __in efsys_mem_t *esmp);
568 extern __checkReturn efx_rc_t
569 efx_mac_stats_periodic(
571 __in efsys_mem_t *esmp,
572 __in uint16_t period_ms,
573 __in boolean_t events);
575 extern __checkReturn efx_rc_t
576 efx_mac_stats_update(
578 __in efsys_mem_t *esmp,
579 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
580 __inout_opt uint32_t *generationp);
582 #endif /* EFSYS_OPT_MAC_STATS */
586 typedef enum efx_mon_type_e {
598 __in efx_nic_t *enp);
600 #endif /* EFSYS_OPT_NAMES */
602 extern __checkReturn efx_rc_t
604 __in efx_nic_t *enp);
606 #if EFSYS_OPT_MON_STATS
608 #define EFX_MON_STATS_PAGE_SIZE 0x100
609 #define EFX_MON_MASK_ELEMENT_SIZE 32
611 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock fcc1b6748432e1ac */
612 typedef enum efx_mon_stat_e {
619 EFX_MON_STAT_EXT_TEMP,
620 EFX_MON_STAT_INT_TEMP,
623 EFX_MON_STAT_INT_COOLING,
624 EFX_MON_STAT_EXT_COOLING,
632 EFX_MON_STAT_AOE_TEMP,
633 EFX_MON_STAT_PSU_AOE_TEMP,
634 EFX_MON_STAT_PSU_TEMP,
640 EFX_MON_STAT_VAOE_IN,
642 EFX_MON_STAT_IAOE_IN,
643 EFX_MON_STAT_NIC_POWER,
647 EFX_MON_STAT_0_9V_ADC,
648 EFX_MON_STAT_INT_TEMP2,
649 EFX_MON_STAT_VREG_TEMP,
650 EFX_MON_STAT_VREG_0_9V_TEMP,
651 EFX_MON_STAT_VREG_1_2V_TEMP,
652 EFX_MON_STAT_INT_VPTAT,
653 EFX_MON_STAT_INT_ADC_TEMP,
654 EFX_MON_STAT_EXT_VPTAT,
655 EFX_MON_STAT_EXT_ADC_TEMP,
656 EFX_MON_STAT_AMBIENT_TEMP,
657 EFX_MON_STAT_AIRFLOW,
658 EFX_MON_STAT_VDD08D_VSS08D_CSR,
659 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
660 EFX_MON_STAT_HOTPOINT_TEMP,
661 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
662 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
663 EFX_MON_STAT_MUM_VCC,
666 EFX_MON_STAT_0V9_A_TEMP,
669 EFX_MON_STAT_0V9_B_TEMP,
670 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
671 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
672 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
673 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
674 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
675 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
676 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
677 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
678 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
679 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
680 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
681 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
682 EFX_MON_STAT_SODIMM_VOUT,
683 EFX_MON_STAT_SODIMM_0_TEMP,
684 EFX_MON_STAT_SODIMM_1_TEMP,
685 EFX_MON_STAT_PHY0_VCC,
686 EFX_MON_STAT_PHY1_VCC,
687 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
688 EFX_MON_STAT_BOARD_FRONT_TEMP,
689 EFX_MON_STAT_BOARD_BACK_TEMP,
697 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
699 typedef enum efx_mon_stat_state_e {
700 EFX_MON_STAT_STATE_OK = 0,
701 EFX_MON_STAT_STATE_WARNING = 1,
702 EFX_MON_STAT_STATE_FATAL = 2,
703 EFX_MON_STAT_STATE_BROKEN = 3,
704 EFX_MON_STAT_STATE_NO_READING = 4,
705 } efx_mon_stat_state_t;
707 typedef struct efx_mon_stat_value_s {
710 } efx_mon_stat_value_t;
717 __in efx_mon_stat_t id);
719 #endif /* EFSYS_OPT_NAMES */
721 extern __checkReturn efx_rc_t
722 efx_mon_stats_update(
724 __in efsys_mem_t *esmp,
725 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
727 #endif /* EFSYS_OPT_MON_STATS */
731 __in efx_nic_t *enp);
735 extern __checkReturn efx_rc_t
737 __in efx_nic_t *enp);
739 #if EFSYS_OPT_PHY_LED_CONTROL
741 typedef enum efx_phy_led_mode_e {
742 EFX_PHY_LED_DEFAULT = 0,
747 } efx_phy_led_mode_t;
749 extern __checkReturn efx_rc_t
752 __in efx_phy_led_mode_t mode);
754 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
756 extern __checkReturn efx_rc_t
758 __in efx_nic_t *enp);
760 #if EFSYS_OPT_LOOPBACK
762 typedef enum efx_loopback_type_e {
763 EFX_LOOPBACK_OFF = 0,
764 EFX_LOOPBACK_DATA = 1,
765 EFX_LOOPBACK_GMAC = 2,
766 EFX_LOOPBACK_XGMII = 3,
767 EFX_LOOPBACK_XGXS = 4,
768 EFX_LOOPBACK_XAUI = 5,
769 EFX_LOOPBACK_GMII = 6,
770 EFX_LOOPBACK_SGMII = 7,
771 EFX_LOOPBACK_XGBR = 8,
772 EFX_LOOPBACK_XFI = 9,
773 EFX_LOOPBACK_XAUI_FAR = 10,
774 EFX_LOOPBACK_GMII_FAR = 11,
775 EFX_LOOPBACK_SGMII_FAR = 12,
776 EFX_LOOPBACK_XFI_FAR = 13,
777 EFX_LOOPBACK_GPHY = 14,
778 EFX_LOOPBACK_PHY_XS = 15,
779 EFX_LOOPBACK_PCS = 16,
780 EFX_LOOPBACK_PMA_PMD = 17,
781 EFX_LOOPBACK_XPORT = 18,
782 EFX_LOOPBACK_XGMII_WS = 19,
783 EFX_LOOPBACK_XAUI_WS = 20,
784 EFX_LOOPBACK_XAUI_WS_FAR = 21,
785 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
786 EFX_LOOPBACK_GMII_WS = 23,
787 EFX_LOOPBACK_XFI_WS = 24,
788 EFX_LOOPBACK_XFI_WS_FAR = 25,
789 EFX_LOOPBACK_PHYXS_WS = 26,
790 EFX_LOOPBACK_PMA_INT = 27,
791 EFX_LOOPBACK_SD_NEAR = 28,
792 EFX_LOOPBACK_SD_FAR = 29,
793 EFX_LOOPBACK_PMA_INT_WS = 30,
794 EFX_LOOPBACK_SD_FEP2_WS = 31,
795 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
796 EFX_LOOPBACK_SD_FEP_WS = 33,
797 EFX_LOOPBACK_SD_FES_WS = 34,
799 } efx_loopback_type_t;
801 typedef enum efx_loopback_kind_e {
802 EFX_LOOPBACK_KIND_OFF = 0,
803 EFX_LOOPBACK_KIND_ALL,
804 EFX_LOOPBACK_KIND_MAC,
805 EFX_LOOPBACK_KIND_PHY,
807 } efx_loopback_kind_t;
811 __in efx_loopback_kind_t loopback_kind,
812 __out efx_qword_t *maskp);
814 extern __checkReturn efx_rc_t
815 efx_port_loopback_set(
817 __in efx_link_mode_t link_mode,
818 __in efx_loopback_type_t type);
822 extern __checkReturn const char *
823 efx_loopback_type_name(
825 __in efx_loopback_type_t type);
827 #endif /* EFSYS_OPT_NAMES */
829 #endif /* EFSYS_OPT_LOOPBACK */
831 extern __checkReturn efx_rc_t
834 __out_opt efx_link_mode_t *link_modep);
838 __in efx_nic_t *enp);
840 typedef enum efx_phy_cap_type_e {
841 EFX_PHY_CAP_INVALID = 0,
848 EFX_PHY_CAP_10000FDX,
852 EFX_PHY_CAP_40000FDX,
854 } efx_phy_cap_type_t;
857 #define EFX_PHY_CAP_CURRENT 0x00000000
858 #define EFX_PHY_CAP_DEFAULT 0x00000001
859 #define EFX_PHY_CAP_PERM 0x00000002
865 __out uint32_t *maskp);
867 extern __checkReturn efx_rc_t
875 __out uint32_t *maskp);
877 extern __checkReturn efx_rc_t
880 __out uint32_t *ouip);
882 typedef enum efx_phy_media_type_e {
883 EFX_PHY_MEDIA_INVALID = 0,
888 EFX_PHY_MEDIA_SFP_PLUS,
889 EFX_PHY_MEDIA_BASE_T,
890 EFX_PHY_MEDIA_QSFP_PLUS,
892 } efx_phy_media_type_t;
895 * Get the type of medium currently used. If the board has ports for
896 * modules, a module is present, and we recognise the media type of
897 * the module, then this will be the media type of the module.
898 * Otherwise it will be the media type of the port.
901 efx_phy_media_type_get(
903 __out efx_phy_media_type_t *typep);
905 extern __checkReturn efx_rc_t
906 efx_phy_module_get_info(
908 __in uint8_t dev_addr,
911 __out_bcount(len) uint8_t *data);
913 #if EFSYS_OPT_PHY_STATS
915 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
916 typedef enum efx_phy_stat_e {
918 EFX_PHY_STAT_PMA_PMD_LINK_UP,
919 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
920 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
921 EFX_PHY_STAT_PMA_PMD_REV_A,
922 EFX_PHY_STAT_PMA_PMD_REV_B,
923 EFX_PHY_STAT_PMA_PMD_REV_C,
924 EFX_PHY_STAT_PMA_PMD_REV_D,
925 EFX_PHY_STAT_PCS_LINK_UP,
926 EFX_PHY_STAT_PCS_RX_FAULT,
927 EFX_PHY_STAT_PCS_TX_FAULT,
928 EFX_PHY_STAT_PCS_BER,
929 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
930 EFX_PHY_STAT_PHY_XS_LINK_UP,
931 EFX_PHY_STAT_PHY_XS_RX_FAULT,
932 EFX_PHY_STAT_PHY_XS_TX_FAULT,
933 EFX_PHY_STAT_PHY_XS_ALIGN,
934 EFX_PHY_STAT_PHY_XS_SYNC_A,
935 EFX_PHY_STAT_PHY_XS_SYNC_B,
936 EFX_PHY_STAT_PHY_XS_SYNC_C,
937 EFX_PHY_STAT_PHY_XS_SYNC_D,
938 EFX_PHY_STAT_AN_LINK_UP,
939 EFX_PHY_STAT_AN_MASTER,
940 EFX_PHY_STAT_AN_LOCAL_RX_OK,
941 EFX_PHY_STAT_AN_REMOTE_RX_OK,
942 EFX_PHY_STAT_CL22EXT_LINK_UP,
947 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
948 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
949 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
950 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
951 EFX_PHY_STAT_AN_COMPLETE,
952 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
953 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
954 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
955 EFX_PHY_STAT_PCS_FW_VERSION_0,
956 EFX_PHY_STAT_PCS_FW_VERSION_1,
957 EFX_PHY_STAT_PCS_FW_VERSION_2,
958 EFX_PHY_STAT_PCS_FW_VERSION_3,
959 EFX_PHY_STAT_PCS_FW_BUILD_YY,
960 EFX_PHY_STAT_PCS_FW_BUILD_MM,
961 EFX_PHY_STAT_PCS_FW_BUILD_DD,
962 EFX_PHY_STAT_PCS_OP_MODE,
966 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
973 __in efx_phy_stat_t stat);
975 #endif /* EFSYS_OPT_NAMES */
977 #define EFX_PHY_STATS_SIZE 0x100
979 extern __checkReturn efx_rc_t
980 efx_phy_stats_update(
982 __in efsys_mem_t *esmp,
983 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
985 #endif /* EFSYS_OPT_PHY_STATS */
990 typedef enum efx_bist_type_e {
991 EFX_BIST_TYPE_UNKNOWN,
992 EFX_BIST_TYPE_PHY_NORMAL,
993 EFX_BIST_TYPE_PHY_CABLE_SHORT,
994 EFX_BIST_TYPE_PHY_CABLE_LONG,
995 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
996 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
997 EFX_BIST_TYPE_REG, /* Test the register memories */
998 EFX_BIST_TYPE_NTYPES,
1001 typedef enum efx_bist_result_e {
1002 EFX_BIST_RESULT_UNKNOWN,
1003 EFX_BIST_RESULT_RUNNING,
1004 EFX_BIST_RESULT_PASSED,
1005 EFX_BIST_RESULT_FAILED,
1006 } efx_bist_result_t;
1008 typedef enum efx_phy_cable_status_e {
1009 EFX_PHY_CABLE_STATUS_OK,
1010 EFX_PHY_CABLE_STATUS_INVALID,
1011 EFX_PHY_CABLE_STATUS_OPEN,
1012 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1013 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1014 EFX_PHY_CABLE_STATUS_BUSY,
1015 } efx_phy_cable_status_t;
1017 typedef enum efx_bist_value_e {
1018 EFX_BIST_PHY_CABLE_LENGTH_A,
1019 EFX_BIST_PHY_CABLE_LENGTH_B,
1020 EFX_BIST_PHY_CABLE_LENGTH_C,
1021 EFX_BIST_PHY_CABLE_LENGTH_D,
1022 EFX_BIST_PHY_CABLE_STATUS_A,
1023 EFX_BIST_PHY_CABLE_STATUS_B,
1024 EFX_BIST_PHY_CABLE_STATUS_C,
1025 EFX_BIST_PHY_CABLE_STATUS_D,
1026 EFX_BIST_FAULT_CODE,
1028 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1034 EFX_BIST_MEM_EXPECT,
1035 EFX_BIST_MEM_ACTUAL,
1037 EFX_BIST_MEM_ECC_PARITY,
1038 EFX_BIST_MEM_ECC_FATAL,
1042 extern __checkReturn efx_rc_t
1043 efx_bist_enable_offline(
1044 __in efx_nic_t *enp);
1046 extern __checkReturn efx_rc_t
1048 __in efx_nic_t *enp,
1049 __in efx_bist_type_t type);
1051 extern __checkReturn efx_rc_t
1053 __in efx_nic_t *enp,
1054 __in efx_bist_type_t type,
1055 __out efx_bist_result_t *resultp,
1056 __out_opt uint32_t *value_maskp,
1057 __out_ecount_opt(count) unsigned long *valuesp,
1062 __in efx_nic_t *enp,
1063 __in efx_bist_type_t type);
1065 #endif /* EFSYS_OPT_BIST */
1067 #define EFX_FEATURE_IPV6 0x00000001
1068 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1069 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1070 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1071 #define EFX_FEATURE_MCDI 0x00000020
1072 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1073 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1074 #define EFX_FEATURE_TURBO 0x00000100
1075 #define EFX_FEATURE_MCDI_DMA 0x00000200
1076 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1077 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1078 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1079 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1080 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1082 typedef enum efx_tunnel_protocol_e {
1083 EFX_TUNNEL_PROTOCOL_NONE = 0,
1084 EFX_TUNNEL_PROTOCOL_VXLAN,
1085 EFX_TUNNEL_PROTOCOL_GENEVE,
1086 EFX_TUNNEL_PROTOCOL_NVGRE,
1088 } efx_tunnel_protocol_t;
1090 typedef struct efx_nic_cfg_s {
1091 uint32_t enc_board_type;
1092 uint32_t enc_phy_type;
1094 char enc_phy_name[21];
1096 char enc_phy_revision[21];
1097 efx_mon_type_t enc_mon_type;
1098 #if EFSYS_OPT_MON_STATS
1099 uint32_t enc_mon_stat_dma_buf_size;
1100 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1102 unsigned int enc_features;
1103 uint8_t enc_mac_addr[6];
1104 uint8_t enc_port; /* PHY port number */
1105 uint32_t enc_intr_vec_base;
1106 uint32_t enc_intr_limit;
1107 uint32_t enc_evq_limit;
1108 uint32_t enc_txq_limit;
1109 uint32_t enc_rxq_limit;
1110 uint32_t enc_txq_max_ndescs;
1111 uint32_t enc_buftbl_limit;
1112 uint32_t enc_piobuf_limit;
1113 uint32_t enc_piobuf_size;
1114 uint32_t enc_piobuf_min_alloc_size;
1115 uint32_t enc_evq_timer_quantum_ns;
1116 uint32_t enc_evq_timer_max_us;
1117 uint32_t enc_clk_mult;
1118 uint32_t enc_rx_prefix_size;
1119 uint32_t enc_rx_buf_align_start;
1120 uint32_t enc_rx_buf_align_end;
1121 uint32_t enc_rx_scale_max_exclusive_contexts;
1122 #if EFSYS_OPT_LOOPBACK
1123 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1124 #endif /* EFSYS_OPT_LOOPBACK */
1125 #if EFSYS_OPT_PHY_FLAGS
1126 uint32_t enc_phy_flags_mask;
1127 #endif /* EFSYS_OPT_PHY_FLAGS */
1128 #if EFSYS_OPT_PHY_LED_CONTROL
1129 uint32_t enc_led_mask;
1130 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1131 #if EFSYS_OPT_PHY_STATS
1132 uint64_t enc_phy_stat_mask;
1133 #endif /* EFSYS_OPT_PHY_STATS */
1135 uint8_t enc_mcdi_mdio_channel;
1136 #if EFSYS_OPT_PHY_STATS
1137 uint32_t enc_mcdi_phy_stat_mask;
1138 #endif /* EFSYS_OPT_PHY_STATS */
1139 #if EFSYS_OPT_MON_STATS
1140 uint32_t *enc_mcdi_sensor_maskp;
1141 uint32_t enc_mcdi_sensor_mask_size;
1142 #endif /* EFSYS_OPT_MON_STATS */
1143 #endif /* EFSYS_OPT_MCDI */
1145 uint32_t enc_bist_mask;
1146 #endif /* EFSYS_OPT_BIST */
1147 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1150 uint32_t enc_privilege_mask;
1151 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1152 boolean_t enc_bug26807_workaround;
1153 boolean_t enc_bug35388_workaround;
1154 boolean_t enc_bug41750_workaround;
1155 boolean_t enc_bug61265_workaround;
1156 boolean_t enc_rx_batching_enabled;
1157 /* Maximum number of descriptors completed in an rx event. */
1158 uint32_t enc_rx_batch_max;
1159 /* Number of rx descriptors the hardware requires for a push. */
1160 uint32_t enc_rx_push_align;
1161 /* Maximum amount of data in DMA descriptor */
1162 uint32_t enc_tx_dma_desc_size_max;
1164 * Boundary which DMA descriptor data must not cross or 0 if no
1167 uint32_t enc_tx_dma_desc_boundary;
1169 * Maximum number of bytes into the packet the TCP header can start for
1170 * the hardware to apply TSO packet edits.
1172 uint32_t enc_tx_tso_tcp_header_offset_limit;
1173 boolean_t enc_fw_assisted_tso_enabled;
1174 boolean_t enc_fw_assisted_tso_v2_enabled;
1175 /* Number of TSO contexts on the NIC (FATSOv2) */
1176 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1177 boolean_t enc_hw_tx_insert_vlan_enabled;
1178 /* Number of PFs on the NIC */
1179 uint32_t enc_hw_pf_count;
1180 /* Datapath firmware vadapter/vport/vswitch support */
1181 boolean_t enc_datapath_cap_evb;
1182 boolean_t enc_rx_disable_scatter_supported;
1183 boolean_t enc_allow_set_mac_with_installed_filters;
1184 boolean_t enc_enhanced_set_mac_supported;
1185 boolean_t enc_init_evq_v2_supported;
1186 boolean_t enc_rx_packed_stream_supported;
1187 boolean_t enc_rx_var_packed_stream_supported;
1188 boolean_t enc_pm_and_rxdp_counters;
1189 boolean_t enc_mac_stats_40g_tx_size_bins;
1190 uint32_t enc_tunnel_encapsulations_supported;
1192 * NIC global maximum for unique UDP tunnel ports shared by all
1195 uint32_t enc_tunnel_config_udp_entries_max;
1196 /* External port identifier */
1197 uint8_t enc_external_port;
1198 uint32_t enc_mcdi_max_payload_length;
1199 /* VPD may be per-PF or global */
1200 boolean_t enc_vpd_is_global;
1201 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1202 uint32_t enc_required_pcie_bandwidth_mbps;
1203 uint32_t enc_max_pcie_link_gen;
1204 /* Firmware verifies integrity of NVRAM updates */
1205 uint32_t enc_nvram_update_verify_result_supported;
1208 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1209 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1211 #define EFX_PCI_FUNCTION(_encp) \
1212 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1214 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1216 extern const efx_nic_cfg_t *
1218 __in efx_nic_t *enp);
1220 typedef struct efx_nic_fw_info_s {
1221 /* Basic FW version information */
1222 uint16_t enfi_mc_fw_version[4];
1224 * If datapath capabilities can be detected,
1225 * additional FW information is to be shown
1227 boolean_t enfi_dpcpu_fw_ids_valid;
1228 /* Rx and Tx datapath CPU FW IDs */
1229 uint16_t enfi_rx_dpcpu_fw_id;
1230 uint16_t enfi_tx_dpcpu_fw_id;
1231 } efx_nic_fw_info_t;
1233 extern __checkReturn efx_rc_t
1234 efx_nic_get_fw_version(
1235 __in efx_nic_t *enp,
1236 __out efx_nic_fw_info_t *enfip);
1238 /* Driver resource limits (minimum required/maximum usable). */
1239 typedef struct efx_drv_limits_s {
1240 uint32_t edl_min_evq_count;
1241 uint32_t edl_max_evq_count;
1243 uint32_t edl_min_rxq_count;
1244 uint32_t edl_max_rxq_count;
1246 uint32_t edl_min_txq_count;
1247 uint32_t edl_max_txq_count;
1249 /* PIO blocks (sub-allocated from piobuf) */
1250 uint32_t edl_min_pio_alloc_size;
1251 uint32_t edl_max_pio_alloc_count;
1254 extern __checkReturn efx_rc_t
1255 efx_nic_set_drv_limits(
1256 __inout efx_nic_t *enp,
1257 __in efx_drv_limits_t *edlp);
1259 typedef enum efx_nic_region_e {
1260 EFX_REGION_VI, /* Memory BAR UC mapping */
1261 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1264 extern __checkReturn efx_rc_t
1265 efx_nic_get_bar_region(
1266 __in efx_nic_t *enp,
1267 __in efx_nic_region_t region,
1268 __out uint32_t *offsetp,
1269 __out size_t *sizep);
1271 extern __checkReturn efx_rc_t
1272 efx_nic_get_vi_pool(
1273 __in efx_nic_t *enp,
1274 __out uint32_t *evq_countp,
1275 __out uint32_t *rxq_countp,
1276 __out uint32_t *txq_countp);
1281 typedef enum efx_vpd_tag_e {
1288 typedef uint16_t efx_vpd_keyword_t;
1290 typedef struct efx_vpd_value_s {
1291 efx_vpd_tag_t evv_tag;
1292 efx_vpd_keyword_t evv_keyword;
1294 uint8_t evv_value[0x100];
1298 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1300 extern __checkReturn efx_rc_t
1302 __in efx_nic_t *enp);
1304 extern __checkReturn efx_rc_t
1306 __in efx_nic_t *enp,
1307 __out size_t *sizep);
1309 extern __checkReturn efx_rc_t
1311 __in efx_nic_t *enp,
1312 __out_bcount(size) caddr_t data,
1315 extern __checkReturn efx_rc_t
1317 __in efx_nic_t *enp,
1318 __in_bcount(size) caddr_t data,
1321 extern __checkReturn efx_rc_t
1323 __in efx_nic_t *enp,
1324 __in_bcount(size) caddr_t data,
1327 extern __checkReturn efx_rc_t
1329 __in efx_nic_t *enp,
1330 __in_bcount(size) caddr_t data,
1332 __inout efx_vpd_value_t *evvp);
1334 extern __checkReturn efx_rc_t
1336 __in efx_nic_t *enp,
1337 __inout_bcount(size) caddr_t data,
1339 __in efx_vpd_value_t *evvp);
1341 extern __checkReturn efx_rc_t
1343 __in efx_nic_t *enp,
1344 __inout_bcount(size) caddr_t data,
1346 __out efx_vpd_value_t *evvp,
1347 __inout unsigned int *contp);
1349 extern __checkReturn efx_rc_t
1351 __in efx_nic_t *enp,
1352 __in_bcount(size) caddr_t data,
1357 __in efx_nic_t *enp);
1359 #endif /* EFSYS_OPT_VPD */
1365 typedef enum efx_nvram_type_e {
1366 EFX_NVRAM_INVALID = 0,
1368 EFX_NVRAM_BOOTROM_CFG,
1369 EFX_NVRAM_MC_FIRMWARE,
1370 EFX_NVRAM_MC_GOLDEN,
1376 EFX_NVRAM_FPGA_BACKUP,
1377 EFX_NVRAM_DYNAMIC_CFG,
1380 EFX_NVRAM_MUM_FIRMWARE,
1384 extern __checkReturn efx_rc_t
1386 __in efx_nic_t *enp);
1390 extern __checkReturn efx_rc_t
1392 __in efx_nic_t *enp);
1394 #endif /* EFSYS_OPT_DIAG */
1396 extern __checkReturn efx_rc_t
1398 __in efx_nic_t *enp,
1399 __in efx_nvram_type_t type,
1400 __out size_t *sizep);
1402 extern __checkReturn efx_rc_t
1404 __in efx_nic_t *enp,
1405 __in efx_nvram_type_t type,
1406 __out_opt size_t *pref_chunkp);
1408 extern __checkReturn efx_rc_t
1409 efx_nvram_rw_finish(
1410 __in efx_nic_t *enp,
1411 __in efx_nvram_type_t type,
1412 __out_opt uint32_t *verify_resultp);
1414 extern __checkReturn efx_rc_t
1415 efx_nvram_get_version(
1416 __in efx_nic_t *enp,
1417 __in efx_nvram_type_t type,
1418 __out uint32_t *subtypep,
1419 __out_ecount(4) uint16_t version[4]);
1421 extern __checkReturn efx_rc_t
1422 efx_nvram_read_chunk(
1423 __in efx_nic_t *enp,
1424 __in efx_nvram_type_t type,
1425 __in unsigned int offset,
1426 __out_bcount(size) caddr_t data,
1429 extern __checkReturn efx_rc_t
1430 efx_nvram_read_backup(
1431 __in efx_nic_t *enp,
1432 __in efx_nvram_type_t type,
1433 __in unsigned int offset,
1434 __out_bcount(size) caddr_t data,
1437 extern __checkReturn efx_rc_t
1438 efx_nvram_set_version(
1439 __in efx_nic_t *enp,
1440 __in efx_nvram_type_t type,
1441 __in_ecount(4) uint16_t version[4]);
1443 extern __checkReturn efx_rc_t
1445 __in efx_nic_t *enp,
1446 __in efx_nvram_type_t type,
1447 __in_bcount(partn_size) caddr_t partn_data,
1448 __in size_t partn_size);
1450 extern __checkReturn efx_rc_t
1452 __in efx_nic_t *enp,
1453 __in efx_nvram_type_t type);
1455 extern __checkReturn efx_rc_t
1456 efx_nvram_write_chunk(
1457 __in efx_nic_t *enp,
1458 __in efx_nvram_type_t type,
1459 __in unsigned int offset,
1460 __in_bcount(size) caddr_t data,
1465 __in efx_nic_t *enp);
1467 #endif /* EFSYS_OPT_NVRAM */
1469 #if EFSYS_OPT_BOOTCFG
1471 /* Report size and offset of bootcfg sector in NVRAM partition. */
1472 extern __checkReturn efx_rc_t
1473 efx_bootcfg_sector_info(
1474 __in efx_nic_t *enp,
1476 __out_opt uint32_t *sector_countp,
1477 __out size_t *offsetp,
1478 __out size_t *max_sizep);
1481 * Copy bootcfg sector data to a target buffer which may differ in size.
1482 * Optionally corrects format errors in source buffer.
1485 efx_bootcfg_copy_sector(
1486 __in efx_nic_t *enp,
1487 __inout_bcount(sector_length)
1489 __in size_t sector_length,
1490 __out_bcount(data_size) uint8_t *data,
1491 __in size_t data_size,
1492 __in boolean_t handle_format_errors);
1496 __in efx_nic_t *enp,
1497 __out_bcount(size) uint8_t *data,
1502 __in efx_nic_t *enp,
1503 __in_bcount(size) uint8_t *data,
1506 #endif /* EFSYS_OPT_BOOTCFG */
1510 typedef enum efx_pattern_type_t {
1511 EFX_PATTERN_BYTE_INCREMENT = 0,
1512 EFX_PATTERN_ALL_THE_SAME,
1513 EFX_PATTERN_BIT_ALTERNATE,
1514 EFX_PATTERN_BYTE_ALTERNATE,
1515 EFX_PATTERN_BYTE_CHANGING,
1516 EFX_PATTERN_BIT_SWEEP,
1518 } efx_pattern_type_t;
1521 (*efx_sram_pattern_fn_t)(
1523 __in boolean_t negate,
1524 __out efx_qword_t *eqp);
1526 extern __checkReturn efx_rc_t
1528 __in efx_nic_t *enp,
1529 __in efx_pattern_type_t type);
1531 #endif /* EFSYS_OPT_DIAG */
1533 extern __checkReturn efx_rc_t
1534 efx_sram_buf_tbl_set(
1535 __in efx_nic_t *enp,
1537 __in efsys_mem_t *esmp,
1541 efx_sram_buf_tbl_clear(
1542 __in efx_nic_t *enp,
1546 #define EFX_BUF_TBL_SIZE 0x20000
1548 #define EFX_BUF_SIZE 4096
1552 typedef struct efx_evq_s efx_evq_t;
1554 #if EFSYS_OPT_QSTATS
1556 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1557 typedef enum efx_ev_qstat_e {
1563 EV_RX_PAUSE_FRM_ERR,
1564 EV_RX_BUF_OWNER_ID_ERR,
1565 EV_RX_IPV4_HDR_CHKSUM_ERR,
1566 EV_RX_TCP_UDP_CHKSUM_ERR,
1570 EV_RX_MCAST_HASH_MATCH,
1587 EV_DRIVER_SRM_UPD_DONE,
1588 EV_DRIVER_TX_DESCQ_FLS_DONE,
1589 EV_DRIVER_RX_DESCQ_FLS_DONE,
1590 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1591 EV_DRIVER_RX_DSC_ERROR,
1592 EV_DRIVER_TX_DSC_ERROR,
1598 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1600 #endif /* EFSYS_OPT_QSTATS */
1602 extern __checkReturn efx_rc_t
1604 __in efx_nic_t *enp);
1608 __in efx_nic_t *enp);
1610 #define EFX_EVQ_MAXNEVS 32768
1611 #define EFX_EVQ_MINNEVS 512
1613 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1614 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1616 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1617 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1618 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1619 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1621 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1622 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1623 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1625 extern __checkReturn efx_rc_t
1627 __in efx_nic_t *enp,
1628 __in unsigned int index,
1629 __in efsys_mem_t *esmp,
1633 __in uint32_t flags,
1634 __deref_out efx_evq_t **eepp);
1638 __in efx_evq_t *eep,
1639 __in uint16_t data);
1641 typedef __checkReturn boolean_t
1642 (*efx_initialized_ev_t)(
1643 __in_opt void *arg);
1645 #define EFX_PKT_UNICAST 0x0004
1646 #define EFX_PKT_START 0x0008
1648 #define EFX_PKT_VLAN_TAGGED 0x0010
1649 #define EFX_CKSUM_TCPUDP 0x0020
1650 #define EFX_CKSUM_IPV4 0x0040
1651 #define EFX_PKT_CONT 0x0080
1653 #define EFX_CHECK_VLAN 0x0100
1654 #define EFX_PKT_TCP 0x0200
1655 #define EFX_PKT_UDP 0x0400
1656 #define EFX_PKT_IPV4 0x0800
1658 #define EFX_PKT_IPV6 0x1000
1659 #define EFX_PKT_PREFIX_LEN 0x2000
1660 #define EFX_ADDR_MISMATCH 0x4000
1661 #define EFX_DISCARD 0x8000
1664 * The following flags are used only for packed stream
1665 * mode. The values for the flags are reused to fit into 16 bit,
1666 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1667 * packed stream mode
1669 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1670 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1673 #define EFX_EV_RX_NLABELS 32
1674 #define EFX_EV_TX_NLABELS 32
1676 typedef __checkReturn boolean_t
1679 __in uint32_t label,
1682 __in uint16_t flags);
1684 #if EFSYS_OPT_RX_PACKED_STREAM
1687 * Packed stream mode is documented in SF-112241-TC.
1688 * The general idea is that, instead of putting each incoming
1689 * packet into a separate buffer which is specified in a RX
1690 * descriptor, a large buffer is provided to the hardware and
1691 * packets are put there in a continuous stream.
1692 * The main advantage of such an approach is that RX queue refilling
1693 * happens much less frequently.
1696 typedef __checkReturn boolean_t
1699 __in uint32_t label,
1701 __in uint32_t pkt_count,
1702 __in uint16_t flags);
1706 typedef __checkReturn boolean_t
1709 __in uint32_t label,
1712 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1713 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1714 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1715 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1716 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1717 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1718 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1719 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1720 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1722 typedef __checkReturn boolean_t
1723 (*efx_exception_ev_t)(
1725 __in uint32_t label,
1726 __in uint32_t data);
1728 typedef __checkReturn boolean_t
1729 (*efx_rxq_flush_done_ev_t)(
1731 __in uint32_t rxq_index);
1733 typedef __checkReturn boolean_t
1734 (*efx_rxq_flush_failed_ev_t)(
1736 __in uint32_t rxq_index);
1738 typedef __checkReturn boolean_t
1739 (*efx_txq_flush_done_ev_t)(
1741 __in uint32_t txq_index);
1743 typedef __checkReturn boolean_t
1744 (*efx_software_ev_t)(
1746 __in uint16_t magic);
1748 typedef __checkReturn boolean_t
1751 __in uint32_t code);
1753 #define EFX_SRAM_CLEAR 0
1754 #define EFX_SRAM_UPDATE 1
1755 #define EFX_SRAM_ILLEGAL_CLEAR 2
1757 typedef __checkReturn boolean_t
1758 (*efx_wake_up_ev_t)(
1760 __in uint32_t label);
1762 typedef __checkReturn boolean_t
1765 __in uint32_t label);
1767 typedef __checkReturn boolean_t
1768 (*efx_link_change_ev_t)(
1770 __in efx_link_mode_t link_mode);
1772 #if EFSYS_OPT_MON_STATS
1774 typedef __checkReturn boolean_t
1775 (*efx_monitor_ev_t)(
1777 __in efx_mon_stat_t id,
1778 __in efx_mon_stat_value_t value);
1780 #endif /* EFSYS_OPT_MON_STATS */
1782 #if EFSYS_OPT_MAC_STATS
1784 typedef __checkReturn boolean_t
1785 (*efx_mac_stats_ev_t)(
1787 __in uint32_t generation);
1789 #endif /* EFSYS_OPT_MAC_STATS */
1791 typedef struct efx_ev_callbacks_s {
1792 efx_initialized_ev_t eec_initialized;
1794 #if EFSYS_OPT_RX_PACKED_STREAM
1795 efx_rx_ps_ev_t eec_rx_ps;
1798 efx_exception_ev_t eec_exception;
1799 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1800 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1801 efx_txq_flush_done_ev_t eec_txq_flush_done;
1802 efx_software_ev_t eec_software;
1803 efx_sram_ev_t eec_sram;
1804 efx_wake_up_ev_t eec_wake_up;
1805 efx_timer_ev_t eec_timer;
1806 efx_link_change_ev_t eec_link_change;
1807 #if EFSYS_OPT_MON_STATS
1808 efx_monitor_ev_t eec_monitor;
1809 #endif /* EFSYS_OPT_MON_STATS */
1810 #if EFSYS_OPT_MAC_STATS
1811 efx_mac_stats_ev_t eec_mac_stats;
1812 #endif /* EFSYS_OPT_MAC_STATS */
1813 } efx_ev_callbacks_t;
1815 extern __checkReturn boolean_t
1817 __in efx_evq_t *eep,
1818 __in unsigned int count);
1820 #if EFSYS_OPT_EV_PREFETCH
1824 __in efx_evq_t *eep,
1825 __in unsigned int count);
1827 #endif /* EFSYS_OPT_EV_PREFETCH */
1831 __in efx_evq_t *eep,
1832 __inout unsigned int *countp,
1833 __in const efx_ev_callbacks_t *eecp,
1834 __in_opt void *arg);
1836 extern __checkReturn efx_rc_t
1837 efx_ev_usecs_to_ticks(
1838 __in efx_nic_t *enp,
1839 __in unsigned int usecs,
1840 __out unsigned int *ticksp);
1842 extern __checkReturn efx_rc_t
1844 __in efx_evq_t *eep,
1845 __in unsigned int us);
1847 extern __checkReturn efx_rc_t
1849 __in efx_evq_t *eep,
1850 __in unsigned int count);
1852 #if EFSYS_OPT_QSTATS
1858 __in efx_nic_t *enp,
1859 __in unsigned int id);
1861 #endif /* EFSYS_OPT_NAMES */
1864 efx_ev_qstats_update(
1865 __in efx_evq_t *eep,
1866 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1868 #endif /* EFSYS_OPT_QSTATS */
1872 __in efx_evq_t *eep);
1876 extern __checkReturn efx_rc_t
1878 __inout efx_nic_t *enp);
1882 __in efx_nic_t *enp);
1884 #if EFSYS_OPT_RX_SCATTER
1885 __checkReturn efx_rc_t
1886 efx_rx_scatter_enable(
1887 __in efx_nic_t *enp,
1888 __in unsigned int buf_size);
1889 #endif /* EFSYS_OPT_RX_SCATTER */
1891 /* Handle to represent use of the default RSS context. */
1892 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1894 #if EFSYS_OPT_RX_SCALE
1896 typedef enum efx_rx_hash_alg_e {
1897 EFX_RX_HASHALG_LFSR = 0,
1898 EFX_RX_HASHALG_TOEPLITZ
1899 } efx_rx_hash_alg_t;
1901 #define EFX_RX_HASH_IPV4 (1U << 0)
1902 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1903 #define EFX_RX_HASH_IPV6 (1U << 2)
1904 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1906 typedef unsigned int efx_rx_hash_type_t;
1908 typedef enum efx_rx_hash_support_e {
1909 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1910 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1911 } efx_rx_hash_support_t;
1913 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1914 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1915 #define EFX_MAXRSS 64 /* RX indirection entry range */
1916 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1918 typedef enum efx_rx_scale_context_type_e {
1919 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1920 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1921 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1922 } efx_rx_scale_context_type_t;
1924 extern __checkReturn efx_rc_t
1925 efx_rx_hash_default_support_get(
1926 __in efx_nic_t *enp,
1927 __out efx_rx_hash_support_t *supportp);
1930 extern __checkReturn efx_rc_t
1931 efx_rx_scale_default_support_get(
1932 __in efx_nic_t *enp,
1933 __out efx_rx_scale_context_type_t *typep);
1935 extern __checkReturn efx_rc_t
1936 efx_rx_scale_context_alloc(
1937 __in efx_nic_t *enp,
1938 __in efx_rx_scale_context_type_t type,
1939 __in uint32_t num_queues,
1940 __out uint32_t *rss_contextp);
1942 extern __checkReturn efx_rc_t
1943 efx_rx_scale_context_free(
1944 __in efx_nic_t *enp,
1945 __in uint32_t rss_context);
1947 extern __checkReturn efx_rc_t
1948 efx_rx_scale_mode_set(
1949 __in efx_nic_t *enp,
1950 __in uint32_t rss_context,
1951 __in efx_rx_hash_alg_t alg,
1952 __in efx_rx_hash_type_t type,
1953 __in boolean_t insert);
1955 extern __checkReturn efx_rc_t
1956 efx_rx_scale_tbl_set(
1957 __in efx_nic_t *enp,
1958 __in uint32_t rss_context,
1959 __in_ecount(n) unsigned int *table,
1962 extern __checkReturn efx_rc_t
1963 efx_rx_scale_key_set(
1964 __in efx_nic_t *enp,
1965 __in uint32_t rss_context,
1966 __in_ecount(n) uint8_t *key,
1969 extern __checkReturn uint32_t
1970 efx_pseudo_hdr_hash_get(
1971 __in efx_rxq_t *erp,
1972 __in efx_rx_hash_alg_t func,
1973 __in uint8_t *buffer);
1975 #endif /* EFSYS_OPT_RX_SCALE */
1977 extern __checkReturn efx_rc_t
1978 efx_pseudo_hdr_pkt_length_get(
1979 __in efx_rxq_t *erp,
1980 __in uint8_t *buffer,
1981 __out uint16_t *pkt_lengthp);
1983 #define EFX_RXQ_MAXNDESCS 4096
1984 #define EFX_RXQ_MINNDESCS 512
1986 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1987 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1988 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1989 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1991 typedef enum efx_rxq_type_e {
1992 EFX_RXQ_TYPE_DEFAULT,
1993 EFX_RXQ_TYPE_PACKED_STREAM,
1998 * Dummy flag to be used instead of 0 to make it clear that the argument
1999 * is receive queue flags.
2001 #define EFX_RXQ_FLAG_NONE 0x0
2002 #define EFX_RXQ_FLAG_SCATTER 0x1
2004 * If tunnels are supported and Rx event can provide information about
2005 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2006 * full-feature firmware variant running), outer classes are requested by
2007 * default. However, if the driver supports tunnels, the flag allows to
2008 * request inner classes which are required to be able to interpret inner
2009 * Rx checksum offload results.
2011 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2013 extern __checkReturn efx_rc_t
2015 __in efx_nic_t *enp,
2016 __in unsigned int index,
2017 __in unsigned int label,
2018 __in efx_rxq_type_t type,
2019 __in efsys_mem_t *esmp,
2022 __in unsigned int flags,
2023 __in efx_evq_t *eep,
2024 __deref_out efx_rxq_t **erpp);
2026 #if EFSYS_OPT_RX_PACKED_STREAM
2028 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2029 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2030 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2031 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2032 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2034 extern __checkReturn efx_rc_t
2035 efx_rx_qcreate_packed_stream(
2036 __in efx_nic_t *enp,
2037 __in unsigned int index,
2038 __in unsigned int label,
2039 __in uint32_t ps_buf_size,
2040 __in efsys_mem_t *esmp,
2042 __in efx_evq_t *eep,
2043 __deref_out efx_rxq_t **erpp);
2047 typedef struct efx_buffer_s {
2048 efsys_dma_addr_t eb_addr;
2053 typedef struct efx_desc_s {
2059 __in efx_rxq_t *erp,
2060 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2062 __in unsigned int ndescs,
2063 __in unsigned int completed,
2064 __in unsigned int added);
2068 __in efx_rxq_t *erp,
2069 __in unsigned int added,
2070 __inout unsigned int *pushedp);
2072 #if EFSYS_OPT_RX_PACKED_STREAM
2075 efx_rx_qpush_ps_credits(
2076 __in efx_rxq_t *erp);
2078 extern __checkReturn uint8_t *
2079 efx_rx_qps_packet_info(
2080 __in efx_rxq_t *erp,
2081 __in uint8_t *buffer,
2082 __in uint32_t buffer_length,
2083 __in uint32_t current_offset,
2084 __out uint16_t *lengthp,
2085 __out uint32_t *next_offsetp,
2086 __out uint32_t *timestamp);
2089 extern __checkReturn efx_rc_t
2091 __in efx_rxq_t *erp);
2095 __in efx_rxq_t *erp);
2099 __in efx_rxq_t *erp);
2103 typedef struct efx_txq_s efx_txq_t;
2105 #if EFSYS_OPT_QSTATS
2107 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2108 typedef enum efx_tx_qstat_e {
2114 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2116 #endif /* EFSYS_OPT_QSTATS */
2118 extern __checkReturn efx_rc_t
2120 __in efx_nic_t *enp);
2124 __in efx_nic_t *enp);
2126 #define EFX_TXQ_MINNDESCS 512
2128 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2129 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2130 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2132 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2134 #define EFX_TXQ_CKSUM_IPV4 0x0001
2135 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2136 #define EFX_TXQ_FATSOV2 0x0004
2137 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2138 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2140 extern __checkReturn efx_rc_t
2142 __in efx_nic_t *enp,
2143 __in unsigned int index,
2144 __in unsigned int label,
2145 __in efsys_mem_t *esmp,
2148 __in uint16_t flags,
2149 __in efx_evq_t *eep,
2150 __deref_out efx_txq_t **etpp,
2151 __out unsigned int *addedp);
2153 extern __checkReturn efx_rc_t
2155 __in efx_txq_t *etp,
2156 __in_ecount(ndescs) efx_buffer_t *eb,
2157 __in unsigned int ndescs,
2158 __in unsigned int completed,
2159 __inout unsigned int *addedp);
2161 extern __checkReturn efx_rc_t
2163 __in efx_txq_t *etp,
2164 __in unsigned int ns);
2168 __in efx_txq_t *etp,
2169 __in unsigned int added,
2170 __in unsigned int pushed);
2172 extern __checkReturn efx_rc_t
2174 __in efx_txq_t *etp);
2178 __in efx_txq_t *etp);
2180 extern __checkReturn efx_rc_t
2182 __in efx_txq_t *etp);
2185 efx_tx_qpio_disable(
2186 __in efx_txq_t *etp);
2188 extern __checkReturn efx_rc_t
2190 __in efx_txq_t *etp,
2191 __in_ecount(buf_length) uint8_t *buffer,
2192 __in size_t buf_length,
2193 __in size_t pio_buf_offset);
2195 extern __checkReturn efx_rc_t
2197 __in efx_txq_t *etp,
2198 __in size_t pkt_length,
2199 __in unsigned int completed,
2200 __inout unsigned int *addedp);
2202 extern __checkReturn efx_rc_t
2204 __in efx_txq_t *etp,
2205 __in_ecount(n) efx_desc_t *ed,
2206 __in unsigned int n,
2207 __in unsigned int completed,
2208 __inout unsigned int *addedp);
2211 efx_tx_qdesc_dma_create(
2212 __in efx_txq_t *etp,
2213 __in efsys_dma_addr_t addr,
2216 __out efx_desc_t *edp);
2219 efx_tx_qdesc_tso_create(
2220 __in efx_txq_t *etp,
2221 __in uint16_t ipv4_id,
2222 __in uint32_t tcp_seq,
2223 __in uint8_t tcp_flags,
2224 __out efx_desc_t *edp);
2226 /* Number of FATSOv2 option descriptors */
2227 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2229 /* Maximum number of DMA segments per TSO packet (not superframe) */
2230 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2233 efx_tx_qdesc_tso2_create(
2234 __in efx_txq_t *etp,
2235 __in uint16_t ipv4_id,
2236 __in uint32_t tcp_seq,
2237 __in uint16_t tcp_mss,
2238 __out_ecount(count) efx_desc_t *edp,
2242 efx_tx_qdesc_vlantci_create(
2243 __in efx_txq_t *etp,
2245 __out efx_desc_t *edp);
2247 #if EFSYS_OPT_QSTATS
2253 __in efx_nic_t *etp,
2254 __in unsigned int id);
2256 #endif /* EFSYS_OPT_NAMES */
2259 efx_tx_qstats_update(
2260 __in efx_txq_t *etp,
2261 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2263 #endif /* EFSYS_OPT_QSTATS */
2267 __in efx_txq_t *etp);
2272 #if EFSYS_OPT_FILTER
2274 #define EFX_ETHER_TYPE_IPV4 0x0800
2275 #define EFX_ETHER_TYPE_IPV6 0x86DD
2277 #define EFX_IPPROTO_TCP 6
2278 #define EFX_IPPROTO_UDP 17
2279 #define EFX_IPPROTO_GRE 47
2281 /* Use RSS to spread across multiple queues */
2282 #define EFX_FILTER_FLAG_RX_RSS 0x01
2283 /* Enable RX scatter */
2284 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2286 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2287 * May only be set by the filter implementation for each type.
2288 * A removal request will restore the automatic filter in its place.
2290 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2291 /* Filter is for RX */
2292 #define EFX_FILTER_FLAG_RX 0x08
2293 /* Filter is for TX */
2294 #define EFX_FILTER_FLAG_TX 0x10
2296 typedef uint8_t efx_filter_flags_t;
2299 * Flags which specify the fields to match on. The values are the same as in the
2300 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2303 /* Match by remote IP host address */
2304 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2305 /* Match by local IP host address */
2306 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2307 /* Match by remote MAC address */
2308 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2309 /* Match by remote TCP/UDP port */
2310 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2311 /* Match by remote TCP/UDP port */
2312 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2313 /* Match by local TCP/UDP port */
2314 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2315 /* Match by Ether-type */
2316 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2317 /* Match by inner VLAN ID */
2318 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2319 /* Match by outer VLAN ID */
2320 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2321 /* Match by IP transport protocol */
2322 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2323 /* For encapsulated packets, match all multicast inner frames */
2324 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2325 /* For encapsulated packets, match all unicast inner frames */
2326 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2327 /* Match otherwise-unmatched multicast and broadcast packets */
2328 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2329 /* Match otherwise-unmatched unicast packets */
2330 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2332 typedef uint32_t efx_filter_match_flags_t;
2334 typedef enum efx_filter_priority_s {
2335 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2336 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2337 * address list or hardware
2338 * requirements. This may only be used
2339 * by the filter implementation for
2341 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2342 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2343 * client (e.g. SR-IOV, HyperV VMQ etc.)
2345 } efx_filter_priority_t;
2348 * FIXME: All these fields are assumed to be in little-endian byte order.
2349 * It may be better for some to be big-endian. See bug42804.
2352 typedef struct efx_filter_spec_s {
2353 efx_filter_match_flags_t efs_match_flags;
2354 uint8_t efs_priority;
2355 efx_filter_flags_t efs_flags;
2356 uint16_t efs_dmaq_id;
2357 uint32_t efs_rss_context;
2358 uint16_t efs_outer_vid;
2359 uint16_t efs_inner_vid;
2360 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2361 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2362 uint16_t efs_ether_type;
2363 uint8_t efs_ip_proto;
2364 efx_tunnel_protocol_t efs_encap_type;
2365 uint16_t efs_loc_port;
2366 uint16_t efs_rem_port;
2367 efx_oword_t efs_rem_host;
2368 efx_oword_t efs_loc_host;
2369 } efx_filter_spec_t;
2372 /* Default values for use in filter specifications */
2373 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2374 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2376 extern __checkReturn efx_rc_t
2378 __in efx_nic_t *enp);
2382 __in efx_nic_t *enp);
2384 extern __checkReturn efx_rc_t
2386 __in efx_nic_t *enp,
2387 __inout efx_filter_spec_t *spec);
2389 extern __checkReturn efx_rc_t
2391 __in efx_nic_t *enp,
2392 __inout efx_filter_spec_t *spec);
2394 extern __checkReturn efx_rc_t
2396 __in efx_nic_t *enp);
2398 extern __checkReturn efx_rc_t
2399 efx_filter_supported_filters(
2400 __in efx_nic_t *enp,
2401 __out_ecount(buffer_length) uint32_t *buffer,
2402 __in size_t buffer_length,
2403 __out size_t *list_lengthp);
2406 efx_filter_spec_init_rx(
2407 __out efx_filter_spec_t *spec,
2408 __in efx_filter_priority_t priority,
2409 __in efx_filter_flags_t flags,
2410 __in efx_rxq_t *erp);
2413 efx_filter_spec_init_tx(
2414 __out efx_filter_spec_t *spec,
2415 __in efx_txq_t *etp);
2417 extern __checkReturn efx_rc_t
2418 efx_filter_spec_set_ipv4_local(
2419 __inout efx_filter_spec_t *spec,
2422 __in uint16_t port);
2424 extern __checkReturn efx_rc_t
2425 efx_filter_spec_set_ipv4_full(
2426 __inout efx_filter_spec_t *spec,
2428 __in uint32_t lhost,
2429 __in uint16_t lport,
2430 __in uint32_t rhost,
2431 __in uint16_t rport);
2433 extern __checkReturn efx_rc_t
2434 efx_filter_spec_set_eth_local(
2435 __inout efx_filter_spec_t *spec,
2437 __in const uint8_t *addr);
2440 efx_filter_spec_set_ether_type(
2441 __inout efx_filter_spec_t *spec,
2442 __in uint16_t ether_type);
2444 extern __checkReturn efx_rc_t
2445 efx_filter_spec_set_uc_def(
2446 __inout efx_filter_spec_t *spec);
2448 extern __checkReturn efx_rc_t
2449 efx_filter_spec_set_mc_def(
2450 __inout efx_filter_spec_t *spec);
2452 typedef enum efx_filter_inner_frame_match_e {
2453 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2454 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2455 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2456 } efx_filter_inner_frame_match_t;
2458 extern __checkReturn efx_rc_t
2459 efx_filter_spec_set_encap_type(
2460 __inout efx_filter_spec_t *spec,
2461 __in efx_tunnel_protocol_t encap_type,
2462 __in efx_filter_inner_frame_match_t inner_frame_match);
2464 #if EFSYS_OPT_RX_SCALE
2465 extern __checkReturn efx_rc_t
2466 efx_filter_spec_set_rss_context(
2467 __inout efx_filter_spec_t *spec,
2468 __in uint32_t rss_context);
2470 #endif /* EFSYS_OPT_FILTER */
2474 extern __checkReturn uint32_t
2476 __in_ecount(count) uint32_t const *input,
2478 __in uint32_t init);
2480 extern __checkReturn uint32_t
2482 __in_ecount(length) uint8_t const *input,
2484 __in uint32_t init);
2486 #if EFSYS_OPT_LICENSING
2490 typedef struct efx_key_stats_s {
2492 uint32_t eks_invalid;
2493 uint32_t eks_blacklisted;
2494 uint32_t eks_unverifiable;
2495 uint32_t eks_wrong_node;
2496 uint32_t eks_licensed_apps_lo;
2497 uint32_t eks_licensed_apps_hi;
2498 uint32_t eks_licensed_features_lo;
2499 uint32_t eks_licensed_features_hi;
2502 extern __checkReturn efx_rc_t
2504 __in efx_nic_t *enp);
2508 __in efx_nic_t *enp);
2510 extern __checkReturn boolean_t
2511 efx_lic_check_support(
2512 __in efx_nic_t *enp);
2514 extern __checkReturn efx_rc_t
2515 efx_lic_update_licenses(
2516 __in efx_nic_t *enp);
2518 extern __checkReturn efx_rc_t
2519 efx_lic_get_key_stats(
2520 __in efx_nic_t *enp,
2521 __out efx_key_stats_t *ksp);
2523 extern __checkReturn efx_rc_t
2525 __in efx_nic_t *enp,
2526 __in uint64_t app_id,
2527 __out boolean_t *licensedp);
2529 extern __checkReturn efx_rc_t
2531 __in efx_nic_t *enp,
2532 __in size_t buffer_size,
2533 __out uint32_t *typep,
2534 __out size_t *lengthp,
2535 __out_opt uint8_t *bufferp);
2538 extern __checkReturn efx_rc_t
2540 __in efx_nic_t *enp,
2541 __in_bcount(buffer_size)
2543 __in size_t buffer_size,
2544 __out uint32_t *startp);
2546 extern __checkReturn efx_rc_t
2548 __in efx_nic_t *enp,
2549 __in_bcount(buffer_size)
2551 __in size_t buffer_size,
2552 __in uint32_t offset,
2553 __out uint32_t *endp);
2555 extern __checkReturn __success(return != B_FALSE) boolean_t
2557 __in efx_nic_t *enp,
2558 __in_bcount(buffer_size)
2560 __in size_t buffer_size,
2561 __in uint32_t offset,
2562 __out uint32_t *startp,
2563 __out uint32_t *lengthp);
2565 extern __checkReturn __success(return != B_FALSE) boolean_t
2566 efx_lic_validate_key(
2567 __in efx_nic_t *enp,
2568 __in_bcount(length) caddr_t keyp,
2569 __in uint32_t length);
2571 extern __checkReturn efx_rc_t
2573 __in efx_nic_t *enp,
2574 __in_bcount(buffer_size)
2576 __in size_t buffer_size,
2577 __in uint32_t offset,
2578 __in uint32_t length,
2579 __out_bcount_part(key_max_size, *lengthp)
2581 __in size_t key_max_size,
2582 __out uint32_t *lengthp);
2584 extern __checkReturn efx_rc_t
2586 __in efx_nic_t *enp,
2587 __in_bcount(buffer_size)
2589 __in size_t buffer_size,
2590 __in uint32_t offset,
2591 __in_bcount(length) caddr_t keyp,
2592 __in uint32_t length,
2593 __out uint32_t *lengthp);
2595 __checkReturn efx_rc_t
2597 __in efx_nic_t *enp,
2598 __in_bcount(buffer_size)
2600 __in size_t buffer_size,
2601 __in uint32_t offset,
2602 __in uint32_t length,
2604 __out uint32_t *deltap);
2606 extern __checkReturn efx_rc_t
2607 efx_lic_create_partition(
2608 __in efx_nic_t *enp,
2609 __in_bcount(buffer_size)
2611 __in size_t buffer_size);
2613 extern __checkReturn efx_rc_t
2614 efx_lic_finish_partition(
2615 __in efx_nic_t *enp,
2616 __in_bcount(buffer_size)
2618 __in size_t buffer_size);
2620 #endif /* EFSYS_OPT_LICENSING */
2624 #if EFSYS_OPT_TUNNEL
2626 extern __checkReturn efx_rc_t
2628 __in efx_nic_t *enp);
2632 __in efx_nic_t *enp);
2635 * For overlay network encapsulation using UDP, the firmware needs to know
2636 * the configured UDP port for the overlay so it can decode encapsulated
2638 * The UDP port/protocol list is global.
2641 extern __checkReturn efx_rc_t
2642 efx_tunnel_config_udp_add(
2643 __in efx_nic_t *enp,
2644 __in uint16_t port /* host/cpu-endian */,
2645 __in efx_tunnel_protocol_t protocol);
2647 extern __checkReturn efx_rc_t
2648 efx_tunnel_config_udp_remove(
2649 __in efx_nic_t *enp,
2650 __in uint16_t port /* host/cpu-endian */,
2651 __in efx_tunnel_protocol_t protocol);
2654 efx_tunnel_config_clear(
2655 __in efx_nic_t *enp);
2658 * Apply tunnel UDP ports configuration to hardware.
2660 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2663 extern __checkReturn efx_rc_t
2664 efx_tunnel_reconfigure(
2665 __in efx_nic_t *enp);
2667 #endif /* EFSYS_OPT_TUNNEL */
2674 #endif /* _SYS_EFX_H */