1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 extern __checkReturn efx_rc_t
134 __in efx_nic_t *enp);
136 extern __checkReturn efx_rc_t
138 __in efx_nic_t *enp);
140 extern __checkReturn efx_rc_t
142 __in efx_nic_t *enp);
146 extern __checkReturn efx_rc_t
147 efx_nic_register_test(
148 __in efx_nic_t *enp);
150 #endif /* EFSYS_OPT_DIAG */
154 __in efx_nic_t *enp);
158 __in efx_nic_t *enp);
162 __in efx_nic_t *enp);
164 #define EFX_PCIE_LINK_SPEED_GEN1 1
165 #define EFX_PCIE_LINK_SPEED_GEN2 2
166 #define EFX_PCIE_LINK_SPEED_GEN3 3
168 typedef enum efx_pcie_link_performance_e {
169 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
170 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
171 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
172 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
173 } efx_pcie_link_performance_t;
175 extern __checkReturn efx_rc_t
176 efx_nic_calculate_pcie_link_bandwidth(
177 __in uint32_t pcie_link_width,
178 __in uint32_t pcie_link_gen,
179 __out uint32_t *bandwidth_mbpsp);
181 extern __checkReturn efx_rc_t
182 efx_nic_check_pcie_link_speed(
184 __in uint32_t pcie_link_width,
185 __in uint32_t pcie_link_gen,
186 __out efx_pcie_link_performance_t *resultp);
190 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
191 /* Huntington and Medford require MCDIv2 commands */
192 #define WITH_MCDI_V2 1
195 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
197 typedef enum efx_mcdi_exception_e {
198 EFX_MCDI_EXCEPTION_MC_REBOOT,
199 EFX_MCDI_EXCEPTION_MC_BADASSERT,
200 } efx_mcdi_exception_t;
202 #if EFSYS_OPT_MCDI_LOGGING
203 typedef enum efx_log_msg_e {
205 EFX_LOG_MCDI_REQUEST,
206 EFX_LOG_MCDI_RESPONSE,
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
210 typedef struct efx_mcdi_transport_s {
212 efsys_mem_t *emt_dma_mem;
213 void (*emt_execute)(void *, efx_mcdi_req_t *);
214 void (*emt_ev_cpl)(void *);
215 void (*emt_exception)(void *, efx_mcdi_exception_t);
216 #if EFSYS_OPT_MCDI_LOGGING
217 void (*emt_logger)(void *, efx_log_msg_t,
218 void *, size_t, void *, size_t);
219 #endif /* EFSYS_OPT_MCDI_LOGGING */
220 #if EFSYS_OPT_MCDI_PROXY_AUTH
221 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
222 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
223 } efx_mcdi_transport_t;
225 extern __checkReturn efx_rc_t
228 __in const efx_mcdi_transport_t *mtp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
236 __in efx_nic_t *enp);
239 efx_mcdi_get_timeout(
241 __in efx_mcdi_req_t *emrp,
242 __out uint32_t *usec_timeoutp);
245 efx_mcdi_request_start(
247 __in efx_mcdi_req_t *emrp,
248 __in boolean_t ev_cpl);
250 extern __checkReturn boolean_t
251 efx_mcdi_request_poll(
252 __in efx_nic_t *enp);
254 extern __checkReturn boolean_t
255 efx_mcdi_request_abort(
256 __in efx_nic_t *enp);
260 __in efx_nic_t *enp);
262 #endif /* EFSYS_OPT_MCDI */
266 #define EFX_NINTR_SIENA 1024
268 typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
275 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
277 extern __checkReturn efx_rc_t
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
285 __in efx_nic_t *enp);
289 __in efx_nic_t *enp);
292 efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
295 #define EFX_INTR_NEVQS 32
297 extern __checkReturn efx_rc_t
300 __in unsigned int level);
303 efx_intr_status_line(
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
309 efx_intr_status_message(
311 __in unsigned int message,
312 __out boolean_t *fatalp);
316 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
324 #if EFSYS_OPT_MAC_STATS
326 /* START MKCONFIG GENERATED EfxHeaderMacBlock 7b5f45054a3b45bc */
327 typedef enum efx_mac_stat_e {
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
409 EFX_MAC_FEC_UNCORRECTED_ERRORS,
410 EFX_MAC_FEC_CORRECTED_ERRORS,
411 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
412 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
413 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
414 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
418 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
420 #endif /* EFSYS_OPT_MAC_STATS */
422 typedef enum efx_link_mode_e {
423 EFX_LINK_UNKNOWN = 0,
439 #define EFX_MAC_ADDR_LEN 6
441 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
443 #define EFX_MAC_MULTICAST_LIST_MAX 256
445 #define EFX_MAC_SDU_MAX 9202
447 #define EFX_MAC_PDU_ADJUSTMENT \
451 + /* bug16011 */ 16) \
453 #define EFX_MAC_PDU(_sdu) \
454 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
457 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
458 * the SDU rounded up slightly.
460 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
462 #define EFX_MAC_PDU_MIN 60
463 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
465 extern __checkReturn efx_rc_t
470 extern __checkReturn efx_rc_t
475 extern __checkReturn efx_rc_t
480 extern __checkReturn efx_rc_t
483 __in boolean_t all_unicst,
484 __in boolean_t mulcst,
485 __in boolean_t all_mulcst,
486 __in boolean_t brdcst);
488 extern __checkReturn efx_rc_t
489 efx_mac_multicast_list_set(
491 __in_ecount(6*count) uint8_t const *addrs,
494 extern __checkReturn efx_rc_t
495 efx_mac_filter_default_rxq_set(
498 __in boolean_t using_rss);
501 efx_mac_filter_default_rxq_clear(
502 __in efx_nic_t *enp);
504 extern __checkReturn efx_rc_t
507 __in boolean_t enabled);
509 extern __checkReturn efx_rc_t
512 __out boolean_t *mac_upp);
514 #define EFX_FCNTL_RESPOND 0x00000001
515 #define EFX_FCNTL_GENERATE 0x00000002
517 extern __checkReturn efx_rc_t
520 __in unsigned int fcntl,
521 __in boolean_t autoneg);
526 __out unsigned int *fcntl_wantedp,
527 __out unsigned int *fcntl_linkp);
530 #if EFSYS_OPT_MAC_STATS
534 extern __checkReturn const char *
537 __in unsigned int id);
539 #endif /* EFSYS_OPT_NAMES */
541 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
543 #define EFX_MAC_STATS_MASK_NPAGES \
544 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
545 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
548 * Get mask of MAC statistics supported by the hardware.
550 * If mask_size is insufficient to return the mask, EINVAL error is
551 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
552 * (which is sizeof (uint32_t)) is sufficient.
554 extern __checkReturn efx_rc_t
555 efx_mac_stats_get_mask(
557 __out_bcount(mask_size) uint32_t *maskp,
558 __in size_t mask_size);
560 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
561 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
562 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
565 extern __checkReturn efx_rc_t
567 __in efx_nic_t *enp);
570 * Upload mac statistics supported by the hardware into the given buffer.
572 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
573 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
575 * The hardware will only DMA statistics that it understands (of course).
576 * Drivers should not make any assumptions about which statistics are
577 * supported, especially when the statistics are generated by firmware.
579 * Thus, drivers should zero this buffer before use, so that not-understood
580 * statistics read back as zero.
582 extern __checkReturn efx_rc_t
583 efx_mac_stats_upload(
585 __in efsys_mem_t *esmp);
587 extern __checkReturn efx_rc_t
588 efx_mac_stats_periodic(
590 __in efsys_mem_t *esmp,
591 __in uint16_t period_ms,
592 __in boolean_t events);
594 extern __checkReturn efx_rc_t
595 efx_mac_stats_update(
597 __in efsys_mem_t *esmp,
598 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
599 __inout_opt uint32_t *generationp);
601 #endif /* EFSYS_OPT_MAC_STATS */
605 typedef enum efx_mon_type_e {
617 __in efx_nic_t *enp);
619 #endif /* EFSYS_OPT_NAMES */
621 extern __checkReturn efx_rc_t
623 __in efx_nic_t *enp);
625 #if EFSYS_OPT_MON_STATS
627 #define EFX_MON_STATS_PAGE_SIZE 0x100
628 #define EFX_MON_MASK_ELEMENT_SIZE 32
630 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
631 typedef enum efx_mon_stat_e {
638 EFX_MON_STAT_EXT_TEMP,
639 EFX_MON_STAT_INT_TEMP,
642 EFX_MON_STAT_INT_COOLING,
643 EFX_MON_STAT_EXT_COOLING,
651 EFX_MON_STAT_AOE_TEMP,
652 EFX_MON_STAT_PSU_AOE_TEMP,
653 EFX_MON_STAT_PSU_TEMP,
659 EFX_MON_STAT_VAOE_IN,
661 EFX_MON_STAT_IAOE_IN,
662 EFX_MON_STAT_NIC_POWER,
666 EFX_MON_STAT_0_9V_ADC,
667 EFX_MON_STAT_INT_TEMP2,
668 EFX_MON_STAT_VREG_TEMP,
669 EFX_MON_STAT_VREG_0_9V_TEMP,
670 EFX_MON_STAT_VREG_1_2V_TEMP,
671 EFX_MON_STAT_INT_VPTAT,
672 EFX_MON_STAT_INT_ADC_TEMP,
673 EFX_MON_STAT_EXT_VPTAT,
674 EFX_MON_STAT_EXT_ADC_TEMP,
675 EFX_MON_STAT_AMBIENT_TEMP,
676 EFX_MON_STAT_AIRFLOW,
677 EFX_MON_STAT_VDD08D_VSS08D_CSR,
678 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
679 EFX_MON_STAT_HOTPOINT_TEMP,
680 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
681 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
682 EFX_MON_STAT_MUM_VCC,
685 EFX_MON_STAT_0V9_A_TEMP,
688 EFX_MON_STAT_0V9_B_TEMP,
689 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
690 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
691 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
692 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
693 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
694 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
695 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
696 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
697 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
698 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
699 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
700 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
701 EFX_MON_STAT_SODIMM_VOUT,
702 EFX_MON_STAT_SODIMM_0_TEMP,
703 EFX_MON_STAT_SODIMM_1_TEMP,
704 EFX_MON_STAT_PHY0_VCC,
705 EFX_MON_STAT_PHY1_VCC,
706 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
707 EFX_MON_STAT_BOARD_FRONT_TEMP,
708 EFX_MON_STAT_BOARD_BACK_TEMP,
718 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
720 typedef enum efx_mon_stat_state_e {
721 EFX_MON_STAT_STATE_OK = 0,
722 EFX_MON_STAT_STATE_WARNING = 1,
723 EFX_MON_STAT_STATE_FATAL = 2,
724 EFX_MON_STAT_STATE_BROKEN = 3,
725 EFX_MON_STAT_STATE_NO_READING = 4,
726 } efx_mon_stat_state_t;
728 typedef struct efx_mon_stat_value_s {
731 } efx_mon_stat_value_t;
738 __in efx_mon_stat_t id);
740 #endif /* EFSYS_OPT_NAMES */
742 extern __checkReturn efx_rc_t
743 efx_mon_stats_update(
745 __in efsys_mem_t *esmp,
746 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
748 #endif /* EFSYS_OPT_MON_STATS */
752 __in efx_nic_t *enp);
756 extern __checkReturn efx_rc_t
758 __in efx_nic_t *enp);
760 #if EFSYS_OPT_PHY_LED_CONTROL
762 typedef enum efx_phy_led_mode_e {
763 EFX_PHY_LED_DEFAULT = 0,
768 } efx_phy_led_mode_t;
770 extern __checkReturn efx_rc_t
773 __in efx_phy_led_mode_t mode);
775 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
777 extern __checkReturn efx_rc_t
779 __in efx_nic_t *enp);
781 #if EFSYS_OPT_LOOPBACK
783 typedef enum efx_loopback_type_e {
784 EFX_LOOPBACK_OFF = 0,
785 EFX_LOOPBACK_DATA = 1,
786 EFX_LOOPBACK_GMAC = 2,
787 EFX_LOOPBACK_XGMII = 3,
788 EFX_LOOPBACK_XGXS = 4,
789 EFX_LOOPBACK_XAUI = 5,
790 EFX_LOOPBACK_GMII = 6,
791 EFX_LOOPBACK_SGMII = 7,
792 EFX_LOOPBACK_XGBR = 8,
793 EFX_LOOPBACK_XFI = 9,
794 EFX_LOOPBACK_XAUI_FAR = 10,
795 EFX_LOOPBACK_GMII_FAR = 11,
796 EFX_LOOPBACK_SGMII_FAR = 12,
797 EFX_LOOPBACK_XFI_FAR = 13,
798 EFX_LOOPBACK_GPHY = 14,
799 EFX_LOOPBACK_PHY_XS = 15,
800 EFX_LOOPBACK_PCS = 16,
801 EFX_LOOPBACK_PMA_PMD = 17,
802 EFX_LOOPBACK_XPORT = 18,
803 EFX_LOOPBACK_XGMII_WS = 19,
804 EFX_LOOPBACK_XAUI_WS = 20,
805 EFX_LOOPBACK_XAUI_WS_FAR = 21,
806 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
807 EFX_LOOPBACK_GMII_WS = 23,
808 EFX_LOOPBACK_XFI_WS = 24,
809 EFX_LOOPBACK_XFI_WS_FAR = 25,
810 EFX_LOOPBACK_PHYXS_WS = 26,
811 EFX_LOOPBACK_PMA_INT = 27,
812 EFX_LOOPBACK_SD_NEAR = 28,
813 EFX_LOOPBACK_SD_FAR = 29,
814 EFX_LOOPBACK_PMA_INT_WS = 30,
815 EFX_LOOPBACK_SD_FEP2_WS = 31,
816 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
817 EFX_LOOPBACK_SD_FEP_WS = 33,
818 EFX_LOOPBACK_SD_FES_WS = 34,
819 EFX_LOOPBACK_AOE_INT_NEAR = 35,
820 EFX_LOOPBACK_DATA_WS = 36,
821 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
823 } efx_loopback_type_t;
825 typedef enum efx_loopback_kind_e {
826 EFX_LOOPBACK_KIND_OFF = 0,
827 EFX_LOOPBACK_KIND_ALL,
828 EFX_LOOPBACK_KIND_MAC,
829 EFX_LOOPBACK_KIND_PHY,
831 } efx_loopback_kind_t;
835 __in efx_loopback_kind_t loopback_kind,
836 __out efx_qword_t *maskp);
838 extern __checkReturn efx_rc_t
839 efx_port_loopback_set(
841 __in efx_link_mode_t link_mode,
842 __in efx_loopback_type_t type);
846 extern __checkReturn const char *
847 efx_loopback_type_name(
849 __in efx_loopback_type_t type);
851 #endif /* EFSYS_OPT_NAMES */
853 #endif /* EFSYS_OPT_LOOPBACK */
855 extern __checkReturn efx_rc_t
858 __out_opt efx_link_mode_t *link_modep);
862 __in efx_nic_t *enp);
864 typedef enum efx_phy_cap_type_e {
865 EFX_PHY_CAP_INVALID = 0,
872 EFX_PHY_CAP_10000FDX,
876 EFX_PHY_CAP_40000FDX,
878 EFX_PHY_CAP_100000FDX,
879 EFX_PHY_CAP_25000FDX,
880 EFX_PHY_CAP_50000FDX,
881 EFX_PHY_CAP_BASER_FEC,
882 EFX_PHY_CAP_BASER_FEC_REQUESTED,
884 EFX_PHY_CAP_RS_FEC_REQUESTED,
885 EFX_PHY_CAP_25G_BASER_FEC,
886 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
888 } efx_phy_cap_type_t;
891 #define EFX_PHY_CAP_CURRENT 0x00000000
892 #define EFX_PHY_CAP_DEFAULT 0x00000001
893 #define EFX_PHY_CAP_PERM 0x00000002
899 __out uint32_t *maskp);
901 extern __checkReturn efx_rc_t
909 __out uint32_t *maskp);
911 extern __checkReturn efx_rc_t
914 __out uint32_t *ouip);
916 typedef enum efx_phy_media_type_e {
917 EFX_PHY_MEDIA_INVALID = 0,
922 EFX_PHY_MEDIA_SFP_PLUS,
923 EFX_PHY_MEDIA_BASE_T,
924 EFX_PHY_MEDIA_QSFP_PLUS,
926 } efx_phy_media_type_t;
929 * Get the type of medium currently used. If the board has ports for
930 * modules, a module is present, and we recognise the media type of
931 * the module, then this will be the media type of the module.
932 * Otherwise it will be the media type of the port.
935 efx_phy_media_type_get(
937 __out efx_phy_media_type_t *typep);
939 extern __checkReturn efx_rc_t
940 efx_phy_module_get_info(
942 __in uint8_t dev_addr,
945 __out_bcount(len) uint8_t *data);
947 #if EFSYS_OPT_PHY_STATS
949 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
950 typedef enum efx_phy_stat_e {
952 EFX_PHY_STAT_PMA_PMD_LINK_UP,
953 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
954 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
955 EFX_PHY_STAT_PMA_PMD_REV_A,
956 EFX_PHY_STAT_PMA_PMD_REV_B,
957 EFX_PHY_STAT_PMA_PMD_REV_C,
958 EFX_PHY_STAT_PMA_PMD_REV_D,
959 EFX_PHY_STAT_PCS_LINK_UP,
960 EFX_PHY_STAT_PCS_RX_FAULT,
961 EFX_PHY_STAT_PCS_TX_FAULT,
962 EFX_PHY_STAT_PCS_BER,
963 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
964 EFX_PHY_STAT_PHY_XS_LINK_UP,
965 EFX_PHY_STAT_PHY_XS_RX_FAULT,
966 EFX_PHY_STAT_PHY_XS_TX_FAULT,
967 EFX_PHY_STAT_PHY_XS_ALIGN,
968 EFX_PHY_STAT_PHY_XS_SYNC_A,
969 EFX_PHY_STAT_PHY_XS_SYNC_B,
970 EFX_PHY_STAT_PHY_XS_SYNC_C,
971 EFX_PHY_STAT_PHY_XS_SYNC_D,
972 EFX_PHY_STAT_AN_LINK_UP,
973 EFX_PHY_STAT_AN_MASTER,
974 EFX_PHY_STAT_AN_LOCAL_RX_OK,
975 EFX_PHY_STAT_AN_REMOTE_RX_OK,
976 EFX_PHY_STAT_CL22EXT_LINK_UP,
981 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
982 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
983 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
984 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
985 EFX_PHY_STAT_AN_COMPLETE,
986 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
987 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
988 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
989 EFX_PHY_STAT_PCS_FW_VERSION_0,
990 EFX_PHY_STAT_PCS_FW_VERSION_1,
991 EFX_PHY_STAT_PCS_FW_VERSION_2,
992 EFX_PHY_STAT_PCS_FW_VERSION_3,
993 EFX_PHY_STAT_PCS_FW_BUILD_YY,
994 EFX_PHY_STAT_PCS_FW_BUILD_MM,
995 EFX_PHY_STAT_PCS_FW_BUILD_DD,
996 EFX_PHY_STAT_PCS_OP_MODE,
1000 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1006 __in efx_nic_t *enp,
1007 __in efx_phy_stat_t stat);
1009 #endif /* EFSYS_OPT_NAMES */
1011 #define EFX_PHY_STATS_SIZE 0x100
1013 extern __checkReturn efx_rc_t
1014 efx_phy_stats_update(
1015 __in efx_nic_t *enp,
1016 __in efsys_mem_t *esmp,
1017 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1019 #endif /* EFSYS_OPT_PHY_STATS */
1024 typedef enum efx_bist_type_e {
1025 EFX_BIST_TYPE_UNKNOWN,
1026 EFX_BIST_TYPE_PHY_NORMAL,
1027 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1028 EFX_BIST_TYPE_PHY_CABLE_LONG,
1029 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1030 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1031 EFX_BIST_TYPE_REG, /* Test the register memories */
1032 EFX_BIST_TYPE_NTYPES,
1035 typedef enum efx_bist_result_e {
1036 EFX_BIST_RESULT_UNKNOWN,
1037 EFX_BIST_RESULT_RUNNING,
1038 EFX_BIST_RESULT_PASSED,
1039 EFX_BIST_RESULT_FAILED,
1040 } efx_bist_result_t;
1042 typedef enum efx_phy_cable_status_e {
1043 EFX_PHY_CABLE_STATUS_OK,
1044 EFX_PHY_CABLE_STATUS_INVALID,
1045 EFX_PHY_CABLE_STATUS_OPEN,
1046 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1047 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1048 EFX_PHY_CABLE_STATUS_BUSY,
1049 } efx_phy_cable_status_t;
1051 typedef enum efx_bist_value_e {
1052 EFX_BIST_PHY_CABLE_LENGTH_A,
1053 EFX_BIST_PHY_CABLE_LENGTH_B,
1054 EFX_BIST_PHY_CABLE_LENGTH_C,
1055 EFX_BIST_PHY_CABLE_LENGTH_D,
1056 EFX_BIST_PHY_CABLE_STATUS_A,
1057 EFX_BIST_PHY_CABLE_STATUS_B,
1058 EFX_BIST_PHY_CABLE_STATUS_C,
1059 EFX_BIST_PHY_CABLE_STATUS_D,
1060 EFX_BIST_FAULT_CODE,
1062 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1068 EFX_BIST_MEM_EXPECT,
1069 EFX_BIST_MEM_ACTUAL,
1071 EFX_BIST_MEM_ECC_PARITY,
1072 EFX_BIST_MEM_ECC_FATAL,
1076 extern __checkReturn efx_rc_t
1077 efx_bist_enable_offline(
1078 __in efx_nic_t *enp);
1080 extern __checkReturn efx_rc_t
1082 __in efx_nic_t *enp,
1083 __in efx_bist_type_t type);
1085 extern __checkReturn efx_rc_t
1087 __in efx_nic_t *enp,
1088 __in efx_bist_type_t type,
1089 __out efx_bist_result_t *resultp,
1090 __out_opt uint32_t *value_maskp,
1091 __out_ecount_opt(count) unsigned long *valuesp,
1096 __in efx_nic_t *enp,
1097 __in efx_bist_type_t type);
1099 #endif /* EFSYS_OPT_BIST */
1101 #define EFX_FEATURE_IPV6 0x00000001
1102 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1103 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1104 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1105 #define EFX_FEATURE_MCDI 0x00000020
1106 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1107 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1108 #define EFX_FEATURE_TURBO 0x00000100
1109 #define EFX_FEATURE_MCDI_DMA 0x00000200
1110 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1111 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1112 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1113 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1114 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1116 typedef enum efx_tunnel_protocol_e {
1117 EFX_TUNNEL_PROTOCOL_NONE = 0,
1118 EFX_TUNNEL_PROTOCOL_VXLAN,
1119 EFX_TUNNEL_PROTOCOL_GENEVE,
1120 EFX_TUNNEL_PROTOCOL_NVGRE,
1122 } efx_tunnel_protocol_t;
1124 typedef enum efx_vi_window_shift_e {
1125 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1126 EFX_VI_WINDOW_SHIFT_8K = 13,
1127 EFX_VI_WINDOW_SHIFT_16K = 14,
1128 EFX_VI_WINDOW_SHIFT_64K = 16,
1129 } efx_vi_window_shift_t;
1131 typedef struct efx_nic_cfg_s {
1132 uint32_t enc_board_type;
1133 uint32_t enc_phy_type;
1135 char enc_phy_name[21];
1137 char enc_phy_revision[21];
1138 efx_mon_type_t enc_mon_type;
1139 #if EFSYS_OPT_MON_STATS
1140 uint32_t enc_mon_stat_dma_buf_size;
1141 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1143 unsigned int enc_features;
1144 efx_vi_window_shift_t enc_vi_window_shift;
1145 uint8_t enc_mac_addr[6];
1146 uint8_t enc_port; /* PHY port number */
1147 uint32_t enc_intr_vec_base;
1148 uint32_t enc_intr_limit;
1149 uint32_t enc_evq_limit;
1150 uint32_t enc_txq_limit;
1151 uint32_t enc_rxq_limit;
1152 uint32_t enc_txq_max_ndescs;
1153 uint32_t enc_buftbl_limit;
1154 uint32_t enc_piobuf_limit;
1155 uint32_t enc_piobuf_size;
1156 uint32_t enc_piobuf_min_alloc_size;
1157 uint32_t enc_evq_timer_quantum_ns;
1158 uint32_t enc_evq_timer_max_us;
1159 uint32_t enc_clk_mult;
1160 uint32_t enc_rx_prefix_size;
1161 uint32_t enc_rx_buf_align_start;
1162 uint32_t enc_rx_buf_align_end;
1163 uint32_t enc_rx_scale_max_exclusive_contexts;
1164 #if EFSYS_OPT_LOOPBACK
1165 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1166 #endif /* EFSYS_OPT_LOOPBACK */
1167 #if EFSYS_OPT_PHY_FLAGS
1168 uint32_t enc_phy_flags_mask;
1169 #endif /* EFSYS_OPT_PHY_FLAGS */
1170 #if EFSYS_OPT_PHY_LED_CONTROL
1171 uint32_t enc_led_mask;
1172 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1173 #if EFSYS_OPT_PHY_STATS
1174 uint64_t enc_phy_stat_mask;
1175 #endif /* EFSYS_OPT_PHY_STATS */
1177 uint8_t enc_mcdi_mdio_channel;
1178 #if EFSYS_OPT_PHY_STATS
1179 uint32_t enc_mcdi_phy_stat_mask;
1180 #endif /* EFSYS_OPT_PHY_STATS */
1181 #if EFSYS_OPT_MON_STATS
1182 uint32_t *enc_mcdi_sensor_maskp;
1183 uint32_t enc_mcdi_sensor_mask_size;
1184 #endif /* EFSYS_OPT_MON_STATS */
1185 #endif /* EFSYS_OPT_MCDI */
1187 uint32_t enc_bist_mask;
1188 #endif /* EFSYS_OPT_BIST */
1189 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1192 uint32_t enc_privilege_mask;
1193 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1194 boolean_t enc_bug26807_workaround;
1195 boolean_t enc_bug35388_workaround;
1196 boolean_t enc_bug41750_workaround;
1197 boolean_t enc_bug61265_workaround;
1198 boolean_t enc_rx_batching_enabled;
1199 /* Maximum number of descriptors completed in an rx event. */
1200 uint32_t enc_rx_batch_max;
1201 /* Number of rx descriptors the hardware requires for a push. */
1202 uint32_t enc_rx_push_align;
1203 /* Maximum amount of data in DMA descriptor */
1204 uint32_t enc_tx_dma_desc_size_max;
1206 * Boundary which DMA descriptor data must not cross or 0 if no
1209 uint32_t enc_tx_dma_desc_boundary;
1211 * Maximum number of bytes into the packet the TCP header can start for
1212 * the hardware to apply TSO packet edits.
1214 uint32_t enc_tx_tso_tcp_header_offset_limit;
1215 boolean_t enc_fw_assisted_tso_enabled;
1216 boolean_t enc_fw_assisted_tso_v2_enabled;
1217 /* Number of TSO contexts on the NIC (FATSOv2) */
1218 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1219 boolean_t enc_hw_tx_insert_vlan_enabled;
1220 /* Number of PFs on the NIC */
1221 uint32_t enc_hw_pf_count;
1222 /* Datapath firmware vadapter/vport/vswitch support */
1223 boolean_t enc_datapath_cap_evb;
1224 boolean_t enc_rx_disable_scatter_supported;
1225 boolean_t enc_allow_set_mac_with_installed_filters;
1226 boolean_t enc_enhanced_set_mac_supported;
1227 boolean_t enc_init_evq_v2_supported;
1228 boolean_t enc_rx_packed_stream_supported;
1229 boolean_t enc_rx_var_packed_stream_supported;
1230 boolean_t enc_pm_and_rxdp_counters;
1231 boolean_t enc_mac_stats_40g_tx_size_bins;
1232 uint32_t enc_tunnel_encapsulations_supported;
1234 * NIC global maximum for unique UDP tunnel ports shared by all
1237 uint32_t enc_tunnel_config_udp_entries_max;
1238 /* External port identifier */
1239 uint8_t enc_external_port;
1240 uint32_t enc_mcdi_max_payload_length;
1241 /* VPD may be per-PF or global */
1242 boolean_t enc_vpd_is_global;
1243 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1244 uint32_t enc_required_pcie_bandwidth_mbps;
1245 uint32_t enc_max_pcie_link_gen;
1246 /* Firmware verifies integrity of NVRAM updates */
1247 uint32_t enc_nvram_update_verify_result_supported;
1248 /* Firmware support for extended MAC_STATS buffer */
1249 uint32_t enc_mac_stats_nstats;
1250 boolean_t enc_fec_counters;
1253 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1254 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1256 #define EFX_PCI_FUNCTION(_encp) \
1257 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1259 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1261 extern const efx_nic_cfg_t *
1263 __in efx_nic_t *enp);
1265 typedef struct efx_nic_fw_info_s {
1266 /* Basic FW version information */
1267 uint16_t enfi_mc_fw_version[4];
1269 * If datapath capabilities can be detected,
1270 * additional FW information is to be shown
1272 boolean_t enfi_dpcpu_fw_ids_valid;
1273 /* Rx and Tx datapath CPU FW IDs */
1274 uint16_t enfi_rx_dpcpu_fw_id;
1275 uint16_t enfi_tx_dpcpu_fw_id;
1276 } efx_nic_fw_info_t;
1278 extern __checkReturn efx_rc_t
1279 efx_nic_get_fw_version(
1280 __in efx_nic_t *enp,
1281 __out efx_nic_fw_info_t *enfip);
1283 /* Driver resource limits (minimum required/maximum usable). */
1284 typedef struct efx_drv_limits_s {
1285 uint32_t edl_min_evq_count;
1286 uint32_t edl_max_evq_count;
1288 uint32_t edl_min_rxq_count;
1289 uint32_t edl_max_rxq_count;
1291 uint32_t edl_min_txq_count;
1292 uint32_t edl_max_txq_count;
1294 /* PIO blocks (sub-allocated from piobuf) */
1295 uint32_t edl_min_pio_alloc_size;
1296 uint32_t edl_max_pio_alloc_count;
1299 extern __checkReturn efx_rc_t
1300 efx_nic_set_drv_limits(
1301 __inout efx_nic_t *enp,
1302 __in efx_drv_limits_t *edlp);
1304 typedef enum efx_nic_region_e {
1305 EFX_REGION_VI, /* Memory BAR UC mapping */
1306 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1309 extern __checkReturn efx_rc_t
1310 efx_nic_get_bar_region(
1311 __in efx_nic_t *enp,
1312 __in efx_nic_region_t region,
1313 __out uint32_t *offsetp,
1314 __out size_t *sizep);
1316 extern __checkReturn efx_rc_t
1317 efx_nic_get_vi_pool(
1318 __in efx_nic_t *enp,
1319 __out uint32_t *evq_countp,
1320 __out uint32_t *rxq_countp,
1321 __out uint32_t *txq_countp);
1326 typedef enum efx_vpd_tag_e {
1333 typedef uint16_t efx_vpd_keyword_t;
1335 typedef struct efx_vpd_value_s {
1336 efx_vpd_tag_t evv_tag;
1337 efx_vpd_keyword_t evv_keyword;
1339 uint8_t evv_value[0x100];
1343 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1345 extern __checkReturn efx_rc_t
1347 __in efx_nic_t *enp);
1349 extern __checkReturn efx_rc_t
1351 __in efx_nic_t *enp,
1352 __out size_t *sizep);
1354 extern __checkReturn efx_rc_t
1356 __in efx_nic_t *enp,
1357 __out_bcount(size) caddr_t data,
1360 extern __checkReturn efx_rc_t
1362 __in efx_nic_t *enp,
1363 __in_bcount(size) caddr_t data,
1366 extern __checkReturn efx_rc_t
1368 __in efx_nic_t *enp,
1369 __in_bcount(size) caddr_t data,
1372 extern __checkReturn efx_rc_t
1374 __in efx_nic_t *enp,
1375 __in_bcount(size) caddr_t data,
1377 __inout efx_vpd_value_t *evvp);
1379 extern __checkReturn efx_rc_t
1381 __in efx_nic_t *enp,
1382 __inout_bcount(size) caddr_t data,
1384 __in efx_vpd_value_t *evvp);
1386 extern __checkReturn efx_rc_t
1388 __in efx_nic_t *enp,
1389 __inout_bcount(size) caddr_t data,
1391 __out efx_vpd_value_t *evvp,
1392 __inout unsigned int *contp);
1394 extern __checkReturn efx_rc_t
1396 __in efx_nic_t *enp,
1397 __in_bcount(size) caddr_t data,
1402 __in efx_nic_t *enp);
1404 #endif /* EFSYS_OPT_VPD */
1410 typedef enum efx_nvram_type_e {
1411 EFX_NVRAM_INVALID = 0,
1413 EFX_NVRAM_BOOTROM_CFG,
1414 EFX_NVRAM_MC_FIRMWARE,
1415 EFX_NVRAM_MC_GOLDEN,
1421 EFX_NVRAM_FPGA_BACKUP,
1422 EFX_NVRAM_DYNAMIC_CFG,
1425 EFX_NVRAM_MUM_FIRMWARE,
1429 extern __checkReturn efx_rc_t
1431 __in efx_nic_t *enp);
1435 extern __checkReturn efx_rc_t
1437 __in efx_nic_t *enp);
1439 #endif /* EFSYS_OPT_DIAG */
1441 extern __checkReturn efx_rc_t
1443 __in efx_nic_t *enp,
1444 __in efx_nvram_type_t type,
1445 __out size_t *sizep);
1447 extern __checkReturn efx_rc_t
1449 __in efx_nic_t *enp,
1450 __in efx_nvram_type_t type,
1451 __out_opt size_t *pref_chunkp);
1453 extern __checkReturn efx_rc_t
1454 efx_nvram_rw_finish(
1455 __in efx_nic_t *enp,
1456 __in efx_nvram_type_t type,
1457 __out_opt uint32_t *verify_resultp);
1459 extern __checkReturn efx_rc_t
1460 efx_nvram_get_version(
1461 __in efx_nic_t *enp,
1462 __in efx_nvram_type_t type,
1463 __out uint32_t *subtypep,
1464 __out_ecount(4) uint16_t version[4]);
1466 extern __checkReturn efx_rc_t
1467 efx_nvram_read_chunk(
1468 __in efx_nic_t *enp,
1469 __in efx_nvram_type_t type,
1470 __in unsigned int offset,
1471 __out_bcount(size) caddr_t data,
1474 extern __checkReturn efx_rc_t
1475 efx_nvram_read_backup(
1476 __in efx_nic_t *enp,
1477 __in efx_nvram_type_t type,
1478 __in unsigned int offset,
1479 __out_bcount(size) caddr_t data,
1482 extern __checkReturn efx_rc_t
1483 efx_nvram_set_version(
1484 __in efx_nic_t *enp,
1485 __in efx_nvram_type_t type,
1486 __in_ecount(4) uint16_t version[4]);
1488 extern __checkReturn efx_rc_t
1490 __in efx_nic_t *enp,
1491 __in efx_nvram_type_t type,
1492 __in_bcount(partn_size) caddr_t partn_data,
1493 __in size_t partn_size);
1495 extern __checkReturn efx_rc_t
1497 __in efx_nic_t *enp,
1498 __in efx_nvram_type_t type);
1500 extern __checkReturn efx_rc_t
1501 efx_nvram_write_chunk(
1502 __in efx_nic_t *enp,
1503 __in efx_nvram_type_t type,
1504 __in unsigned int offset,
1505 __in_bcount(size) caddr_t data,
1510 __in efx_nic_t *enp);
1512 #endif /* EFSYS_OPT_NVRAM */
1514 #if EFSYS_OPT_BOOTCFG
1516 /* Report size and offset of bootcfg sector in NVRAM partition. */
1517 extern __checkReturn efx_rc_t
1518 efx_bootcfg_sector_info(
1519 __in efx_nic_t *enp,
1521 __out_opt uint32_t *sector_countp,
1522 __out size_t *offsetp,
1523 __out size_t *max_sizep);
1526 * Copy bootcfg sector data to a target buffer which may differ in size.
1527 * Optionally corrects format errors in source buffer.
1530 efx_bootcfg_copy_sector(
1531 __in efx_nic_t *enp,
1532 __inout_bcount(sector_length)
1534 __in size_t sector_length,
1535 __out_bcount(data_size) uint8_t *data,
1536 __in size_t data_size,
1537 __in boolean_t handle_format_errors);
1541 __in efx_nic_t *enp,
1542 __out_bcount(size) uint8_t *data,
1547 __in efx_nic_t *enp,
1548 __in_bcount(size) uint8_t *data,
1551 #endif /* EFSYS_OPT_BOOTCFG */
1555 typedef enum efx_pattern_type_t {
1556 EFX_PATTERN_BYTE_INCREMENT = 0,
1557 EFX_PATTERN_ALL_THE_SAME,
1558 EFX_PATTERN_BIT_ALTERNATE,
1559 EFX_PATTERN_BYTE_ALTERNATE,
1560 EFX_PATTERN_BYTE_CHANGING,
1561 EFX_PATTERN_BIT_SWEEP,
1563 } efx_pattern_type_t;
1566 (*efx_sram_pattern_fn_t)(
1568 __in boolean_t negate,
1569 __out efx_qword_t *eqp);
1571 extern __checkReturn efx_rc_t
1573 __in efx_nic_t *enp,
1574 __in efx_pattern_type_t type);
1576 #endif /* EFSYS_OPT_DIAG */
1578 extern __checkReturn efx_rc_t
1579 efx_sram_buf_tbl_set(
1580 __in efx_nic_t *enp,
1582 __in efsys_mem_t *esmp,
1586 efx_sram_buf_tbl_clear(
1587 __in efx_nic_t *enp,
1591 #define EFX_BUF_TBL_SIZE 0x20000
1593 #define EFX_BUF_SIZE 4096
1597 typedef struct efx_evq_s efx_evq_t;
1599 #if EFSYS_OPT_QSTATS
1601 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1602 typedef enum efx_ev_qstat_e {
1608 EV_RX_PAUSE_FRM_ERR,
1609 EV_RX_BUF_OWNER_ID_ERR,
1610 EV_RX_IPV4_HDR_CHKSUM_ERR,
1611 EV_RX_TCP_UDP_CHKSUM_ERR,
1615 EV_RX_MCAST_HASH_MATCH,
1632 EV_DRIVER_SRM_UPD_DONE,
1633 EV_DRIVER_TX_DESCQ_FLS_DONE,
1634 EV_DRIVER_RX_DESCQ_FLS_DONE,
1635 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1636 EV_DRIVER_RX_DSC_ERROR,
1637 EV_DRIVER_TX_DSC_ERROR,
1643 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1645 #endif /* EFSYS_OPT_QSTATS */
1647 extern __checkReturn efx_rc_t
1649 __in efx_nic_t *enp);
1653 __in efx_nic_t *enp);
1655 #define EFX_EVQ_MAXNEVS 32768
1656 #define EFX_EVQ_MINNEVS 512
1658 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1659 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1661 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1662 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1663 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1664 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1666 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1667 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1668 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1670 extern __checkReturn efx_rc_t
1672 __in efx_nic_t *enp,
1673 __in unsigned int index,
1674 __in efsys_mem_t *esmp,
1678 __in uint32_t flags,
1679 __deref_out efx_evq_t **eepp);
1683 __in efx_evq_t *eep,
1684 __in uint16_t data);
1686 typedef __checkReturn boolean_t
1687 (*efx_initialized_ev_t)(
1688 __in_opt void *arg);
1690 #define EFX_PKT_UNICAST 0x0004
1691 #define EFX_PKT_START 0x0008
1693 #define EFX_PKT_VLAN_TAGGED 0x0010
1694 #define EFX_CKSUM_TCPUDP 0x0020
1695 #define EFX_CKSUM_IPV4 0x0040
1696 #define EFX_PKT_CONT 0x0080
1698 #define EFX_CHECK_VLAN 0x0100
1699 #define EFX_PKT_TCP 0x0200
1700 #define EFX_PKT_UDP 0x0400
1701 #define EFX_PKT_IPV4 0x0800
1703 #define EFX_PKT_IPV6 0x1000
1704 #define EFX_PKT_PREFIX_LEN 0x2000
1705 #define EFX_ADDR_MISMATCH 0x4000
1706 #define EFX_DISCARD 0x8000
1709 * The following flags are used only for packed stream
1710 * mode. The values for the flags are reused to fit into 16 bit,
1711 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1712 * packed stream mode
1714 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1715 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1718 #define EFX_EV_RX_NLABELS 32
1719 #define EFX_EV_TX_NLABELS 32
1721 typedef __checkReturn boolean_t
1724 __in uint32_t label,
1727 __in uint16_t flags);
1729 #if EFSYS_OPT_RX_PACKED_STREAM
1732 * Packed stream mode is documented in SF-112241-TC.
1733 * The general idea is that, instead of putting each incoming
1734 * packet into a separate buffer which is specified in a RX
1735 * descriptor, a large buffer is provided to the hardware and
1736 * packets are put there in a continuous stream.
1737 * The main advantage of such an approach is that RX queue refilling
1738 * happens much less frequently.
1741 typedef __checkReturn boolean_t
1744 __in uint32_t label,
1746 __in uint32_t pkt_count,
1747 __in uint16_t flags);
1751 typedef __checkReturn boolean_t
1754 __in uint32_t label,
1757 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1758 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1759 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1760 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1761 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1762 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1763 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1764 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1765 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1767 typedef __checkReturn boolean_t
1768 (*efx_exception_ev_t)(
1770 __in uint32_t label,
1771 __in uint32_t data);
1773 typedef __checkReturn boolean_t
1774 (*efx_rxq_flush_done_ev_t)(
1776 __in uint32_t rxq_index);
1778 typedef __checkReturn boolean_t
1779 (*efx_rxq_flush_failed_ev_t)(
1781 __in uint32_t rxq_index);
1783 typedef __checkReturn boolean_t
1784 (*efx_txq_flush_done_ev_t)(
1786 __in uint32_t txq_index);
1788 typedef __checkReturn boolean_t
1789 (*efx_software_ev_t)(
1791 __in uint16_t magic);
1793 typedef __checkReturn boolean_t
1796 __in uint32_t code);
1798 #define EFX_SRAM_CLEAR 0
1799 #define EFX_SRAM_UPDATE 1
1800 #define EFX_SRAM_ILLEGAL_CLEAR 2
1802 typedef __checkReturn boolean_t
1803 (*efx_wake_up_ev_t)(
1805 __in uint32_t label);
1807 typedef __checkReturn boolean_t
1810 __in uint32_t label);
1812 typedef __checkReturn boolean_t
1813 (*efx_link_change_ev_t)(
1815 __in efx_link_mode_t link_mode);
1817 #if EFSYS_OPT_MON_STATS
1819 typedef __checkReturn boolean_t
1820 (*efx_monitor_ev_t)(
1822 __in efx_mon_stat_t id,
1823 __in efx_mon_stat_value_t value);
1825 #endif /* EFSYS_OPT_MON_STATS */
1827 #if EFSYS_OPT_MAC_STATS
1829 typedef __checkReturn boolean_t
1830 (*efx_mac_stats_ev_t)(
1832 __in uint32_t generation);
1834 #endif /* EFSYS_OPT_MAC_STATS */
1836 typedef struct efx_ev_callbacks_s {
1837 efx_initialized_ev_t eec_initialized;
1839 #if EFSYS_OPT_RX_PACKED_STREAM
1840 efx_rx_ps_ev_t eec_rx_ps;
1843 efx_exception_ev_t eec_exception;
1844 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1845 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1846 efx_txq_flush_done_ev_t eec_txq_flush_done;
1847 efx_software_ev_t eec_software;
1848 efx_sram_ev_t eec_sram;
1849 efx_wake_up_ev_t eec_wake_up;
1850 efx_timer_ev_t eec_timer;
1851 efx_link_change_ev_t eec_link_change;
1852 #if EFSYS_OPT_MON_STATS
1853 efx_monitor_ev_t eec_monitor;
1854 #endif /* EFSYS_OPT_MON_STATS */
1855 #if EFSYS_OPT_MAC_STATS
1856 efx_mac_stats_ev_t eec_mac_stats;
1857 #endif /* EFSYS_OPT_MAC_STATS */
1858 } efx_ev_callbacks_t;
1860 extern __checkReturn boolean_t
1862 __in efx_evq_t *eep,
1863 __in unsigned int count);
1865 #if EFSYS_OPT_EV_PREFETCH
1869 __in efx_evq_t *eep,
1870 __in unsigned int count);
1872 #endif /* EFSYS_OPT_EV_PREFETCH */
1876 __in efx_evq_t *eep,
1877 __inout unsigned int *countp,
1878 __in const efx_ev_callbacks_t *eecp,
1879 __in_opt void *arg);
1881 extern __checkReturn efx_rc_t
1882 efx_ev_usecs_to_ticks(
1883 __in efx_nic_t *enp,
1884 __in unsigned int usecs,
1885 __out unsigned int *ticksp);
1887 extern __checkReturn efx_rc_t
1889 __in efx_evq_t *eep,
1890 __in unsigned int us);
1892 extern __checkReturn efx_rc_t
1894 __in efx_evq_t *eep,
1895 __in unsigned int count);
1897 #if EFSYS_OPT_QSTATS
1903 __in efx_nic_t *enp,
1904 __in unsigned int id);
1906 #endif /* EFSYS_OPT_NAMES */
1909 efx_ev_qstats_update(
1910 __in efx_evq_t *eep,
1911 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1913 #endif /* EFSYS_OPT_QSTATS */
1917 __in efx_evq_t *eep);
1921 extern __checkReturn efx_rc_t
1923 __inout efx_nic_t *enp);
1927 __in efx_nic_t *enp);
1929 #if EFSYS_OPT_RX_SCATTER
1930 __checkReturn efx_rc_t
1931 efx_rx_scatter_enable(
1932 __in efx_nic_t *enp,
1933 __in unsigned int buf_size);
1934 #endif /* EFSYS_OPT_RX_SCATTER */
1936 /* Handle to represent use of the default RSS context. */
1937 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1939 #if EFSYS_OPT_RX_SCALE
1941 typedef enum efx_rx_hash_alg_e {
1942 EFX_RX_HASHALG_LFSR = 0,
1943 EFX_RX_HASHALG_TOEPLITZ
1944 } efx_rx_hash_alg_t;
1946 #define EFX_RX_HASH_IPV4 (1U << 0)
1947 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1948 #define EFX_RX_HASH_IPV6 (1U << 2)
1949 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1951 typedef unsigned int efx_rx_hash_type_t;
1953 typedef enum efx_rx_hash_support_e {
1954 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1955 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1956 } efx_rx_hash_support_t;
1958 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1959 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1960 #define EFX_MAXRSS 64 /* RX indirection entry range */
1961 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1963 typedef enum efx_rx_scale_context_type_e {
1964 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1965 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1966 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1967 } efx_rx_scale_context_type_t;
1969 extern __checkReturn efx_rc_t
1970 efx_rx_hash_default_support_get(
1971 __in efx_nic_t *enp,
1972 __out efx_rx_hash_support_t *supportp);
1975 extern __checkReturn efx_rc_t
1976 efx_rx_scale_default_support_get(
1977 __in efx_nic_t *enp,
1978 __out efx_rx_scale_context_type_t *typep);
1980 extern __checkReturn efx_rc_t
1981 efx_rx_scale_context_alloc(
1982 __in efx_nic_t *enp,
1983 __in efx_rx_scale_context_type_t type,
1984 __in uint32_t num_queues,
1985 __out uint32_t *rss_contextp);
1987 extern __checkReturn efx_rc_t
1988 efx_rx_scale_context_free(
1989 __in efx_nic_t *enp,
1990 __in uint32_t rss_context);
1992 extern __checkReturn efx_rc_t
1993 efx_rx_scale_mode_set(
1994 __in efx_nic_t *enp,
1995 __in uint32_t rss_context,
1996 __in efx_rx_hash_alg_t alg,
1997 __in efx_rx_hash_type_t type,
1998 __in boolean_t insert);
2000 extern __checkReturn efx_rc_t
2001 efx_rx_scale_tbl_set(
2002 __in efx_nic_t *enp,
2003 __in uint32_t rss_context,
2004 __in_ecount(n) unsigned int *table,
2007 extern __checkReturn efx_rc_t
2008 efx_rx_scale_key_set(
2009 __in efx_nic_t *enp,
2010 __in uint32_t rss_context,
2011 __in_ecount(n) uint8_t *key,
2014 extern __checkReturn uint32_t
2015 efx_pseudo_hdr_hash_get(
2016 __in efx_rxq_t *erp,
2017 __in efx_rx_hash_alg_t func,
2018 __in uint8_t *buffer);
2020 #endif /* EFSYS_OPT_RX_SCALE */
2022 extern __checkReturn efx_rc_t
2023 efx_pseudo_hdr_pkt_length_get(
2024 __in efx_rxq_t *erp,
2025 __in uint8_t *buffer,
2026 __out uint16_t *pkt_lengthp);
2028 #define EFX_RXQ_MAXNDESCS 4096
2029 #define EFX_RXQ_MINNDESCS 512
2031 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2032 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2033 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2034 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2036 typedef enum efx_rxq_type_e {
2037 EFX_RXQ_TYPE_DEFAULT,
2038 EFX_RXQ_TYPE_PACKED_STREAM,
2043 * Dummy flag to be used instead of 0 to make it clear that the argument
2044 * is receive queue flags.
2046 #define EFX_RXQ_FLAG_NONE 0x0
2047 #define EFX_RXQ_FLAG_SCATTER 0x1
2049 * If tunnels are supported and Rx event can provide information about
2050 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2051 * full-feature firmware variant running), outer classes are requested by
2052 * default. However, if the driver supports tunnels, the flag allows to
2053 * request inner classes which are required to be able to interpret inner
2054 * Rx checksum offload results.
2056 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2058 extern __checkReturn efx_rc_t
2060 __in efx_nic_t *enp,
2061 __in unsigned int index,
2062 __in unsigned int label,
2063 __in efx_rxq_type_t type,
2064 __in efsys_mem_t *esmp,
2067 __in unsigned int flags,
2068 __in efx_evq_t *eep,
2069 __deref_out efx_rxq_t **erpp);
2071 #if EFSYS_OPT_RX_PACKED_STREAM
2073 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2074 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2075 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2076 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2077 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2079 extern __checkReturn efx_rc_t
2080 efx_rx_qcreate_packed_stream(
2081 __in efx_nic_t *enp,
2082 __in unsigned int index,
2083 __in unsigned int label,
2084 __in uint32_t ps_buf_size,
2085 __in efsys_mem_t *esmp,
2087 __in efx_evq_t *eep,
2088 __deref_out efx_rxq_t **erpp);
2092 typedef struct efx_buffer_s {
2093 efsys_dma_addr_t eb_addr;
2098 typedef struct efx_desc_s {
2104 __in efx_rxq_t *erp,
2105 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2107 __in unsigned int ndescs,
2108 __in unsigned int completed,
2109 __in unsigned int added);
2113 __in efx_rxq_t *erp,
2114 __in unsigned int added,
2115 __inout unsigned int *pushedp);
2117 #if EFSYS_OPT_RX_PACKED_STREAM
2120 efx_rx_qpush_ps_credits(
2121 __in efx_rxq_t *erp);
2123 extern __checkReturn uint8_t *
2124 efx_rx_qps_packet_info(
2125 __in efx_rxq_t *erp,
2126 __in uint8_t *buffer,
2127 __in uint32_t buffer_length,
2128 __in uint32_t current_offset,
2129 __out uint16_t *lengthp,
2130 __out uint32_t *next_offsetp,
2131 __out uint32_t *timestamp);
2134 extern __checkReturn efx_rc_t
2136 __in efx_rxq_t *erp);
2140 __in efx_rxq_t *erp);
2144 __in efx_rxq_t *erp);
2148 typedef struct efx_txq_s efx_txq_t;
2150 #if EFSYS_OPT_QSTATS
2152 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2153 typedef enum efx_tx_qstat_e {
2159 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2161 #endif /* EFSYS_OPT_QSTATS */
2163 extern __checkReturn efx_rc_t
2165 __in efx_nic_t *enp);
2169 __in efx_nic_t *enp);
2171 #define EFX_TXQ_MINNDESCS 512
2173 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2174 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2175 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2177 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2179 #define EFX_TXQ_CKSUM_IPV4 0x0001
2180 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2181 #define EFX_TXQ_FATSOV2 0x0004
2182 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2183 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2185 extern __checkReturn efx_rc_t
2187 __in efx_nic_t *enp,
2188 __in unsigned int index,
2189 __in unsigned int label,
2190 __in efsys_mem_t *esmp,
2193 __in uint16_t flags,
2194 __in efx_evq_t *eep,
2195 __deref_out efx_txq_t **etpp,
2196 __out unsigned int *addedp);
2198 extern __checkReturn efx_rc_t
2200 __in efx_txq_t *etp,
2201 __in_ecount(ndescs) efx_buffer_t *eb,
2202 __in unsigned int ndescs,
2203 __in unsigned int completed,
2204 __inout unsigned int *addedp);
2206 extern __checkReturn efx_rc_t
2208 __in efx_txq_t *etp,
2209 __in unsigned int ns);
2213 __in efx_txq_t *etp,
2214 __in unsigned int added,
2215 __in unsigned int pushed);
2217 extern __checkReturn efx_rc_t
2219 __in efx_txq_t *etp);
2223 __in efx_txq_t *etp);
2225 extern __checkReturn efx_rc_t
2227 __in efx_txq_t *etp);
2230 efx_tx_qpio_disable(
2231 __in efx_txq_t *etp);
2233 extern __checkReturn efx_rc_t
2235 __in efx_txq_t *etp,
2236 __in_ecount(buf_length) uint8_t *buffer,
2237 __in size_t buf_length,
2238 __in size_t pio_buf_offset);
2240 extern __checkReturn efx_rc_t
2242 __in efx_txq_t *etp,
2243 __in size_t pkt_length,
2244 __in unsigned int completed,
2245 __inout unsigned int *addedp);
2247 extern __checkReturn efx_rc_t
2249 __in efx_txq_t *etp,
2250 __in_ecount(n) efx_desc_t *ed,
2251 __in unsigned int n,
2252 __in unsigned int completed,
2253 __inout unsigned int *addedp);
2256 efx_tx_qdesc_dma_create(
2257 __in efx_txq_t *etp,
2258 __in efsys_dma_addr_t addr,
2261 __out efx_desc_t *edp);
2264 efx_tx_qdesc_tso_create(
2265 __in efx_txq_t *etp,
2266 __in uint16_t ipv4_id,
2267 __in uint32_t tcp_seq,
2268 __in uint8_t tcp_flags,
2269 __out efx_desc_t *edp);
2271 /* Number of FATSOv2 option descriptors */
2272 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2274 /* Maximum number of DMA segments per TSO packet (not superframe) */
2275 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2278 efx_tx_qdesc_tso2_create(
2279 __in efx_txq_t *etp,
2280 __in uint16_t ipv4_id,
2281 __in uint32_t tcp_seq,
2282 __in uint16_t tcp_mss,
2283 __out_ecount(count) efx_desc_t *edp,
2287 efx_tx_qdesc_vlantci_create(
2288 __in efx_txq_t *etp,
2290 __out efx_desc_t *edp);
2293 efx_tx_qdesc_checksum_create(
2294 __in efx_txq_t *etp,
2295 __in uint16_t flags,
2296 __out efx_desc_t *edp);
2298 #if EFSYS_OPT_QSTATS
2304 __in efx_nic_t *etp,
2305 __in unsigned int id);
2307 #endif /* EFSYS_OPT_NAMES */
2310 efx_tx_qstats_update(
2311 __in efx_txq_t *etp,
2312 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2314 #endif /* EFSYS_OPT_QSTATS */
2318 __in efx_txq_t *etp);
2323 #if EFSYS_OPT_FILTER
2325 #define EFX_ETHER_TYPE_IPV4 0x0800
2326 #define EFX_ETHER_TYPE_IPV6 0x86DD
2328 #define EFX_IPPROTO_TCP 6
2329 #define EFX_IPPROTO_UDP 17
2330 #define EFX_IPPROTO_GRE 47
2332 /* Use RSS to spread across multiple queues */
2333 #define EFX_FILTER_FLAG_RX_RSS 0x01
2334 /* Enable RX scatter */
2335 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2337 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2338 * May only be set by the filter implementation for each type.
2339 * A removal request will restore the automatic filter in its place.
2341 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2342 /* Filter is for RX */
2343 #define EFX_FILTER_FLAG_RX 0x08
2344 /* Filter is for TX */
2345 #define EFX_FILTER_FLAG_TX 0x10
2347 typedef uint8_t efx_filter_flags_t;
2350 * Flags which specify the fields to match on. The values are the same as in the
2351 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2354 /* Match by remote IP host address */
2355 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2356 /* Match by local IP host address */
2357 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2358 /* Match by remote MAC address */
2359 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2360 /* Match by remote TCP/UDP port */
2361 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2362 /* Match by remote TCP/UDP port */
2363 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2364 /* Match by local TCP/UDP port */
2365 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2366 /* Match by Ether-type */
2367 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2368 /* Match by inner VLAN ID */
2369 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2370 /* Match by outer VLAN ID */
2371 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2372 /* Match by IP transport protocol */
2373 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2374 /* For encapsulated packets, match all multicast inner frames */
2375 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2376 /* For encapsulated packets, match all unicast inner frames */
2377 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2378 /* Match otherwise-unmatched multicast and broadcast packets */
2379 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2380 /* Match otherwise-unmatched unicast packets */
2381 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2383 typedef uint32_t efx_filter_match_flags_t;
2385 typedef enum efx_filter_priority_s {
2386 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2387 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2388 * address list or hardware
2389 * requirements. This may only be used
2390 * by the filter implementation for
2392 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2393 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2394 * client (e.g. SR-IOV, HyperV VMQ etc.)
2396 } efx_filter_priority_t;
2399 * FIXME: All these fields are assumed to be in little-endian byte order.
2400 * It may be better for some to be big-endian. See bug42804.
2403 typedef struct efx_filter_spec_s {
2404 efx_filter_match_flags_t efs_match_flags;
2405 uint8_t efs_priority;
2406 efx_filter_flags_t efs_flags;
2407 uint16_t efs_dmaq_id;
2408 uint32_t efs_rss_context;
2409 uint16_t efs_outer_vid;
2410 uint16_t efs_inner_vid;
2411 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2412 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2413 uint16_t efs_ether_type;
2414 uint8_t efs_ip_proto;
2415 efx_tunnel_protocol_t efs_encap_type;
2416 uint16_t efs_loc_port;
2417 uint16_t efs_rem_port;
2418 efx_oword_t efs_rem_host;
2419 efx_oword_t efs_loc_host;
2420 } efx_filter_spec_t;
2423 /* Default values for use in filter specifications */
2424 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2425 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2427 extern __checkReturn efx_rc_t
2429 __in efx_nic_t *enp);
2433 __in efx_nic_t *enp);
2435 extern __checkReturn efx_rc_t
2437 __in efx_nic_t *enp,
2438 __inout efx_filter_spec_t *spec);
2440 extern __checkReturn efx_rc_t
2442 __in efx_nic_t *enp,
2443 __inout efx_filter_spec_t *spec);
2445 extern __checkReturn efx_rc_t
2447 __in efx_nic_t *enp);
2449 extern __checkReturn efx_rc_t
2450 efx_filter_supported_filters(
2451 __in efx_nic_t *enp,
2452 __out_ecount(buffer_length) uint32_t *buffer,
2453 __in size_t buffer_length,
2454 __out size_t *list_lengthp);
2457 efx_filter_spec_init_rx(
2458 __out efx_filter_spec_t *spec,
2459 __in efx_filter_priority_t priority,
2460 __in efx_filter_flags_t flags,
2461 __in efx_rxq_t *erp);
2464 efx_filter_spec_init_tx(
2465 __out efx_filter_spec_t *spec,
2466 __in efx_txq_t *etp);
2468 extern __checkReturn efx_rc_t
2469 efx_filter_spec_set_ipv4_local(
2470 __inout efx_filter_spec_t *spec,
2473 __in uint16_t port);
2475 extern __checkReturn efx_rc_t
2476 efx_filter_spec_set_ipv4_full(
2477 __inout efx_filter_spec_t *spec,
2479 __in uint32_t lhost,
2480 __in uint16_t lport,
2481 __in uint32_t rhost,
2482 __in uint16_t rport);
2484 extern __checkReturn efx_rc_t
2485 efx_filter_spec_set_eth_local(
2486 __inout efx_filter_spec_t *spec,
2488 __in const uint8_t *addr);
2491 efx_filter_spec_set_ether_type(
2492 __inout efx_filter_spec_t *spec,
2493 __in uint16_t ether_type);
2495 extern __checkReturn efx_rc_t
2496 efx_filter_spec_set_uc_def(
2497 __inout efx_filter_spec_t *spec);
2499 extern __checkReturn efx_rc_t
2500 efx_filter_spec_set_mc_def(
2501 __inout efx_filter_spec_t *spec);
2503 typedef enum efx_filter_inner_frame_match_e {
2504 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2505 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2506 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2507 } efx_filter_inner_frame_match_t;
2509 extern __checkReturn efx_rc_t
2510 efx_filter_spec_set_encap_type(
2511 __inout efx_filter_spec_t *spec,
2512 __in efx_tunnel_protocol_t encap_type,
2513 __in efx_filter_inner_frame_match_t inner_frame_match);
2515 #if EFSYS_OPT_RX_SCALE
2516 extern __checkReturn efx_rc_t
2517 efx_filter_spec_set_rss_context(
2518 __inout efx_filter_spec_t *spec,
2519 __in uint32_t rss_context);
2521 #endif /* EFSYS_OPT_FILTER */
2525 extern __checkReturn uint32_t
2527 __in_ecount(count) uint32_t const *input,
2529 __in uint32_t init);
2531 extern __checkReturn uint32_t
2533 __in_ecount(length) uint8_t const *input,
2535 __in uint32_t init);
2537 #if EFSYS_OPT_LICENSING
2541 typedef struct efx_key_stats_s {
2543 uint32_t eks_invalid;
2544 uint32_t eks_blacklisted;
2545 uint32_t eks_unverifiable;
2546 uint32_t eks_wrong_node;
2547 uint32_t eks_licensed_apps_lo;
2548 uint32_t eks_licensed_apps_hi;
2549 uint32_t eks_licensed_features_lo;
2550 uint32_t eks_licensed_features_hi;
2553 extern __checkReturn efx_rc_t
2555 __in efx_nic_t *enp);
2559 __in efx_nic_t *enp);
2561 extern __checkReturn boolean_t
2562 efx_lic_check_support(
2563 __in efx_nic_t *enp);
2565 extern __checkReturn efx_rc_t
2566 efx_lic_update_licenses(
2567 __in efx_nic_t *enp);
2569 extern __checkReturn efx_rc_t
2570 efx_lic_get_key_stats(
2571 __in efx_nic_t *enp,
2572 __out efx_key_stats_t *ksp);
2574 extern __checkReturn efx_rc_t
2576 __in efx_nic_t *enp,
2577 __in uint64_t app_id,
2578 __out boolean_t *licensedp);
2580 extern __checkReturn efx_rc_t
2582 __in efx_nic_t *enp,
2583 __in size_t buffer_size,
2584 __out uint32_t *typep,
2585 __out size_t *lengthp,
2586 __out_opt uint8_t *bufferp);
2589 extern __checkReturn efx_rc_t
2591 __in efx_nic_t *enp,
2592 __in_bcount(buffer_size)
2594 __in size_t buffer_size,
2595 __out uint32_t *startp);
2597 extern __checkReturn efx_rc_t
2599 __in efx_nic_t *enp,
2600 __in_bcount(buffer_size)
2602 __in size_t buffer_size,
2603 __in uint32_t offset,
2604 __out uint32_t *endp);
2606 extern __checkReturn __success(return != B_FALSE) boolean_t
2608 __in efx_nic_t *enp,
2609 __in_bcount(buffer_size)
2611 __in size_t buffer_size,
2612 __in uint32_t offset,
2613 __out uint32_t *startp,
2614 __out uint32_t *lengthp);
2616 extern __checkReturn __success(return != B_FALSE) boolean_t
2617 efx_lic_validate_key(
2618 __in efx_nic_t *enp,
2619 __in_bcount(length) caddr_t keyp,
2620 __in uint32_t length);
2622 extern __checkReturn efx_rc_t
2624 __in efx_nic_t *enp,
2625 __in_bcount(buffer_size)
2627 __in size_t buffer_size,
2628 __in uint32_t offset,
2629 __in uint32_t length,
2630 __out_bcount_part(key_max_size, *lengthp)
2632 __in size_t key_max_size,
2633 __out uint32_t *lengthp);
2635 extern __checkReturn efx_rc_t
2637 __in efx_nic_t *enp,
2638 __in_bcount(buffer_size)
2640 __in size_t buffer_size,
2641 __in uint32_t offset,
2642 __in_bcount(length) caddr_t keyp,
2643 __in uint32_t length,
2644 __out uint32_t *lengthp);
2646 __checkReturn efx_rc_t
2648 __in efx_nic_t *enp,
2649 __in_bcount(buffer_size)
2651 __in size_t buffer_size,
2652 __in uint32_t offset,
2653 __in uint32_t length,
2655 __out uint32_t *deltap);
2657 extern __checkReturn efx_rc_t
2658 efx_lic_create_partition(
2659 __in efx_nic_t *enp,
2660 __in_bcount(buffer_size)
2662 __in size_t buffer_size);
2664 extern __checkReturn efx_rc_t
2665 efx_lic_finish_partition(
2666 __in efx_nic_t *enp,
2667 __in_bcount(buffer_size)
2669 __in size_t buffer_size);
2671 #endif /* EFSYS_OPT_LICENSING */
2675 #if EFSYS_OPT_TUNNEL
2677 extern __checkReturn efx_rc_t
2679 __in efx_nic_t *enp);
2683 __in efx_nic_t *enp);
2686 * For overlay network encapsulation using UDP, the firmware needs to know
2687 * the configured UDP port for the overlay so it can decode encapsulated
2689 * The UDP port/protocol list is global.
2692 extern __checkReturn efx_rc_t
2693 efx_tunnel_config_udp_add(
2694 __in efx_nic_t *enp,
2695 __in uint16_t port /* host/cpu-endian */,
2696 __in efx_tunnel_protocol_t protocol);
2698 extern __checkReturn efx_rc_t
2699 efx_tunnel_config_udp_remove(
2700 __in efx_nic_t *enp,
2701 __in uint16_t port /* host/cpu-endian */,
2702 __in efx_tunnel_protocol_t protocol);
2705 efx_tunnel_config_clear(
2706 __in efx_nic_t *enp);
2709 * Apply tunnel UDP ports configuration to hardware.
2711 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2714 extern __checkReturn efx_rc_t
2715 efx_tunnel_reconfigure(
2716 __in efx_nic_t *enp);
2718 #endif /* EFSYS_OPT_TUNNEL */
2725 #endif /* _SYS_EFX_H */