2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 extern __checkReturn efx_rc_t
152 efx_nic_register_test(
153 __in efx_nic_t *enp);
155 #endif /* EFSYS_OPT_DIAG */
159 __in efx_nic_t *enp);
163 __in efx_nic_t *enp);
167 __in efx_nic_t *enp);
169 #define EFX_PCIE_LINK_SPEED_GEN1 1
170 #define EFX_PCIE_LINK_SPEED_GEN2 2
171 #define EFX_PCIE_LINK_SPEED_GEN3 3
173 typedef enum efx_pcie_link_performance_e {
174 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
175 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
176 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
177 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
178 } efx_pcie_link_performance_t;
180 extern __checkReturn efx_rc_t
181 efx_nic_calculate_pcie_link_bandwidth(
182 __in uint32_t pcie_link_width,
183 __in uint32_t pcie_link_gen,
184 __out uint32_t *bandwidth_mbpsp);
186 extern __checkReturn efx_rc_t
187 efx_nic_check_pcie_link_speed(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out efx_pcie_link_performance_t *resultp);
195 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
196 /* Huntington and Medford require MCDIv2 commands */
197 #define WITH_MCDI_V2 1
200 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
202 typedef enum efx_mcdi_exception_e {
203 EFX_MCDI_EXCEPTION_MC_REBOOT,
204 EFX_MCDI_EXCEPTION_MC_BADASSERT,
205 } efx_mcdi_exception_t;
207 #if EFSYS_OPT_MCDI_LOGGING
208 typedef enum efx_log_msg_e {
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_get_timeout(
246 __in efx_mcdi_req_t *emrp,
247 __out uint32_t *usec_timeoutp);
250 efx_mcdi_request_start(
252 __in efx_mcdi_req_t *emrp,
253 __in boolean_t ev_cpl);
255 extern __checkReturn boolean_t
256 efx_mcdi_request_poll(
257 __in efx_nic_t *enp);
259 extern __checkReturn boolean_t
260 efx_mcdi_request_abort(
261 __in efx_nic_t *enp);
265 __in efx_nic_t *enp);
267 #endif /* EFSYS_OPT_MCDI */
271 #define EFX_NINTR_SIENA 1024
273 typedef enum efx_intr_type_e {
274 EFX_INTR_INVALID = 0,
280 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
282 extern __checkReturn efx_rc_t
285 __in efx_intr_type_t type,
286 __in efsys_mem_t *esmp);
290 __in efx_nic_t *enp);
294 __in efx_nic_t *enp);
297 efx_intr_disable_unlocked(
298 __in efx_nic_t *enp);
300 #define EFX_INTR_NEVQS 32
302 extern __checkReturn efx_rc_t
305 __in unsigned int level);
308 efx_intr_status_line(
310 __out boolean_t *fatalp,
311 __out uint32_t *maskp);
314 efx_intr_status_message(
316 __in unsigned int message,
317 __out boolean_t *fatalp);
321 __in efx_nic_t *enp);
325 __in efx_nic_t *enp);
329 #if EFSYS_OPT_MAC_STATS
331 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
332 typedef enum efx_mac_stat_e {
335 EFX_MAC_RX_UNICST_PKTS,
336 EFX_MAC_RX_MULTICST_PKTS,
337 EFX_MAC_RX_BRDCST_PKTS,
338 EFX_MAC_RX_PAUSE_PKTS,
339 EFX_MAC_RX_LE_64_PKTS,
340 EFX_MAC_RX_65_TO_127_PKTS,
341 EFX_MAC_RX_128_TO_255_PKTS,
342 EFX_MAC_RX_256_TO_511_PKTS,
343 EFX_MAC_RX_512_TO_1023_PKTS,
344 EFX_MAC_RX_1024_TO_15XX_PKTS,
345 EFX_MAC_RX_GE_15XX_PKTS,
347 EFX_MAC_RX_FCS_ERRORS,
348 EFX_MAC_RX_DROP_EVENTS,
349 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
350 EFX_MAC_RX_SYMBOL_ERRORS,
351 EFX_MAC_RX_ALIGN_ERRORS,
352 EFX_MAC_RX_INTERNAL_ERRORS,
353 EFX_MAC_RX_JABBER_PKTS,
354 EFX_MAC_RX_LANE0_CHAR_ERR,
355 EFX_MAC_RX_LANE1_CHAR_ERR,
356 EFX_MAC_RX_LANE2_CHAR_ERR,
357 EFX_MAC_RX_LANE3_CHAR_ERR,
358 EFX_MAC_RX_LANE0_DISP_ERR,
359 EFX_MAC_RX_LANE1_DISP_ERR,
360 EFX_MAC_RX_LANE2_DISP_ERR,
361 EFX_MAC_RX_LANE3_DISP_ERR,
362 EFX_MAC_RX_MATCH_FAULT,
363 EFX_MAC_RX_NODESC_DROP_CNT,
366 EFX_MAC_TX_UNICST_PKTS,
367 EFX_MAC_TX_MULTICST_PKTS,
368 EFX_MAC_TX_BRDCST_PKTS,
369 EFX_MAC_TX_PAUSE_PKTS,
370 EFX_MAC_TX_LE_64_PKTS,
371 EFX_MAC_TX_65_TO_127_PKTS,
372 EFX_MAC_TX_128_TO_255_PKTS,
373 EFX_MAC_TX_256_TO_511_PKTS,
374 EFX_MAC_TX_512_TO_1023_PKTS,
375 EFX_MAC_TX_1024_TO_15XX_PKTS,
376 EFX_MAC_TX_GE_15XX_PKTS,
378 EFX_MAC_TX_SGL_COL_PKTS,
379 EFX_MAC_TX_MULT_COL_PKTS,
380 EFX_MAC_TX_EX_COL_PKTS,
381 EFX_MAC_TX_LATE_COL_PKTS,
383 EFX_MAC_TX_EX_DEF_PKTS,
384 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
385 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
386 EFX_MAC_PM_TRUNC_VFIFO_FULL,
387 EFX_MAC_PM_DISCARD_VFIFO_FULL,
388 EFX_MAC_PM_TRUNC_QBB,
389 EFX_MAC_PM_DISCARD_QBB,
390 EFX_MAC_PM_DISCARD_MAPPING,
391 EFX_MAC_RXDP_Q_DISABLED_PKTS,
392 EFX_MAC_RXDP_DI_DROPPED_PKTS,
393 EFX_MAC_RXDP_STREAMING_PKTS,
394 EFX_MAC_RXDP_HLB_FETCH,
395 EFX_MAC_RXDP_HLB_WAIT,
396 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
397 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
398 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
399 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
400 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
401 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
402 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
403 EFX_MAC_VADAPTER_RX_BAD_BYTES,
404 EFX_MAC_VADAPTER_RX_OVERFLOW,
405 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
406 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
407 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
408 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
409 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
410 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
411 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
412 EFX_MAC_VADAPTER_TX_BAD_BYTES,
413 EFX_MAC_VADAPTER_TX_OVERFLOW,
417 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
419 #endif /* EFSYS_OPT_MAC_STATS */
421 typedef enum efx_link_mode_e {
422 EFX_LINK_UNKNOWN = 0,
435 #define EFX_MAC_ADDR_LEN 6
437 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
439 #define EFX_MAC_MULTICAST_LIST_MAX 256
441 #define EFX_MAC_SDU_MAX 9202
443 #define EFX_MAC_PDU_ADJUSTMENT \
447 + /* bug16011 */ 16) \
449 #define EFX_MAC_PDU(_sdu) \
450 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
453 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
454 * the SDU rounded up slightly.
456 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
458 #define EFX_MAC_PDU_MIN 60
459 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
461 extern __checkReturn efx_rc_t
466 extern __checkReturn efx_rc_t
471 extern __checkReturn efx_rc_t
476 extern __checkReturn efx_rc_t
479 __in boolean_t all_unicst,
480 __in boolean_t mulcst,
481 __in boolean_t all_mulcst,
482 __in boolean_t brdcst);
484 extern __checkReturn efx_rc_t
485 efx_mac_multicast_list_set(
487 __in_ecount(6*count) uint8_t const *addrs,
490 extern __checkReturn efx_rc_t
491 efx_mac_filter_default_rxq_set(
494 __in boolean_t using_rss);
497 efx_mac_filter_default_rxq_clear(
498 __in efx_nic_t *enp);
500 extern __checkReturn efx_rc_t
503 __in boolean_t enabled);
505 extern __checkReturn efx_rc_t
508 __out boolean_t *mac_upp);
510 #define EFX_FCNTL_RESPOND 0x00000001
511 #define EFX_FCNTL_GENERATE 0x00000002
513 extern __checkReturn efx_rc_t
516 __in unsigned int fcntl,
517 __in boolean_t autoneg);
522 __out unsigned int *fcntl_wantedp,
523 __out unsigned int *fcntl_linkp);
526 #if EFSYS_OPT_MAC_STATS
530 extern __checkReturn const char *
533 __in unsigned int id);
535 #endif /* EFSYS_OPT_NAMES */
537 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
539 #define EFX_MAC_STATS_MASK_NPAGES \
540 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
541 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
544 * Get mask of MAC statistics supported by the hardware.
546 * If mask_size is insufficient to return the mask, EINVAL error is
547 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
548 * (which is sizeof (uint32_t)) is sufficient.
550 extern __checkReturn efx_rc_t
551 efx_mac_stats_get_mask(
553 __out_bcount(mask_size) uint32_t *maskp,
554 __in size_t mask_size);
556 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
557 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
558 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
560 #define EFX_MAC_STATS_SIZE 0x400
563 * Upload mac statistics supported by the hardware into the given buffer.
565 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
568 * The hardware will only DMA statistics that it understands (of course).
569 * Drivers should not make any assumptions about which statistics are
570 * supported, especially when the statistics are generated by firmware.
572 * Thus, drivers should zero this buffer before use, so that not-understood
573 * statistics read back as zero.
575 extern __checkReturn efx_rc_t
576 efx_mac_stats_upload(
578 __in efsys_mem_t *esmp);
580 extern __checkReturn efx_rc_t
581 efx_mac_stats_periodic(
583 __in efsys_mem_t *esmp,
584 __in uint16_t period_ms,
585 __in boolean_t events);
587 extern __checkReturn efx_rc_t
588 efx_mac_stats_update(
590 __in efsys_mem_t *esmp,
591 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
592 __inout_opt uint32_t *generationp);
594 #endif /* EFSYS_OPT_MAC_STATS */
598 typedef enum efx_mon_type_e {
610 __in efx_nic_t *enp);
612 #endif /* EFSYS_OPT_NAMES */
614 extern __checkReturn efx_rc_t
616 __in efx_nic_t *enp);
620 __in efx_nic_t *enp);
624 extern __checkReturn efx_rc_t
626 __in efx_nic_t *enp);
628 #if EFSYS_OPT_PHY_LED_CONTROL
630 typedef enum efx_phy_led_mode_e {
631 EFX_PHY_LED_DEFAULT = 0,
636 } efx_phy_led_mode_t;
638 extern __checkReturn efx_rc_t
641 __in efx_phy_led_mode_t mode);
643 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
645 extern __checkReturn efx_rc_t
647 __in efx_nic_t *enp);
649 #if EFSYS_OPT_LOOPBACK
651 typedef enum efx_loopback_type_e {
652 EFX_LOOPBACK_OFF = 0,
653 EFX_LOOPBACK_DATA = 1,
654 EFX_LOOPBACK_GMAC = 2,
655 EFX_LOOPBACK_XGMII = 3,
656 EFX_LOOPBACK_XGXS = 4,
657 EFX_LOOPBACK_XAUI = 5,
658 EFX_LOOPBACK_GMII = 6,
659 EFX_LOOPBACK_SGMII = 7,
660 EFX_LOOPBACK_XGBR = 8,
661 EFX_LOOPBACK_XFI = 9,
662 EFX_LOOPBACK_XAUI_FAR = 10,
663 EFX_LOOPBACK_GMII_FAR = 11,
664 EFX_LOOPBACK_SGMII_FAR = 12,
665 EFX_LOOPBACK_XFI_FAR = 13,
666 EFX_LOOPBACK_GPHY = 14,
667 EFX_LOOPBACK_PHY_XS = 15,
668 EFX_LOOPBACK_PCS = 16,
669 EFX_LOOPBACK_PMA_PMD = 17,
670 EFX_LOOPBACK_XPORT = 18,
671 EFX_LOOPBACK_XGMII_WS = 19,
672 EFX_LOOPBACK_XAUI_WS = 20,
673 EFX_LOOPBACK_XAUI_WS_FAR = 21,
674 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
675 EFX_LOOPBACK_GMII_WS = 23,
676 EFX_LOOPBACK_XFI_WS = 24,
677 EFX_LOOPBACK_XFI_WS_FAR = 25,
678 EFX_LOOPBACK_PHYXS_WS = 26,
679 EFX_LOOPBACK_PMA_INT = 27,
680 EFX_LOOPBACK_SD_NEAR = 28,
681 EFX_LOOPBACK_SD_FAR = 29,
682 EFX_LOOPBACK_PMA_INT_WS = 30,
683 EFX_LOOPBACK_SD_FEP2_WS = 31,
684 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
685 EFX_LOOPBACK_SD_FEP_WS = 33,
686 EFX_LOOPBACK_SD_FES_WS = 34,
688 } efx_loopback_type_t;
690 typedef enum efx_loopback_kind_e {
691 EFX_LOOPBACK_KIND_OFF = 0,
692 EFX_LOOPBACK_KIND_ALL,
693 EFX_LOOPBACK_KIND_MAC,
694 EFX_LOOPBACK_KIND_PHY,
696 } efx_loopback_kind_t;
700 __in efx_loopback_kind_t loopback_kind,
701 __out efx_qword_t *maskp);
703 extern __checkReturn efx_rc_t
704 efx_port_loopback_set(
706 __in efx_link_mode_t link_mode,
707 __in efx_loopback_type_t type);
711 extern __checkReturn const char *
712 efx_loopback_type_name(
714 __in efx_loopback_type_t type);
716 #endif /* EFSYS_OPT_NAMES */
718 #endif /* EFSYS_OPT_LOOPBACK */
720 extern __checkReturn efx_rc_t
723 __out_opt efx_link_mode_t *link_modep);
727 __in efx_nic_t *enp);
729 typedef enum efx_phy_cap_type_e {
730 EFX_PHY_CAP_INVALID = 0,
737 EFX_PHY_CAP_10000FDX,
741 EFX_PHY_CAP_40000FDX,
743 } efx_phy_cap_type_t;
746 #define EFX_PHY_CAP_CURRENT 0x00000000
747 #define EFX_PHY_CAP_DEFAULT 0x00000001
748 #define EFX_PHY_CAP_PERM 0x00000002
754 __out uint32_t *maskp);
756 extern __checkReturn efx_rc_t
764 __out uint32_t *maskp);
766 extern __checkReturn efx_rc_t
769 __out uint32_t *ouip);
771 typedef enum efx_phy_media_type_e {
772 EFX_PHY_MEDIA_INVALID = 0,
777 EFX_PHY_MEDIA_SFP_PLUS,
778 EFX_PHY_MEDIA_BASE_T,
779 EFX_PHY_MEDIA_QSFP_PLUS,
781 } efx_phy_media_type_t;
783 /* Get the type of medium currently used. If the board has ports for
784 * modules, a module is present, and we recognise the media type of
785 * the module, then this will be the media type of the module.
786 * Otherwise it will be the media type of the port.
789 efx_phy_media_type_get(
791 __out efx_phy_media_type_t *typep);
794 efx_phy_module_get_info(
796 __in uint8_t dev_addr,
799 __out_bcount(len) uint8_t *data);
801 #if EFSYS_OPT_PHY_STATS
803 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
804 typedef enum efx_phy_stat_e {
806 EFX_PHY_STAT_PMA_PMD_LINK_UP,
807 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
808 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
809 EFX_PHY_STAT_PMA_PMD_REV_A,
810 EFX_PHY_STAT_PMA_PMD_REV_B,
811 EFX_PHY_STAT_PMA_PMD_REV_C,
812 EFX_PHY_STAT_PMA_PMD_REV_D,
813 EFX_PHY_STAT_PCS_LINK_UP,
814 EFX_PHY_STAT_PCS_RX_FAULT,
815 EFX_PHY_STAT_PCS_TX_FAULT,
816 EFX_PHY_STAT_PCS_BER,
817 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
818 EFX_PHY_STAT_PHY_XS_LINK_UP,
819 EFX_PHY_STAT_PHY_XS_RX_FAULT,
820 EFX_PHY_STAT_PHY_XS_TX_FAULT,
821 EFX_PHY_STAT_PHY_XS_ALIGN,
822 EFX_PHY_STAT_PHY_XS_SYNC_A,
823 EFX_PHY_STAT_PHY_XS_SYNC_B,
824 EFX_PHY_STAT_PHY_XS_SYNC_C,
825 EFX_PHY_STAT_PHY_XS_SYNC_D,
826 EFX_PHY_STAT_AN_LINK_UP,
827 EFX_PHY_STAT_AN_MASTER,
828 EFX_PHY_STAT_AN_LOCAL_RX_OK,
829 EFX_PHY_STAT_AN_REMOTE_RX_OK,
830 EFX_PHY_STAT_CL22EXT_LINK_UP,
835 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
836 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
837 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
838 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
839 EFX_PHY_STAT_AN_COMPLETE,
840 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
841 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
842 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
843 EFX_PHY_STAT_PCS_FW_VERSION_0,
844 EFX_PHY_STAT_PCS_FW_VERSION_1,
845 EFX_PHY_STAT_PCS_FW_VERSION_2,
846 EFX_PHY_STAT_PCS_FW_VERSION_3,
847 EFX_PHY_STAT_PCS_FW_BUILD_YY,
848 EFX_PHY_STAT_PCS_FW_BUILD_MM,
849 EFX_PHY_STAT_PCS_FW_BUILD_DD,
850 EFX_PHY_STAT_PCS_OP_MODE,
854 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
861 __in efx_phy_stat_t stat);
863 #endif /* EFSYS_OPT_NAMES */
865 #define EFX_PHY_STATS_SIZE 0x100
867 extern __checkReturn efx_rc_t
868 efx_phy_stats_update(
870 __in efsys_mem_t *esmp,
871 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
873 #endif /* EFSYS_OPT_PHY_STATS */
878 typedef enum efx_bist_type_e {
879 EFX_BIST_TYPE_UNKNOWN,
880 EFX_BIST_TYPE_PHY_NORMAL,
881 EFX_BIST_TYPE_PHY_CABLE_SHORT,
882 EFX_BIST_TYPE_PHY_CABLE_LONG,
883 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
884 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
885 EFX_BIST_TYPE_REG, /* Test the register memories */
886 EFX_BIST_TYPE_NTYPES,
889 typedef enum efx_bist_result_e {
890 EFX_BIST_RESULT_UNKNOWN,
891 EFX_BIST_RESULT_RUNNING,
892 EFX_BIST_RESULT_PASSED,
893 EFX_BIST_RESULT_FAILED,
896 typedef enum efx_phy_cable_status_e {
897 EFX_PHY_CABLE_STATUS_OK,
898 EFX_PHY_CABLE_STATUS_INVALID,
899 EFX_PHY_CABLE_STATUS_OPEN,
900 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
901 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
902 EFX_PHY_CABLE_STATUS_BUSY,
903 } efx_phy_cable_status_t;
905 typedef enum efx_bist_value_e {
906 EFX_BIST_PHY_CABLE_LENGTH_A,
907 EFX_BIST_PHY_CABLE_LENGTH_B,
908 EFX_BIST_PHY_CABLE_LENGTH_C,
909 EFX_BIST_PHY_CABLE_LENGTH_D,
910 EFX_BIST_PHY_CABLE_STATUS_A,
911 EFX_BIST_PHY_CABLE_STATUS_B,
912 EFX_BIST_PHY_CABLE_STATUS_C,
913 EFX_BIST_PHY_CABLE_STATUS_D,
915 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
923 EFX_BIST_MEM_ECC_PARITY,
924 EFX_BIST_MEM_ECC_FATAL,
928 extern __checkReturn efx_rc_t
929 efx_bist_enable_offline(
930 __in efx_nic_t *enp);
932 extern __checkReturn efx_rc_t
935 __in efx_bist_type_t type);
937 extern __checkReturn efx_rc_t
940 __in efx_bist_type_t type,
941 __out efx_bist_result_t *resultp,
942 __out_opt uint32_t *value_maskp,
943 __out_ecount_opt(count) unsigned long *valuesp,
949 __in efx_bist_type_t type);
951 #endif /* EFSYS_OPT_BIST */
953 #define EFX_FEATURE_IPV6 0x00000001
954 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
955 #define EFX_FEATURE_LINK_EVENTS 0x00000004
956 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
957 #define EFX_FEATURE_MCDI 0x00000020
958 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
959 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
960 #define EFX_FEATURE_TURBO 0x00000100
961 #define EFX_FEATURE_MCDI_DMA 0x00000200
962 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
963 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
964 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
965 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
966 #define EFX_FEATURE_PACKED_STREAM 0x00004000
968 typedef struct efx_nic_cfg_s {
969 uint32_t enc_board_type;
970 uint32_t enc_phy_type;
972 char enc_phy_name[21];
974 char enc_phy_revision[21];
975 efx_mon_type_t enc_mon_type;
976 unsigned int enc_features;
977 uint8_t enc_mac_addr[6];
978 uint8_t enc_port; /* PHY port number */
979 uint32_t enc_intr_vec_base;
980 uint32_t enc_intr_limit;
981 uint32_t enc_evq_limit;
982 uint32_t enc_txq_limit;
983 uint32_t enc_rxq_limit;
984 uint32_t enc_txq_max_ndescs;
985 uint32_t enc_buftbl_limit;
986 uint32_t enc_piobuf_limit;
987 uint32_t enc_piobuf_size;
988 uint32_t enc_piobuf_min_alloc_size;
989 uint32_t enc_evq_timer_quantum_ns;
990 uint32_t enc_evq_timer_max_us;
991 uint32_t enc_clk_mult;
992 uint32_t enc_rx_prefix_size;
993 uint32_t enc_rx_buf_align_start;
994 uint32_t enc_rx_buf_align_end;
995 #if EFSYS_OPT_LOOPBACK
996 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
997 #endif /* EFSYS_OPT_LOOPBACK */
998 #if EFSYS_OPT_PHY_FLAGS
999 uint32_t enc_phy_flags_mask;
1000 #endif /* EFSYS_OPT_PHY_FLAGS */
1001 #if EFSYS_OPT_PHY_LED_CONTROL
1002 uint32_t enc_led_mask;
1003 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1004 #if EFSYS_OPT_PHY_STATS
1005 uint64_t enc_phy_stat_mask;
1006 #endif /* EFSYS_OPT_PHY_STATS */
1008 uint8_t enc_mcdi_mdio_channel;
1009 #if EFSYS_OPT_PHY_STATS
1010 uint32_t enc_mcdi_phy_stat_mask;
1011 #endif /* EFSYS_OPT_PHY_STATS */
1012 #endif /* EFSYS_OPT_MCDI */
1014 uint32_t enc_bist_mask;
1015 #endif /* EFSYS_OPT_BIST */
1016 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1019 uint32_t enc_privilege_mask;
1020 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1021 boolean_t enc_bug26807_workaround;
1022 boolean_t enc_bug35388_workaround;
1023 boolean_t enc_bug41750_workaround;
1024 boolean_t enc_bug61265_workaround;
1025 boolean_t enc_rx_batching_enabled;
1026 /* Maximum number of descriptors completed in an rx event. */
1027 uint32_t enc_rx_batch_max;
1028 /* Number of rx descriptors the hardware requires for a push. */
1029 uint32_t enc_rx_push_align;
1031 * Maximum number of bytes into the packet the TCP header can start for
1032 * the hardware to apply TSO packet edits.
1034 uint32_t enc_tx_tso_tcp_header_offset_limit;
1035 boolean_t enc_fw_assisted_tso_enabled;
1036 boolean_t enc_fw_assisted_tso_v2_enabled;
1037 /* Number of TSO contexts on the NIC (FATSOv2) */
1038 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1039 boolean_t enc_hw_tx_insert_vlan_enabled;
1040 /* Number of PFs on the NIC */
1041 uint32_t enc_hw_pf_count;
1042 /* Datapath firmware vadapter/vport/vswitch support */
1043 boolean_t enc_datapath_cap_evb;
1044 boolean_t enc_rx_disable_scatter_supported;
1045 boolean_t enc_allow_set_mac_with_installed_filters;
1046 boolean_t enc_enhanced_set_mac_supported;
1047 boolean_t enc_init_evq_v2_supported;
1048 boolean_t enc_rx_packed_stream_supported;
1049 boolean_t enc_rx_var_packed_stream_supported;
1050 boolean_t enc_pm_and_rxdp_counters;
1051 boolean_t enc_mac_stats_40g_tx_size_bins;
1052 /* External port identifier */
1053 uint8_t enc_external_port;
1054 uint32_t enc_mcdi_max_payload_length;
1055 /* VPD may be per-PF or global */
1056 boolean_t enc_vpd_is_global;
1057 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1058 uint32_t enc_required_pcie_bandwidth_mbps;
1059 uint32_t enc_max_pcie_link_gen;
1060 /* Firmware verifies integrity of NVRAM updates */
1061 uint32_t enc_fw_verified_nvram_update_required;
1064 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1065 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1067 #define EFX_PCI_FUNCTION(_encp) \
1068 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1070 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1072 extern const efx_nic_cfg_t *
1074 __in efx_nic_t *enp);
1076 /* Driver resource limits (minimum required/maximum usable). */
1077 typedef struct efx_drv_limits_s {
1078 uint32_t edl_min_evq_count;
1079 uint32_t edl_max_evq_count;
1081 uint32_t edl_min_rxq_count;
1082 uint32_t edl_max_rxq_count;
1084 uint32_t edl_min_txq_count;
1085 uint32_t edl_max_txq_count;
1087 /* PIO blocks (sub-allocated from piobuf) */
1088 uint32_t edl_min_pio_alloc_size;
1089 uint32_t edl_max_pio_alloc_count;
1092 extern __checkReturn efx_rc_t
1093 efx_nic_set_drv_limits(
1094 __inout efx_nic_t *enp,
1095 __in efx_drv_limits_t *edlp);
1097 typedef enum efx_nic_region_e {
1098 EFX_REGION_VI, /* Memory BAR UC mapping */
1099 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1102 extern __checkReturn efx_rc_t
1103 efx_nic_get_bar_region(
1104 __in efx_nic_t *enp,
1105 __in efx_nic_region_t region,
1106 __out uint32_t *offsetp,
1107 __out size_t *sizep);
1109 extern __checkReturn efx_rc_t
1110 efx_nic_get_vi_pool(
1111 __in efx_nic_t *enp,
1112 __out uint32_t *evq_countp,
1113 __out uint32_t *rxq_countp,
1114 __out uint32_t *txq_countp);
1121 typedef enum efx_pattern_type_t {
1122 EFX_PATTERN_BYTE_INCREMENT = 0,
1123 EFX_PATTERN_ALL_THE_SAME,
1124 EFX_PATTERN_BIT_ALTERNATE,
1125 EFX_PATTERN_BYTE_ALTERNATE,
1126 EFX_PATTERN_BYTE_CHANGING,
1127 EFX_PATTERN_BIT_SWEEP,
1129 } efx_pattern_type_t;
1132 (*efx_sram_pattern_fn_t)(
1134 __in boolean_t negate,
1135 __out efx_qword_t *eqp);
1137 extern __checkReturn efx_rc_t
1139 __in efx_nic_t *enp,
1140 __in efx_pattern_type_t type);
1142 #endif /* EFSYS_OPT_DIAG */
1144 extern __checkReturn efx_rc_t
1145 efx_sram_buf_tbl_set(
1146 __in efx_nic_t *enp,
1148 __in efsys_mem_t *esmp,
1152 efx_sram_buf_tbl_clear(
1153 __in efx_nic_t *enp,
1157 #define EFX_BUF_TBL_SIZE 0x20000
1159 #define EFX_BUF_SIZE 4096
1163 typedef struct efx_evq_s efx_evq_t;
1165 #if EFSYS_OPT_QSTATS
1167 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1168 typedef enum efx_ev_qstat_e {
1174 EV_RX_PAUSE_FRM_ERR,
1175 EV_RX_BUF_OWNER_ID_ERR,
1176 EV_RX_IPV4_HDR_CHKSUM_ERR,
1177 EV_RX_TCP_UDP_CHKSUM_ERR,
1181 EV_RX_MCAST_HASH_MATCH,
1198 EV_DRIVER_SRM_UPD_DONE,
1199 EV_DRIVER_TX_DESCQ_FLS_DONE,
1200 EV_DRIVER_RX_DESCQ_FLS_DONE,
1201 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1202 EV_DRIVER_RX_DSC_ERROR,
1203 EV_DRIVER_TX_DSC_ERROR,
1209 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1211 #endif /* EFSYS_OPT_QSTATS */
1213 extern __checkReturn efx_rc_t
1215 __in efx_nic_t *enp);
1219 __in efx_nic_t *enp);
1221 #define EFX_EVQ_MAXNEVS 32768
1222 #define EFX_EVQ_MINNEVS 512
1224 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1225 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1227 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1228 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1229 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1230 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1232 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1233 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1234 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1236 extern __checkReturn efx_rc_t
1238 __in efx_nic_t *enp,
1239 __in unsigned int index,
1240 __in efsys_mem_t *esmp,
1244 __in uint32_t flags,
1245 __deref_out efx_evq_t **eepp);
1249 __in efx_evq_t *eep,
1250 __in uint16_t data);
1252 typedef __checkReturn boolean_t
1253 (*efx_initialized_ev_t)(
1254 __in_opt void *arg);
1256 #define EFX_PKT_UNICAST 0x0004
1257 #define EFX_PKT_START 0x0008
1259 #define EFX_PKT_VLAN_TAGGED 0x0010
1260 #define EFX_CKSUM_TCPUDP 0x0020
1261 #define EFX_CKSUM_IPV4 0x0040
1262 #define EFX_PKT_CONT 0x0080
1264 #define EFX_CHECK_VLAN 0x0100
1265 #define EFX_PKT_TCP 0x0200
1266 #define EFX_PKT_UDP 0x0400
1267 #define EFX_PKT_IPV4 0x0800
1269 #define EFX_PKT_IPV6 0x1000
1270 #define EFX_PKT_PREFIX_LEN 0x2000
1271 #define EFX_ADDR_MISMATCH 0x4000
1272 #define EFX_DISCARD 0x8000
1275 * The following flags are used only for packed stream
1276 * mode. The values for the flags are reused to fit into 16 bit,
1277 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1278 * packed stream mode
1280 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1281 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1284 #define EFX_EV_RX_NLABELS 32
1285 #define EFX_EV_TX_NLABELS 32
1287 typedef __checkReturn boolean_t
1290 __in uint32_t label,
1293 __in uint16_t flags);
1295 typedef __checkReturn boolean_t
1298 __in uint32_t label,
1301 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1302 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1303 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1304 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1305 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1306 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1307 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1308 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1309 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1311 typedef __checkReturn boolean_t
1312 (*efx_exception_ev_t)(
1314 __in uint32_t label,
1315 __in uint32_t data);
1317 typedef __checkReturn boolean_t
1318 (*efx_rxq_flush_done_ev_t)(
1320 __in uint32_t rxq_index);
1322 typedef __checkReturn boolean_t
1323 (*efx_rxq_flush_failed_ev_t)(
1325 __in uint32_t rxq_index);
1327 typedef __checkReturn boolean_t
1328 (*efx_txq_flush_done_ev_t)(
1330 __in uint32_t txq_index);
1332 typedef __checkReturn boolean_t
1333 (*efx_software_ev_t)(
1335 __in uint16_t magic);
1337 typedef __checkReturn boolean_t
1340 __in uint32_t code);
1342 #define EFX_SRAM_CLEAR 0
1343 #define EFX_SRAM_UPDATE 1
1344 #define EFX_SRAM_ILLEGAL_CLEAR 2
1346 typedef __checkReturn boolean_t
1347 (*efx_wake_up_ev_t)(
1349 __in uint32_t label);
1351 typedef __checkReturn boolean_t
1354 __in uint32_t label);
1356 typedef __checkReturn boolean_t
1357 (*efx_link_change_ev_t)(
1359 __in efx_link_mode_t link_mode);
1361 #if EFSYS_OPT_MAC_STATS
1363 typedef __checkReturn boolean_t
1364 (*efx_mac_stats_ev_t)(
1366 __in uint32_t generation
1369 #endif /* EFSYS_OPT_MAC_STATS */
1371 typedef struct efx_ev_callbacks_s {
1372 efx_initialized_ev_t eec_initialized;
1375 efx_exception_ev_t eec_exception;
1376 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1377 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1378 efx_txq_flush_done_ev_t eec_txq_flush_done;
1379 efx_software_ev_t eec_software;
1380 efx_sram_ev_t eec_sram;
1381 efx_wake_up_ev_t eec_wake_up;
1382 efx_timer_ev_t eec_timer;
1383 efx_link_change_ev_t eec_link_change;
1384 #if EFSYS_OPT_MAC_STATS
1385 efx_mac_stats_ev_t eec_mac_stats;
1386 #endif /* EFSYS_OPT_MAC_STATS */
1387 } efx_ev_callbacks_t;
1389 extern __checkReturn boolean_t
1391 __in efx_evq_t *eep,
1392 __in unsigned int count);
1394 #if EFSYS_OPT_EV_PREFETCH
1398 __in efx_evq_t *eep,
1399 __in unsigned int count);
1401 #endif /* EFSYS_OPT_EV_PREFETCH */
1405 __in efx_evq_t *eep,
1406 __inout unsigned int *countp,
1407 __in const efx_ev_callbacks_t *eecp,
1408 __in_opt void *arg);
1410 extern __checkReturn efx_rc_t
1411 efx_ev_usecs_to_ticks(
1412 __in efx_nic_t *enp,
1413 __in unsigned int usecs,
1414 __out unsigned int *ticksp);
1416 extern __checkReturn efx_rc_t
1418 __in efx_evq_t *eep,
1419 __in unsigned int us);
1421 extern __checkReturn efx_rc_t
1423 __in efx_evq_t *eep,
1424 __in unsigned int count);
1426 #if EFSYS_OPT_QSTATS
1432 __in efx_nic_t *enp,
1433 __in unsigned int id);
1435 #endif /* EFSYS_OPT_NAMES */
1438 efx_ev_qstats_update(
1439 __in efx_evq_t *eep,
1440 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1442 #endif /* EFSYS_OPT_QSTATS */
1446 __in efx_evq_t *eep);
1450 extern __checkReturn efx_rc_t
1452 __inout efx_nic_t *enp);
1456 __in efx_nic_t *enp);
1458 #if EFSYS_OPT_RX_SCATTER
1459 __checkReturn efx_rc_t
1460 efx_rx_scatter_enable(
1461 __in efx_nic_t *enp,
1462 __in unsigned int buf_size);
1463 #endif /* EFSYS_OPT_RX_SCATTER */
1465 #if EFSYS_OPT_RX_SCALE
1467 typedef enum efx_rx_hash_alg_e {
1468 EFX_RX_HASHALG_LFSR = 0,
1469 EFX_RX_HASHALG_TOEPLITZ
1470 } efx_rx_hash_alg_t;
1472 typedef enum efx_rx_hash_type_e {
1473 EFX_RX_HASH_IPV4 = 0,
1474 EFX_RX_HASH_TCPIPV4,
1476 EFX_RX_HASH_TCPIPV6,
1477 } efx_rx_hash_type_t;
1479 typedef enum efx_rx_hash_support_e {
1480 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1481 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1482 } efx_rx_hash_support_t;
1484 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1485 #define EFX_MAXRSS 64 /* RX indirection entry range */
1486 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1488 typedef enum efx_rx_scale_support_e {
1489 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1490 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1491 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1492 } efx_rx_scale_support_t;
1494 extern __checkReturn efx_rc_t
1495 efx_rx_hash_support_get(
1496 __in efx_nic_t *enp,
1497 __out efx_rx_hash_support_t *supportp);
1500 extern __checkReturn efx_rc_t
1501 efx_rx_scale_support_get(
1502 __in efx_nic_t *enp,
1503 __out efx_rx_scale_support_t *supportp);
1505 extern __checkReturn efx_rc_t
1506 efx_rx_scale_mode_set(
1507 __in efx_nic_t *enp,
1508 __in efx_rx_hash_alg_t alg,
1509 __in efx_rx_hash_type_t type,
1510 __in boolean_t insert);
1512 extern __checkReturn efx_rc_t
1513 efx_rx_scale_tbl_set(
1514 __in efx_nic_t *enp,
1515 __in_ecount(n) unsigned int *table,
1518 extern __checkReturn efx_rc_t
1519 efx_rx_scale_key_set(
1520 __in efx_nic_t *enp,
1521 __in_ecount(n) uint8_t *key,
1524 extern __checkReturn uint32_t
1525 efx_pseudo_hdr_hash_get(
1526 __in efx_rxq_t *erp,
1527 __in efx_rx_hash_alg_t func,
1528 __in uint8_t *buffer);
1530 #endif /* EFSYS_OPT_RX_SCALE */
1532 extern __checkReturn efx_rc_t
1533 efx_pseudo_hdr_pkt_length_get(
1534 __in efx_rxq_t *erp,
1535 __in uint8_t *buffer,
1536 __out uint16_t *pkt_lengthp);
1538 #define EFX_RXQ_MAXNDESCS 4096
1539 #define EFX_RXQ_MINNDESCS 512
1541 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1542 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1543 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1544 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1546 typedef enum efx_rxq_type_e {
1547 EFX_RXQ_TYPE_DEFAULT,
1548 EFX_RXQ_TYPE_SCATTER,
1549 EFX_RXQ_TYPE_PACKED_STREAM_1M,
1550 EFX_RXQ_TYPE_PACKED_STREAM_512K,
1551 EFX_RXQ_TYPE_PACKED_STREAM_256K,
1552 EFX_RXQ_TYPE_PACKED_STREAM_128K,
1553 EFX_RXQ_TYPE_PACKED_STREAM_64K,
1557 extern __checkReturn efx_rc_t
1559 __in efx_nic_t *enp,
1560 __in unsigned int index,
1561 __in unsigned int label,
1562 __in efx_rxq_type_t type,
1563 __in efsys_mem_t *esmp,
1566 __in efx_evq_t *eep,
1567 __deref_out efx_rxq_t **erpp);
1569 typedef struct efx_buffer_s {
1570 efsys_dma_addr_t eb_addr;
1575 typedef struct efx_desc_s {
1581 __in efx_rxq_t *erp,
1582 __in_ecount(n) efsys_dma_addr_t *addrp,
1584 __in unsigned int n,
1585 __in unsigned int completed,
1586 __in unsigned int added);
1590 __in efx_rxq_t *erp,
1591 __in unsigned int added,
1592 __inout unsigned int *pushedp);
1594 extern __checkReturn efx_rc_t
1596 __in efx_rxq_t *erp);
1600 __in efx_rxq_t *erp);
1604 __in efx_rxq_t *erp);
1608 typedef struct efx_txq_s efx_txq_t;
1610 #if EFSYS_OPT_QSTATS
1612 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1613 typedef enum efx_tx_qstat_e {
1619 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1621 #endif /* EFSYS_OPT_QSTATS */
1623 extern __checkReturn efx_rc_t
1625 __in efx_nic_t *enp);
1629 __in efx_nic_t *enp);
1631 #define EFX_TXQ_MINNDESCS 512
1633 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1634 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1635 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1636 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1638 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1640 #define EFX_TXQ_CKSUM_IPV4 0x0001
1641 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1642 #define EFX_TXQ_FATSOV2 0x0004
1644 extern __checkReturn efx_rc_t
1646 __in efx_nic_t *enp,
1647 __in unsigned int index,
1648 __in unsigned int label,
1649 __in efsys_mem_t *esmp,
1652 __in uint16_t flags,
1653 __in efx_evq_t *eep,
1654 __deref_out efx_txq_t **etpp,
1655 __out unsigned int *addedp);
1657 extern __checkReturn efx_rc_t
1659 __in efx_txq_t *etp,
1660 __in_ecount(n) efx_buffer_t *eb,
1661 __in unsigned int n,
1662 __in unsigned int completed,
1663 __inout unsigned int *addedp);
1665 extern __checkReturn efx_rc_t
1667 __in efx_txq_t *etp,
1668 __in unsigned int ns);
1672 __in efx_txq_t *etp,
1673 __in unsigned int added,
1674 __in unsigned int pushed);
1676 extern __checkReturn efx_rc_t
1678 __in efx_txq_t *etp);
1682 __in efx_txq_t *etp);
1684 extern __checkReturn efx_rc_t
1686 __in efx_txq_t *etp);
1689 efx_tx_qpio_disable(
1690 __in efx_txq_t *etp);
1692 extern __checkReturn efx_rc_t
1694 __in efx_txq_t *etp,
1695 __in_ecount(buf_length) uint8_t *buffer,
1696 __in size_t buf_length,
1697 __in size_t pio_buf_offset);
1699 extern __checkReturn efx_rc_t
1701 __in efx_txq_t *etp,
1702 __in size_t pkt_length,
1703 __in unsigned int completed,
1704 __inout unsigned int *addedp);
1706 extern __checkReturn efx_rc_t
1708 __in efx_txq_t *etp,
1709 __in_ecount(n) efx_desc_t *ed,
1710 __in unsigned int n,
1711 __in unsigned int completed,
1712 __inout unsigned int *addedp);
1715 efx_tx_qdesc_dma_create(
1716 __in efx_txq_t *etp,
1717 __in efsys_dma_addr_t addr,
1720 __out efx_desc_t *edp);
1723 efx_tx_qdesc_tso_create(
1724 __in efx_txq_t *etp,
1725 __in uint16_t ipv4_id,
1726 __in uint32_t tcp_seq,
1727 __in uint8_t tcp_flags,
1728 __out efx_desc_t *edp);
1730 /* Number of FATSOv2 option descriptors */
1731 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1733 /* Maximum number of DMA segments per TSO packet (not superframe) */
1734 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1737 efx_tx_qdesc_tso2_create(
1738 __in efx_txq_t *etp,
1739 __in uint16_t ipv4_id,
1740 __in uint32_t tcp_seq,
1741 __in uint16_t tcp_mss,
1742 __out_ecount(count) efx_desc_t *edp,
1746 efx_tx_qdesc_vlantci_create(
1747 __in efx_txq_t *etp,
1749 __out efx_desc_t *edp);
1751 #if EFSYS_OPT_QSTATS
1757 __in efx_nic_t *etp,
1758 __in unsigned int id);
1760 #endif /* EFSYS_OPT_NAMES */
1763 efx_tx_qstats_update(
1764 __in efx_txq_t *etp,
1765 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1767 #endif /* EFSYS_OPT_QSTATS */
1771 __in efx_txq_t *etp);
1776 #if EFSYS_OPT_FILTER
1778 #define EFX_ETHER_TYPE_IPV4 0x0800
1779 #define EFX_ETHER_TYPE_IPV6 0x86DD
1781 #define EFX_IPPROTO_TCP 6
1782 #define EFX_IPPROTO_UDP 17
1784 /* Use RSS to spread across multiple queues */
1785 #define EFX_FILTER_FLAG_RX_RSS 0x01
1786 /* Enable RX scatter */
1787 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1789 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1790 * May only be set by the filter implementation for each type.
1791 * A removal request will restore the automatic filter in its place.
1793 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1794 /* Filter is for RX */
1795 #define EFX_FILTER_FLAG_RX 0x08
1796 /* Filter is for TX */
1797 #define EFX_FILTER_FLAG_TX 0x10
1799 typedef unsigned int efx_filter_flags_t;
1801 typedef enum efx_filter_match_flags_e {
1802 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1804 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1806 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1807 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1808 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1809 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1810 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1811 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1812 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1813 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1815 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1816 * I/G bit. Used for RX default
1817 * unicast and multicast/
1818 * broadcast filters. */
1819 } efx_filter_match_flags_t;
1821 typedef enum efx_filter_priority_s {
1822 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1823 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1824 * address list or hardware
1825 * requirements. This may only be used
1826 * by the filter implementation for
1828 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1829 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1830 * client (e.g. SR-IOV, HyperV VMQ etc.)
1832 } efx_filter_priority_t;
1835 * FIXME: All these fields are assumed to be in little-endian byte order.
1836 * It may be better for some to be big-endian. See bug42804.
1839 typedef struct efx_filter_spec_s {
1840 uint32_t efs_match_flags:12;
1841 uint32_t efs_priority:2;
1842 uint32_t efs_flags:6;
1843 uint32_t efs_dmaq_id:12;
1844 uint32_t efs_rss_context;
1845 uint16_t efs_outer_vid;
1846 uint16_t efs_inner_vid;
1847 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1848 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1849 uint16_t efs_ether_type;
1850 uint8_t efs_ip_proto;
1851 uint16_t efs_loc_port;
1852 uint16_t efs_rem_port;
1853 efx_oword_t efs_rem_host;
1854 efx_oword_t efs_loc_host;
1855 } efx_filter_spec_t;
1858 /* Default values for use in filter specifications */
1859 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1860 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1861 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1863 extern __checkReturn efx_rc_t
1865 __in efx_nic_t *enp);
1869 __in efx_nic_t *enp);
1871 extern __checkReturn efx_rc_t
1873 __in efx_nic_t *enp,
1874 __inout efx_filter_spec_t *spec);
1876 extern __checkReturn efx_rc_t
1878 __in efx_nic_t *enp,
1879 __inout efx_filter_spec_t *spec);
1881 extern __checkReturn efx_rc_t
1883 __in efx_nic_t *enp);
1885 extern __checkReturn efx_rc_t
1886 efx_filter_supported_filters(
1887 __in efx_nic_t *enp,
1888 __out uint32_t *list,
1889 __out size_t *length);
1892 efx_filter_spec_init_rx(
1893 __out efx_filter_spec_t *spec,
1894 __in efx_filter_priority_t priority,
1895 __in efx_filter_flags_t flags,
1896 __in efx_rxq_t *erp);
1899 efx_filter_spec_init_tx(
1900 __out efx_filter_spec_t *spec,
1901 __in efx_txq_t *etp);
1903 extern __checkReturn efx_rc_t
1904 efx_filter_spec_set_ipv4_local(
1905 __inout efx_filter_spec_t *spec,
1908 __in uint16_t port);
1910 extern __checkReturn efx_rc_t
1911 efx_filter_spec_set_ipv4_full(
1912 __inout efx_filter_spec_t *spec,
1914 __in uint32_t lhost,
1915 __in uint16_t lport,
1916 __in uint32_t rhost,
1917 __in uint16_t rport);
1919 extern __checkReturn efx_rc_t
1920 efx_filter_spec_set_eth_local(
1921 __inout efx_filter_spec_t *spec,
1923 __in const uint8_t *addr);
1925 extern __checkReturn efx_rc_t
1926 efx_filter_spec_set_uc_def(
1927 __inout efx_filter_spec_t *spec);
1929 extern __checkReturn efx_rc_t
1930 efx_filter_spec_set_mc_def(
1931 __inout efx_filter_spec_t *spec);
1933 #endif /* EFSYS_OPT_FILTER */
1937 extern __checkReturn uint32_t
1939 __in_ecount(count) uint32_t const *input,
1941 __in uint32_t init);
1943 extern __checkReturn uint32_t
1945 __in_ecount(length) uint8_t const *input,
1947 __in uint32_t init);
1955 #endif /* _SYS_EFX_H */