1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_check.h"
13 #include "efx_phy_ids.h"
19 #define EFX_STATIC_ASSERT(_cond) \
20 ((void)sizeof (char[(_cond) ? 1 : -1]))
22 #define EFX_ARRAY_SIZE(_array) \
23 (sizeof (_array) / sizeof ((_array)[0]))
25 #define EFX_FIELD_OFFSET(_type, _field) \
26 ((size_t)&(((_type *)0)->_field))
28 /* The macro expands divider twice */
29 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
33 typedef __success(return == 0) int efx_rc_t;
38 typedef enum efx_family_e {
40 EFX_FAMILY_FALCON, /* Obsolete and not supported */
42 EFX_FAMILY_HUNTINGTON,
48 extern __checkReturn efx_rc_t
52 __out efx_family_t *efp,
53 __out unsigned int *membarp);
56 #define EFX_PCI_VENID_SFC 0x1924
58 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
60 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
61 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
62 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
64 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
65 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
66 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
68 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
69 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
71 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
72 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
73 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
75 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
76 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
77 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
80 #define EFX_MEM_BAR_SIENA 2
82 #define EFX_MEM_BAR_HUNTINGTON_PF 2
83 #define EFX_MEM_BAR_HUNTINGTON_VF 0
85 #define EFX_MEM_BAR_MEDFORD_PF 2
86 #define EFX_MEM_BAR_MEDFORD_VF 0
88 #define EFX_MEM_BAR_MEDFORD2 0
109 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
110 extern __checkReturn uint32_t
112 __in uint32_t crc_init,
113 __in_ecount(length) uint8_t const *input,
117 /* Type prototypes */
119 typedef struct efx_rxq_s efx_rxq_t;
123 typedef struct efx_nic_s efx_nic_t;
125 extern __checkReturn efx_rc_t
127 __in efx_family_t family,
128 __in efsys_identifier_t *esip,
129 __in efsys_bar_t *esbp,
130 __in efsys_lock_t *eslp,
131 __deref_out efx_nic_t **enpp);
133 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
134 typedef enum efx_fw_variant_e {
135 EFX_FW_VARIANT_FULL_FEATURED,
136 EFX_FW_VARIANT_LOW_LATENCY,
137 EFX_FW_VARIANT_PACKED_STREAM,
138 EFX_FW_VARIANT_HIGH_TX_RATE,
139 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
140 EFX_FW_VARIANT_RULES_ENGINE,
142 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
145 extern __checkReturn efx_rc_t
148 __in efx_fw_variant_t efv);
150 extern __checkReturn efx_rc_t
152 __in efx_nic_t *enp);
154 extern __checkReturn efx_rc_t
156 __in efx_nic_t *enp);
160 extern __checkReturn efx_rc_t
161 efx_nic_register_test(
162 __in efx_nic_t *enp);
164 #endif /* EFSYS_OPT_DIAG */
168 __in efx_nic_t *enp);
172 __in efx_nic_t *enp);
176 __in efx_nic_t *enp);
178 #define EFX_PCIE_LINK_SPEED_GEN1 1
179 #define EFX_PCIE_LINK_SPEED_GEN2 2
180 #define EFX_PCIE_LINK_SPEED_GEN3 3
182 typedef enum efx_pcie_link_performance_e {
183 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
184 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
185 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
186 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
187 } efx_pcie_link_performance_t;
189 extern __checkReturn efx_rc_t
190 efx_nic_calculate_pcie_link_bandwidth(
191 __in uint32_t pcie_link_width,
192 __in uint32_t pcie_link_gen,
193 __out uint32_t *bandwidth_mbpsp);
195 extern __checkReturn efx_rc_t
196 efx_nic_check_pcie_link_speed(
198 __in uint32_t pcie_link_width,
199 __in uint32_t pcie_link_gen,
200 __out efx_pcie_link_performance_t *resultp);
204 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
205 /* Huntington and Medford require MCDIv2 commands */
206 #define WITH_MCDI_V2 1
209 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
211 typedef enum efx_mcdi_exception_e {
212 EFX_MCDI_EXCEPTION_MC_REBOOT,
213 EFX_MCDI_EXCEPTION_MC_BADASSERT,
214 } efx_mcdi_exception_t;
216 #if EFSYS_OPT_MCDI_LOGGING
217 typedef enum efx_log_msg_e {
219 EFX_LOG_MCDI_REQUEST,
220 EFX_LOG_MCDI_RESPONSE,
222 #endif /* EFSYS_OPT_MCDI_LOGGING */
224 typedef struct efx_mcdi_transport_s {
226 efsys_mem_t *emt_dma_mem;
227 void (*emt_execute)(void *, efx_mcdi_req_t *);
228 void (*emt_ev_cpl)(void *);
229 void (*emt_exception)(void *, efx_mcdi_exception_t);
230 #if EFSYS_OPT_MCDI_LOGGING
231 void (*emt_logger)(void *, efx_log_msg_t,
232 void *, size_t, void *, size_t);
233 #endif /* EFSYS_OPT_MCDI_LOGGING */
234 #if EFSYS_OPT_MCDI_PROXY_AUTH
235 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
236 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
237 } efx_mcdi_transport_t;
239 extern __checkReturn efx_rc_t
242 __in const efx_mcdi_transport_t *mtp);
244 extern __checkReturn efx_rc_t
246 __in efx_nic_t *enp);
250 __in efx_nic_t *enp);
253 efx_mcdi_get_timeout(
255 __in efx_mcdi_req_t *emrp,
256 __out uint32_t *usec_timeoutp);
259 efx_mcdi_request_start(
261 __in efx_mcdi_req_t *emrp,
262 __in boolean_t ev_cpl);
264 extern __checkReturn boolean_t
265 efx_mcdi_request_poll(
266 __in efx_nic_t *enp);
268 extern __checkReturn boolean_t
269 efx_mcdi_request_abort(
270 __in efx_nic_t *enp);
274 __in efx_nic_t *enp);
276 #endif /* EFSYS_OPT_MCDI */
280 #define EFX_NINTR_SIENA 1024
282 typedef enum efx_intr_type_e {
283 EFX_INTR_INVALID = 0,
289 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
291 extern __checkReturn efx_rc_t
294 __in efx_intr_type_t type,
295 __in efsys_mem_t *esmp);
299 __in efx_nic_t *enp);
303 __in efx_nic_t *enp);
306 efx_intr_disable_unlocked(
307 __in efx_nic_t *enp);
309 #define EFX_INTR_NEVQS 32
311 extern __checkReturn efx_rc_t
314 __in unsigned int level);
317 efx_intr_status_line(
319 __out boolean_t *fatalp,
320 __out uint32_t *maskp);
323 efx_intr_status_message(
325 __in unsigned int message,
326 __out boolean_t *fatalp);
330 __in efx_nic_t *enp);
334 __in efx_nic_t *enp);
338 #if EFSYS_OPT_MAC_STATS
340 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
341 typedef enum efx_mac_stat_e {
344 EFX_MAC_RX_UNICST_PKTS,
345 EFX_MAC_RX_MULTICST_PKTS,
346 EFX_MAC_RX_BRDCST_PKTS,
347 EFX_MAC_RX_PAUSE_PKTS,
348 EFX_MAC_RX_LE_64_PKTS,
349 EFX_MAC_RX_65_TO_127_PKTS,
350 EFX_MAC_RX_128_TO_255_PKTS,
351 EFX_MAC_RX_256_TO_511_PKTS,
352 EFX_MAC_RX_512_TO_1023_PKTS,
353 EFX_MAC_RX_1024_TO_15XX_PKTS,
354 EFX_MAC_RX_GE_15XX_PKTS,
356 EFX_MAC_RX_FCS_ERRORS,
357 EFX_MAC_RX_DROP_EVENTS,
358 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
359 EFX_MAC_RX_SYMBOL_ERRORS,
360 EFX_MAC_RX_ALIGN_ERRORS,
361 EFX_MAC_RX_INTERNAL_ERRORS,
362 EFX_MAC_RX_JABBER_PKTS,
363 EFX_MAC_RX_LANE0_CHAR_ERR,
364 EFX_MAC_RX_LANE1_CHAR_ERR,
365 EFX_MAC_RX_LANE2_CHAR_ERR,
366 EFX_MAC_RX_LANE3_CHAR_ERR,
367 EFX_MAC_RX_LANE0_DISP_ERR,
368 EFX_MAC_RX_LANE1_DISP_ERR,
369 EFX_MAC_RX_LANE2_DISP_ERR,
370 EFX_MAC_RX_LANE3_DISP_ERR,
371 EFX_MAC_RX_MATCH_FAULT,
372 EFX_MAC_RX_NODESC_DROP_CNT,
375 EFX_MAC_TX_UNICST_PKTS,
376 EFX_MAC_TX_MULTICST_PKTS,
377 EFX_MAC_TX_BRDCST_PKTS,
378 EFX_MAC_TX_PAUSE_PKTS,
379 EFX_MAC_TX_LE_64_PKTS,
380 EFX_MAC_TX_65_TO_127_PKTS,
381 EFX_MAC_TX_128_TO_255_PKTS,
382 EFX_MAC_TX_256_TO_511_PKTS,
383 EFX_MAC_TX_512_TO_1023_PKTS,
384 EFX_MAC_TX_1024_TO_15XX_PKTS,
385 EFX_MAC_TX_GE_15XX_PKTS,
387 EFX_MAC_TX_SGL_COL_PKTS,
388 EFX_MAC_TX_MULT_COL_PKTS,
389 EFX_MAC_TX_EX_COL_PKTS,
390 EFX_MAC_TX_LATE_COL_PKTS,
392 EFX_MAC_TX_EX_DEF_PKTS,
393 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
394 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
395 EFX_MAC_PM_TRUNC_VFIFO_FULL,
396 EFX_MAC_PM_DISCARD_VFIFO_FULL,
397 EFX_MAC_PM_TRUNC_QBB,
398 EFX_MAC_PM_DISCARD_QBB,
399 EFX_MAC_PM_DISCARD_MAPPING,
400 EFX_MAC_RXDP_Q_DISABLED_PKTS,
401 EFX_MAC_RXDP_DI_DROPPED_PKTS,
402 EFX_MAC_RXDP_STREAMING_PKTS,
403 EFX_MAC_RXDP_HLB_FETCH,
404 EFX_MAC_RXDP_HLB_WAIT,
405 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
406 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
407 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
408 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
409 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
410 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
411 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
412 EFX_MAC_VADAPTER_RX_BAD_BYTES,
413 EFX_MAC_VADAPTER_RX_OVERFLOW,
414 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
415 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
416 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
417 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
418 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
419 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
420 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
421 EFX_MAC_VADAPTER_TX_BAD_BYTES,
422 EFX_MAC_VADAPTER_TX_OVERFLOW,
423 EFX_MAC_FEC_UNCORRECTED_ERRORS,
424 EFX_MAC_FEC_CORRECTED_ERRORS,
425 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
426 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
427 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
428 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
429 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
430 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
431 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
432 EFX_MAC_CTPIO_OVERFLOW_FAIL,
433 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
434 EFX_MAC_CTPIO_TIMEOUT_FAIL,
435 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
436 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
437 EFX_MAC_CTPIO_INVALID_WR_FAIL,
438 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
439 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
440 EFX_MAC_CTPIO_RUNT_FALLBACK,
441 EFX_MAC_CTPIO_SUCCESS,
442 EFX_MAC_CTPIO_FALLBACK,
443 EFX_MAC_CTPIO_POISON,
445 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
446 EFX_MAC_RXDP_HLB_IDLE,
447 EFX_MAC_RXDP_HLB_TIMEOUT,
451 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
453 #endif /* EFSYS_OPT_MAC_STATS */
455 typedef enum efx_link_mode_e {
456 EFX_LINK_UNKNOWN = 0,
472 #define EFX_MAC_ADDR_LEN 6
474 #define EFX_VNI_OR_VSID_LEN 3
476 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
478 #define EFX_MAC_MULTICAST_LIST_MAX 256
480 #define EFX_MAC_SDU_MAX 9202
482 #define EFX_MAC_PDU_ADJUSTMENT \
486 + /* bug16011 */ 16) \
488 #define EFX_MAC_PDU(_sdu) \
489 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
492 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
493 * the SDU rounded up slightly.
495 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
497 #define EFX_MAC_PDU_MIN 60
498 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
500 extern __checkReturn efx_rc_t
505 extern __checkReturn efx_rc_t
510 extern __checkReturn efx_rc_t
515 extern __checkReturn efx_rc_t
518 __in boolean_t all_unicst,
519 __in boolean_t mulcst,
520 __in boolean_t all_mulcst,
521 __in boolean_t brdcst);
523 extern __checkReturn efx_rc_t
524 efx_mac_multicast_list_set(
526 __in_ecount(6*count) uint8_t const *addrs,
529 extern __checkReturn efx_rc_t
530 efx_mac_filter_default_rxq_set(
533 __in boolean_t using_rss);
536 efx_mac_filter_default_rxq_clear(
537 __in efx_nic_t *enp);
539 extern __checkReturn efx_rc_t
542 __in boolean_t enabled);
544 extern __checkReturn efx_rc_t
547 __out boolean_t *mac_upp);
549 #define EFX_FCNTL_RESPOND 0x00000001
550 #define EFX_FCNTL_GENERATE 0x00000002
552 extern __checkReturn efx_rc_t
555 __in unsigned int fcntl,
556 __in boolean_t autoneg);
561 __out unsigned int *fcntl_wantedp,
562 __out unsigned int *fcntl_linkp);
565 #if EFSYS_OPT_MAC_STATS
569 extern __checkReturn const char *
572 __in unsigned int id);
574 #endif /* EFSYS_OPT_NAMES */
576 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
578 #define EFX_MAC_STATS_MASK_NPAGES \
579 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
580 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
583 * Get mask of MAC statistics supported by the hardware.
585 * If mask_size is insufficient to return the mask, EINVAL error is
586 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
587 * (which is sizeof (uint32_t)) is sufficient.
589 extern __checkReturn efx_rc_t
590 efx_mac_stats_get_mask(
592 __out_bcount(mask_size) uint32_t *maskp,
593 __in size_t mask_size);
595 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
596 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
597 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
600 extern __checkReturn efx_rc_t
602 __in efx_nic_t *enp);
605 * Upload mac statistics supported by the hardware into the given buffer.
607 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
608 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
610 * The hardware will only DMA statistics that it understands (of course).
611 * Drivers should not make any assumptions about which statistics are
612 * supported, especially when the statistics are generated by firmware.
614 * Thus, drivers should zero this buffer before use, so that not-understood
615 * statistics read back as zero.
617 extern __checkReturn efx_rc_t
618 efx_mac_stats_upload(
620 __in efsys_mem_t *esmp);
622 extern __checkReturn efx_rc_t
623 efx_mac_stats_periodic(
625 __in efsys_mem_t *esmp,
626 __in uint16_t period_ms,
627 __in boolean_t events);
629 extern __checkReturn efx_rc_t
630 efx_mac_stats_update(
632 __in efsys_mem_t *esmp,
633 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
634 __inout_opt uint32_t *generationp);
636 #endif /* EFSYS_OPT_MAC_STATS */
640 typedef enum efx_mon_type_e {
652 __in efx_nic_t *enp);
654 #endif /* EFSYS_OPT_NAMES */
656 extern __checkReturn efx_rc_t
658 __in efx_nic_t *enp);
660 #if EFSYS_OPT_MON_STATS
662 #define EFX_MON_STATS_PAGE_SIZE 0x100
663 #define EFX_MON_MASK_ELEMENT_SIZE 32
665 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
666 typedef enum efx_mon_stat_e {
673 EFX_MON_STAT_EXT_TEMP,
674 EFX_MON_STAT_INT_TEMP,
677 EFX_MON_STAT_INT_COOLING,
678 EFX_MON_STAT_EXT_COOLING,
686 EFX_MON_STAT_AOE_TEMP,
687 EFX_MON_STAT_PSU_AOE_TEMP,
688 EFX_MON_STAT_PSU_TEMP,
694 EFX_MON_STAT_VAOE_IN,
696 EFX_MON_STAT_IAOE_IN,
697 EFX_MON_STAT_NIC_POWER,
701 EFX_MON_STAT_0_9V_ADC,
702 EFX_MON_STAT_INT_TEMP2,
703 EFX_MON_STAT_VREG_TEMP,
704 EFX_MON_STAT_VREG_0_9V_TEMP,
705 EFX_MON_STAT_VREG_1_2V_TEMP,
706 EFX_MON_STAT_INT_VPTAT,
707 EFX_MON_STAT_INT_ADC_TEMP,
708 EFX_MON_STAT_EXT_VPTAT,
709 EFX_MON_STAT_EXT_ADC_TEMP,
710 EFX_MON_STAT_AMBIENT_TEMP,
711 EFX_MON_STAT_AIRFLOW,
712 EFX_MON_STAT_VDD08D_VSS08D_CSR,
713 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
714 EFX_MON_STAT_HOTPOINT_TEMP,
715 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
716 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
717 EFX_MON_STAT_MUM_VCC,
720 EFX_MON_STAT_0V9_A_TEMP,
723 EFX_MON_STAT_0V9_B_TEMP,
724 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
725 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
726 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
727 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
728 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
729 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
730 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
731 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
732 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
733 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
734 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
735 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
736 EFX_MON_STAT_SODIMM_VOUT,
737 EFX_MON_STAT_SODIMM_0_TEMP,
738 EFX_MON_STAT_SODIMM_1_TEMP,
739 EFX_MON_STAT_PHY0_VCC,
740 EFX_MON_STAT_PHY1_VCC,
741 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
742 EFX_MON_STAT_BOARD_FRONT_TEMP,
743 EFX_MON_STAT_BOARD_BACK_TEMP,
753 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
755 typedef enum efx_mon_stat_state_e {
756 EFX_MON_STAT_STATE_OK = 0,
757 EFX_MON_STAT_STATE_WARNING = 1,
758 EFX_MON_STAT_STATE_FATAL = 2,
759 EFX_MON_STAT_STATE_BROKEN = 3,
760 EFX_MON_STAT_STATE_NO_READING = 4,
761 } efx_mon_stat_state_t;
763 typedef struct efx_mon_stat_value_s {
766 } efx_mon_stat_value_t;
773 __in efx_mon_stat_t id);
775 #endif /* EFSYS_OPT_NAMES */
777 extern __checkReturn efx_rc_t
778 efx_mon_stats_update(
780 __in efsys_mem_t *esmp,
781 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
783 #endif /* EFSYS_OPT_MON_STATS */
787 __in efx_nic_t *enp);
791 extern __checkReturn efx_rc_t
793 __in efx_nic_t *enp);
795 #if EFSYS_OPT_PHY_LED_CONTROL
797 typedef enum efx_phy_led_mode_e {
798 EFX_PHY_LED_DEFAULT = 0,
803 } efx_phy_led_mode_t;
805 extern __checkReturn efx_rc_t
808 __in efx_phy_led_mode_t mode);
810 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
812 extern __checkReturn efx_rc_t
814 __in efx_nic_t *enp);
816 #if EFSYS_OPT_LOOPBACK
818 typedef enum efx_loopback_type_e {
819 EFX_LOOPBACK_OFF = 0,
820 EFX_LOOPBACK_DATA = 1,
821 EFX_LOOPBACK_GMAC = 2,
822 EFX_LOOPBACK_XGMII = 3,
823 EFX_LOOPBACK_XGXS = 4,
824 EFX_LOOPBACK_XAUI = 5,
825 EFX_LOOPBACK_GMII = 6,
826 EFX_LOOPBACK_SGMII = 7,
827 EFX_LOOPBACK_XGBR = 8,
828 EFX_LOOPBACK_XFI = 9,
829 EFX_LOOPBACK_XAUI_FAR = 10,
830 EFX_LOOPBACK_GMII_FAR = 11,
831 EFX_LOOPBACK_SGMII_FAR = 12,
832 EFX_LOOPBACK_XFI_FAR = 13,
833 EFX_LOOPBACK_GPHY = 14,
834 EFX_LOOPBACK_PHY_XS = 15,
835 EFX_LOOPBACK_PCS = 16,
836 EFX_LOOPBACK_PMA_PMD = 17,
837 EFX_LOOPBACK_XPORT = 18,
838 EFX_LOOPBACK_XGMII_WS = 19,
839 EFX_LOOPBACK_XAUI_WS = 20,
840 EFX_LOOPBACK_XAUI_WS_FAR = 21,
841 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
842 EFX_LOOPBACK_GMII_WS = 23,
843 EFX_LOOPBACK_XFI_WS = 24,
844 EFX_LOOPBACK_XFI_WS_FAR = 25,
845 EFX_LOOPBACK_PHYXS_WS = 26,
846 EFX_LOOPBACK_PMA_INT = 27,
847 EFX_LOOPBACK_SD_NEAR = 28,
848 EFX_LOOPBACK_SD_FAR = 29,
849 EFX_LOOPBACK_PMA_INT_WS = 30,
850 EFX_LOOPBACK_SD_FEP2_WS = 31,
851 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
852 EFX_LOOPBACK_SD_FEP_WS = 33,
853 EFX_LOOPBACK_SD_FES_WS = 34,
854 EFX_LOOPBACK_AOE_INT_NEAR = 35,
855 EFX_LOOPBACK_DATA_WS = 36,
856 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
858 } efx_loopback_type_t;
860 typedef enum efx_loopback_kind_e {
861 EFX_LOOPBACK_KIND_OFF = 0,
862 EFX_LOOPBACK_KIND_ALL,
863 EFX_LOOPBACK_KIND_MAC,
864 EFX_LOOPBACK_KIND_PHY,
866 } efx_loopback_kind_t;
870 __in efx_loopback_kind_t loopback_kind,
871 __out efx_qword_t *maskp);
873 extern __checkReturn efx_rc_t
874 efx_port_loopback_set(
876 __in efx_link_mode_t link_mode,
877 __in efx_loopback_type_t type);
881 extern __checkReturn const char *
882 efx_loopback_type_name(
884 __in efx_loopback_type_t type);
886 #endif /* EFSYS_OPT_NAMES */
888 #endif /* EFSYS_OPT_LOOPBACK */
890 extern __checkReturn efx_rc_t
893 __out_opt efx_link_mode_t *link_modep);
897 __in efx_nic_t *enp);
899 typedef enum efx_phy_cap_type_e {
900 EFX_PHY_CAP_INVALID = 0,
907 EFX_PHY_CAP_10000FDX,
911 EFX_PHY_CAP_40000FDX,
913 EFX_PHY_CAP_100000FDX,
914 EFX_PHY_CAP_25000FDX,
915 EFX_PHY_CAP_50000FDX,
916 EFX_PHY_CAP_BASER_FEC,
917 EFX_PHY_CAP_BASER_FEC_REQUESTED,
919 EFX_PHY_CAP_RS_FEC_REQUESTED,
920 EFX_PHY_CAP_25G_BASER_FEC,
921 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
923 } efx_phy_cap_type_t;
926 #define EFX_PHY_CAP_CURRENT 0x00000000
927 #define EFX_PHY_CAP_DEFAULT 0x00000001
928 #define EFX_PHY_CAP_PERM 0x00000002
934 __out uint32_t *maskp);
936 extern __checkReturn efx_rc_t
944 __out uint32_t *maskp);
946 extern __checkReturn efx_rc_t
949 __out uint32_t *ouip);
951 typedef enum efx_phy_media_type_e {
952 EFX_PHY_MEDIA_INVALID = 0,
957 EFX_PHY_MEDIA_SFP_PLUS,
958 EFX_PHY_MEDIA_BASE_T,
959 EFX_PHY_MEDIA_QSFP_PLUS,
961 } efx_phy_media_type_t;
964 * Get the type of medium currently used. If the board has ports for
965 * modules, a module is present, and we recognise the media type of
966 * the module, then this will be the media type of the module.
967 * Otherwise it will be the media type of the port.
970 efx_phy_media_type_get(
972 __out efx_phy_media_type_t *typep);
974 extern __checkReturn efx_rc_t
975 efx_phy_module_get_info(
977 __in uint8_t dev_addr,
980 __out_bcount(len) uint8_t *data);
982 #if EFSYS_OPT_PHY_STATS
984 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
985 typedef enum efx_phy_stat_e {
987 EFX_PHY_STAT_PMA_PMD_LINK_UP,
988 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
989 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
990 EFX_PHY_STAT_PMA_PMD_REV_A,
991 EFX_PHY_STAT_PMA_PMD_REV_B,
992 EFX_PHY_STAT_PMA_PMD_REV_C,
993 EFX_PHY_STAT_PMA_PMD_REV_D,
994 EFX_PHY_STAT_PCS_LINK_UP,
995 EFX_PHY_STAT_PCS_RX_FAULT,
996 EFX_PHY_STAT_PCS_TX_FAULT,
997 EFX_PHY_STAT_PCS_BER,
998 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
999 EFX_PHY_STAT_PHY_XS_LINK_UP,
1000 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1001 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1002 EFX_PHY_STAT_PHY_XS_ALIGN,
1003 EFX_PHY_STAT_PHY_XS_SYNC_A,
1004 EFX_PHY_STAT_PHY_XS_SYNC_B,
1005 EFX_PHY_STAT_PHY_XS_SYNC_C,
1006 EFX_PHY_STAT_PHY_XS_SYNC_D,
1007 EFX_PHY_STAT_AN_LINK_UP,
1008 EFX_PHY_STAT_AN_MASTER,
1009 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1010 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1011 EFX_PHY_STAT_CL22EXT_LINK_UP,
1016 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1017 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1018 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1019 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1020 EFX_PHY_STAT_AN_COMPLETE,
1021 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1022 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1023 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1024 EFX_PHY_STAT_PCS_FW_VERSION_0,
1025 EFX_PHY_STAT_PCS_FW_VERSION_1,
1026 EFX_PHY_STAT_PCS_FW_VERSION_2,
1027 EFX_PHY_STAT_PCS_FW_VERSION_3,
1028 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1029 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1030 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1031 EFX_PHY_STAT_PCS_OP_MODE,
1035 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1041 __in efx_nic_t *enp,
1042 __in efx_phy_stat_t stat);
1044 #endif /* EFSYS_OPT_NAMES */
1046 #define EFX_PHY_STATS_SIZE 0x100
1048 extern __checkReturn efx_rc_t
1049 efx_phy_stats_update(
1050 __in efx_nic_t *enp,
1051 __in efsys_mem_t *esmp,
1052 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1054 #endif /* EFSYS_OPT_PHY_STATS */
1059 typedef enum efx_bist_type_e {
1060 EFX_BIST_TYPE_UNKNOWN,
1061 EFX_BIST_TYPE_PHY_NORMAL,
1062 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1063 EFX_BIST_TYPE_PHY_CABLE_LONG,
1064 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1065 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1066 EFX_BIST_TYPE_REG, /* Test the register memories */
1067 EFX_BIST_TYPE_NTYPES,
1070 typedef enum efx_bist_result_e {
1071 EFX_BIST_RESULT_UNKNOWN,
1072 EFX_BIST_RESULT_RUNNING,
1073 EFX_BIST_RESULT_PASSED,
1074 EFX_BIST_RESULT_FAILED,
1075 } efx_bist_result_t;
1077 typedef enum efx_phy_cable_status_e {
1078 EFX_PHY_CABLE_STATUS_OK,
1079 EFX_PHY_CABLE_STATUS_INVALID,
1080 EFX_PHY_CABLE_STATUS_OPEN,
1081 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1082 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1083 EFX_PHY_CABLE_STATUS_BUSY,
1084 } efx_phy_cable_status_t;
1086 typedef enum efx_bist_value_e {
1087 EFX_BIST_PHY_CABLE_LENGTH_A,
1088 EFX_BIST_PHY_CABLE_LENGTH_B,
1089 EFX_BIST_PHY_CABLE_LENGTH_C,
1090 EFX_BIST_PHY_CABLE_LENGTH_D,
1091 EFX_BIST_PHY_CABLE_STATUS_A,
1092 EFX_BIST_PHY_CABLE_STATUS_B,
1093 EFX_BIST_PHY_CABLE_STATUS_C,
1094 EFX_BIST_PHY_CABLE_STATUS_D,
1095 EFX_BIST_FAULT_CODE,
1097 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1103 EFX_BIST_MEM_EXPECT,
1104 EFX_BIST_MEM_ACTUAL,
1106 EFX_BIST_MEM_ECC_PARITY,
1107 EFX_BIST_MEM_ECC_FATAL,
1111 extern __checkReturn efx_rc_t
1112 efx_bist_enable_offline(
1113 __in efx_nic_t *enp);
1115 extern __checkReturn efx_rc_t
1117 __in efx_nic_t *enp,
1118 __in efx_bist_type_t type);
1120 extern __checkReturn efx_rc_t
1122 __in efx_nic_t *enp,
1123 __in efx_bist_type_t type,
1124 __out efx_bist_result_t *resultp,
1125 __out_opt uint32_t *value_maskp,
1126 __out_ecount_opt(count) unsigned long *valuesp,
1131 __in efx_nic_t *enp,
1132 __in efx_bist_type_t type);
1134 #endif /* EFSYS_OPT_BIST */
1136 #define EFX_FEATURE_IPV6 0x00000001
1137 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1138 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1139 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1140 #define EFX_FEATURE_MCDI 0x00000020
1141 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1142 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1143 #define EFX_FEATURE_TURBO 0x00000100
1144 #define EFX_FEATURE_MCDI_DMA 0x00000200
1145 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1146 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1147 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1148 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1149 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1151 typedef enum efx_tunnel_protocol_e {
1152 EFX_TUNNEL_PROTOCOL_NONE = 0,
1153 EFX_TUNNEL_PROTOCOL_VXLAN,
1154 EFX_TUNNEL_PROTOCOL_GENEVE,
1155 EFX_TUNNEL_PROTOCOL_NVGRE,
1157 } efx_tunnel_protocol_t;
1159 typedef enum efx_vi_window_shift_e {
1160 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1161 EFX_VI_WINDOW_SHIFT_8K = 13,
1162 EFX_VI_WINDOW_SHIFT_16K = 14,
1163 EFX_VI_WINDOW_SHIFT_64K = 16,
1164 } efx_vi_window_shift_t;
1166 typedef struct efx_nic_cfg_s {
1167 uint32_t enc_board_type;
1168 uint32_t enc_phy_type;
1170 char enc_phy_name[21];
1172 char enc_phy_revision[21];
1173 efx_mon_type_t enc_mon_type;
1174 #if EFSYS_OPT_MON_STATS
1175 uint32_t enc_mon_stat_dma_buf_size;
1176 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1178 unsigned int enc_features;
1179 efx_vi_window_shift_t enc_vi_window_shift;
1180 uint8_t enc_mac_addr[6];
1181 uint8_t enc_port; /* PHY port number */
1182 uint32_t enc_intr_vec_base;
1183 uint32_t enc_intr_limit;
1184 uint32_t enc_evq_limit;
1185 uint32_t enc_txq_limit;
1186 uint32_t enc_rxq_limit;
1187 uint32_t enc_txq_max_ndescs;
1188 uint32_t enc_buftbl_limit;
1189 uint32_t enc_piobuf_limit;
1190 uint32_t enc_piobuf_size;
1191 uint32_t enc_piobuf_min_alloc_size;
1192 uint32_t enc_evq_timer_quantum_ns;
1193 uint32_t enc_evq_timer_max_us;
1194 uint32_t enc_clk_mult;
1195 uint32_t enc_rx_prefix_size;
1196 uint32_t enc_rx_buf_align_start;
1197 uint32_t enc_rx_buf_align_end;
1198 uint32_t enc_rx_scale_max_exclusive_contexts;
1200 * Mask of supported hash algorithms.
1201 * Hash algorithm types are used as the bit indices.
1203 uint32_t enc_rx_scale_hash_alg_mask;
1205 * Indicates whether port numbers can be included to the
1206 * input data for hash computation.
1208 boolean_t enc_rx_scale_l4_hash_supported;
1209 boolean_t enc_rx_scale_additional_modes_supported;
1210 #if EFSYS_OPT_LOOPBACK
1211 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1212 #endif /* EFSYS_OPT_LOOPBACK */
1213 #if EFSYS_OPT_PHY_FLAGS
1214 uint32_t enc_phy_flags_mask;
1215 #endif /* EFSYS_OPT_PHY_FLAGS */
1216 #if EFSYS_OPT_PHY_LED_CONTROL
1217 uint32_t enc_led_mask;
1218 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1219 #if EFSYS_OPT_PHY_STATS
1220 uint64_t enc_phy_stat_mask;
1221 #endif /* EFSYS_OPT_PHY_STATS */
1223 uint8_t enc_mcdi_mdio_channel;
1224 #if EFSYS_OPT_PHY_STATS
1225 uint32_t enc_mcdi_phy_stat_mask;
1226 #endif /* EFSYS_OPT_PHY_STATS */
1227 #if EFSYS_OPT_MON_STATS
1228 uint32_t *enc_mcdi_sensor_maskp;
1229 uint32_t enc_mcdi_sensor_mask_size;
1230 #endif /* EFSYS_OPT_MON_STATS */
1231 #endif /* EFSYS_OPT_MCDI */
1233 uint32_t enc_bist_mask;
1234 #endif /* EFSYS_OPT_BIST */
1235 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1238 uint32_t enc_privilege_mask;
1239 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1240 boolean_t enc_bug26807_workaround;
1241 boolean_t enc_bug35388_workaround;
1242 boolean_t enc_bug41750_workaround;
1243 boolean_t enc_bug61265_workaround;
1244 boolean_t enc_rx_batching_enabled;
1245 /* Maximum number of descriptors completed in an rx event. */
1246 uint32_t enc_rx_batch_max;
1247 /* Number of rx descriptors the hardware requires for a push. */
1248 uint32_t enc_rx_push_align;
1249 /* Maximum amount of data in DMA descriptor */
1250 uint32_t enc_tx_dma_desc_size_max;
1252 * Boundary which DMA descriptor data must not cross or 0 if no
1255 uint32_t enc_tx_dma_desc_boundary;
1257 * Maximum number of bytes into the packet the TCP header can start for
1258 * the hardware to apply TSO packet edits.
1260 uint32_t enc_tx_tso_tcp_header_offset_limit;
1261 boolean_t enc_fw_assisted_tso_enabled;
1262 boolean_t enc_fw_assisted_tso_v2_enabled;
1263 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1264 /* Number of TSO contexts on the NIC (FATSOv2) */
1265 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1266 boolean_t enc_hw_tx_insert_vlan_enabled;
1267 /* Number of PFs on the NIC */
1268 uint32_t enc_hw_pf_count;
1269 /* Datapath firmware vadapter/vport/vswitch support */
1270 boolean_t enc_datapath_cap_evb;
1271 boolean_t enc_rx_disable_scatter_supported;
1272 boolean_t enc_allow_set_mac_with_installed_filters;
1273 boolean_t enc_enhanced_set_mac_supported;
1274 boolean_t enc_init_evq_v2_supported;
1275 boolean_t enc_rx_packed_stream_supported;
1276 boolean_t enc_rx_var_packed_stream_supported;
1277 boolean_t enc_rx_es_super_buffer_supported;
1278 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1279 boolean_t enc_pm_and_rxdp_counters;
1280 boolean_t enc_mac_stats_40g_tx_size_bins;
1281 uint32_t enc_tunnel_encapsulations_supported;
1283 * NIC global maximum for unique UDP tunnel ports shared by all
1286 uint32_t enc_tunnel_config_udp_entries_max;
1287 /* External port identifier */
1288 uint8_t enc_external_port;
1289 uint32_t enc_mcdi_max_payload_length;
1290 /* VPD may be per-PF or global */
1291 boolean_t enc_vpd_is_global;
1292 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1293 uint32_t enc_required_pcie_bandwidth_mbps;
1294 uint32_t enc_max_pcie_link_gen;
1295 /* Firmware verifies integrity of NVRAM updates */
1296 uint32_t enc_nvram_update_verify_result_supported;
1297 /* Firmware support for extended MAC_STATS buffer */
1298 uint32_t enc_mac_stats_nstats;
1299 boolean_t enc_fec_counters;
1300 boolean_t enc_hlb_counters;
1301 /* Firmware support for "FLAG" and "MARK" filter actions */
1302 boolean_t enc_filter_action_flag_supported;
1303 boolean_t enc_filter_action_mark_supported;
1304 uint32_t enc_filter_action_mark_max;
1307 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1308 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1310 #define EFX_PCI_FUNCTION(_encp) \
1311 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1313 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1315 extern const efx_nic_cfg_t *
1317 __in efx_nic_t *enp);
1319 /* RxDPCPU firmware id values by which FW variant can be identified */
1320 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1321 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1322 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1323 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1324 #define EFX_RXDP_DPDK_FW_ID 0x6
1326 typedef struct efx_nic_fw_info_s {
1327 /* Basic FW version information */
1328 uint16_t enfi_mc_fw_version[4];
1330 * If datapath capabilities can be detected,
1331 * additional FW information is to be shown
1333 boolean_t enfi_dpcpu_fw_ids_valid;
1334 /* Rx and Tx datapath CPU FW IDs */
1335 uint16_t enfi_rx_dpcpu_fw_id;
1336 uint16_t enfi_tx_dpcpu_fw_id;
1337 } efx_nic_fw_info_t;
1339 extern __checkReturn efx_rc_t
1340 efx_nic_get_fw_version(
1341 __in efx_nic_t *enp,
1342 __out efx_nic_fw_info_t *enfip);
1344 /* Driver resource limits (minimum required/maximum usable). */
1345 typedef struct efx_drv_limits_s {
1346 uint32_t edl_min_evq_count;
1347 uint32_t edl_max_evq_count;
1349 uint32_t edl_min_rxq_count;
1350 uint32_t edl_max_rxq_count;
1352 uint32_t edl_min_txq_count;
1353 uint32_t edl_max_txq_count;
1355 /* PIO blocks (sub-allocated from piobuf) */
1356 uint32_t edl_min_pio_alloc_size;
1357 uint32_t edl_max_pio_alloc_count;
1360 extern __checkReturn efx_rc_t
1361 efx_nic_set_drv_limits(
1362 __inout efx_nic_t *enp,
1363 __in efx_drv_limits_t *edlp);
1365 typedef enum efx_nic_region_e {
1366 EFX_REGION_VI, /* Memory BAR UC mapping */
1367 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1370 extern __checkReturn efx_rc_t
1371 efx_nic_get_bar_region(
1372 __in efx_nic_t *enp,
1373 __in efx_nic_region_t region,
1374 __out uint32_t *offsetp,
1375 __out size_t *sizep);
1377 extern __checkReturn efx_rc_t
1378 efx_nic_get_vi_pool(
1379 __in efx_nic_t *enp,
1380 __out uint32_t *evq_countp,
1381 __out uint32_t *rxq_countp,
1382 __out uint32_t *txq_countp);
1387 typedef enum efx_vpd_tag_e {
1394 typedef uint16_t efx_vpd_keyword_t;
1396 typedef struct efx_vpd_value_s {
1397 efx_vpd_tag_t evv_tag;
1398 efx_vpd_keyword_t evv_keyword;
1400 uint8_t evv_value[0x100];
1404 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1406 extern __checkReturn efx_rc_t
1408 __in efx_nic_t *enp);
1410 extern __checkReturn efx_rc_t
1412 __in efx_nic_t *enp,
1413 __out size_t *sizep);
1415 extern __checkReturn efx_rc_t
1417 __in efx_nic_t *enp,
1418 __out_bcount(size) caddr_t data,
1421 extern __checkReturn efx_rc_t
1423 __in efx_nic_t *enp,
1424 __in_bcount(size) caddr_t data,
1427 extern __checkReturn efx_rc_t
1429 __in efx_nic_t *enp,
1430 __in_bcount(size) caddr_t data,
1433 extern __checkReturn efx_rc_t
1435 __in efx_nic_t *enp,
1436 __in_bcount(size) caddr_t data,
1438 __inout efx_vpd_value_t *evvp);
1440 extern __checkReturn efx_rc_t
1442 __in efx_nic_t *enp,
1443 __inout_bcount(size) caddr_t data,
1445 __in efx_vpd_value_t *evvp);
1447 extern __checkReturn efx_rc_t
1449 __in efx_nic_t *enp,
1450 __inout_bcount(size) caddr_t data,
1452 __out efx_vpd_value_t *evvp,
1453 __inout unsigned int *contp);
1455 extern __checkReturn efx_rc_t
1457 __in efx_nic_t *enp,
1458 __in_bcount(size) caddr_t data,
1463 __in efx_nic_t *enp);
1465 #endif /* EFSYS_OPT_VPD */
1471 typedef enum efx_nvram_type_e {
1472 EFX_NVRAM_INVALID = 0,
1474 EFX_NVRAM_BOOTROM_CFG,
1475 EFX_NVRAM_MC_FIRMWARE,
1476 EFX_NVRAM_MC_GOLDEN,
1482 EFX_NVRAM_FPGA_BACKUP,
1483 EFX_NVRAM_DYNAMIC_CFG,
1486 EFX_NVRAM_MUM_FIRMWARE,
1487 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1488 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1492 extern __checkReturn efx_rc_t
1494 __in efx_nic_t *enp);
1498 extern __checkReturn efx_rc_t
1500 __in efx_nic_t *enp);
1502 #endif /* EFSYS_OPT_DIAG */
1504 extern __checkReturn efx_rc_t
1506 __in efx_nic_t *enp,
1507 __in efx_nvram_type_t type,
1508 __out size_t *sizep);
1510 extern __checkReturn efx_rc_t
1512 __in efx_nic_t *enp,
1513 __in efx_nvram_type_t type,
1514 __out_opt size_t *pref_chunkp);
1516 extern __checkReturn efx_rc_t
1517 efx_nvram_rw_finish(
1518 __in efx_nic_t *enp,
1519 __in efx_nvram_type_t type,
1520 __out_opt uint32_t *verify_resultp);
1522 extern __checkReturn efx_rc_t
1523 efx_nvram_get_version(
1524 __in efx_nic_t *enp,
1525 __in efx_nvram_type_t type,
1526 __out uint32_t *subtypep,
1527 __out_ecount(4) uint16_t version[4]);
1529 extern __checkReturn efx_rc_t
1530 efx_nvram_read_chunk(
1531 __in efx_nic_t *enp,
1532 __in efx_nvram_type_t type,
1533 __in unsigned int offset,
1534 __out_bcount(size) caddr_t data,
1537 extern __checkReturn efx_rc_t
1538 efx_nvram_read_backup(
1539 __in efx_nic_t *enp,
1540 __in efx_nvram_type_t type,
1541 __in unsigned int offset,
1542 __out_bcount(size) caddr_t data,
1545 extern __checkReturn efx_rc_t
1546 efx_nvram_set_version(
1547 __in efx_nic_t *enp,
1548 __in efx_nvram_type_t type,
1549 __in_ecount(4) uint16_t version[4]);
1551 extern __checkReturn efx_rc_t
1553 __in efx_nic_t *enp,
1554 __in efx_nvram_type_t type,
1555 __in_bcount(partn_size) caddr_t partn_data,
1556 __in size_t partn_size);
1558 extern __checkReturn efx_rc_t
1560 __in efx_nic_t *enp,
1561 __in efx_nvram_type_t type);
1563 extern __checkReturn efx_rc_t
1564 efx_nvram_write_chunk(
1565 __in efx_nic_t *enp,
1566 __in efx_nvram_type_t type,
1567 __in unsigned int offset,
1568 __in_bcount(size) caddr_t data,
1573 __in efx_nic_t *enp);
1575 #endif /* EFSYS_OPT_NVRAM */
1577 #if EFSYS_OPT_BOOTCFG
1579 /* Report size and offset of bootcfg sector in NVRAM partition. */
1580 extern __checkReturn efx_rc_t
1581 efx_bootcfg_sector_info(
1582 __in efx_nic_t *enp,
1584 __out_opt uint32_t *sector_countp,
1585 __out size_t *offsetp,
1586 __out size_t *max_sizep);
1589 * Copy bootcfg sector data to a target buffer which may differ in size.
1590 * Optionally corrects format errors in source buffer.
1593 efx_bootcfg_copy_sector(
1594 __in efx_nic_t *enp,
1595 __inout_bcount(sector_length)
1597 __in size_t sector_length,
1598 __out_bcount(data_size) uint8_t *data,
1599 __in size_t data_size,
1600 __in boolean_t handle_format_errors);
1604 __in efx_nic_t *enp,
1605 __out_bcount(size) uint8_t *data,
1610 __in efx_nic_t *enp,
1611 __in_bcount(size) uint8_t *data,
1614 #endif /* EFSYS_OPT_BOOTCFG */
1616 #if EFSYS_OPT_IMAGE_LAYOUT
1618 #include "ef10_signed_image_layout.h"
1621 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1624 * The image header format is extensible. However, older drivers require an
1625 * exact match of image header version and header length when validating and
1626 * writing firmware images.
1628 * To avoid breaking backward compatibility, we use the upper bits of the
1629 * controller version fields to contain an extra version number used for
1630 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1631 * version). See bug39254 and SF-102785-PS for details.
1633 typedef struct efx_image_header_s {
1635 uint32_t eih_version;
1637 uint32_t eih_subtype;
1638 uint32_t eih_code_size;
1641 uint32_t eih_controller_version_min;
1643 uint16_t eih_controller_version_min_short;
1644 uint8_t eih_extra_version_a;
1645 uint8_t eih_extra_version_b;
1649 uint32_t eih_controller_version_max;
1651 uint16_t eih_controller_version_max_short;
1652 uint8_t eih_extra_version_c;
1653 uint8_t eih_extra_version_d;
1656 uint16_t eih_code_version_a;
1657 uint16_t eih_code_version_b;
1658 uint16_t eih_code_version_c;
1659 uint16_t eih_code_version_d;
1660 } efx_image_header_t;
1662 #define EFX_IMAGE_HEADER_SIZE (40)
1663 #define EFX_IMAGE_HEADER_VERSION (4)
1664 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1667 typedef struct efx_image_trailer_s {
1669 } efx_image_trailer_t;
1671 #define EFX_IMAGE_TRAILER_SIZE (4)
1673 typedef enum efx_image_format_e {
1674 EFX_IMAGE_FORMAT_NO_IMAGE,
1675 EFX_IMAGE_FORMAT_INVALID,
1676 EFX_IMAGE_FORMAT_UNSIGNED,
1677 EFX_IMAGE_FORMAT_SIGNED,
1678 } efx_image_format_t;
1680 typedef struct efx_image_info_s {
1681 efx_image_format_t eii_format;
1682 uint8_t * eii_imagep;
1683 size_t eii_image_size;
1684 efx_image_header_t * eii_headerp;
1687 extern __checkReturn efx_rc_t
1688 efx_check_reflash_image(
1690 __in uint32_t buffer_size,
1691 __out efx_image_info_t *infop);
1693 extern __checkReturn efx_rc_t
1694 efx_build_signed_image_write_buffer(
1695 __out_bcount(buffer_size)
1697 __in uint32_t buffer_size,
1698 __in efx_image_info_t *infop,
1699 __out efx_image_header_t **headerpp);
1701 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1705 typedef enum efx_pattern_type_t {
1706 EFX_PATTERN_BYTE_INCREMENT = 0,
1707 EFX_PATTERN_ALL_THE_SAME,
1708 EFX_PATTERN_BIT_ALTERNATE,
1709 EFX_PATTERN_BYTE_ALTERNATE,
1710 EFX_PATTERN_BYTE_CHANGING,
1711 EFX_PATTERN_BIT_SWEEP,
1713 } efx_pattern_type_t;
1716 (*efx_sram_pattern_fn_t)(
1718 __in boolean_t negate,
1719 __out efx_qword_t *eqp);
1721 extern __checkReturn efx_rc_t
1723 __in efx_nic_t *enp,
1724 __in efx_pattern_type_t type);
1726 #endif /* EFSYS_OPT_DIAG */
1728 extern __checkReturn efx_rc_t
1729 efx_sram_buf_tbl_set(
1730 __in efx_nic_t *enp,
1732 __in efsys_mem_t *esmp,
1736 efx_sram_buf_tbl_clear(
1737 __in efx_nic_t *enp,
1741 #define EFX_BUF_TBL_SIZE 0x20000
1743 #define EFX_BUF_SIZE 4096
1747 typedef struct efx_evq_s efx_evq_t;
1749 #if EFSYS_OPT_QSTATS
1751 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1752 typedef enum efx_ev_qstat_e {
1758 EV_RX_PAUSE_FRM_ERR,
1759 EV_RX_BUF_OWNER_ID_ERR,
1760 EV_RX_IPV4_HDR_CHKSUM_ERR,
1761 EV_RX_TCP_UDP_CHKSUM_ERR,
1765 EV_RX_MCAST_HASH_MATCH,
1782 EV_DRIVER_SRM_UPD_DONE,
1783 EV_DRIVER_TX_DESCQ_FLS_DONE,
1784 EV_DRIVER_RX_DESCQ_FLS_DONE,
1785 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1786 EV_DRIVER_RX_DSC_ERROR,
1787 EV_DRIVER_TX_DSC_ERROR,
1793 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1795 #endif /* EFSYS_OPT_QSTATS */
1797 extern __checkReturn efx_rc_t
1799 __in efx_nic_t *enp);
1803 __in efx_nic_t *enp);
1805 #define EFX_EVQ_MAXNEVS 32768
1806 #define EFX_EVQ_MINNEVS 512
1808 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1809 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1811 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1812 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1813 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1814 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1816 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1817 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1818 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1820 extern __checkReturn efx_rc_t
1822 __in efx_nic_t *enp,
1823 __in unsigned int index,
1824 __in efsys_mem_t *esmp,
1828 __in uint32_t flags,
1829 __deref_out efx_evq_t **eepp);
1833 __in efx_evq_t *eep,
1834 __in uint16_t data);
1836 typedef __checkReturn boolean_t
1837 (*efx_initialized_ev_t)(
1838 __in_opt void *arg);
1840 #define EFX_PKT_UNICAST 0x0004
1841 #define EFX_PKT_START 0x0008
1843 #define EFX_PKT_VLAN_TAGGED 0x0010
1844 #define EFX_CKSUM_TCPUDP 0x0020
1845 #define EFX_CKSUM_IPV4 0x0040
1846 #define EFX_PKT_CONT 0x0080
1848 #define EFX_CHECK_VLAN 0x0100
1849 #define EFX_PKT_TCP 0x0200
1850 #define EFX_PKT_UDP 0x0400
1851 #define EFX_PKT_IPV4 0x0800
1853 #define EFX_PKT_IPV6 0x1000
1854 #define EFX_PKT_PREFIX_LEN 0x2000
1855 #define EFX_ADDR_MISMATCH 0x4000
1856 #define EFX_DISCARD 0x8000
1859 * The following flags are used only for packed stream
1860 * mode. The values for the flags are reused to fit into 16 bit,
1861 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1862 * packed stream mode
1864 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1865 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1868 #define EFX_EV_RX_NLABELS 32
1869 #define EFX_EV_TX_NLABELS 32
1871 typedef __checkReturn boolean_t
1874 __in uint32_t label,
1877 __in uint16_t flags);
1879 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1882 * Packed stream mode is documented in SF-112241-TC.
1883 * The general idea is that, instead of putting each incoming
1884 * packet into a separate buffer which is specified in a RX
1885 * descriptor, a large buffer is provided to the hardware and
1886 * packets are put there in a continuous stream.
1887 * The main advantage of such an approach is that RX queue refilling
1888 * happens much less frequently.
1890 * Equal stride packed stream mode is documented in SF-119419-TC.
1891 * The general idea is to utilize advantages of the packed stream,
1892 * but avoid indirection in packets representation.
1893 * The main advantage of such an approach is that RX queue refilling
1894 * happens much less frequently and packets buffers are independent
1895 * from upper layers point of view.
1898 typedef __checkReturn boolean_t
1901 __in uint32_t label,
1903 __in uint32_t pkt_count,
1904 __in uint16_t flags);
1908 typedef __checkReturn boolean_t
1911 __in uint32_t label,
1914 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1915 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1916 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1917 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1918 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1919 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1920 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1921 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1922 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1924 typedef __checkReturn boolean_t
1925 (*efx_exception_ev_t)(
1927 __in uint32_t label,
1928 __in uint32_t data);
1930 typedef __checkReturn boolean_t
1931 (*efx_rxq_flush_done_ev_t)(
1933 __in uint32_t rxq_index);
1935 typedef __checkReturn boolean_t
1936 (*efx_rxq_flush_failed_ev_t)(
1938 __in uint32_t rxq_index);
1940 typedef __checkReturn boolean_t
1941 (*efx_txq_flush_done_ev_t)(
1943 __in uint32_t txq_index);
1945 typedef __checkReturn boolean_t
1946 (*efx_software_ev_t)(
1948 __in uint16_t magic);
1950 typedef __checkReturn boolean_t
1953 __in uint32_t code);
1955 #define EFX_SRAM_CLEAR 0
1956 #define EFX_SRAM_UPDATE 1
1957 #define EFX_SRAM_ILLEGAL_CLEAR 2
1959 typedef __checkReturn boolean_t
1960 (*efx_wake_up_ev_t)(
1962 __in uint32_t label);
1964 typedef __checkReturn boolean_t
1967 __in uint32_t label);
1969 typedef __checkReturn boolean_t
1970 (*efx_link_change_ev_t)(
1972 __in efx_link_mode_t link_mode);
1974 #if EFSYS_OPT_MON_STATS
1976 typedef __checkReturn boolean_t
1977 (*efx_monitor_ev_t)(
1979 __in efx_mon_stat_t id,
1980 __in efx_mon_stat_value_t value);
1982 #endif /* EFSYS_OPT_MON_STATS */
1984 #if EFSYS_OPT_MAC_STATS
1986 typedef __checkReturn boolean_t
1987 (*efx_mac_stats_ev_t)(
1989 __in uint32_t generation);
1991 #endif /* EFSYS_OPT_MAC_STATS */
1993 typedef struct efx_ev_callbacks_s {
1994 efx_initialized_ev_t eec_initialized;
1996 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1997 efx_rx_ps_ev_t eec_rx_ps;
2000 efx_exception_ev_t eec_exception;
2001 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2002 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2003 efx_txq_flush_done_ev_t eec_txq_flush_done;
2004 efx_software_ev_t eec_software;
2005 efx_sram_ev_t eec_sram;
2006 efx_wake_up_ev_t eec_wake_up;
2007 efx_timer_ev_t eec_timer;
2008 efx_link_change_ev_t eec_link_change;
2009 #if EFSYS_OPT_MON_STATS
2010 efx_monitor_ev_t eec_monitor;
2011 #endif /* EFSYS_OPT_MON_STATS */
2012 #if EFSYS_OPT_MAC_STATS
2013 efx_mac_stats_ev_t eec_mac_stats;
2014 #endif /* EFSYS_OPT_MAC_STATS */
2015 } efx_ev_callbacks_t;
2017 extern __checkReturn boolean_t
2019 __in efx_evq_t *eep,
2020 __in unsigned int count);
2022 #if EFSYS_OPT_EV_PREFETCH
2026 __in efx_evq_t *eep,
2027 __in unsigned int count);
2029 #endif /* EFSYS_OPT_EV_PREFETCH */
2033 __in efx_evq_t *eep,
2034 __inout unsigned int *countp,
2035 __in const efx_ev_callbacks_t *eecp,
2036 __in_opt void *arg);
2038 extern __checkReturn efx_rc_t
2039 efx_ev_usecs_to_ticks(
2040 __in efx_nic_t *enp,
2041 __in unsigned int usecs,
2042 __out unsigned int *ticksp);
2044 extern __checkReturn efx_rc_t
2046 __in efx_evq_t *eep,
2047 __in unsigned int us);
2049 extern __checkReturn efx_rc_t
2051 __in efx_evq_t *eep,
2052 __in unsigned int count);
2054 #if EFSYS_OPT_QSTATS
2060 __in efx_nic_t *enp,
2061 __in unsigned int id);
2063 #endif /* EFSYS_OPT_NAMES */
2066 efx_ev_qstats_update(
2067 __in efx_evq_t *eep,
2068 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2070 #endif /* EFSYS_OPT_QSTATS */
2074 __in efx_evq_t *eep);
2078 extern __checkReturn efx_rc_t
2080 __inout efx_nic_t *enp);
2084 __in efx_nic_t *enp);
2086 #if EFSYS_OPT_RX_SCATTER
2087 __checkReturn efx_rc_t
2088 efx_rx_scatter_enable(
2089 __in efx_nic_t *enp,
2090 __in unsigned int buf_size);
2091 #endif /* EFSYS_OPT_RX_SCATTER */
2093 /* Handle to represent use of the default RSS context. */
2094 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2096 #if EFSYS_OPT_RX_SCALE
2098 typedef enum efx_rx_hash_alg_e {
2099 EFX_RX_HASHALG_LFSR = 0,
2100 EFX_RX_HASHALG_TOEPLITZ,
2101 EFX_RX_HASHALG_PACKED_STREAM,
2103 } efx_rx_hash_alg_t;
2106 * Legacy hash type flags.
2108 * They represent standard tuples for distinct traffic classes.
2110 #define EFX_RX_HASH_IPV4 (1U << 0)
2111 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2112 #define EFX_RX_HASH_IPV6 (1U << 2)
2113 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2115 #define EFX_RX_HASH_LEGACY_MASK \
2116 (EFX_RX_HASH_IPV4 | \
2117 EFX_RX_HASH_TCPIPV4 | \
2118 EFX_RX_HASH_IPV6 | \
2119 EFX_RX_HASH_TCPIPV6)
2122 * The type of the argument used by efx_rx_scale_mode_set() to
2123 * provide a means for the client drivers to configure hashing.
2125 * A properly constructed value can either be:
2126 * - a combination of legacy flags
2127 * - a combination of EFX_RX_HASH() flags
2129 typedef unsigned int efx_rx_hash_type_t;
2131 typedef enum efx_rx_hash_support_e {
2132 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2133 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2134 } efx_rx_hash_support_t;
2136 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2137 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2138 #define EFX_MAXRSS 64 /* RX indirection entry range */
2139 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2141 typedef enum efx_rx_scale_context_type_e {
2142 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2143 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2144 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2145 } efx_rx_scale_context_type_t;
2148 * Traffic classes eligible for hash computation.
2150 * Select packet headers used in computing the receive hash.
2151 * This uses the same encoding as the RSS_MODES field of
2152 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2154 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2155 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2156 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2157 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2158 #define EFX_RX_CLASS_IPV4_LBN 16
2159 #define EFX_RX_CLASS_IPV4_WIDTH 4
2160 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2161 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2162 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2163 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2164 #define EFX_RX_CLASS_IPV6_LBN 28
2165 #define EFX_RX_CLASS_IPV6_WIDTH 4
2167 #define EFX_RX_NCLASSES 6
2170 * Ancillary flags used to construct generic hash tuples.
2171 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2173 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2174 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2175 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2176 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2179 * Generic hash tuples.
2181 * They express combinations of packet fields
2182 * which can contribute to the hash value for
2183 * a particular traffic class.
2185 #define EFX_RX_CLASS_HASH_DISABLE 0
2187 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2188 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2190 #define EFX_RX_CLASS_HASH_2TUPLE \
2191 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2192 EFX_RX_CLASS_HASH_DST_ADDR)
2194 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2195 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2196 EFX_RX_CLASS_HASH_SRC_PORT)
2198 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2199 (EFX_RX_CLASS_HASH_DST_ADDR | \
2200 EFX_RX_CLASS_HASH_DST_PORT)
2202 #define EFX_RX_CLASS_HASH_4TUPLE \
2203 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2204 EFX_RX_CLASS_HASH_DST_ADDR | \
2205 EFX_RX_CLASS_HASH_SRC_PORT | \
2206 EFX_RX_CLASS_HASH_DST_PORT)
2208 #define EFX_RX_CLASS_HASH_NTUPLES 7
2211 * Hash flag constructor.
2213 * Resulting flags encode hash tuples for specific traffic classes.
2214 * The client drivers are encouraged to use these flags to form
2215 * a hash type value.
2217 #define EFX_RX_HASH(_class, _tuple) \
2218 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2219 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2222 * The maximum number of EFX_RX_HASH() flags.
2224 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2226 extern __checkReturn efx_rc_t
2227 efx_rx_scale_hash_flags_get(
2228 __in efx_nic_t *enp,
2229 __in efx_rx_hash_alg_t hash_alg,
2230 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
2231 __out unsigned int *nflagsp);
2233 extern __checkReturn efx_rc_t
2234 efx_rx_hash_default_support_get(
2235 __in efx_nic_t *enp,
2236 __out efx_rx_hash_support_t *supportp);
2239 extern __checkReturn efx_rc_t
2240 efx_rx_scale_default_support_get(
2241 __in efx_nic_t *enp,
2242 __out efx_rx_scale_context_type_t *typep);
2244 extern __checkReturn efx_rc_t
2245 efx_rx_scale_context_alloc(
2246 __in efx_nic_t *enp,
2247 __in efx_rx_scale_context_type_t type,
2248 __in uint32_t num_queues,
2249 __out uint32_t *rss_contextp);
2251 extern __checkReturn efx_rc_t
2252 efx_rx_scale_context_free(
2253 __in efx_nic_t *enp,
2254 __in uint32_t rss_context);
2256 extern __checkReturn efx_rc_t
2257 efx_rx_scale_mode_set(
2258 __in efx_nic_t *enp,
2259 __in uint32_t rss_context,
2260 __in efx_rx_hash_alg_t alg,
2261 __in efx_rx_hash_type_t type,
2262 __in boolean_t insert);
2264 extern __checkReturn efx_rc_t
2265 efx_rx_scale_tbl_set(
2266 __in efx_nic_t *enp,
2267 __in uint32_t rss_context,
2268 __in_ecount(n) unsigned int *table,
2271 extern __checkReturn efx_rc_t
2272 efx_rx_scale_key_set(
2273 __in efx_nic_t *enp,
2274 __in uint32_t rss_context,
2275 __in_ecount(n) uint8_t *key,
2278 extern __checkReturn uint32_t
2279 efx_pseudo_hdr_hash_get(
2280 __in efx_rxq_t *erp,
2281 __in efx_rx_hash_alg_t func,
2282 __in uint8_t *buffer);
2284 #endif /* EFSYS_OPT_RX_SCALE */
2286 extern __checkReturn efx_rc_t
2287 efx_pseudo_hdr_pkt_length_get(
2288 __in efx_rxq_t *erp,
2289 __in uint8_t *buffer,
2290 __out uint16_t *pkt_lengthp);
2292 #define EFX_RXQ_MAXNDESCS 4096
2293 #define EFX_RXQ_MINNDESCS 512
2295 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2296 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2297 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2298 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2300 typedef enum efx_rxq_type_e {
2301 EFX_RXQ_TYPE_DEFAULT,
2302 EFX_RXQ_TYPE_PACKED_STREAM,
2303 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2308 * Dummy flag to be used instead of 0 to make it clear that the argument
2309 * is receive queue flags.
2311 #define EFX_RXQ_FLAG_NONE 0x0
2312 #define EFX_RXQ_FLAG_SCATTER 0x1
2314 * If tunnels are supported and Rx event can provide information about
2315 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2316 * full-feature firmware variant running), outer classes are requested by
2317 * default. However, if the driver supports tunnels, the flag allows to
2318 * request inner classes which are required to be able to interpret inner
2319 * Rx checksum offload results.
2321 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2323 extern __checkReturn efx_rc_t
2325 __in efx_nic_t *enp,
2326 __in unsigned int index,
2327 __in unsigned int label,
2328 __in efx_rxq_type_t type,
2329 __in efsys_mem_t *esmp,
2332 __in unsigned int flags,
2333 __in efx_evq_t *eep,
2334 __deref_out efx_rxq_t **erpp);
2336 #if EFSYS_OPT_RX_PACKED_STREAM
2338 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2339 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2340 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2341 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2342 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2344 extern __checkReturn efx_rc_t
2345 efx_rx_qcreate_packed_stream(
2346 __in efx_nic_t *enp,
2347 __in unsigned int index,
2348 __in unsigned int label,
2349 __in uint32_t ps_buf_size,
2350 __in efsys_mem_t *esmp,
2352 __in efx_evq_t *eep,
2353 __deref_out efx_rxq_t **erpp);
2357 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2359 /* Maximum head-of-line block timeout in nanoseconds */
2360 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2362 extern __checkReturn efx_rc_t
2363 efx_rx_qcreate_es_super_buffer(
2364 __in efx_nic_t *enp,
2365 __in unsigned int index,
2366 __in unsigned int label,
2367 __in uint32_t n_bufs_per_desc,
2368 __in uint32_t max_dma_len,
2369 __in uint32_t buf_stride,
2370 __in uint32_t hol_block_timeout,
2371 __in efsys_mem_t *esmp,
2373 __in unsigned int flags,
2374 __in efx_evq_t *eep,
2375 __deref_out efx_rxq_t **erpp);
2379 typedef struct efx_buffer_s {
2380 efsys_dma_addr_t eb_addr;
2385 typedef struct efx_desc_s {
2391 __in efx_rxq_t *erp,
2392 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2394 __in unsigned int ndescs,
2395 __in unsigned int completed,
2396 __in unsigned int added);
2400 __in efx_rxq_t *erp,
2401 __in unsigned int added,
2402 __inout unsigned int *pushedp);
2404 #if EFSYS_OPT_RX_PACKED_STREAM
2407 efx_rx_qpush_ps_credits(
2408 __in efx_rxq_t *erp);
2410 extern __checkReturn uint8_t *
2411 efx_rx_qps_packet_info(
2412 __in efx_rxq_t *erp,
2413 __in uint8_t *buffer,
2414 __in uint32_t buffer_length,
2415 __in uint32_t current_offset,
2416 __out uint16_t *lengthp,
2417 __out uint32_t *next_offsetp,
2418 __out uint32_t *timestamp);
2421 extern __checkReturn efx_rc_t
2423 __in efx_rxq_t *erp);
2427 __in efx_rxq_t *erp);
2431 __in efx_rxq_t *erp);
2435 typedef struct efx_txq_s efx_txq_t;
2437 #if EFSYS_OPT_QSTATS
2439 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2440 typedef enum efx_tx_qstat_e {
2446 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2448 #endif /* EFSYS_OPT_QSTATS */
2450 extern __checkReturn efx_rc_t
2452 __in efx_nic_t *enp);
2456 __in efx_nic_t *enp);
2458 #define EFX_TXQ_MINNDESCS 512
2460 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2461 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2462 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2464 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2466 #define EFX_TXQ_CKSUM_IPV4 0x0001
2467 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2468 #define EFX_TXQ_FATSOV2 0x0004
2469 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2470 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2472 extern __checkReturn efx_rc_t
2474 __in efx_nic_t *enp,
2475 __in unsigned int index,
2476 __in unsigned int label,
2477 __in efsys_mem_t *esmp,
2480 __in uint16_t flags,
2481 __in efx_evq_t *eep,
2482 __deref_out efx_txq_t **etpp,
2483 __out unsigned int *addedp);
2485 extern __checkReturn efx_rc_t
2487 __in efx_txq_t *etp,
2488 __in_ecount(ndescs) efx_buffer_t *eb,
2489 __in unsigned int ndescs,
2490 __in unsigned int completed,
2491 __inout unsigned int *addedp);
2493 extern __checkReturn efx_rc_t
2495 __in efx_txq_t *etp,
2496 __in unsigned int ns);
2500 __in efx_txq_t *etp,
2501 __in unsigned int added,
2502 __in unsigned int pushed);
2504 extern __checkReturn efx_rc_t
2506 __in efx_txq_t *etp);
2510 __in efx_txq_t *etp);
2512 extern __checkReturn efx_rc_t
2514 __in efx_txq_t *etp);
2517 efx_tx_qpio_disable(
2518 __in efx_txq_t *etp);
2520 extern __checkReturn efx_rc_t
2522 __in efx_txq_t *etp,
2523 __in_ecount(buf_length) uint8_t *buffer,
2524 __in size_t buf_length,
2525 __in size_t pio_buf_offset);
2527 extern __checkReturn efx_rc_t
2529 __in efx_txq_t *etp,
2530 __in size_t pkt_length,
2531 __in unsigned int completed,
2532 __inout unsigned int *addedp);
2534 extern __checkReturn efx_rc_t
2536 __in efx_txq_t *etp,
2537 __in_ecount(n) efx_desc_t *ed,
2538 __in unsigned int n,
2539 __in unsigned int completed,
2540 __inout unsigned int *addedp);
2543 efx_tx_qdesc_dma_create(
2544 __in efx_txq_t *etp,
2545 __in efsys_dma_addr_t addr,
2548 __out efx_desc_t *edp);
2551 efx_tx_qdesc_tso_create(
2552 __in efx_txq_t *etp,
2553 __in uint16_t ipv4_id,
2554 __in uint32_t tcp_seq,
2555 __in uint8_t tcp_flags,
2556 __out efx_desc_t *edp);
2558 /* Number of FATSOv2 option descriptors */
2559 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2561 /* Maximum number of DMA segments per TSO packet (not superframe) */
2562 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2565 efx_tx_qdesc_tso2_create(
2566 __in efx_txq_t *etp,
2567 __in uint16_t ipv4_id,
2568 __in uint16_t outer_ipv4_id,
2569 __in uint32_t tcp_seq,
2570 __in uint16_t tcp_mss,
2571 __out_ecount(count) efx_desc_t *edp,
2575 efx_tx_qdesc_vlantci_create(
2576 __in efx_txq_t *etp,
2578 __out efx_desc_t *edp);
2581 efx_tx_qdesc_checksum_create(
2582 __in efx_txq_t *etp,
2583 __in uint16_t flags,
2584 __out efx_desc_t *edp);
2586 #if EFSYS_OPT_QSTATS
2592 __in efx_nic_t *etp,
2593 __in unsigned int id);
2595 #endif /* EFSYS_OPT_NAMES */
2598 efx_tx_qstats_update(
2599 __in efx_txq_t *etp,
2600 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2602 #endif /* EFSYS_OPT_QSTATS */
2606 __in efx_txq_t *etp);
2611 #if EFSYS_OPT_FILTER
2613 #define EFX_ETHER_TYPE_IPV4 0x0800
2614 #define EFX_ETHER_TYPE_IPV6 0x86DD
2616 #define EFX_IPPROTO_TCP 6
2617 #define EFX_IPPROTO_UDP 17
2618 #define EFX_IPPROTO_GRE 47
2620 /* Use RSS to spread across multiple queues */
2621 #define EFX_FILTER_FLAG_RX_RSS 0x01
2622 /* Enable RX scatter */
2623 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2625 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2626 * May only be set by the filter implementation for each type.
2627 * A removal request will restore the automatic filter in its place.
2629 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2630 /* Filter is for RX */
2631 #define EFX_FILTER_FLAG_RX 0x08
2632 /* Filter is for TX */
2633 #define EFX_FILTER_FLAG_TX 0x10
2634 /* Set match flag on the received packet */
2635 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2636 /* Set match mark on the received packet */
2637 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2639 typedef uint8_t efx_filter_flags_t;
2642 * Flags which specify the fields to match on. The values are the same as in the
2643 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2646 /* Match by remote IP host address */
2647 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2648 /* Match by local IP host address */
2649 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2650 /* Match by remote MAC address */
2651 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2652 /* Match by remote TCP/UDP port */
2653 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2654 /* Match by remote TCP/UDP port */
2655 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2656 /* Match by local TCP/UDP port */
2657 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2658 /* Match by Ether-type */
2659 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2660 /* Match by inner VLAN ID */
2661 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2662 /* Match by outer VLAN ID */
2663 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2664 /* Match by IP transport protocol */
2665 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2666 /* Match by VNI or VSID */
2667 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2668 /* For encapsulated packets, match by inner frame local MAC address */
2669 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2670 /* For encapsulated packets, match all multicast inner frames */
2671 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2672 /* For encapsulated packets, match all unicast inner frames */
2673 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2675 * Match by encap type, this flag does not correspond to
2676 * the MCDI match flags and any unoccupied value may be used
2678 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2679 /* Match otherwise-unmatched multicast and broadcast packets */
2680 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2681 /* Match otherwise-unmatched unicast packets */
2682 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2684 typedef uint32_t efx_filter_match_flags_t;
2686 typedef enum efx_filter_priority_s {
2687 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2688 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2689 * address list or hardware
2690 * requirements. This may only be used
2691 * by the filter implementation for
2693 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2694 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2695 * client (e.g. SR-IOV, HyperV VMQ etc.)
2697 } efx_filter_priority_t;
2700 * FIXME: All these fields are assumed to be in little-endian byte order.
2701 * It may be better for some to be big-endian. See bug42804.
2704 typedef struct efx_filter_spec_s {
2705 efx_filter_match_flags_t efs_match_flags;
2706 uint8_t efs_priority;
2707 efx_filter_flags_t efs_flags;
2708 uint16_t efs_dmaq_id;
2709 uint32_t efs_rss_context;
2710 uint16_t efs_outer_vid;
2711 uint16_t efs_inner_vid;
2712 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2713 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2714 uint16_t efs_ether_type;
2715 uint8_t efs_ip_proto;
2716 efx_tunnel_protocol_t efs_encap_type;
2717 uint16_t efs_loc_port;
2718 uint16_t efs_rem_port;
2719 efx_oword_t efs_rem_host;
2720 efx_oword_t efs_loc_host;
2721 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2722 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2724 } efx_filter_spec_t;
2727 /* Default values for use in filter specifications */
2728 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2729 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2731 extern __checkReturn efx_rc_t
2733 __in efx_nic_t *enp);
2737 __in efx_nic_t *enp);
2739 extern __checkReturn efx_rc_t
2741 __in efx_nic_t *enp,
2742 __inout efx_filter_spec_t *spec);
2744 extern __checkReturn efx_rc_t
2746 __in efx_nic_t *enp,
2747 __inout efx_filter_spec_t *spec);
2749 extern __checkReturn efx_rc_t
2751 __in efx_nic_t *enp);
2753 extern __checkReturn efx_rc_t
2754 efx_filter_supported_filters(
2755 __in efx_nic_t *enp,
2756 __out_ecount(buffer_length) uint32_t *buffer,
2757 __in size_t buffer_length,
2758 __out size_t *list_lengthp);
2761 efx_filter_spec_init_rx(
2762 __out efx_filter_spec_t *spec,
2763 __in efx_filter_priority_t priority,
2764 __in efx_filter_flags_t flags,
2765 __in efx_rxq_t *erp);
2768 efx_filter_spec_init_tx(
2769 __out efx_filter_spec_t *spec,
2770 __in efx_txq_t *etp);
2772 extern __checkReturn efx_rc_t
2773 efx_filter_spec_set_ipv4_local(
2774 __inout efx_filter_spec_t *spec,
2777 __in uint16_t port);
2779 extern __checkReturn efx_rc_t
2780 efx_filter_spec_set_ipv4_full(
2781 __inout efx_filter_spec_t *spec,
2783 __in uint32_t lhost,
2784 __in uint16_t lport,
2785 __in uint32_t rhost,
2786 __in uint16_t rport);
2788 extern __checkReturn efx_rc_t
2789 efx_filter_spec_set_eth_local(
2790 __inout efx_filter_spec_t *spec,
2792 __in const uint8_t *addr);
2795 efx_filter_spec_set_ether_type(
2796 __inout efx_filter_spec_t *spec,
2797 __in uint16_t ether_type);
2799 extern __checkReturn efx_rc_t
2800 efx_filter_spec_set_uc_def(
2801 __inout efx_filter_spec_t *spec);
2803 extern __checkReturn efx_rc_t
2804 efx_filter_spec_set_mc_def(
2805 __inout efx_filter_spec_t *spec);
2807 typedef enum efx_filter_inner_frame_match_e {
2808 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2809 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2810 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2811 } efx_filter_inner_frame_match_t;
2813 extern __checkReturn efx_rc_t
2814 efx_filter_spec_set_encap_type(
2815 __inout efx_filter_spec_t *spec,
2816 __in efx_tunnel_protocol_t encap_type,
2817 __in efx_filter_inner_frame_match_t inner_frame_match);
2819 extern __checkReturn efx_rc_t
2820 efx_filter_spec_set_vxlan_full(
2821 __inout efx_filter_spec_t *spec,
2822 __in const uint8_t *vxlan_id,
2823 __in const uint8_t *inner_addr,
2824 __in const uint8_t *outer_addr);
2826 #if EFSYS_OPT_RX_SCALE
2827 extern __checkReturn efx_rc_t
2828 efx_filter_spec_set_rss_context(
2829 __inout efx_filter_spec_t *spec,
2830 __in uint32_t rss_context);
2832 #endif /* EFSYS_OPT_FILTER */
2836 extern __checkReturn uint32_t
2838 __in_ecount(count) uint32_t const *input,
2840 __in uint32_t init);
2842 extern __checkReturn uint32_t
2844 __in_ecount(length) uint8_t const *input,
2846 __in uint32_t init);
2848 #if EFSYS_OPT_LICENSING
2852 typedef struct efx_key_stats_s {
2854 uint32_t eks_invalid;
2855 uint32_t eks_blacklisted;
2856 uint32_t eks_unverifiable;
2857 uint32_t eks_wrong_node;
2858 uint32_t eks_licensed_apps_lo;
2859 uint32_t eks_licensed_apps_hi;
2860 uint32_t eks_licensed_features_lo;
2861 uint32_t eks_licensed_features_hi;
2864 extern __checkReturn efx_rc_t
2866 __in efx_nic_t *enp);
2870 __in efx_nic_t *enp);
2872 extern __checkReturn boolean_t
2873 efx_lic_check_support(
2874 __in efx_nic_t *enp);
2876 extern __checkReturn efx_rc_t
2877 efx_lic_update_licenses(
2878 __in efx_nic_t *enp);
2880 extern __checkReturn efx_rc_t
2881 efx_lic_get_key_stats(
2882 __in efx_nic_t *enp,
2883 __out efx_key_stats_t *ksp);
2885 extern __checkReturn efx_rc_t
2887 __in efx_nic_t *enp,
2888 __in uint64_t app_id,
2889 __out boolean_t *licensedp);
2891 extern __checkReturn efx_rc_t
2893 __in efx_nic_t *enp,
2894 __in size_t buffer_size,
2895 __out uint32_t *typep,
2896 __out size_t *lengthp,
2897 __out_opt uint8_t *bufferp);
2900 extern __checkReturn efx_rc_t
2902 __in efx_nic_t *enp,
2903 __in_bcount(buffer_size)
2905 __in size_t buffer_size,
2906 __out uint32_t *startp);
2908 extern __checkReturn efx_rc_t
2910 __in efx_nic_t *enp,
2911 __in_bcount(buffer_size)
2913 __in size_t buffer_size,
2914 __in uint32_t offset,
2915 __out uint32_t *endp);
2917 extern __checkReturn __success(return != B_FALSE) boolean_t
2919 __in efx_nic_t *enp,
2920 __in_bcount(buffer_size)
2922 __in size_t buffer_size,
2923 __in uint32_t offset,
2924 __out uint32_t *startp,
2925 __out uint32_t *lengthp);
2927 extern __checkReturn __success(return != B_FALSE) boolean_t
2928 efx_lic_validate_key(
2929 __in efx_nic_t *enp,
2930 __in_bcount(length) caddr_t keyp,
2931 __in uint32_t length);
2933 extern __checkReturn efx_rc_t
2935 __in efx_nic_t *enp,
2936 __in_bcount(buffer_size)
2938 __in size_t buffer_size,
2939 __in uint32_t offset,
2940 __in uint32_t length,
2941 __out_bcount_part(key_max_size, *lengthp)
2943 __in size_t key_max_size,
2944 __out uint32_t *lengthp);
2946 extern __checkReturn efx_rc_t
2948 __in efx_nic_t *enp,
2949 __in_bcount(buffer_size)
2951 __in size_t buffer_size,
2952 __in uint32_t offset,
2953 __in_bcount(length) caddr_t keyp,
2954 __in uint32_t length,
2955 __out uint32_t *lengthp);
2957 __checkReturn efx_rc_t
2959 __in efx_nic_t *enp,
2960 __in_bcount(buffer_size)
2962 __in size_t buffer_size,
2963 __in uint32_t offset,
2964 __in uint32_t length,
2966 __out uint32_t *deltap);
2968 extern __checkReturn efx_rc_t
2969 efx_lic_create_partition(
2970 __in efx_nic_t *enp,
2971 __in_bcount(buffer_size)
2973 __in size_t buffer_size);
2975 extern __checkReturn efx_rc_t
2976 efx_lic_finish_partition(
2977 __in efx_nic_t *enp,
2978 __in_bcount(buffer_size)
2980 __in size_t buffer_size);
2982 #endif /* EFSYS_OPT_LICENSING */
2986 #if EFSYS_OPT_TUNNEL
2988 extern __checkReturn efx_rc_t
2990 __in efx_nic_t *enp);
2994 __in efx_nic_t *enp);
2997 * For overlay network encapsulation using UDP, the firmware needs to know
2998 * the configured UDP port for the overlay so it can decode encapsulated
3000 * The UDP port/protocol list is global.
3003 extern __checkReturn efx_rc_t
3004 efx_tunnel_config_udp_add(
3005 __in efx_nic_t *enp,
3006 __in uint16_t port /* host/cpu-endian */,
3007 __in efx_tunnel_protocol_t protocol);
3009 extern __checkReturn efx_rc_t
3010 efx_tunnel_config_udp_remove(
3011 __in efx_nic_t *enp,
3012 __in uint16_t port /* host/cpu-endian */,
3013 __in efx_tunnel_protocol_t protocol);
3016 efx_tunnel_config_clear(
3017 __in efx_nic_t *enp);
3020 * Apply tunnel UDP ports configuration to hardware.
3022 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3025 extern __checkReturn efx_rc_t
3026 efx_tunnel_reconfigure(
3027 __in efx_nic_t *enp);
3029 #endif /* EFSYS_OPT_TUNNEL */
3031 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3034 * Firmware subvariant choice options.
3036 * It may be switched to no Tx checksum if attached drivers are either
3037 * preboot or firmware subvariant aware and no VIS are allocated.
3038 * If may be always switched to default explicitly using set request or
3039 * implicitly if unaware driver is attaching. If switching is done when
3040 * a driver is attached, it gets MC_REBOOT event and should recreate its
3043 * See SF-119419-TC DPDK Firmware Driver Interface and
3044 * SF-109306-TC EF10 for Driver Writers for details.
3046 typedef enum efx_nic_fw_subvariant_e {
3047 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3048 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3049 EFX_NIC_FW_SUBVARIANT_NTYPES
3050 } efx_nic_fw_subvariant_t;
3052 extern __checkReturn efx_rc_t
3053 efx_nic_get_fw_subvariant(
3054 __in efx_nic_t *enp,
3055 __out efx_nic_fw_subvariant_t *subvariantp);
3057 extern __checkReturn efx_rc_t
3058 efx_nic_set_fw_subvariant(
3059 __in efx_nic_t *enp,
3060 __in efx_nic_fw_subvariant_t subvariant);
3062 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3068 #endif /* _SYS_EFX_H */