1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
46 extern __checkReturn efx_rc_t
50 __out efx_family_t *efp);
53 #define EFX_PCI_VENID_SFC 0x1924
55 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
57 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
58 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
59 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
61 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
62 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
63 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
65 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
66 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
68 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
69 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
70 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
92 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
93 extern __checkReturn uint32_t
95 __in uint32_t crc_init,
96 __in_ecount(length) uint8_t const *input,
100 /* Type prototypes */
102 typedef struct efx_rxq_s efx_rxq_t;
106 typedef struct efx_nic_s efx_nic_t;
108 extern __checkReturn efx_rc_t
110 __in efx_family_t family,
111 __in efsys_identifier_t *esip,
112 __in efsys_bar_t *esbp,
113 __in efsys_lock_t *eslp,
114 __deref_out efx_nic_t **enpp);
116 extern __checkReturn efx_rc_t
118 __in efx_nic_t *enp);
120 extern __checkReturn efx_rc_t
122 __in efx_nic_t *enp);
124 extern __checkReturn efx_rc_t
126 __in efx_nic_t *enp);
130 extern __checkReturn efx_rc_t
131 efx_nic_register_test(
132 __in efx_nic_t *enp);
134 #endif /* EFSYS_OPT_DIAG */
138 __in efx_nic_t *enp);
142 __in efx_nic_t *enp);
146 __in efx_nic_t *enp);
148 #define EFX_PCIE_LINK_SPEED_GEN1 1
149 #define EFX_PCIE_LINK_SPEED_GEN2 2
150 #define EFX_PCIE_LINK_SPEED_GEN3 3
152 typedef enum efx_pcie_link_performance_e {
153 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
154 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
155 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
156 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
157 } efx_pcie_link_performance_t;
159 extern __checkReturn efx_rc_t
160 efx_nic_calculate_pcie_link_bandwidth(
161 __in uint32_t pcie_link_width,
162 __in uint32_t pcie_link_gen,
163 __out uint32_t *bandwidth_mbpsp);
165 extern __checkReturn efx_rc_t
166 efx_nic_check_pcie_link_speed(
168 __in uint32_t pcie_link_width,
169 __in uint32_t pcie_link_gen,
170 __out efx_pcie_link_performance_t *resultp);
174 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
175 /* Huntington and Medford require MCDIv2 commands */
176 #define WITH_MCDI_V2 1
179 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
181 typedef enum efx_mcdi_exception_e {
182 EFX_MCDI_EXCEPTION_MC_REBOOT,
183 EFX_MCDI_EXCEPTION_MC_BADASSERT,
184 } efx_mcdi_exception_t;
186 #if EFSYS_OPT_MCDI_LOGGING
187 typedef enum efx_log_msg_e {
189 EFX_LOG_MCDI_REQUEST,
190 EFX_LOG_MCDI_RESPONSE,
192 #endif /* EFSYS_OPT_MCDI_LOGGING */
194 typedef struct efx_mcdi_transport_s {
196 efsys_mem_t *emt_dma_mem;
197 void (*emt_execute)(void *, efx_mcdi_req_t *);
198 void (*emt_ev_cpl)(void *);
199 void (*emt_exception)(void *, efx_mcdi_exception_t);
200 #if EFSYS_OPT_MCDI_LOGGING
201 void (*emt_logger)(void *, efx_log_msg_t,
202 void *, size_t, void *, size_t);
203 #endif /* EFSYS_OPT_MCDI_LOGGING */
204 #if EFSYS_OPT_MCDI_PROXY_AUTH
205 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
206 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
207 } efx_mcdi_transport_t;
209 extern __checkReturn efx_rc_t
212 __in const efx_mcdi_transport_t *mtp);
214 extern __checkReturn efx_rc_t
216 __in efx_nic_t *enp);
220 __in efx_nic_t *enp);
223 efx_mcdi_get_timeout(
225 __in efx_mcdi_req_t *emrp,
226 __out uint32_t *usec_timeoutp);
229 efx_mcdi_request_start(
231 __in efx_mcdi_req_t *emrp,
232 __in boolean_t ev_cpl);
234 extern __checkReturn boolean_t
235 efx_mcdi_request_poll(
236 __in efx_nic_t *enp);
238 extern __checkReturn boolean_t
239 efx_mcdi_request_abort(
240 __in efx_nic_t *enp);
244 __in efx_nic_t *enp);
246 #endif /* EFSYS_OPT_MCDI */
250 #define EFX_NINTR_SIENA 1024
252 typedef enum efx_intr_type_e {
253 EFX_INTR_INVALID = 0,
259 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
261 extern __checkReturn efx_rc_t
264 __in efx_intr_type_t type,
265 __in efsys_mem_t *esmp);
269 __in efx_nic_t *enp);
273 __in efx_nic_t *enp);
276 efx_intr_disable_unlocked(
277 __in efx_nic_t *enp);
279 #define EFX_INTR_NEVQS 32
281 extern __checkReturn efx_rc_t
284 __in unsigned int level);
287 efx_intr_status_line(
289 __out boolean_t *fatalp,
290 __out uint32_t *maskp);
293 efx_intr_status_message(
295 __in unsigned int message,
296 __out boolean_t *fatalp);
300 __in efx_nic_t *enp);
304 __in efx_nic_t *enp);
308 #if EFSYS_OPT_MAC_STATS
310 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
311 typedef enum efx_mac_stat_e {
314 EFX_MAC_RX_UNICST_PKTS,
315 EFX_MAC_RX_MULTICST_PKTS,
316 EFX_MAC_RX_BRDCST_PKTS,
317 EFX_MAC_RX_PAUSE_PKTS,
318 EFX_MAC_RX_LE_64_PKTS,
319 EFX_MAC_RX_65_TO_127_PKTS,
320 EFX_MAC_RX_128_TO_255_PKTS,
321 EFX_MAC_RX_256_TO_511_PKTS,
322 EFX_MAC_RX_512_TO_1023_PKTS,
323 EFX_MAC_RX_1024_TO_15XX_PKTS,
324 EFX_MAC_RX_GE_15XX_PKTS,
326 EFX_MAC_RX_FCS_ERRORS,
327 EFX_MAC_RX_DROP_EVENTS,
328 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
329 EFX_MAC_RX_SYMBOL_ERRORS,
330 EFX_MAC_RX_ALIGN_ERRORS,
331 EFX_MAC_RX_INTERNAL_ERRORS,
332 EFX_MAC_RX_JABBER_PKTS,
333 EFX_MAC_RX_LANE0_CHAR_ERR,
334 EFX_MAC_RX_LANE1_CHAR_ERR,
335 EFX_MAC_RX_LANE2_CHAR_ERR,
336 EFX_MAC_RX_LANE3_CHAR_ERR,
337 EFX_MAC_RX_LANE0_DISP_ERR,
338 EFX_MAC_RX_LANE1_DISP_ERR,
339 EFX_MAC_RX_LANE2_DISP_ERR,
340 EFX_MAC_RX_LANE3_DISP_ERR,
341 EFX_MAC_RX_MATCH_FAULT,
342 EFX_MAC_RX_NODESC_DROP_CNT,
345 EFX_MAC_TX_UNICST_PKTS,
346 EFX_MAC_TX_MULTICST_PKTS,
347 EFX_MAC_TX_BRDCST_PKTS,
348 EFX_MAC_TX_PAUSE_PKTS,
349 EFX_MAC_TX_LE_64_PKTS,
350 EFX_MAC_TX_65_TO_127_PKTS,
351 EFX_MAC_TX_128_TO_255_PKTS,
352 EFX_MAC_TX_256_TO_511_PKTS,
353 EFX_MAC_TX_512_TO_1023_PKTS,
354 EFX_MAC_TX_1024_TO_15XX_PKTS,
355 EFX_MAC_TX_GE_15XX_PKTS,
357 EFX_MAC_TX_SGL_COL_PKTS,
358 EFX_MAC_TX_MULT_COL_PKTS,
359 EFX_MAC_TX_EX_COL_PKTS,
360 EFX_MAC_TX_LATE_COL_PKTS,
362 EFX_MAC_TX_EX_DEF_PKTS,
363 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
364 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
365 EFX_MAC_PM_TRUNC_VFIFO_FULL,
366 EFX_MAC_PM_DISCARD_VFIFO_FULL,
367 EFX_MAC_PM_TRUNC_QBB,
368 EFX_MAC_PM_DISCARD_QBB,
369 EFX_MAC_PM_DISCARD_MAPPING,
370 EFX_MAC_RXDP_Q_DISABLED_PKTS,
371 EFX_MAC_RXDP_DI_DROPPED_PKTS,
372 EFX_MAC_RXDP_STREAMING_PKTS,
373 EFX_MAC_RXDP_HLB_FETCH,
374 EFX_MAC_RXDP_HLB_WAIT,
375 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
376 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
377 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
378 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
379 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
380 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
381 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
382 EFX_MAC_VADAPTER_RX_BAD_BYTES,
383 EFX_MAC_VADAPTER_RX_OVERFLOW,
384 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
385 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
386 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
387 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
388 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
389 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
390 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
391 EFX_MAC_VADAPTER_TX_BAD_BYTES,
392 EFX_MAC_VADAPTER_TX_OVERFLOW,
396 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
398 #endif /* EFSYS_OPT_MAC_STATS */
400 typedef enum efx_link_mode_e {
401 EFX_LINK_UNKNOWN = 0,
414 #define EFX_MAC_ADDR_LEN 6
416 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
418 #define EFX_MAC_MULTICAST_LIST_MAX 256
420 #define EFX_MAC_SDU_MAX 9202
422 #define EFX_MAC_PDU_ADJUSTMENT \
426 + /* bug16011 */ 16) \
428 #define EFX_MAC_PDU(_sdu) \
429 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
432 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
433 * the SDU rounded up slightly.
435 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
437 #define EFX_MAC_PDU_MIN 60
438 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
440 extern __checkReturn efx_rc_t
445 extern __checkReturn efx_rc_t
450 extern __checkReturn efx_rc_t
455 extern __checkReturn efx_rc_t
458 __in boolean_t all_unicst,
459 __in boolean_t mulcst,
460 __in boolean_t all_mulcst,
461 __in boolean_t brdcst);
463 extern __checkReturn efx_rc_t
464 efx_mac_multicast_list_set(
466 __in_ecount(6*count) uint8_t const *addrs,
469 extern __checkReturn efx_rc_t
470 efx_mac_filter_default_rxq_set(
473 __in boolean_t using_rss);
476 efx_mac_filter_default_rxq_clear(
477 __in efx_nic_t *enp);
479 extern __checkReturn efx_rc_t
482 __in boolean_t enabled);
484 extern __checkReturn efx_rc_t
487 __out boolean_t *mac_upp);
489 #define EFX_FCNTL_RESPOND 0x00000001
490 #define EFX_FCNTL_GENERATE 0x00000002
492 extern __checkReturn efx_rc_t
495 __in unsigned int fcntl,
496 __in boolean_t autoneg);
501 __out unsigned int *fcntl_wantedp,
502 __out unsigned int *fcntl_linkp);
505 #if EFSYS_OPT_MAC_STATS
509 extern __checkReturn const char *
512 __in unsigned int id);
514 #endif /* EFSYS_OPT_NAMES */
516 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
518 #define EFX_MAC_STATS_MASK_NPAGES \
519 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
520 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
523 * Get mask of MAC statistics supported by the hardware.
525 * If mask_size is insufficient to return the mask, EINVAL error is
526 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
527 * (which is sizeof (uint32_t)) is sufficient.
529 extern __checkReturn efx_rc_t
530 efx_mac_stats_get_mask(
532 __out_bcount(mask_size) uint32_t *maskp,
533 __in size_t mask_size);
535 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
536 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
537 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
539 #define EFX_MAC_STATS_SIZE 0x400
541 extern __checkReturn efx_rc_t
543 __in efx_nic_t *enp);
546 * Upload mac statistics supported by the hardware into the given buffer.
548 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
551 * The hardware will only DMA statistics that it understands (of course).
552 * Drivers should not make any assumptions about which statistics are
553 * supported, especially when the statistics are generated by firmware.
555 * Thus, drivers should zero this buffer before use, so that not-understood
556 * statistics read back as zero.
558 extern __checkReturn efx_rc_t
559 efx_mac_stats_upload(
561 __in efsys_mem_t *esmp);
563 extern __checkReturn efx_rc_t
564 efx_mac_stats_periodic(
566 __in efsys_mem_t *esmp,
567 __in uint16_t period_ms,
568 __in boolean_t events);
570 extern __checkReturn efx_rc_t
571 efx_mac_stats_update(
573 __in efsys_mem_t *esmp,
574 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
575 __inout_opt uint32_t *generationp);
577 #endif /* EFSYS_OPT_MAC_STATS */
581 typedef enum efx_mon_type_e {
593 __in efx_nic_t *enp);
595 #endif /* EFSYS_OPT_NAMES */
597 extern __checkReturn efx_rc_t
599 __in efx_nic_t *enp);
601 #if EFSYS_OPT_MON_STATS
603 #define EFX_MON_STATS_PAGE_SIZE 0x100
604 #define EFX_MON_MASK_ELEMENT_SIZE 32
606 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock fcc1b6748432e1ac */
607 typedef enum efx_mon_stat_e {
614 EFX_MON_STAT_EXT_TEMP,
615 EFX_MON_STAT_INT_TEMP,
618 EFX_MON_STAT_INT_COOLING,
619 EFX_MON_STAT_EXT_COOLING,
627 EFX_MON_STAT_AOE_TEMP,
628 EFX_MON_STAT_PSU_AOE_TEMP,
629 EFX_MON_STAT_PSU_TEMP,
635 EFX_MON_STAT_VAOE_IN,
637 EFX_MON_STAT_IAOE_IN,
638 EFX_MON_STAT_NIC_POWER,
642 EFX_MON_STAT_0_9V_ADC,
643 EFX_MON_STAT_INT_TEMP2,
644 EFX_MON_STAT_VREG_TEMP,
645 EFX_MON_STAT_VREG_0_9V_TEMP,
646 EFX_MON_STAT_VREG_1_2V_TEMP,
647 EFX_MON_STAT_INT_VPTAT,
648 EFX_MON_STAT_INT_ADC_TEMP,
649 EFX_MON_STAT_EXT_VPTAT,
650 EFX_MON_STAT_EXT_ADC_TEMP,
651 EFX_MON_STAT_AMBIENT_TEMP,
652 EFX_MON_STAT_AIRFLOW,
653 EFX_MON_STAT_VDD08D_VSS08D_CSR,
654 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
655 EFX_MON_STAT_HOTPOINT_TEMP,
656 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
657 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
658 EFX_MON_STAT_MUM_VCC,
661 EFX_MON_STAT_0V9_A_TEMP,
664 EFX_MON_STAT_0V9_B_TEMP,
665 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
666 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
667 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
668 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
669 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
670 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
671 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
672 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
673 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
674 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
675 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
676 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
677 EFX_MON_STAT_SODIMM_VOUT,
678 EFX_MON_STAT_SODIMM_0_TEMP,
679 EFX_MON_STAT_SODIMM_1_TEMP,
680 EFX_MON_STAT_PHY0_VCC,
681 EFX_MON_STAT_PHY1_VCC,
682 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
683 EFX_MON_STAT_BOARD_FRONT_TEMP,
684 EFX_MON_STAT_BOARD_BACK_TEMP,
692 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
694 typedef enum efx_mon_stat_state_e {
695 EFX_MON_STAT_STATE_OK = 0,
696 EFX_MON_STAT_STATE_WARNING = 1,
697 EFX_MON_STAT_STATE_FATAL = 2,
698 EFX_MON_STAT_STATE_BROKEN = 3,
699 EFX_MON_STAT_STATE_NO_READING = 4,
700 } efx_mon_stat_state_t;
702 typedef struct efx_mon_stat_value_s {
705 } efx_mon_stat_value_t;
712 __in efx_mon_stat_t id);
714 #endif /* EFSYS_OPT_NAMES */
716 extern __checkReturn efx_rc_t
717 efx_mon_stats_update(
719 __in efsys_mem_t *esmp,
720 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
722 #endif /* EFSYS_OPT_MON_STATS */
726 __in efx_nic_t *enp);
730 extern __checkReturn efx_rc_t
732 __in efx_nic_t *enp);
734 #if EFSYS_OPT_PHY_LED_CONTROL
736 typedef enum efx_phy_led_mode_e {
737 EFX_PHY_LED_DEFAULT = 0,
742 } efx_phy_led_mode_t;
744 extern __checkReturn efx_rc_t
747 __in efx_phy_led_mode_t mode);
749 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
751 extern __checkReturn efx_rc_t
753 __in efx_nic_t *enp);
755 #if EFSYS_OPT_LOOPBACK
757 typedef enum efx_loopback_type_e {
758 EFX_LOOPBACK_OFF = 0,
759 EFX_LOOPBACK_DATA = 1,
760 EFX_LOOPBACK_GMAC = 2,
761 EFX_LOOPBACK_XGMII = 3,
762 EFX_LOOPBACK_XGXS = 4,
763 EFX_LOOPBACK_XAUI = 5,
764 EFX_LOOPBACK_GMII = 6,
765 EFX_LOOPBACK_SGMII = 7,
766 EFX_LOOPBACK_XGBR = 8,
767 EFX_LOOPBACK_XFI = 9,
768 EFX_LOOPBACK_XAUI_FAR = 10,
769 EFX_LOOPBACK_GMII_FAR = 11,
770 EFX_LOOPBACK_SGMII_FAR = 12,
771 EFX_LOOPBACK_XFI_FAR = 13,
772 EFX_LOOPBACK_GPHY = 14,
773 EFX_LOOPBACK_PHY_XS = 15,
774 EFX_LOOPBACK_PCS = 16,
775 EFX_LOOPBACK_PMA_PMD = 17,
776 EFX_LOOPBACK_XPORT = 18,
777 EFX_LOOPBACK_XGMII_WS = 19,
778 EFX_LOOPBACK_XAUI_WS = 20,
779 EFX_LOOPBACK_XAUI_WS_FAR = 21,
780 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
781 EFX_LOOPBACK_GMII_WS = 23,
782 EFX_LOOPBACK_XFI_WS = 24,
783 EFX_LOOPBACK_XFI_WS_FAR = 25,
784 EFX_LOOPBACK_PHYXS_WS = 26,
785 EFX_LOOPBACK_PMA_INT = 27,
786 EFX_LOOPBACK_SD_NEAR = 28,
787 EFX_LOOPBACK_SD_FAR = 29,
788 EFX_LOOPBACK_PMA_INT_WS = 30,
789 EFX_LOOPBACK_SD_FEP2_WS = 31,
790 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
791 EFX_LOOPBACK_SD_FEP_WS = 33,
792 EFX_LOOPBACK_SD_FES_WS = 34,
794 } efx_loopback_type_t;
796 typedef enum efx_loopback_kind_e {
797 EFX_LOOPBACK_KIND_OFF = 0,
798 EFX_LOOPBACK_KIND_ALL,
799 EFX_LOOPBACK_KIND_MAC,
800 EFX_LOOPBACK_KIND_PHY,
802 } efx_loopback_kind_t;
806 __in efx_loopback_kind_t loopback_kind,
807 __out efx_qword_t *maskp);
809 extern __checkReturn efx_rc_t
810 efx_port_loopback_set(
812 __in efx_link_mode_t link_mode,
813 __in efx_loopback_type_t type);
817 extern __checkReturn const char *
818 efx_loopback_type_name(
820 __in efx_loopback_type_t type);
822 #endif /* EFSYS_OPT_NAMES */
824 #endif /* EFSYS_OPT_LOOPBACK */
826 extern __checkReturn efx_rc_t
829 __out_opt efx_link_mode_t *link_modep);
833 __in efx_nic_t *enp);
835 typedef enum efx_phy_cap_type_e {
836 EFX_PHY_CAP_INVALID = 0,
843 EFX_PHY_CAP_10000FDX,
847 EFX_PHY_CAP_40000FDX,
849 } efx_phy_cap_type_t;
852 #define EFX_PHY_CAP_CURRENT 0x00000000
853 #define EFX_PHY_CAP_DEFAULT 0x00000001
854 #define EFX_PHY_CAP_PERM 0x00000002
860 __out uint32_t *maskp);
862 extern __checkReturn efx_rc_t
870 __out uint32_t *maskp);
872 extern __checkReturn efx_rc_t
875 __out uint32_t *ouip);
877 typedef enum efx_phy_media_type_e {
878 EFX_PHY_MEDIA_INVALID = 0,
883 EFX_PHY_MEDIA_SFP_PLUS,
884 EFX_PHY_MEDIA_BASE_T,
885 EFX_PHY_MEDIA_QSFP_PLUS,
887 } efx_phy_media_type_t;
890 * Get the type of medium currently used. If the board has ports for
891 * modules, a module is present, and we recognise the media type of
892 * the module, then this will be the media type of the module.
893 * Otherwise it will be the media type of the port.
896 efx_phy_media_type_get(
898 __out efx_phy_media_type_t *typep);
900 extern __checkReturn efx_rc_t
901 efx_phy_module_get_info(
903 __in uint8_t dev_addr,
906 __out_bcount(len) uint8_t *data);
908 #if EFSYS_OPT_PHY_STATS
910 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
911 typedef enum efx_phy_stat_e {
913 EFX_PHY_STAT_PMA_PMD_LINK_UP,
914 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
915 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
916 EFX_PHY_STAT_PMA_PMD_REV_A,
917 EFX_PHY_STAT_PMA_PMD_REV_B,
918 EFX_PHY_STAT_PMA_PMD_REV_C,
919 EFX_PHY_STAT_PMA_PMD_REV_D,
920 EFX_PHY_STAT_PCS_LINK_UP,
921 EFX_PHY_STAT_PCS_RX_FAULT,
922 EFX_PHY_STAT_PCS_TX_FAULT,
923 EFX_PHY_STAT_PCS_BER,
924 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
925 EFX_PHY_STAT_PHY_XS_LINK_UP,
926 EFX_PHY_STAT_PHY_XS_RX_FAULT,
927 EFX_PHY_STAT_PHY_XS_TX_FAULT,
928 EFX_PHY_STAT_PHY_XS_ALIGN,
929 EFX_PHY_STAT_PHY_XS_SYNC_A,
930 EFX_PHY_STAT_PHY_XS_SYNC_B,
931 EFX_PHY_STAT_PHY_XS_SYNC_C,
932 EFX_PHY_STAT_PHY_XS_SYNC_D,
933 EFX_PHY_STAT_AN_LINK_UP,
934 EFX_PHY_STAT_AN_MASTER,
935 EFX_PHY_STAT_AN_LOCAL_RX_OK,
936 EFX_PHY_STAT_AN_REMOTE_RX_OK,
937 EFX_PHY_STAT_CL22EXT_LINK_UP,
942 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
943 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
944 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
945 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
946 EFX_PHY_STAT_AN_COMPLETE,
947 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
948 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
949 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
950 EFX_PHY_STAT_PCS_FW_VERSION_0,
951 EFX_PHY_STAT_PCS_FW_VERSION_1,
952 EFX_PHY_STAT_PCS_FW_VERSION_2,
953 EFX_PHY_STAT_PCS_FW_VERSION_3,
954 EFX_PHY_STAT_PCS_FW_BUILD_YY,
955 EFX_PHY_STAT_PCS_FW_BUILD_MM,
956 EFX_PHY_STAT_PCS_FW_BUILD_DD,
957 EFX_PHY_STAT_PCS_OP_MODE,
961 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
968 __in efx_phy_stat_t stat);
970 #endif /* EFSYS_OPT_NAMES */
972 #define EFX_PHY_STATS_SIZE 0x100
974 extern __checkReturn efx_rc_t
975 efx_phy_stats_update(
977 __in efsys_mem_t *esmp,
978 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
980 #endif /* EFSYS_OPT_PHY_STATS */
985 typedef enum efx_bist_type_e {
986 EFX_BIST_TYPE_UNKNOWN,
987 EFX_BIST_TYPE_PHY_NORMAL,
988 EFX_BIST_TYPE_PHY_CABLE_SHORT,
989 EFX_BIST_TYPE_PHY_CABLE_LONG,
990 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
991 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
992 EFX_BIST_TYPE_REG, /* Test the register memories */
993 EFX_BIST_TYPE_NTYPES,
996 typedef enum efx_bist_result_e {
997 EFX_BIST_RESULT_UNKNOWN,
998 EFX_BIST_RESULT_RUNNING,
999 EFX_BIST_RESULT_PASSED,
1000 EFX_BIST_RESULT_FAILED,
1001 } efx_bist_result_t;
1003 typedef enum efx_phy_cable_status_e {
1004 EFX_PHY_CABLE_STATUS_OK,
1005 EFX_PHY_CABLE_STATUS_INVALID,
1006 EFX_PHY_CABLE_STATUS_OPEN,
1007 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1008 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1009 EFX_PHY_CABLE_STATUS_BUSY,
1010 } efx_phy_cable_status_t;
1012 typedef enum efx_bist_value_e {
1013 EFX_BIST_PHY_CABLE_LENGTH_A,
1014 EFX_BIST_PHY_CABLE_LENGTH_B,
1015 EFX_BIST_PHY_CABLE_LENGTH_C,
1016 EFX_BIST_PHY_CABLE_LENGTH_D,
1017 EFX_BIST_PHY_CABLE_STATUS_A,
1018 EFX_BIST_PHY_CABLE_STATUS_B,
1019 EFX_BIST_PHY_CABLE_STATUS_C,
1020 EFX_BIST_PHY_CABLE_STATUS_D,
1021 EFX_BIST_FAULT_CODE,
1023 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1029 EFX_BIST_MEM_EXPECT,
1030 EFX_BIST_MEM_ACTUAL,
1032 EFX_BIST_MEM_ECC_PARITY,
1033 EFX_BIST_MEM_ECC_FATAL,
1037 extern __checkReturn efx_rc_t
1038 efx_bist_enable_offline(
1039 __in efx_nic_t *enp);
1041 extern __checkReturn efx_rc_t
1043 __in efx_nic_t *enp,
1044 __in efx_bist_type_t type);
1046 extern __checkReturn efx_rc_t
1048 __in efx_nic_t *enp,
1049 __in efx_bist_type_t type,
1050 __out efx_bist_result_t *resultp,
1051 __out_opt uint32_t *value_maskp,
1052 __out_ecount_opt(count) unsigned long *valuesp,
1057 __in efx_nic_t *enp,
1058 __in efx_bist_type_t type);
1060 #endif /* EFSYS_OPT_BIST */
1062 #define EFX_FEATURE_IPV6 0x00000001
1063 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1064 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1065 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1066 #define EFX_FEATURE_MCDI 0x00000020
1067 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1068 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1069 #define EFX_FEATURE_TURBO 0x00000100
1070 #define EFX_FEATURE_MCDI_DMA 0x00000200
1071 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1072 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1073 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1074 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1075 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1077 typedef enum efx_tunnel_protocol_e {
1078 EFX_TUNNEL_PROTOCOL_NONE = 0,
1079 EFX_TUNNEL_PROTOCOL_VXLAN,
1080 EFX_TUNNEL_PROTOCOL_GENEVE,
1081 EFX_TUNNEL_PROTOCOL_NVGRE,
1083 } efx_tunnel_protocol_t;
1085 typedef struct efx_nic_cfg_s {
1086 uint32_t enc_board_type;
1087 uint32_t enc_phy_type;
1089 char enc_phy_name[21];
1091 char enc_phy_revision[21];
1092 efx_mon_type_t enc_mon_type;
1093 #if EFSYS_OPT_MON_STATS
1094 uint32_t enc_mon_stat_dma_buf_size;
1095 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1097 unsigned int enc_features;
1098 uint8_t enc_mac_addr[6];
1099 uint8_t enc_port; /* PHY port number */
1100 uint32_t enc_intr_vec_base;
1101 uint32_t enc_intr_limit;
1102 uint32_t enc_evq_limit;
1103 uint32_t enc_txq_limit;
1104 uint32_t enc_rxq_limit;
1105 uint32_t enc_txq_max_ndescs;
1106 uint32_t enc_buftbl_limit;
1107 uint32_t enc_piobuf_limit;
1108 uint32_t enc_piobuf_size;
1109 uint32_t enc_piobuf_min_alloc_size;
1110 uint32_t enc_evq_timer_quantum_ns;
1111 uint32_t enc_evq_timer_max_us;
1112 uint32_t enc_clk_mult;
1113 uint32_t enc_rx_prefix_size;
1114 uint32_t enc_rx_buf_align_start;
1115 uint32_t enc_rx_buf_align_end;
1116 uint32_t enc_rx_scale_max_exclusive_contexts;
1117 #if EFSYS_OPT_LOOPBACK
1118 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1119 #endif /* EFSYS_OPT_LOOPBACK */
1120 #if EFSYS_OPT_PHY_FLAGS
1121 uint32_t enc_phy_flags_mask;
1122 #endif /* EFSYS_OPT_PHY_FLAGS */
1123 #if EFSYS_OPT_PHY_LED_CONTROL
1124 uint32_t enc_led_mask;
1125 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1126 #if EFSYS_OPT_PHY_STATS
1127 uint64_t enc_phy_stat_mask;
1128 #endif /* EFSYS_OPT_PHY_STATS */
1130 uint8_t enc_mcdi_mdio_channel;
1131 #if EFSYS_OPT_PHY_STATS
1132 uint32_t enc_mcdi_phy_stat_mask;
1133 #endif /* EFSYS_OPT_PHY_STATS */
1134 #if EFSYS_OPT_MON_STATS
1135 uint32_t *enc_mcdi_sensor_maskp;
1136 uint32_t enc_mcdi_sensor_mask_size;
1137 #endif /* EFSYS_OPT_MON_STATS */
1138 #endif /* EFSYS_OPT_MCDI */
1140 uint32_t enc_bist_mask;
1141 #endif /* EFSYS_OPT_BIST */
1142 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1145 uint32_t enc_privilege_mask;
1146 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1147 boolean_t enc_bug26807_workaround;
1148 boolean_t enc_bug35388_workaround;
1149 boolean_t enc_bug41750_workaround;
1150 boolean_t enc_bug61265_workaround;
1151 boolean_t enc_rx_batching_enabled;
1152 /* Maximum number of descriptors completed in an rx event. */
1153 uint32_t enc_rx_batch_max;
1154 /* Number of rx descriptors the hardware requires for a push. */
1155 uint32_t enc_rx_push_align;
1156 /* Maximum amount of data in DMA descriptor */
1157 uint32_t enc_tx_dma_desc_size_max;
1159 * Boundary which DMA descriptor data must not cross or 0 if no
1162 uint32_t enc_tx_dma_desc_boundary;
1164 * Maximum number of bytes into the packet the TCP header can start for
1165 * the hardware to apply TSO packet edits.
1167 uint32_t enc_tx_tso_tcp_header_offset_limit;
1168 boolean_t enc_fw_assisted_tso_enabled;
1169 boolean_t enc_fw_assisted_tso_v2_enabled;
1170 /* Number of TSO contexts on the NIC (FATSOv2) */
1171 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1172 boolean_t enc_hw_tx_insert_vlan_enabled;
1173 /* Number of PFs on the NIC */
1174 uint32_t enc_hw_pf_count;
1175 /* Datapath firmware vadapter/vport/vswitch support */
1176 boolean_t enc_datapath_cap_evb;
1177 boolean_t enc_rx_disable_scatter_supported;
1178 boolean_t enc_allow_set_mac_with_installed_filters;
1179 boolean_t enc_enhanced_set_mac_supported;
1180 boolean_t enc_init_evq_v2_supported;
1181 boolean_t enc_rx_packed_stream_supported;
1182 boolean_t enc_rx_var_packed_stream_supported;
1183 boolean_t enc_pm_and_rxdp_counters;
1184 boolean_t enc_mac_stats_40g_tx_size_bins;
1185 uint32_t enc_tunnel_encapsulations_supported;
1187 * NIC global maximum for unique UDP tunnel ports shared by all
1190 uint32_t enc_tunnel_config_udp_entries_max;
1191 /* External port identifier */
1192 uint8_t enc_external_port;
1193 uint32_t enc_mcdi_max_payload_length;
1194 /* VPD may be per-PF or global */
1195 boolean_t enc_vpd_is_global;
1196 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1197 uint32_t enc_required_pcie_bandwidth_mbps;
1198 uint32_t enc_max_pcie_link_gen;
1199 /* Firmware verifies integrity of NVRAM updates */
1200 uint32_t enc_nvram_update_verify_result_supported;
1203 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1204 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1206 #define EFX_PCI_FUNCTION(_encp) \
1207 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1209 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1211 extern const efx_nic_cfg_t *
1213 __in efx_nic_t *enp);
1215 typedef struct efx_nic_fw_info_s {
1216 /* Basic FW version information */
1217 uint16_t enfi_mc_fw_version[4];
1219 * If datapath capabilities can be detected,
1220 * additional FW information is to be shown
1222 boolean_t enfi_dpcpu_fw_ids_valid;
1223 /* Rx and Tx datapath CPU FW IDs */
1224 uint16_t enfi_rx_dpcpu_fw_id;
1225 uint16_t enfi_tx_dpcpu_fw_id;
1226 } efx_nic_fw_info_t;
1228 extern __checkReturn efx_rc_t
1229 efx_nic_get_fw_version(
1230 __in efx_nic_t *enp,
1231 __out efx_nic_fw_info_t *enfip);
1233 /* Driver resource limits (minimum required/maximum usable). */
1234 typedef struct efx_drv_limits_s {
1235 uint32_t edl_min_evq_count;
1236 uint32_t edl_max_evq_count;
1238 uint32_t edl_min_rxq_count;
1239 uint32_t edl_max_rxq_count;
1241 uint32_t edl_min_txq_count;
1242 uint32_t edl_max_txq_count;
1244 /* PIO blocks (sub-allocated from piobuf) */
1245 uint32_t edl_min_pio_alloc_size;
1246 uint32_t edl_max_pio_alloc_count;
1249 extern __checkReturn efx_rc_t
1250 efx_nic_set_drv_limits(
1251 __inout efx_nic_t *enp,
1252 __in efx_drv_limits_t *edlp);
1254 typedef enum efx_nic_region_e {
1255 EFX_REGION_VI, /* Memory BAR UC mapping */
1256 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1259 extern __checkReturn efx_rc_t
1260 efx_nic_get_bar_region(
1261 __in efx_nic_t *enp,
1262 __in efx_nic_region_t region,
1263 __out uint32_t *offsetp,
1264 __out size_t *sizep);
1266 extern __checkReturn efx_rc_t
1267 efx_nic_get_vi_pool(
1268 __in efx_nic_t *enp,
1269 __out uint32_t *evq_countp,
1270 __out uint32_t *rxq_countp,
1271 __out uint32_t *txq_countp);
1276 typedef enum efx_vpd_tag_e {
1283 typedef uint16_t efx_vpd_keyword_t;
1285 typedef struct efx_vpd_value_s {
1286 efx_vpd_tag_t evv_tag;
1287 efx_vpd_keyword_t evv_keyword;
1289 uint8_t evv_value[0x100];
1293 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1295 extern __checkReturn efx_rc_t
1297 __in efx_nic_t *enp);
1299 extern __checkReturn efx_rc_t
1301 __in efx_nic_t *enp,
1302 __out size_t *sizep);
1304 extern __checkReturn efx_rc_t
1306 __in efx_nic_t *enp,
1307 __out_bcount(size) caddr_t data,
1310 extern __checkReturn efx_rc_t
1312 __in efx_nic_t *enp,
1313 __in_bcount(size) caddr_t data,
1316 extern __checkReturn efx_rc_t
1318 __in efx_nic_t *enp,
1319 __in_bcount(size) caddr_t data,
1322 extern __checkReturn efx_rc_t
1324 __in efx_nic_t *enp,
1325 __in_bcount(size) caddr_t data,
1327 __inout efx_vpd_value_t *evvp);
1329 extern __checkReturn efx_rc_t
1331 __in efx_nic_t *enp,
1332 __inout_bcount(size) caddr_t data,
1334 __in efx_vpd_value_t *evvp);
1336 extern __checkReturn efx_rc_t
1338 __in efx_nic_t *enp,
1339 __inout_bcount(size) caddr_t data,
1341 __out efx_vpd_value_t *evvp,
1342 __inout unsigned int *contp);
1344 extern __checkReturn efx_rc_t
1346 __in efx_nic_t *enp,
1347 __in_bcount(size) caddr_t data,
1352 __in efx_nic_t *enp);
1354 #endif /* EFSYS_OPT_VPD */
1360 typedef enum efx_nvram_type_e {
1361 EFX_NVRAM_INVALID = 0,
1363 EFX_NVRAM_BOOTROM_CFG,
1364 EFX_NVRAM_MC_FIRMWARE,
1365 EFX_NVRAM_MC_GOLDEN,
1371 EFX_NVRAM_FPGA_BACKUP,
1372 EFX_NVRAM_DYNAMIC_CFG,
1375 EFX_NVRAM_MUM_FIRMWARE,
1379 extern __checkReturn efx_rc_t
1381 __in efx_nic_t *enp);
1385 extern __checkReturn efx_rc_t
1387 __in efx_nic_t *enp);
1389 #endif /* EFSYS_OPT_DIAG */
1391 extern __checkReturn efx_rc_t
1393 __in efx_nic_t *enp,
1394 __in efx_nvram_type_t type,
1395 __out size_t *sizep);
1397 extern __checkReturn efx_rc_t
1399 __in efx_nic_t *enp,
1400 __in efx_nvram_type_t type,
1401 __out_opt size_t *pref_chunkp);
1403 extern __checkReturn efx_rc_t
1404 efx_nvram_rw_finish(
1405 __in efx_nic_t *enp,
1406 __in efx_nvram_type_t type,
1407 __out_opt uint32_t *verify_resultp);
1409 extern __checkReturn efx_rc_t
1410 efx_nvram_get_version(
1411 __in efx_nic_t *enp,
1412 __in efx_nvram_type_t type,
1413 __out uint32_t *subtypep,
1414 __out_ecount(4) uint16_t version[4]);
1416 extern __checkReturn efx_rc_t
1417 efx_nvram_read_chunk(
1418 __in efx_nic_t *enp,
1419 __in efx_nvram_type_t type,
1420 __in unsigned int offset,
1421 __out_bcount(size) caddr_t data,
1424 extern __checkReturn efx_rc_t
1425 efx_nvram_read_backup(
1426 __in efx_nic_t *enp,
1427 __in efx_nvram_type_t type,
1428 __in unsigned int offset,
1429 __out_bcount(size) caddr_t data,
1432 extern __checkReturn efx_rc_t
1433 efx_nvram_set_version(
1434 __in efx_nic_t *enp,
1435 __in efx_nvram_type_t type,
1436 __in_ecount(4) uint16_t version[4]);
1438 extern __checkReturn efx_rc_t
1440 __in efx_nic_t *enp,
1441 __in efx_nvram_type_t type,
1442 __in_bcount(partn_size) caddr_t partn_data,
1443 __in size_t partn_size);
1445 extern __checkReturn efx_rc_t
1447 __in efx_nic_t *enp,
1448 __in efx_nvram_type_t type);
1450 extern __checkReturn efx_rc_t
1451 efx_nvram_write_chunk(
1452 __in efx_nic_t *enp,
1453 __in efx_nvram_type_t type,
1454 __in unsigned int offset,
1455 __in_bcount(size) caddr_t data,
1460 __in efx_nic_t *enp);
1462 #endif /* EFSYS_OPT_NVRAM */
1464 #if EFSYS_OPT_BOOTCFG
1466 /* Report size and offset of bootcfg sector in NVRAM partition. */
1467 extern __checkReturn efx_rc_t
1468 efx_bootcfg_sector_info(
1469 __in efx_nic_t *enp,
1471 __out_opt uint32_t *sector_countp,
1472 __out size_t *offsetp,
1473 __out size_t *max_sizep);
1476 * Copy bootcfg sector data to a target buffer which may differ in size.
1477 * Optionally corrects format errors in source buffer.
1480 efx_bootcfg_copy_sector(
1481 __in efx_nic_t *enp,
1482 __inout_bcount(sector_length)
1484 __in size_t sector_length,
1485 __out_bcount(data_size) uint8_t *data,
1486 __in size_t data_size,
1487 __in boolean_t handle_format_errors);
1491 __in efx_nic_t *enp,
1492 __out_bcount(size) uint8_t *data,
1497 __in efx_nic_t *enp,
1498 __in_bcount(size) uint8_t *data,
1501 #endif /* EFSYS_OPT_BOOTCFG */
1505 typedef enum efx_pattern_type_t {
1506 EFX_PATTERN_BYTE_INCREMENT = 0,
1507 EFX_PATTERN_ALL_THE_SAME,
1508 EFX_PATTERN_BIT_ALTERNATE,
1509 EFX_PATTERN_BYTE_ALTERNATE,
1510 EFX_PATTERN_BYTE_CHANGING,
1511 EFX_PATTERN_BIT_SWEEP,
1513 } efx_pattern_type_t;
1516 (*efx_sram_pattern_fn_t)(
1518 __in boolean_t negate,
1519 __out efx_qword_t *eqp);
1521 extern __checkReturn efx_rc_t
1523 __in efx_nic_t *enp,
1524 __in efx_pattern_type_t type);
1526 #endif /* EFSYS_OPT_DIAG */
1528 extern __checkReturn efx_rc_t
1529 efx_sram_buf_tbl_set(
1530 __in efx_nic_t *enp,
1532 __in efsys_mem_t *esmp,
1536 efx_sram_buf_tbl_clear(
1537 __in efx_nic_t *enp,
1541 #define EFX_BUF_TBL_SIZE 0x20000
1543 #define EFX_BUF_SIZE 4096
1547 typedef struct efx_evq_s efx_evq_t;
1549 #if EFSYS_OPT_QSTATS
1551 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1552 typedef enum efx_ev_qstat_e {
1558 EV_RX_PAUSE_FRM_ERR,
1559 EV_RX_BUF_OWNER_ID_ERR,
1560 EV_RX_IPV4_HDR_CHKSUM_ERR,
1561 EV_RX_TCP_UDP_CHKSUM_ERR,
1565 EV_RX_MCAST_HASH_MATCH,
1582 EV_DRIVER_SRM_UPD_DONE,
1583 EV_DRIVER_TX_DESCQ_FLS_DONE,
1584 EV_DRIVER_RX_DESCQ_FLS_DONE,
1585 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1586 EV_DRIVER_RX_DSC_ERROR,
1587 EV_DRIVER_TX_DSC_ERROR,
1593 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1595 #endif /* EFSYS_OPT_QSTATS */
1597 extern __checkReturn efx_rc_t
1599 __in efx_nic_t *enp);
1603 __in efx_nic_t *enp);
1605 #define EFX_EVQ_MAXNEVS 32768
1606 #define EFX_EVQ_MINNEVS 512
1608 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1609 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1611 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1612 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1613 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1614 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1616 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1617 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1618 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1620 extern __checkReturn efx_rc_t
1622 __in efx_nic_t *enp,
1623 __in unsigned int index,
1624 __in efsys_mem_t *esmp,
1628 __in uint32_t flags,
1629 __deref_out efx_evq_t **eepp);
1633 __in efx_evq_t *eep,
1634 __in uint16_t data);
1636 typedef __checkReturn boolean_t
1637 (*efx_initialized_ev_t)(
1638 __in_opt void *arg);
1640 #define EFX_PKT_UNICAST 0x0004
1641 #define EFX_PKT_START 0x0008
1643 #define EFX_PKT_VLAN_TAGGED 0x0010
1644 #define EFX_CKSUM_TCPUDP 0x0020
1645 #define EFX_CKSUM_IPV4 0x0040
1646 #define EFX_PKT_CONT 0x0080
1648 #define EFX_CHECK_VLAN 0x0100
1649 #define EFX_PKT_TCP 0x0200
1650 #define EFX_PKT_UDP 0x0400
1651 #define EFX_PKT_IPV4 0x0800
1653 #define EFX_PKT_IPV6 0x1000
1654 #define EFX_PKT_PREFIX_LEN 0x2000
1655 #define EFX_ADDR_MISMATCH 0x4000
1656 #define EFX_DISCARD 0x8000
1659 * The following flags are used only for packed stream
1660 * mode. The values for the flags are reused to fit into 16 bit,
1661 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1662 * packed stream mode
1664 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1665 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1668 #define EFX_EV_RX_NLABELS 32
1669 #define EFX_EV_TX_NLABELS 32
1671 typedef __checkReturn boolean_t
1674 __in uint32_t label,
1677 __in uint16_t flags);
1679 #if EFSYS_OPT_RX_PACKED_STREAM
1682 * Packed stream mode is documented in SF-112241-TC.
1683 * The general idea is that, instead of putting each incoming
1684 * packet into a separate buffer which is specified in a RX
1685 * descriptor, a large buffer is provided to the hardware and
1686 * packets are put there in a continuous stream.
1687 * The main advantage of such an approach is that RX queue refilling
1688 * happens much less frequently.
1691 typedef __checkReturn boolean_t
1694 __in uint32_t label,
1696 __in uint32_t pkt_count,
1697 __in uint16_t flags);
1701 typedef __checkReturn boolean_t
1704 __in uint32_t label,
1707 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1708 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1709 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1710 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1711 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1712 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1713 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1714 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1715 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1717 typedef __checkReturn boolean_t
1718 (*efx_exception_ev_t)(
1720 __in uint32_t label,
1721 __in uint32_t data);
1723 typedef __checkReturn boolean_t
1724 (*efx_rxq_flush_done_ev_t)(
1726 __in uint32_t rxq_index);
1728 typedef __checkReturn boolean_t
1729 (*efx_rxq_flush_failed_ev_t)(
1731 __in uint32_t rxq_index);
1733 typedef __checkReturn boolean_t
1734 (*efx_txq_flush_done_ev_t)(
1736 __in uint32_t txq_index);
1738 typedef __checkReturn boolean_t
1739 (*efx_software_ev_t)(
1741 __in uint16_t magic);
1743 typedef __checkReturn boolean_t
1746 __in uint32_t code);
1748 #define EFX_SRAM_CLEAR 0
1749 #define EFX_SRAM_UPDATE 1
1750 #define EFX_SRAM_ILLEGAL_CLEAR 2
1752 typedef __checkReturn boolean_t
1753 (*efx_wake_up_ev_t)(
1755 __in uint32_t label);
1757 typedef __checkReturn boolean_t
1760 __in uint32_t label);
1762 typedef __checkReturn boolean_t
1763 (*efx_link_change_ev_t)(
1765 __in efx_link_mode_t link_mode);
1767 #if EFSYS_OPT_MON_STATS
1769 typedef __checkReturn boolean_t
1770 (*efx_monitor_ev_t)(
1772 __in efx_mon_stat_t id,
1773 __in efx_mon_stat_value_t value);
1775 #endif /* EFSYS_OPT_MON_STATS */
1777 #if EFSYS_OPT_MAC_STATS
1779 typedef __checkReturn boolean_t
1780 (*efx_mac_stats_ev_t)(
1782 __in uint32_t generation);
1784 #endif /* EFSYS_OPT_MAC_STATS */
1786 typedef struct efx_ev_callbacks_s {
1787 efx_initialized_ev_t eec_initialized;
1789 #if EFSYS_OPT_RX_PACKED_STREAM
1790 efx_rx_ps_ev_t eec_rx_ps;
1793 efx_exception_ev_t eec_exception;
1794 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1795 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1796 efx_txq_flush_done_ev_t eec_txq_flush_done;
1797 efx_software_ev_t eec_software;
1798 efx_sram_ev_t eec_sram;
1799 efx_wake_up_ev_t eec_wake_up;
1800 efx_timer_ev_t eec_timer;
1801 efx_link_change_ev_t eec_link_change;
1802 #if EFSYS_OPT_MON_STATS
1803 efx_monitor_ev_t eec_monitor;
1804 #endif /* EFSYS_OPT_MON_STATS */
1805 #if EFSYS_OPT_MAC_STATS
1806 efx_mac_stats_ev_t eec_mac_stats;
1807 #endif /* EFSYS_OPT_MAC_STATS */
1808 } efx_ev_callbacks_t;
1810 extern __checkReturn boolean_t
1812 __in efx_evq_t *eep,
1813 __in unsigned int count);
1815 #if EFSYS_OPT_EV_PREFETCH
1819 __in efx_evq_t *eep,
1820 __in unsigned int count);
1822 #endif /* EFSYS_OPT_EV_PREFETCH */
1826 __in efx_evq_t *eep,
1827 __inout unsigned int *countp,
1828 __in const efx_ev_callbacks_t *eecp,
1829 __in_opt void *arg);
1831 extern __checkReturn efx_rc_t
1832 efx_ev_usecs_to_ticks(
1833 __in efx_nic_t *enp,
1834 __in unsigned int usecs,
1835 __out unsigned int *ticksp);
1837 extern __checkReturn efx_rc_t
1839 __in efx_evq_t *eep,
1840 __in unsigned int us);
1842 extern __checkReturn efx_rc_t
1844 __in efx_evq_t *eep,
1845 __in unsigned int count);
1847 #if EFSYS_OPT_QSTATS
1853 __in efx_nic_t *enp,
1854 __in unsigned int id);
1856 #endif /* EFSYS_OPT_NAMES */
1859 efx_ev_qstats_update(
1860 __in efx_evq_t *eep,
1861 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1863 #endif /* EFSYS_OPT_QSTATS */
1867 __in efx_evq_t *eep);
1871 extern __checkReturn efx_rc_t
1873 __inout efx_nic_t *enp);
1877 __in efx_nic_t *enp);
1879 #if EFSYS_OPT_RX_SCATTER
1880 __checkReturn efx_rc_t
1881 efx_rx_scatter_enable(
1882 __in efx_nic_t *enp,
1883 __in unsigned int buf_size);
1884 #endif /* EFSYS_OPT_RX_SCATTER */
1886 /* Handle to represent use of the default RSS context. */
1887 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1889 #if EFSYS_OPT_RX_SCALE
1891 typedef enum efx_rx_hash_alg_e {
1892 EFX_RX_HASHALG_LFSR = 0,
1893 EFX_RX_HASHALG_TOEPLITZ
1894 } efx_rx_hash_alg_t;
1896 #define EFX_RX_HASH_IPV4 (1U << 0)
1897 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1898 #define EFX_RX_HASH_IPV6 (1U << 2)
1899 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1901 typedef unsigned int efx_rx_hash_type_t;
1903 typedef enum efx_rx_hash_support_e {
1904 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1905 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1906 } efx_rx_hash_support_t;
1908 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1909 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1910 #define EFX_MAXRSS 64 /* RX indirection entry range */
1911 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1913 typedef enum efx_rx_scale_context_type_e {
1914 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1915 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1916 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1917 } efx_rx_scale_context_type_t;
1919 extern __checkReturn efx_rc_t
1920 efx_rx_hash_default_support_get(
1921 __in efx_nic_t *enp,
1922 __out efx_rx_hash_support_t *supportp);
1925 extern __checkReturn efx_rc_t
1926 efx_rx_scale_default_support_get(
1927 __in efx_nic_t *enp,
1928 __out efx_rx_scale_context_type_t *typep);
1930 extern __checkReturn efx_rc_t
1931 efx_rx_scale_context_alloc(
1932 __in efx_nic_t *enp,
1933 __in efx_rx_scale_context_type_t type,
1934 __in uint32_t num_queues,
1935 __out uint32_t *rss_contextp);
1937 extern __checkReturn efx_rc_t
1938 efx_rx_scale_context_free(
1939 __in efx_nic_t *enp,
1940 __in uint32_t rss_context);
1942 extern __checkReturn efx_rc_t
1943 efx_rx_scale_mode_set(
1944 __in efx_nic_t *enp,
1945 __in uint32_t rss_context,
1946 __in efx_rx_hash_alg_t alg,
1947 __in efx_rx_hash_type_t type,
1948 __in boolean_t insert);
1950 extern __checkReturn efx_rc_t
1951 efx_rx_scale_tbl_set(
1952 __in efx_nic_t *enp,
1953 __in uint32_t rss_context,
1954 __in_ecount(n) unsigned int *table,
1957 extern __checkReturn efx_rc_t
1958 efx_rx_scale_key_set(
1959 __in efx_nic_t *enp,
1960 __in uint32_t rss_context,
1961 __in_ecount(n) uint8_t *key,
1964 extern __checkReturn uint32_t
1965 efx_pseudo_hdr_hash_get(
1966 __in efx_rxq_t *erp,
1967 __in efx_rx_hash_alg_t func,
1968 __in uint8_t *buffer);
1970 #endif /* EFSYS_OPT_RX_SCALE */
1972 extern __checkReturn efx_rc_t
1973 efx_pseudo_hdr_pkt_length_get(
1974 __in efx_rxq_t *erp,
1975 __in uint8_t *buffer,
1976 __out uint16_t *pkt_lengthp);
1978 #define EFX_RXQ_MAXNDESCS 4096
1979 #define EFX_RXQ_MINNDESCS 512
1981 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1982 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1983 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1984 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1986 typedef enum efx_rxq_type_e {
1987 EFX_RXQ_TYPE_DEFAULT,
1988 EFX_RXQ_TYPE_PACKED_STREAM,
1993 * Dummy flag to be used instead of 0 to make it clear that the argument
1994 * is receive queue flags.
1996 #define EFX_RXQ_FLAG_NONE 0x0
1997 #define EFX_RXQ_FLAG_SCATTER 0x1
1999 * If tunnels are supported and Rx event can provide information about
2000 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2001 * full-feature firmware variant running), outer classes are requested by
2002 * default. However, if the driver supports tunnels, the flag allows to
2003 * request inner classes which are required to be able to interpret inner
2004 * Rx checksum offload results.
2006 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2008 extern __checkReturn efx_rc_t
2010 __in efx_nic_t *enp,
2011 __in unsigned int index,
2012 __in unsigned int label,
2013 __in efx_rxq_type_t type,
2014 __in efsys_mem_t *esmp,
2017 __in unsigned int flags,
2018 __in efx_evq_t *eep,
2019 __deref_out efx_rxq_t **erpp);
2021 #if EFSYS_OPT_RX_PACKED_STREAM
2023 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2024 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2025 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2026 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2027 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2029 extern __checkReturn efx_rc_t
2030 efx_rx_qcreate_packed_stream(
2031 __in efx_nic_t *enp,
2032 __in unsigned int index,
2033 __in unsigned int label,
2034 __in uint32_t ps_buf_size,
2035 __in efsys_mem_t *esmp,
2037 __in efx_evq_t *eep,
2038 __deref_out efx_rxq_t **erpp);
2042 typedef struct efx_buffer_s {
2043 efsys_dma_addr_t eb_addr;
2048 typedef struct efx_desc_s {
2054 __in efx_rxq_t *erp,
2055 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2057 __in unsigned int ndescs,
2058 __in unsigned int completed,
2059 __in unsigned int added);
2063 __in efx_rxq_t *erp,
2064 __in unsigned int added,
2065 __inout unsigned int *pushedp);
2067 #if EFSYS_OPT_RX_PACKED_STREAM
2070 efx_rx_qpush_ps_credits(
2071 __in efx_rxq_t *erp);
2073 extern __checkReturn uint8_t *
2074 efx_rx_qps_packet_info(
2075 __in efx_rxq_t *erp,
2076 __in uint8_t *buffer,
2077 __in uint32_t buffer_length,
2078 __in uint32_t current_offset,
2079 __out uint16_t *lengthp,
2080 __out uint32_t *next_offsetp,
2081 __out uint32_t *timestamp);
2084 extern __checkReturn efx_rc_t
2086 __in efx_rxq_t *erp);
2090 __in efx_rxq_t *erp);
2094 __in efx_rxq_t *erp);
2098 typedef struct efx_txq_s efx_txq_t;
2100 #if EFSYS_OPT_QSTATS
2102 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2103 typedef enum efx_tx_qstat_e {
2109 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2111 #endif /* EFSYS_OPT_QSTATS */
2113 extern __checkReturn efx_rc_t
2115 __in efx_nic_t *enp);
2119 __in efx_nic_t *enp);
2121 #define EFX_TXQ_MINNDESCS 512
2123 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2124 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2125 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2127 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2129 #define EFX_TXQ_CKSUM_IPV4 0x0001
2130 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2131 #define EFX_TXQ_FATSOV2 0x0004
2132 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2133 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2135 extern __checkReturn efx_rc_t
2137 __in efx_nic_t *enp,
2138 __in unsigned int index,
2139 __in unsigned int label,
2140 __in efsys_mem_t *esmp,
2143 __in uint16_t flags,
2144 __in efx_evq_t *eep,
2145 __deref_out efx_txq_t **etpp,
2146 __out unsigned int *addedp);
2148 extern __checkReturn efx_rc_t
2150 __in efx_txq_t *etp,
2151 __in_ecount(ndescs) efx_buffer_t *eb,
2152 __in unsigned int ndescs,
2153 __in unsigned int completed,
2154 __inout unsigned int *addedp);
2156 extern __checkReturn efx_rc_t
2158 __in efx_txq_t *etp,
2159 __in unsigned int ns);
2163 __in efx_txq_t *etp,
2164 __in unsigned int added,
2165 __in unsigned int pushed);
2167 extern __checkReturn efx_rc_t
2169 __in efx_txq_t *etp);
2173 __in efx_txq_t *etp);
2175 extern __checkReturn efx_rc_t
2177 __in efx_txq_t *etp);
2180 efx_tx_qpio_disable(
2181 __in efx_txq_t *etp);
2183 extern __checkReturn efx_rc_t
2185 __in efx_txq_t *etp,
2186 __in_ecount(buf_length) uint8_t *buffer,
2187 __in size_t buf_length,
2188 __in size_t pio_buf_offset);
2190 extern __checkReturn efx_rc_t
2192 __in efx_txq_t *etp,
2193 __in size_t pkt_length,
2194 __in unsigned int completed,
2195 __inout unsigned int *addedp);
2197 extern __checkReturn efx_rc_t
2199 __in efx_txq_t *etp,
2200 __in_ecount(n) efx_desc_t *ed,
2201 __in unsigned int n,
2202 __in unsigned int completed,
2203 __inout unsigned int *addedp);
2206 efx_tx_qdesc_dma_create(
2207 __in efx_txq_t *etp,
2208 __in efsys_dma_addr_t addr,
2211 __out efx_desc_t *edp);
2214 efx_tx_qdesc_tso_create(
2215 __in efx_txq_t *etp,
2216 __in uint16_t ipv4_id,
2217 __in uint32_t tcp_seq,
2218 __in uint8_t tcp_flags,
2219 __out efx_desc_t *edp);
2221 /* Number of FATSOv2 option descriptors */
2222 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2224 /* Maximum number of DMA segments per TSO packet (not superframe) */
2225 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2228 efx_tx_qdesc_tso2_create(
2229 __in efx_txq_t *etp,
2230 __in uint16_t ipv4_id,
2231 __in uint32_t tcp_seq,
2232 __in uint16_t tcp_mss,
2233 __out_ecount(count) efx_desc_t *edp,
2237 efx_tx_qdesc_vlantci_create(
2238 __in efx_txq_t *etp,
2240 __out efx_desc_t *edp);
2242 #if EFSYS_OPT_QSTATS
2248 __in efx_nic_t *etp,
2249 __in unsigned int id);
2251 #endif /* EFSYS_OPT_NAMES */
2254 efx_tx_qstats_update(
2255 __in efx_txq_t *etp,
2256 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2258 #endif /* EFSYS_OPT_QSTATS */
2262 __in efx_txq_t *etp);
2267 #if EFSYS_OPT_FILTER
2269 #define EFX_ETHER_TYPE_IPV4 0x0800
2270 #define EFX_ETHER_TYPE_IPV6 0x86DD
2272 #define EFX_IPPROTO_TCP 6
2273 #define EFX_IPPROTO_UDP 17
2274 #define EFX_IPPROTO_GRE 47
2276 /* Use RSS to spread across multiple queues */
2277 #define EFX_FILTER_FLAG_RX_RSS 0x01
2278 /* Enable RX scatter */
2279 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2281 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2282 * May only be set by the filter implementation for each type.
2283 * A removal request will restore the automatic filter in its place.
2285 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2286 /* Filter is for RX */
2287 #define EFX_FILTER_FLAG_RX 0x08
2288 /* Filter is for TX */
2289 #define EFX_FILTER_FLAG_TX 0x10
2291 typedef uint8_t efx_filter_flags_t;
2294 * Flags which specify the fields to match on. The values are the same as in the
2295 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2298 /* Match by remote IP host address */
2299 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2300 /* Match by local IP host address */
2301 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2302 /* Match by remote MAC address */
2303 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2304 /* Match by remote TCP/UDP port */
2305 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2306 /* Match by remote TCP/UDP port */
2307 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2308 /* Match by local TCP/UDP port */
2309 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2310 /* Match by Ether-type */
2311 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2312 /* Match by inner VLAN ID */
2313 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2314 /* Match by outer VLAN ID */
2315 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2316 /* Match by IP transport protocol */
2317 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2318 /* For encapsulated packets, match all multicast inner frames */
2319 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2320 /* For encapsulated packets, match all unicast inner frames */
2321 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2322 /* Match otherwise-unmatched multicast and broadcast packets */
2323 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2324 /* Match otherwise-unmatched unicast packets */
2325 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2327 typedef uint32_t efx_filter_match_flags_t;
2329 typedef enum efx_filter_priority_s {
2330 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2331 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2332 * address list or hardware
2333 * requirements. This may only be used
2334 * by the filter implementation for
2336 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2337 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2338 * client (e.g. SR-IOV, HyperV VMQ etc.)
2340 } efx_filter_priority_t;
2343 * FIXME: All these fields are assumed to be in little-endian byte order.
2344 * It may be better for some to be big-endian. See bug42804.
2347 typedef struct efx_filter_spec_s {
2348 efx_filter_match_flags_t efs_match_flags;
2349 uint8_t efs_priority;
2350 efx_filter_flags_t efs_flags;
2351 uint16_t efs_dmaq_id;
2352 uint32_t efs_rss_context;
2353 uint16_t efs_outer_vid;
2354 uint16_t efs_inner_vid;
2355 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2356 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2357 uint16_t efs_ether_type;
2358 uint8_t efs_ip_proto;
2359 efx_tunnel_protocol_t efs_encap_type;
2360 uint16_t efs_loc_port;
2361 uint16_t efs_rem_port;
2362 efx_oword_t efs_rem_host;
2363 efx_oword_t efs_loc_host;
2364 } efx_filter_spec_t;
2367 /* Default values for use in filter specifications */
2368 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2369 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2371 extern __checkReturn efx_rc_t
2373 __in efx_nic_t *enp);
2377 __in efx_nic_t *enp);
2379 extern __checkReturn efx_rc_t
2381 __in efx_nic_t *enp,
2382 __inout efx_filter_spec_t *spec);
2384 extern __checkReturn efx_rc_t
2386 __in efx_nic_t *enp,
2387 __inout efx_filter_spec_t *spec);
2389 extern __checkReturn efx_rc_t
2391 __in efx_nic_t *enp);
2393 extern __checkReturn efx_rc_t
2394 efx_filter_supported_filters(
2395 __in efx_nic_t *enp,
2396 __out_ecount(buffer_length) uint32_t *buffer,
2397 __in size_t buffer_length,
2398 __out size_t *list_lengthp);
2401 efx_filter_spec_init_rx(
2402 __out efx_filter_spec_t *spec,
2403 __in efx_filter_priority_t priority,
2404 __in efx_filter_flags_t flags,
2405 __in efx_rxq_t *erp);
2408 efx_filter_spec_init_tx(
2409 __out efx_filter_spec_t *spec,
2410 __in efx_txq_t *etp);
2412 extern __checkReturn efx_rc_t
2413 efx_filter_spec_set_ipv4_local(
2414 __inout efx_filter_spec_t *spec,
2417 __in uint16_t port);
2419 extern __checkReturn efx_rc_t
2420 efx_filter_spec_set_ipv4_full(
2421 __inout efx_filter_spec_t *spec,
2423 __in uint32_t lhost,
2424 __in uint16_t lport,
2425 __in uint32_t rhost,
2426 __in uint16_t rport);
2428 extern __checkReturn efx_rc_t
2429 efx_filter_spec_set_eth_local(
2430 __inout efx_filter_spec_t *spec,
2432 __in const uint8_t *addr);
2435 efx_filter_spec_set_ether_type(
2436 __inout efx_filter_spec_t *spec,
2437 __in uint16_t ether_type);
2439 extern __checkReturn efx_rc_t
2440 efx_filter_spec_set_uc_def(
2441 __inout efx_filter_spec_t *spec);
2443 extern __checkReturn efx_rc_t
2444 efx_filter_spec_set_mc_def(
2445 __inout efx_filter_spec_t *spec);
2447 typedef enum efx_filter_inner_frame_match_e {
2448 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2449 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2450 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2451 } efx_filter_inner_frame_match_t;
2453 extern __checkReturn efx_rc_t
2454 efx_filter_spec_set_encap_type(
2455 __inout efx_filter_spec_t *spec,
2456 __in efx_tunnel_protocol_t encap_type,
2457 __in efx_filter_inner_frame_match_t inner_frame_match);
2459 #if EFSYS_OPT_RX_SCALE
2460 extern __checkReturn efx_rc_t
2461 efx_filter_spec_set_rss_context(
2462 __inout efx_filter_spec_t *spec,
2463 __in uint32_t rss_context);
2465 #endif /* EFSYS_OPT_FILTER */
2469 extern __checkReturn uint32_t
2471 __in_ecount(count) uint32_t const *input,
2473 __in uint32_t init);
2475 extern __checkReturn uint32_t
2477 __in_ecount(length) uint8_t const *input,
2479 __in uint32_t init);
2481 #if EFSYS_OPT_LICENSING
2485 typedef struct efx_key_stats_s {
2487 uint32_t eks_invalid;
2488 uint32_t eks_blacklisted;
2489 uint32_t eks_unverifiable;
2490 uint32_t eks_wrong_node;
2491 uint32_t eks_licensed_apps_lo;
2492 uint32_t eks_licensed_apps_hi;
2493 uint32_t eks_licensed_features_lo;
2494 uint32_t eks_licensed_features_hi;
2497 extern __checkReturn efx_rc_t
2499 __in efx_nic_t *enp);
2503 __in efx_nic_t *enp);
2505 extern __checkReturn boolean_t
2506 efx_lic_check_support(
2507 __in efx_nic_t *enp);
2509 extern __checkReturn efx_rc_t
2510 efx_lic_update_licenses(
2511 __in efx_nic_t *enp);
2513 extern __checkReturn efx_rc_t
2514 efx_lic_get_key_stats(
2515 __in efx_nic_t *enp,
2516 __out efx_key_stats_t *ksp);
2518 extern __checkReturn efx_rc_t
2520 __in efx_nic_t *enp,
2521 __in uint64_t app_id,
2522 __out boolean_t *licensedp);
2524 extern __checkReturn efx_rc_t
2526 __in efx_nic_t *enp,
2527 __in size_t buffer_size,
2528 __out uint32_t *typep,
2529 __out size_t *lengthp,
2530 __out_opt uint8_t *bufferp);
2533 extern __checkReturn efx_rc_t
2535 __in efx_nic_t *enp,
2536 __in_bcount(buffer_size)
2538 __in size_t buffer_size,
2539 __out uint32_t *startp);
2541 extern __checkReturn efx_rc_t
2543 __in efx_nic_t *enp,
2544 __in_bcount(buffer_size)
2546 __in size_t buffer_size,
2547 __in uint32_t offset,
2548 __out uint32_t *endp);
2550 extern __checkReturn __success(return != B_FALSE) boolean_t
2552 __in efx_nic_t *enp,
2553 __in_bcount(buffer_size)
2555 __in size_t buffer_size,
2556 __in uint32_t offset,
2557 __out uint32_t *startp,
2558 __out uint32_t *lengthp);
2560 extern __checkReturn __success(return != B_FALSE) boolean_t
2561 efx_lic_validate_key(
2562 __in efx_nic_t *enp,
2563 __in_bcount(length) caddr_t keyp,
2564 __in uint32_t length);
2566 extern __checkReturn efx_rc_t
2568 __in efx_nic_t *enp,
2569 __in_bcount(buffer_size)
2571 __in size_t buffer_size,
2572 __in uint32_t offset,
2573 __in uint32_t length,
2574 __out_bcount_part(key_max_size, *lengthp)
2576 __in size_t key_max_size,
2577 __out uint32_t *lengthp);
2579 extern __checkReturn efx_rc_t
2581 __in efx_nic_t *enp,
2582 __in_bcount(buffer_size)
2584 __in size_t buffer_size,
2585 __in uint32_t offset,
2586 __in_bcount(length) caddr_t keyp,
2587 __in uint32_t length,
2588 __out uint32_t *lengthp);
2590 __checkReturn efx_rc_t
2592 __in efx_nic_t *enp,
2593 __in_bcount(buffer_size)
2595 __in size_t buffer_size,
2596 __in uint32_t offset,
2597 __in uint32_t length,
2599 __out uint32_t *deltap);
2601 extern __checkReturn efx_rc_t
2602 efx_lic_create_partition(
2603 __in efx_nic_t *enp,
2604 __in_bcount(buffer_size)
2606 __in size_t buffer_size);
2608 extern __checkReturn efx_rc_t
2609 efx_lic_finish_partition(
2610 __in efx_nic_t *enp,
2611 __in_bcount(buffer_size)
2613 __in size_t buffer_size);
2615 #endif /* EFSYS_OPT_LICENSING */
2619 #if EFSYS_OPT_TUNNEL
2621 extern __checkReturn efx_rc_t
2623 __in efx_nic_t *enp);
2627 __in efx_nic_t *enp);
2630 * For overlay network encapsulation using UDP, the firmware needs to know
2631 * the configured UDP port for the overlay so it can decode encapsulated
2633 * The UDP port/protocol list is global.
2636 extern __checkReturn efx_rc_t
2637 efx_tunnel_config_udp_add(
2638 __in efx_nic_t *enp,
2639 __in uint16_t port /* host/cpu-endian */,
2640 __in efx_tunnel_protocol_t protocol);
2642 extern __checkReturn efx_rc_t
2643 efx_tunnel_config_udp_remove(
2644 __in efx_nic_t *enp,
2645 __in uint16_t port /* host/cpu-endian */,
2646 __in efx_tunnel_protocol_t protocol);
2649 efx_tunnel_config_clear(
2650 __in efx_nic_t *enp);
2653 * Apply tunnel UDP ports configuration to hardware.
2655 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2658 extern __checkReturn efx_rc_t
2659 efx_tunnel_reconfigure(
2660 __in efx_nic_t *enp);
2662 #endif /* EFSYS_OPT_TUNNEL */
2669 #endif /* _SYS_EFX_H */