1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
34 typedef __success(return == 0) int efx_rc_t;
39 typedef enum efx_family_e {
41 EFX_FAMILY_FALCON, /* Obsolete and not supported */
43 EFX_FAMILY_HUNTINGTON,
49 extern __checkReturn efx_rc_t
53 __out efx_family_t *efp,
54 __out unsigned int *membarp);
57 #define EFX_PCI_VENID_SFC 0x1924
59 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
61 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
62 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
63 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
65 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
66 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
67 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
69 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
70 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
72 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
73 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
74 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
76 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
77 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
78 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
81 #define EFX_MEM_BAR_SIENA 2
83 #define EFX_MEM_BAR_HUNTINGTON_PF 2
84 #define EFX_MEM_BAR_HUNTINGTON_VF 0
86 #define EFX_MEM_BAR_MEDFORD_PF 2
87 #define EFX_MEM_BAR_MEDFORD_VF 0
89 #define EFX_MEM_BAR_MEDFORD2 0
110 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
111 extern __checkReturn uint32_t
113 __in uint32_t crc_init,
114 __in_ecount(length) uint8_t const *input,
118 /* Type prototypes */
120 typedef struct efx_rxq_s efx_rxq_t;
124 typedef struct efx_nic_s efx_nic_t;
126 extern __checkReturn efx_rc_t
128 __in efx_family_t family,
129 __in efsys_identifier_t *esip,
130 __in efsys_bar_t *esbp,
131 __in efsys_lock_t *eslp,
132 __deref_out efx_nic_t **enpp);
134 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
135 typedef enum efx_fw_variant_e {
136 EFX_FW_VARIANT_FULL_FEATURED,
137 EFX_FW_VARIANT_LOW_LATENCY,
138 EFX_FW_VARIANT_PACKED_STREAM,
139 EFX_FW_VARIANT_HIGH_TX_RATE,
140 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
141 EFX_FW_VARIANT_RULES_ENGINE,
143 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
146 extern __checkReturn efx_rc_t
149 __in efx_fw_variant_t efv);
151 extern __checkReturn efx_rc_t
153 __in efx_nic_t *enp);
155 extern __checkReturn efx_rc_t
157 __in efx_nic_t *enp);
159 extern __checkReturn boolean_t
160 efx_nic_hw_unavailable(
161 __in efx_nic_t *enp);
164 efx_nic_set_hw_unavailable(
165 __in efx_nic_t *enp);
169 extern __checkReturn efx_rc_t
170 efx_nic_register_test(
171 __in efx_nic_t *enp);
173 #endif /* EFSYS_OPT_DIAG */
177 __in efx_nic_t *enp);
181 __in efx_nic_t *enp);
185 __in efx_nic_t *enp);
187 #define EFX_PCIE_LINK_SPEED_GEN1 1
188 #define EFX_PCIE_LINK_SPEED_GEN2 2
189 #define EFX_PCIE_LINK_SPEED_GEN3 3
191 typedef enum efx_pcie_link_performance_e {
192 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
193 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
194 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
195 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
196 } efx_pcie_link_performance_t;
198 extern __checkReturn efx_rc_t
199 efx_nic_calculate_pcie_link_bandwidth(
200 __in uint32_t pcie_link_width,
201 __in uint32_t pcie_link_gen,
202 __out uint32_t *bandwidth_mbpsp);
204 extern __checkReturn efx_rc_t
205 efx_nic_check_pcie_link_speed(
207 __in uint32_t pcie_link_width,
208 __in uint32_t pcie_link_gen,
209 __out efx_pcie_link_performance_t *resultp);
214 /* EF10 architecture NICs require MCDIv2 commands */
215 #define WITH_MCDI_V2 1
218 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
220 typedef enum efx_mcdi_exception_e {
221 EFX_MCDI_EXCEPTION_MC_REBOOT,
222 EFX_MCDI_EXCEPTION_MC_BADASSERT,
223 } efx_mcdi_exception_t;
225 #if EFSYS_OPT_MCDI_LOGGING
226 typedef enum efx_log_msg_e {
228 EFX_LOG_MCDI_REQUEST,
229 EFX_LOG_MCDI_RESPONSE,
231 #endif /* EFSYS_OPT_MCDI_LOGGING */
233 typedef struct efx_mcdi_transport_s {
235 efsys_mem_t *emt_dma_mem;
236 void (*emt_execute)(void *, efx_mcdi_req_t *);
237 void (*emt_ev_cpl)(void *);
238 void (*emt_exception)(void *, efx_mcdi_exception_t);
239 #if EFSYS_OPT_MCDI_LOGGING
240 void (*emt_logger)(void *, efx_log_msg_t,
241 void *, size_t, void *, size_t);
242 #endif /* EFSYS_OPT_MCDI_LOGGING */
243 #if EFSYS_OPT_MCDI_PROXY_AUTH
244 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
245 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
246 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
247 void (*emt_ev_proxy_request)(void *, uint32_t);
248 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
249 } efx_mcdi_transport_t;
251 extern __checkReturn efx_rc_t
254 __in const efx_mcdi_transport_t *mtp);
256 extern __checkReturn efx_rc_t
258 __in efx_nic_t *enp);
262 __in efx_nic_t *enp);
265 efx_mcdi_get_timeout(
267 __in efx_mcdi_req_t *emrp,
268 __out uint32_t *usec_timeoutp);
271 efx_mcdi_request_start(
273 __in efx_mcdi_req_t *emrp,
274 __in boolean_t ev_cpl);
276 extern __checkReturn boolean_t
277 efx_mcdi_request_poll(
278 __in efx_nic_t *enp);
280 extern __checkReturn boolean_t
281 efx_mcdi_request_abort(
282 __in efx_nic_t *enp);
286 __in efx_nic_t *enp);
288 #endif /* EFSYS_OPT_MCDI */
292 #define EFX_NINTR_SIENA 1024
294 typedef enum efx_intr_type_e {
295 EFX_INTR_INVALID = 0,
301 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
303 extern __checkReturn efx_rc_t
306 __in efx_intr_type_t type,
307 __in_opt efsys_mem_t *esmp);
311 __in efx_nic_t *enp);
315 __in efx_nic_t *enp);
318 efx_intr_disable_unlocked(
319 __in efx_nic_t *enp);
321 #define EFX_INTR_NEVQS 32
323 extern __checkReturn efx_rc_t
326 __in unsigned int level);
329 efx_intr_status_line(
331 __out boolean_t *fatalp,
332 __out uint32_t *maskp);
335 efx_intr_status_message(
337 __in unsigned int message,
338 __out boolean_t *fatalp);
342 __in efx_nic_t *enp);
346 __in efx_nic_t *enp);
350 #if EFSYS_OPT_MAC_STATS
352 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
353 typedef enum efx_mac_stat_e {
356 EFX_MAC_RX_UNICST_PKTS,
357 EFX_MAC_RX_MULTICST_PKTS,
358 EFX_MAC_RX_BRDCST_PKTS,
359 EFX_MAC_RX_PAUSE_PKTS,
360 EFX_MAC_RX_LE_64_PKTS,
361 EFX_MAC_RX_65_TO_127_PKTS,
362 EFX_MAC_RX_128_TO_255_PKTS,
363 EFX_MAC_RX_256_TO_511_PKTS,
364 EFX_MAC_RX_512_TO_1023_PKTS,
365 EFX_MAC_RX_1024_TO_15XX_PKTS,
366 EFX_MAC_RX_GE_15XX_PKTS,
368 EFX_MAC_RX_FCS_ERRORS,
369 EFX_MAC_RX_DROP_EVENTS,
370 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
371 EFX_MAC_RX_SYMBOL_ERRORS,
372 EFX_MAC_RX_ALIGN_ERRORS,
373 EFX_MAC_RX_INTERNAL_ERRORS,
374 EFX_MAC_RX_JABBER_PKTS,
375 EFX_MAC_RX_LANE0_CHAR_ERR,
376 EFX_MAC_RX_LANE1_CHAR_ERR,
377 EFX_MAC_RX_LANE2_CHAR_ERR,
378 EFX_MAC_RX_LANE3_CHAR_ERR,
379 EFX_MAC_RX_LANE0_DISP_ERR,
380 EFX_MAC_RX_LANE1_DISP_ERR,
381 EFX_MAC_RX_LANE2_DISP_ERR,
382 EFX_MAC_RX_LANE3_DISP_ERR,
383 EFX_MAC_RX_MATCH_FAULT,
384 EFX_MAC_RX_NODESC_DROP_CNT,
387 EFX_MAC_TX_UNICST_PKTS,
388 EFX_MAC_TX_MULTICST_PKTS,
389 EFX_MAC_TX_BRDCST_PKTS,
390 EFX_MAC_TX_PAUSE_PKTS,
391 EFX_MAC_TX_LE_64_PKTS,
392 EFX_MAC_TX_65_TO_127_PKTS,
393 EFX_MAC_TX_128_TO_255_PKTS,
394 EFX_MAC_TX_256_TO_511_PKTS,
395 EFX_MAC_TX_512_TO_1023_PKTS,
396 EFX_MAC_TX_1024_TO_15XX_PKTS,
397 EFX_MAC_TX_GE_15XX_PKTS,
399 EFX_MAC_TX_SGL_COL_PKTS,
400 EFX_MAC_TX_MULT_COL_PKTS,
401 EFX_MAC_TX_EX_COL_PKTS,
402 EFX_MAC_TX_LATE_COL_PKTS,
404 EFX_MAC_TX_EX_DEF_PKTS,
405 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
406 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
407 EFX_MAC_PM_TRUNC_VFIFO_FULL,
408 EFX_MAC_PM_DISCARD_VFIFO_FULL,
409 EFX_MAC_PM_TRUNC_QBB,
410 EFX_MAC_PM_DISCARD_QBB,
411 EFX_MAC_PM_DISCARD_MAPPING,
412 EFX_MAC_RXDP_Q_DISABLED_PKTS,
413 EFX_MAC_RXDP_DI_DROPPED_PKTS,
414 EFX_MAC_RXDP_STREAMING_PKTS,
415 EFX_MAC_RXDP_HLB_FETCH,
416 EFX_MAC_RXDP_HLB_WAIT,
417 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
418 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
419 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
420 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
421 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
422 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
423 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
424 EFX_MAC_VADAPTER_RX_BAD_BYTES,
425 EFX_MAC_VADAPTER_RX_OVERFLOW,
426 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
427 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
428 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
429 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
430 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
431 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
432 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
433 EFX_MAC_VADAPTER_TX_BAD_BYTES,
434 EFX_MAC_VADAPTER_TX_OVERFLOW,
435 EFX_MAC_FEC_UNCORRECTED_ERRORS,
436 EFX_MAC_FEC_CORRECTED_ERRORS,
437 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
438 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
439 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
440 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
441 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
442 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
443 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
444 EFX_MAC_CTPIO_OVERFLOW_FAIL,
445 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
446 EFX_MAC_CTPIO_TIMEOUT_FAIL,
447 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
448 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
449 EFX_MAC_CTPIO_INVALID_WR_FAIL,
450 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
451 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
452 EFX_MAC_CTPIO_RUNT_FALLBACK,
453 EFX_MAC_CTPIO_SUCCESS,
454 EFX_MAC_CTPIO_FALLBACK,
455 EFX_MAC_CTPIO_POISON,
457 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
458 EFX_MAC_RXDP_HLB_IDLE,
459 EFX_MAC_RXDP_HLB_TIMEOUT,
463 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
465 #endif /* EFSYS_OPT_MAC_STATS */
467 typedef enum efx_link_mode_e {
468 EFX_LINK_UNKNOWN = 0,
484 #define EFX_MAC_ADDR_LEN 6
486 #define EFX_VNI_OR_VSID_LEN 3
488 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
490 #define EFX_MAC_MULTICAST_LIST_MAX 256
492 #define EFX_MAC_SDU_MAX 9202
494 #define EFX_MAC_PDU_ADJUSTMENT \
498 + /* bug16011 */ 16) \
500 #define EFX_MAC_PDU(_sdu) \
501 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
504 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
505 * the SDU rounded up slightly.
507 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
509 #define EFX_MAC_PDU_MIN 60
510 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
512 extern __checkReturn efx_rc_t
517 extern __checkReturn efx_rc_t
522 extern __checkReturn efx_rc_t
527 extern __checkReturn efx_rc_t
530 __in boolean_t all_unicst,
531 __in boolean_t mulcst,
532 __in boolean_t all_mulcst,
533 __in boolean_t brdcst);
535 extern __checkReturn efx_rc_t
536 efx_mac_multicast_list_set(
538 __in_ecount(6*count) uint8_t const *addrs,
541 extern __checkReturn efx_rc_t
542 efx_mac_filter_default_rxq_set(
545 __in boolean_t using_rss);
548 efx_mac_filter_default_rxq_clear(
549 __in efx_nic_t *enp);
551 extern __checkReturn efx_rc_t
554 __in boolean_t enabled);
556 extern __checkReturn efx_rc_t
559 __out boolean_t *mac_upp);
561 #define EFX_FCNTL_RESPOND 0x00000001
562 #define EFX_FCNTL_GENERATE 0x00000002
564 extern __checkReturn efx_rc_t
567 __in unsigned int fcntl,
568 __in boolean_t autoneg);
573 __out unsigned int *fcntl_wantedp,
574 __out unsigned int *fcntl_linkp);
577 #if EFSYS_OPT_MAC_STATS
581 extern __checkReturn const char *
584 __in unsigned int id);
586 #endif /* EFSYS_OPT_NAMES */
588 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
590 #define EFX_MAC_STATS_MASK_NPAGES \
591 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
592 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
595 * Get mask of MAC statistics supported by the hardware.
597 * If mask_size is insufficient to return the mask, EINVAL error is
598 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
599 * (which is sizeof (uint32_t)) is sufficient.
601 extern __checkReturn efx_rc_t
602 efx_mac_stats_get_mask(
604 __out_bcount(mask_size) uint32_t *maskp,
605 __in size_t mask_size);
607 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
608 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
609 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
612 extern __checkReturn efx_rc_t
614 __in efx_nic_t *enp);
617 * Upload mac statistics supported by the hardware into the given buffer.
619 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
620 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
622 * The hardware will only DMA statistics that it understands (of course).
623 * Drivers should not make any assumptions about which statistics are
624 * supported, especially when the statistics are generated by firmware.
626 * Thus, drivers should zero this buffer before use, so that not-understood
627 * statistics read back as zero.
629 extern __checkReturn efx_rc_t
630 efx_mac_stats_upload(
632 __in efsys_mem_t *esmp);
634 extern __checkReturn efx_rc_t
635 efx_mac_stats_periodic(
637 __in efsys_mem_t *esmp,
638 __in uint16_t period_ms,
639 __in boolean_t events);
641 extern __checkReturn efx_rc_t
642 efx_mac_stats_update(
644 __in efsys_mem_t *esmp,
645 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
646 __inout_opt uint32_t *generationp);
648 #endif /* EFSYS_OPT_MAC_STATS */
652 typedef enum efx_mon_type_e {
664 __in efx_nic_t *enp);
666 #endif /* EFSYS_OPT_NAMES */
668 extern __checkReturn efx_rc_t
670 __in efx_nic_t *enp);
672 #if EFSYS_OPT_MON_STATS
674 #define EFX_MON_STATS_PAGE_SIZE 0x100
675 #define EFX_MON_MASK_ELEMENT_SIZE 32
677 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
678 typedef enum efx_mon_stat_e {
679 EFX_MON_STAT_CONTROLLER_TEMP,
680 EFX_MON_STAT_PHY_COMMON_TEMP,
681 EFX_MON_STAT_CONTROLLER_COOLING,
682 EFX_MON_STAT_PHY0_TEMP,
683 EFX_MON_STAT_PHY0_COOLING,
684 EFX_MON_STAT_PHY1_TEMP,
685 EFX_MON_STAT_PHY1_COOLING,
691 EFX_MON_STAT_IN_12V0,
692 EFX_MON_STAT_IN_1V2A,
693 EFX_MON_STAT_IN_VREF,
694 EFX_MON_STAT_OUT_VAOE,
695 EFX_MON_STAT_AOE_TEMP,
696 EFX_MON_STAT_PSU_AOE_TEMP,
697 EFX_MON_STAT_PSU_TEMP,
703 EFX_MON_STAT_IN_VAOE,
704 EFX_MON_STAT_OUT_IAOE,
705 EFX_MON_STAT_IN_IAOE,
706 EFX_MON_STAT_NIC_POWER,
708 EFX_MON_STAT_IN_I0V9,
709 EFX_MON_STAT_IN_I1V2,
710 EFX_MON_STAT_IN_0V9_ADC,
711 EFX_MON_STAT_CONTROLLER_2_TEMP,
712 EFX_MON_STAT_VREG_INTERNAL_TEMP,
713 EFX_MON_STAT_VREG_0V9_TEMP,
714 EFX_MON_STAT_VREG_1V2_TEMP,
715 EFX_MON_STAT_CONTROLLER_VPTAT,
716 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
717 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
718 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
719 EFX_MON_STAT_AMBIENT_TEMP,
720 EFX_MON_STAT_AIRFLOW,
721 EFX_MON_STAT_VDD08D_VSS08D_CSR,
722 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
723 EFX_MON_STAT_HOTPOINT_TEMP,
724 EFX_MON_STAT_PHY_POWER_PORT0,
725 EFX_MON_STAT_PHY_POWER_PORT1,
726 EFX_MON_STAT_MUM_VCC,
727 EFX_MON_STAT_IN_0V9_A,
728 EFX_MON_STAT_IN_I0V9_A,
729 EFX_MON_STAT_VREG_0V9_A_TEMP,
730 EFX_MON_STAT_IN_0V9_B,
731 EFX_MON_STAT_IN_I0V9_B,
732 EFX_MON_STAT_VREG_0V9_B_TEMP,
733 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
734 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
735 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
736 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
737 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
738 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
739 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
740 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
741 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
742 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
743 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
744 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
745 EFX_MON_STAT_SODIMM_VOUT,
746 EFX_MON_STAT_SODIMM_0_TEMP,
747 EFX_MON_STAT_SODIMM_1_TEMP,
748 EFX_MON_STAT_PHY0_VCC,
749 EFX_MON_STAT_PHY1_VCC,
750 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
751 EFX_MON_STAT_BOARD_FRONT_TEMP,
752 EFX_MON_STAT_BOARD_BACK_TEMP,
753 EFX_MON_STAT_IN_I1V8,
754 EFX_MON_STAT_IN_I2V5,
755 EFX_MON_STAT_IN_I3V3,
756 EFX_MON_STAT_IN_I12V0,
758 EFX_MON_STAT_IN_I1V3,
762 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
764 typedef enum efx_mon_stat_state_e {
765 EFX_MON_STAT_STATE_OK = 0,
766 EFX_MON_STAT_STATE_WARNING = 1,
767 EFX_MON_STAT_STATE_FATAL = 2,
768 EFX_MON_STAT_STATE_BROKEN = 3,
769 EFX_MON_STAT_STATE_NO_READING = 4,
770 } efx_mon_stat_state_t;
772 typedef enum efx_mon_stat_unit_e {
773 EFX_MON_STAT_UNIT_UNKNOWN = 0,
774 EFX_MON_STAT_UNIT_BOOL,
775 EFX_MON_STAT_UNIT_TEMP_C,
776 EFX_MON_STAT_UNIT_VOLTAGE_MV,
777 EFX_MON_STAT_UNIT_CURRENT_MA,
778 EFX_MON_STAT_UNIT_POWER_W,
779 EFX_MON_STAT_UNIT_RPM,
781 } efx_mon_stat_unit_t;
783 typedef struct efx_mon_stat_value_s {
785 efx_mon_stat_state_t emsv_state;
786 efx_mon_stat_unit_t emsv_unit;
787 } efx_mon_stat_value_t;
789 typedef struct efx_mon_limit_value_s {
790 uint16_t emlv_warning_min;
791 uint16_t emlv_warning_max;
792 uint16_t emlv_fatal_min;
793 uint16_t emlv_fatal_max;
794 } efx_mon_stat_limits_t;
796 typedef enum efx_mon_stat_portmask_e {
797 EFX_MON_STAT_PORTMAP_NONE = 0,
798 EFX_MON_STAT_PORTMAP_PORT0 = 1,
799 EFX_MON_STAT_PORTMAP_PORT1 = 2,
800 EFX_MON_STAT_PORTMAP_PORT2 = 3,
801 EFX_MON_STAT_PORTMAP_PORT3 = 4,
802 EFX_MON_STAT_PORTMAP_ALL = (-1),
803 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
804 } efx_mon_stat_portmask_t;
811 __in efx_mon_stat_t id);
814 efx_mon_stat_description(
816 __in efx_mon_stat_t id);
818 #endif /* EFSYS_OPT_NAMES */
820 extern __checkReturn boolean_t
821 efx_mon_mcdi_to_efx_stat(
823 __out efx_mon_stat_t *statp);
825 extern __checkReturn boolean_t
826 efx_mon_get_stat_unit(
827 __in efx_mon_stat_t stat,
828 __out efx_mon_stat_unit_t *unitp);
830 extern __checkReturn boolean_t
831 efx_mon_get_stat_portmap(
832 __in efx_mon_stat_t stat,
833 __out efx_mon_stat_portmask_t *maskp);
835 extern __checkReturn efx_rc_t
836 efx_mon_stats_update(
838 __in efsys_mem_t *esmp,
839 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
841 extern __checkReturn efx_rc_t
842 efx_mon_limits_update(
844 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
846 #endif /* EFSYS_OPT_MON_STATS */
850 __in efx_nic_t *enp);
854 extern __checkReturn efx_rc_t
856 __in efx_nic_t *enp);
858 #if EFSYS_OPT_PHY_LED_CONTROL
860 typedef enum efx_phy_led_mode_e {
861 EFX_PHY_LED_DEFAULT = 0,
866 } efx_phy_led_mode_t;
868 extern __checkReturn efx_rc_t
871 __in efx_phy_led_mode_t mode);
873 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
875 extern __checkReturn efx_rc_t
877 __in efx_nic_t *enp);
879 #if EFSYS_OPT_LOOPBACK
881 typedef enum efx_loopback_type_e {
882 EFX_LOOPBACK_OFF = 0,
883 EFX_LOOPBACK_DATA = 1,
884 EFX_LOOPBACK_GMAC = 2,
885 EFX_LOOPBACK_XGMII = 3,
886 EFX_LOOPBACK_XGXS = 4,
887 EFX_LOOPBACK_XAUI = 5,
888 EFX_LOOPBACK_GMII = 6,
889 EFX_LOOPBACK_SGMII = 7,
890 EFX_LOOPBACK_XGBR = 8,
891 EFX_LOOPBACK_XFI = 9,
892 EFX_LOOPBACK_XAUI_FAR = 10,
893 EFX_LOOPBACK_GMII_FAR = 11,
894 EFX_LOOPBACK_SGMII_FAR = 12,
895 EFX_LOOPBACK_XFI_FAR = 13,
896 EFX_LOOPBACK_GPHY = 14,
897 EFX_LOOPBACK_PHY_XS = 15,
898 EFX_LOOPBACK_PCS = 16,
899 EFX_LOOPBACK_PMA_PMD = 17,
900 EFX_LOOPBACK_XPORT = 18,
901 EFX_LOOPBACK_XGMII_WS = 19,
902 EFX_LOOPBACK_XAUI_WS = 20,
903 EFX_LOOPBACK_XAUI_WS_FAR = 21,
904 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
905 EFX_LOOPBACK_GMII_WS = 23,
906 EFX_LOOPBACK_XFI_WS = 24,
907 EFX_LOOPBACK_XFI_WS_FAR = 25,
908 EFX_LOOPBACK_PHYXS_WS = 26,
909 EFX_LOOPBACK_PMA_INT = 27,
910 EFX_LOOPBACK_SD_NEAR = 28,
911 EFX_LOOPBACK_SD_FAR = 29,
912 EFX_LOOPBACK_PMA_INT_WS = 30,
913 EFX_LOOPBACK_SD_FEP2_WS = 31,
914 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
915 EFX_LOOPBACK_SD_FEP_WS = 33,
916 EFX_LOOPBACK_SD_FES_WS = 34,
917 EFX_LOOPBACK_AOE_INT_NEAR = 35,
918 EFX_LOOPBACK_DATA_WS = 36,
919 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
921 } efx_loopback_type_t;
923 typedef enum efx_loopback_kind_e {
924 EFX_LOOPBACK_KIND_OFF = 0,
925 EFX_LOOPBACK_KIND_ALL,
926 EFX_LOOPBACK_KIND_MAC,
927 EFX_LOOPBACK_KIND_PHY,
929 } efx_loopback_kind_t;
933 __in efx_loopback_kind_t loopback_kind,
934 __out efx_qword_t *maskp);
936 extern __checkReturn efx_rc_t
937 efx_port_loopback_set(
939 __in efx_link_mode_t link_mode,
940 __in efx_loopback_type_t type);
944 extern __checkReturn const char *
945 efx_loopback_type_name(
947 __in efx_loopback_type_t type);
949 #endif /* EFSYS_OPT_NAMES */
951 #endif /* EFSYS_OPT_LOOPBACK */
953 extern __checkReturn efx_rc_t
956 __out_opt efx_link_mode_t *link_modep);
960 __in efx_nic_t *enp);
962 typedef enum efx_phy_cap_type_e {
963 EFX_PHY_CAP_INVALID = 0,
970 EFX_PHY_CAP_10000FDX,
974 EFX_PHY_CAP_40000FDX,
976 EFX_PHY_CAP_100000FDX,
977 EFX_PHY_CAP_25000FDX,
978 EFX_PHY_CAP_50000FDX,
979 EFX_PHY_CAP_BASER_FEC,
980 EFX_PHY_CAP_BASER_FEC_REQUESTED,
982 EFX_PHY_CAP_RS_FEC_REQUESTED,
983 EFX_PHY_CAP_25G_BASER_FEC,
984 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
986 } efx_phy_cap_type_t;
989 #define EFX_PHY_CAP_CURRENT 0x00000000
990 #define EFX_PHY_CAP_DEFAULT 0x00000001
991 #define EFX_PHY_CAP_PERM 0x00000002
997 __out uint32_t *maskp);
999 extern __checkReturn efx_rc_t
1000 efx_phy_adv_cap_set(
1001 __in efx_nic_t *enp,
1002 __in uint32_t mask);
1006 __in efx_nic_t *enp,
1007 __out uint32_t *maskp);
1009 extern __checkReturn efx_rc_t
1011 __in efx_nic_t *enp,
1012 __out uint32_t *ouip);
1014 typedef enum efx_phy_media_type_e {
1015 EFX_PHY_MEDIA_INVALID = 0,
1020 EFX_PHY_MEDIA_SFP_PLUS,
1021 EFX_PHY_MEDIA_BASE_T,
1022 EFX_PHY_MEDIA_QSFP_PLUS,
1023 EFX_PHY_MEDIA_NTYPES
1024 } efx_phy_media_type_t;
1027 * Get the type of medium currently used. If the board has ports for
1028 * modules, a module is present, and we recognise the media type of
1029 * the module, then this will be the media type of the module.
1030 * Otherwise it will be the media type of the port.
1033 efx_phy_media_type_get(
1034 __in efx_nic_t *enp,
1035 __out efx_phy_media_type_t *typep);
1038 * 2-wire device address of the base information in accordance with SFF-8472
1039 * Diagnostic Monitoring Interface for Optical Transceivers section
1040 * 4 Memory Organization.
1042 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1045 * 2-wire device address of the digital diagnostics monitoring interface
1046 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1047 * Transceivers section 4 Memory Organization.
1049 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1052 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1053 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1056 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1059 * Maximum accessible data offset for PHY module information.
1061 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1064 extern __checkReturn efx_rc_t
1065 efx_phy_module_get_info(
1066 __in efx_nic_t *enp,
1067 __in uint8_t dev_addr,
1070 __out_bcount(len) uint8_t *data);
1072 #if EFSYS_OPT_PHY_STATS
1074 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1075 typedef enum efx_phy_stat_e {
1077 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1078 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1079 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1080 EFX_PHY_STAT_PMA_PMD_REV_A,
1081 EFX_PHY_STAT_PMA_PMD_REV_B,
1082 EFX_PHY_STAT_PMA_PMD_REV_C,
1083 EFX_PHY_STAT_PMA_PMD_REV_D,
1084 EFX_PHY_STAT_PCS_LINK_UP,
1085 EFX_PHY_STAT_PCS_RX_FAULT,
1086 EFX_PHY_STAT_PCS_TX_FAULT,
1087 EFX_PHY_STAT_PCS_BER,
1088 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1089 EFX_PHY_STAT_PHY_XS_LINK_UP,
1090 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1091 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1092 EFX_PHY_STAT_PHY_XS_ALIGN,
1093 EFX_PHY_STAT_PHY_XS_SYNC_A,
1094 EFX_PHY_STAT_PHY_XS_SYNC_B,
1095 EFX_PHY_STAT_PHY_XS_SYNC_C,
1096 EFX_PHY_STAT_PHY_XS_SYNC_D,
1097 EFX_PHY_STAT_AN_LINK_UP,
1098 EFX_PHY_STAT_AN_MASTER,
1099 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1100 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1101 EFX_PHY_STAT_CL22EXT_LINK_UP,
1106 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1107 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1108 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1109 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1110 EFX_PHY_STAT_AN_COMPLETE,
1111 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1112 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1113 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1114 EFX_PHY_STAT_PCS_FW_VERSION_0,
1115 EFX_PHY_STAT_PCS_FW_VERSION_1,
1116 EFX_PHY_STAT_PCS_FW_VERSION_2,
1117 EFX_PHY_STAT_PCS_FW_VERSION_3,
1118 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1119 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1120 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1121 EFX_PHY_STAT_PCS_OP_MODE,
1125 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1131 __in efx_nic_t *enp,
1132 __in efx_phy_stat_t stat);
1134 #endif /* EFSYS_OPT_NAMES */
1136 #define EFX_PHY_STATS_SIZE 0x100
1138 extern __checkReturn efx_rc_t
1139 efx_phy_stats_update(
1140 __in efx_nic_t *enp,
1141 __in efsys_mem_t *esmp,
1142 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1144 #endif /* EFSYS_OPT_PHY_STATS */
1149 typedef enum efx_bist_type_e {
1150 EFX_BIST_TYPE_UNKNOWN,
1151 EFX_BIST_TYPE_PHY_NORMAL,
1152 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1153 EFX_BIST_TYPE_PHY_CABLE_LONG,
1154 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1155 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1156 EFX_BIST_TYPE_REG, /* Test the register memories */
1157 EFX_BIST_TYPE_NTYPES,
1160 typedef enum efx_bist_result_e {
1161 EFX_BIST_RESULT_UNKNOWN,
1162 EFX_BIST_RESULT_RUNNING,
1163 EFX_BIST_RESULT_PASSED,
1164 EFX_BIST_RESULT_FAILED,
1165 } efx_bist_result_t;
1167 typedef enum efx_phy_cable_status_e {
1168 EFX_PHY_CABLE_STATUS_OK,
1169 EFX_PHY_CABLE_STATUS_INVALID,
1170 EFX_PHY_CABLE_STATUS_OPEN,
1171 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1172 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1173 EFX_PHY_CABLE_STATUS_BUSY,
1174 } efx_phy_cable_status_t;
1176 typedef enum efx_bist_value_e {
1177 EFX_BIST_PHY_CABLE_LENGTH_A,
1178 EFX_BIST_PHY_CABLE_LENGTH_B,
1179 EFX_BIST_PHY_CABLE_LENGTH_C,
1180 EFX_BIST_PHY_CABLE_LENGTH_D,
1181 EFX_BIST_PHY_CABLE_STATUS_A,
1182 EFX_BIST_PHY_CABLE_STATUS_B,
1183 EFX_BIST_PHY_CABLE_STATUS_C,
1184 EFX_BIST_PHY_CABLE_STATUS_D,
1185 EFX_BIST_FAULT_CODE,
1187 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1193 EFX_BIST_MEM_EXPECT,
1194 EFX_BIST_MEM_ACTUAL,
1196 EFX_BIST_MEM_ECC_PARITY,
1197 EFX_BIST_MEM_ECC_FATAL,
1201 extern __checkReturn efx_rc_t
1202 efx_bist_enable_offline(
1203 __in efx_nic_t *enp);
1205 extern __checkReturn efx_rc_t
1207 __in efx_nic_t *enp,
1208 __in efx_bist_type_t type);
1210 extern __checkReturn efx_rc_t
1212 __in efx_nic_t *enp,
1213 __in efx_bist_type_t type,
1214 __out efx_bist_result_t *resultp,
1215 __out_opt uint32_t *value_maskp,
1216 __out_ecount_opt(count) unsigned long *valuesp,
1221 __in efx_nic_t *enp,
1222 __in efx_bist_type_t type);
1224 #endif /* EFSYS_OPT_BIST */
1226 #define EFX_FEATURE_IPV6 0x00000001
1227 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1228 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1229 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1230 #define EFX_FEATURE_MCDI 0x00000020
1231 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1232 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1233 #define EFX_FEATURE_TURBO 0x00000100
1234 #define EFX_FEATURE_MCDI_DMA 0x00000200
1235 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1236 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1237 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1238 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1239 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1240 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1242 typedef enum efx_tunnel_protocol_e {
1243 EFX_TUNNEL_PROTOCOL_NONE = 0,
1244 EFX_TUNNEL_PROTOCOL_VXLAN,
1245 EFX_TUNNEL_PROTOCOL_GENEVE,
1246 EFX_TUNNEL_PROTOCOL_NVGRE,
1248 } efx_tunnel_protocol_t;
1250 typedef enum efx_vi_window_shift_e {
1251 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1252 EFX_VI_WINDOW_SHIFT_8K = 13,
1253 EFX_VI_WINDOW_SHIFT_16K = 14,
1254 EFX_VI_WINDOW_SHIFT_64K = 16,
1255 } efx_vi_window_shift_t;
1257 typedef struct efx_nic_cfg_s {
1258 uint32_t enc_board_type;
1259 uint32_t enc_phy_type;
1261 char enc_phy_name[21];
1263 char enc_phy_revision[21];
1264 efx_mon_type_t enc_mon_type;
1265 #if EFSYS_OPT_MON_STATS
1266 uint32_t enc_mon_stat_dma_buf_size;
1267 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1269 unsigned int enc_features;
1270 efx_vi_window_shift_t enc_vi_window_shift;
1271 uint8_t enc_mac_addr[6];
1272 uint8_t enc_port; /* PHY port number */
1273 uint32_t enc_intr_vec_base;
1274 uint32_t enc_intr_limit;
1275 uint32_t enc_evq_limit;
1276 uint32_t enc_txq_limit;
1277 uint32_t enc_rxq_limit;
1278 uint32_t enc_evq_max_nevs;
1279 uint32_t enc_evq_min_nevs;
1280 uint32_t enc_rxq_max_ndescs;
1281 uint32_t enc_rxq_min_ndescs;
1282 uint32_t enc_txq_max_ndescs;
1283 uint32_t enc_txq_min_ndescs;
1284 uint32_t enc_buftbl_limit;
1285 uint32_t enc_piobuf_limit;
1286 uint32_t enc_piobuf_size;
1287 uint32_t enc_piobuf_min_alloc_size;
1288 uint32_t enc_evq_timer_quantum_ns;
1289 uint32_t enc_evq_timer_max_us;
1290 uint32_t enc_clk_mult;
1291 uint32_t enc_ev_desc_size;
1292 uint32_t enc_rx_desc_size;
1293 uint32_t enc_tx_desc_size;
1294 uint32_t enc_rx_prefix_size;
1295 uint32_t enc_rx_buf_align_start;
1296 uint32_t enc_rx_buf_align_end;
1297 #if EFSYS_OPT_RX_SCALE
1298 uint32_t enc_rx_scale_max_exclusive_contexts;
1300 * Mask of supported hash algorithms.
1301 * Hash algorithm types are used as the bit indices.
1303 uint32_t enc_rx_scale_hash_alg_mask;
1305 * Indicates whether port numbers can be included to the
1306 * input data for hash computation.
1308 boolean_t enc_rx_scale_l4_hash_supported;
1309 boolean_t enc_rx_scale_additional_modes_supported;
1310 #endif /* EFSYS_OPT_RX_SCALE */
1311 #if EFSYS_OPT_LOOPBACK
1312 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1313 #endif /* EFSYS_OPT_LOOPBACK */
1314 #if EFSYS_OPT_PHY_FLAGS
1315 uint32_t enc_phy_flags_mask;
1316 #endif /* EFSYS_OPT_PHY_FLAGS */
1317 #if EFSYS_OPT_PHY_LED_CONTROL
1318 uint32_t enc_led_mask;
1319 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1320 #if EFSYS_OPT_PHY_STATS
1321 uint64_t enc_phy_stat_mask;
1322 #endif /* EFSYS_OPT_PHY_STATS */
1324 uint8_t enc_mcdi_mdio_channel;
1325 #if EFSYS_OPT_PHY_STATS
1326 uint32_t enc_mcdi_phy_stat_mask;
1327 #endif /* EFSYS_OPT_PHY_STATS */
1328 #if EFSYS_OPT_MON_STATS
1329 uint32_t *enc_mcdi_sensor_maskp;
1330 uint32_t enc_mcdi_sensor_mask_size;
1331 #endif /* EFSYS_OPT_MON_STATS */
1332 #endif /* EFSYS_OPT_MCDI */
1334 uint32_t enc_bist_mask;
1335 #endif /* EFSYS_OPT_BIST */
1339 uint32_t enc_privilege_mask;
1340 #endif /* EFX_OPTS_EF10() */
1341 boolean_t enc_bug26807_workaround;
1342 boolean_t enc_bug35388_workaround;
1343 boolean_t enc_bug41750_workaround;
1344 boolean_t enc_bug61265_workaround;
1345 boolean_t enc_bug61297_workaround;
1346 boolean_t enc_rx_batching_enabled;
1347 /* Maximum number of descriptors completed in an rx event. */
1348 uint32_t enc_rx_batch_max;
1349 /* Number of rx descriptors the hardware requires for a push. */
1350 uint32_t enc_rx_push_align;
1351 /* Maximum amount of data in DMA descriptor */
1352 uint32_t enc_tx_dma_desc_size_max;
1354 * Boundary which DMA descriptor data must not cross or 0 if no
1357 uint32_t enc_tx_dma_desc_boundary;
1359 * Maximum number of bytes into the packet the TCP header can start for
1360 * the hardware to apply TSO packet edits.
1362 uint32_t enc_tx_tso_tcp_header_offset_limit;
1363 boolean_t enc_fw_assisted_tso_enabled;
1364 boolean_t enc_fw_assisted_tso_v2_enabled;
1365 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1366 /* Number of TSO contexts on the NIC (FATSOv2) */
1367 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1368 boolean_t enc_hw_tx_insert_vlan_enabled;
1369 /* Number of PFs on the NIC */
1370 uint32_t enc_hw_pf_count;
1371 /* Datapath firmware vadapter/vport/vswitch support */
1372 boolean_t enc_datapath_cap_evb;
1373 /* Datapath firmware vport reconfigure support */
1374 boolean_t enc_vport_reconfigure_supported;
1375 boolean_t enc_rx_disable_scatter_supported;
1376 boolean_t enc_allow_set_mac_with_installed_filters;
1377 boolean_t enc_enhanced_set_mac_supported;
1378 boolean_t enc_init_evq_v2_supported;
1379 boolean_t enc_no_cont_ev_mode_supported;
1380 boolean_t enc_init_rxq_with_buffer_size;
1381 boolean_t enc_rx_packed_stream_supported;
1382 boolean_t enc_rx_var_packed_stream_supported;
1383 boolean_t enc_rx_es_super_buffer_supported;
1384 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1385 boolean_t enc_pm_and_rxdp_counters;
1386 boolean_t enc_mac_stats_40g_tx_size_bins;
1387 uint32_t enc_tunnel_encapsulations_supported;
1389 * NIC global maximum for unique UDP tunnel ports shared by all
1392 uint32_t enc_tunnel_config_udp_entries_max;
1393 /* External port identifier */
1394 uint8_t enc_external_port;
1395 uint32_t enc_mcdi_max_payload_length;
1396 /* VPD may be per-PF or global */
1397 boolean_t enc_vpd_is_global;
1398 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1399 uint32_t enc_required_pcie_bandwidth_mbps;
1400 uint32_t enc_max_pcie_link_gen;
1401 /* Firmware verifies integrity of NVRAM updates */
1402 boolean_t enc_nvram_update_verify_result_supported;
1403 /* Firmware supports polled NVRAM updates on select partitions */
1404 boolean_t enc_nvram_update_poll_verify_result_supported;
1405 /* Firmware accepts updates via the BUNDLE partition */
1406 boolean_t enc_nvram_bundle_update_supported;
1407 /* Firmware support for extended MAC_STATS buffer */
1408 uint32_t enc_mac_stats_nstats;
1409 boolean_t enc_fec_counters;
1410 boolean_t enc_hlb_counters;
1411 /* Firmware support for "FLAG" and "MARK" filter actions */
1412 boolean_t enc_filter_action_flag_supported;
1413 boolean_t enc_filter_action_mark_supported;
1414 uint32_t enc_filter_action_mark_max;
1415 /* Port assigned to this PCI function */
1416 uint32_t enc_assigned_port;
1419 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1420 ((configp)->evc_function == 0xffff)
1422 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1423 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1425 #define EFX_PCI_FUNCTION(_encp) \
1426 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1428 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1430 extern const efx_nic_cfg_t *
1432 __in const efx_nic_t *enp);
1434 /* RxDPCPU firmware id values by which FW variant can be identified */
1435 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1436 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1437 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1438 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1439 #define EFX_RXDP_DPDK_FW_ID 0x6
1441 typedef struct efx_nic_fw_info_s {
1442 /* Basic FW version information */
1443 uint16_t enfi_mc_fw_version[4];
1445 * If datapath capabilities can be detected,
1446 * additional FW information is to be shown
1448 boolean_t enfi_dpcpu_fw_ids_valid;
1449 /* Rx and Tx datapath CPU FW IDs */
1450 uint16_t enfi_rx_dpcpu_fw_id;
1451 uint16_t enfi_tx_dpcpu_fw_id;
1452 } efx_nic_fw_info_t;
1454 extern __checkReturn efx_rc_t
1455 efx_nic_get_fw_version(
1456 __in efx_nic_t *enp,
1457 __out efx_nic_fw_info_t *enfip);
1459 /* Driver resource limits (minimum required/maximum usable). */
1460 typedef struct efx_drv_limits_s {
1461 uint32_t edl_min_evq_count;
1462 uint32_t edl_max_evq_count;
1464 uint32_t edl_min_rxq_count;
1465 uint32_t edl_max_rxq_count;
1467 uint32_t edl_min_txq_count;
1468 uint32_t edl_max_txq_count;
1470 /* PIO blocks (sub-allocated from piobuf) */
1471 uint32_t edl_min_pio_alloc_size;
1472 uint32_t edl_max_pio_alloc_count;
1475 extern __checkReturn efx_rc_t
1476 efx_nic_set_drv_limits(
1477 __inout efx_nic_t *enp,
1478 __in efx_drv_limits_t *edlp);
1481 * Register the OS driver version string for management agents
1482 * (e.g. via NC-SI). The content length is provided (i.e. no
1483 * NUL terminator). Use length 0 to indicate no version string
1484 * should be advertised. It is valid to set the version string
1485 * only before efx_nic_probe() is called.
1487 extern __checkReturn efx_rc_t
1488 efx_nic_set_drv_version(
1489 __inout efx_nic_t *enp,
1490 __in_ecount(length) char const *verp,
1491 __in size_t length);
1493 typedef enum efx_nic_region_e {
1494 EFX_REGION_VI, /* Memory BAR UC mapping */
1495 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1498 extern __checkReturn efx_rc_t
1499 efx_nic_get_bar_region(
1500 __in efx_nic_t *enp,
1501 __in efx_nic_region_t region,
1502 __out uint32_t *offsetp,
1503 __out size_t *sizep);
1505 extern __checkReturn efx_rc_t
1506 efx_nic_get_vi_pool(
1507 __in efx_nic_t *enp,
1508 __out uint32_t *evq_countp,
1509 __out uint32_t *rxq_countp,
1510 __out uint32_t *txq_countp);
1515 typedef enum efx_vpd_tag_e {
1522 typedef uint16_t efx_vpd_keyword_t;
1524 typedef struct efx_vpd_value_s {
1525 efx_vpd_tag_t evv_tag;
1526 efx_vpd_keyword_t evv_keyword;
1528 uint8_t evv_value[0x100];
1532 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1534 extern __checkReturn efx_rc_t
1536 __in efx_nic_t *enp);
1538 extern __checkReturn efx_rc_t
1540 __in efx_nic_t *enp,
1541 __out size_t *sizep);
1543 extern __checkReturn efx_rc_t
1545 __in efx_nic_t *enp,
1546 __out_bcount(size) caddr_t data,
1549 extern __checkReturn efx_rc_t
1551 __in efx_nic_t *enp,
1552 __in_bcount(size) caddr_t data,
1555 extern __checkReturn efx_rc_t
1557 __in efx_nic_t *enp,
1558 __in_bcount(size) caddr_t data,
1561 extern __checkReturn efx_rc_t
1563 __in efx_nic_t *enp,
1564 __in_bcount(size) caddr_t data,
1566 __inout efx_vpd_value_t *evvp);
1568 extern __checkReturn efx_rc_t
1570 __in efx_nic_t *enp,
1571 __inout_bcount(size) caddr_t data,
1573 __in efx_vpd_value_t *evvp);
1575 extern __checkReturn efx_rc_t
1577 __in efx_nic_t *enp,
1578 __inout_bcount(size) caddr_t data,
1580 __out efx_vpd_value_t *evvp,
1581 __inout unsigned int *contp);
1583 extern __checkReturn efx_rc_t
1585 __in efx_nic_t *enp,
1586 __in_bcount(size) caddr_t data,
1591 __in efx_nic_t *enp);
1593 #endif /* EFSYS_OPT_VPD */
1599 typedef enum efx_nvram_type_e {
1600 EFX_NVRAM_INVALID = 0,
1602 EFX_NVRAM_BOOTROM_CFG,
1603 EFX_NVRAM_MC_FIRMWARE,
1604 EFX_NVRAM_MC_GOLDEN,
1610 EFX_NVRAM_FPGA_BACKUP,
1611 EFX_NVRAM_DYNAMIC_CFG,
1614 EFX_NVRAM_MUM_FIRMWARE,
1615 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1616 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1618 EFX_NVRAM_BUNDLE_METADATA,
1622 typedef struct efx_nvram_info_s {
1624 uint32_t eni_partn_size;
1625 uint32_t eni_address;
1626 uint32_t eni_erase_size;
1627 uint32_t eni_write_size;
1630 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1632 extern __checkReturn efx_rc_t
1634 __in efx_nic_t *enp);
1638 extern __checkReturn efx_rc_t
1640 __in efx_nic_t *enp);
1642 #endif /* EFSYS_OPT_DIAG */
1644 extern __checkReturn efx_rc_t
1646 __in efx_nic_t *enp,
1647 __in efx_nvram_type_t type,
1648 __out size_t *sizep);
1650 extern __checkReturn efx_rc_t
1652 __in efx_nic_t *enp,
1653 __in efx_nvram_type_t type,
1654 __out efx_nvram_info_t *enip);
1656 extern __checkReturn efx_rc_t
1658 __in efx_nic_t *enp,
1659 __in efx_nvram_type_t type,
1660 __out_opt size_t *pref_chunkp);
1662 extern __checkReturn efx_rc_t
1663 efx_nvram_rw_finish(
1664 __in efx_nic_t *enp,
1665 __in efx_nvram_type_t type,
1666 __out_opt uint32_t *verify_resultp);
1668 extern __checkReturn efx_rc_t
1669 efx_nvram_get_version(
1670 __in efx_nic_t *enp,
1671 __in efx_nvram_type_t type,
1672 __out uint32_t *subtypep,
1673 __out_ecount(4) uint16_t version[4]);
1675 extern __checkReturn efx_rc_t
1676 efx_nvram_read_chunk(
1677 __in efx_nic_t *enp,
1678 __in efx_nvram_type_t type,
1679 __in unsigned int offset,
1680 __out_bcount(size) caddr_t data,
1683 extern __checkReturn efx_rc_t
1684 efx_nvram_read_backup(
1685 __in efx_nic_t *enp,
1686 __in efx_nvram_type_t type,
1687 __in unsigned int offset,
1688 __out_bcount(size) caddr_t data,
1691 extern __checkReturn efx_rc_t
1692 efx_nvram_set_version(
1693 __in efx_nic_t *enp,
1694 __in efx_nvram_type_t type,
1695 __in_ecount(4) uint16_t version[4]);
1697 extern __checkReturn efx_rc_t
1699 __in efx_nic_t *enp,
1700 __in efx_nvram_type_t type,
1701 __in_bcount(partn_size) caddr_t partn_data,
1702 __in size_t partn_size);
1704 extern __checkReturn efx_rc_t
1706 __in efx_nic_t *enp,
1707 __in efx_nvram_type_t type);
1709 extern __checkReturn efx_rc_t
1710 efx_nvram_write_chunk(
1711 __in efx_nic_t *enp,
1712 __in efx_nvram_type_t type,
1713 __in unsigned int offset,
1714 __in_bcount(size) caddr_t data,
1719 __in efx_nic_t *enp);
1721 #endif /* EFSYS_OPT_NVRAM */
1723 #if EFSYS_OPT_BOOTCFG
1725 /* Report size and offset of bootcfg sector in NVRAM partition. */
1726 extern __checkReturn efx_rc_t
1727 efx_bootcfg_sector_info(
1728 __in efx_nic_t *enp,
1730 __out_opt uint32_t *sector_countp,
1731 __out size_t *offsetp,
1732 __out size_t *max_sizep);
1735 * Copy bootcfg sector data to a target buffer which may differ in size.
1736 * Optionally corrects format errors in source buffer.
1739 efx_bootcfg_copy_sector(
1740 __in efx_nic_t *enp,
1741 __inout_bcount(sector_length)
1743 __in size_t sector_length,
1744 __out_bcount(data_size) uint8_t *data,
1745 __in size_t data_size,
1746 __in boolean_t handle_format_errors);
1750 __in efx_nic_t *enp,
1751 __out_bcount(size) uint8_t *data,
1756 __in efx_nic_t *enp,
1757 __in_bcount(size) uint8_t *data,
1762 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1763 * (see https://tools.ietf.org/html/rfc1533)
1765 * Summarising the format: the buffer is a sequence of options. All options
1766 * begin with a tag octet, which uniquely identifies the option. Fixed-
1767 * length options without data consist of only a tag octet. Only options PAD
1768 * (0) and END (255) are fixed length. All other options are variable-length
1769 * with a length octet following the tag octet. The value of the length
1770 * octet does not include the two octets specifying the tag and length. The
1771 * length octet is followed by "length" octets of data.
1773 * Option data may be a sequence of sub-options in the same format. The data
1774 * content of the encapsulating option is one or more encapsulated sub-options,
1775 * with no terminating END tag is required.
1777 * To be valid, the top-level sequence of options should be terminated by an
1778 * END tag. The buffer should be padded with the PAD byte.
1780 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1781 * checksum octet. The full buffer (including after the END tag) contributes
1782 * to the checksum, hence the need to fill the buffer to the end with PAD.
1785 #define EFX_DHCP_END ((uint8_t)0xff)
1786 #define EFX_DHCP_PAD ((uint8_t)0)
1788 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1789 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1791 extern __checkReturn uint8_t
1793 __in_bcount(size) uint8_t const *data,
1796 extern __checkReturn efx_rc_t
1798 __in_bcount(size) uint8_t const *data,
1800 __out_opt size_t *usedp);
1802 extern __checkReturn efx_rc_t
1804 __in_bcount(buffer_length) uint8_t *bufferp,
1805 __in size_t buffer_length,
1807 __deref_out uint8_t **valuepp,
1808 __out size_t *value_lengthp);
1810 extern __checkReturn efx_rc_t
1812 __in_bcount(buffer_length) uint8_t *bufferp,
1813 __in size_t buffer_length,
1814 __deref_out uint8_t **endpp);
1817 extern __checkReturn efx_rc_t
1818 efx_dhcp_delete_tag(
1819 __inout_bcount(buffer_length) uint8_t *bufferp,
1820 __in size_t buffer_length,
1823 extern __checkReturn efx_rc_t
1825 __inout_bcount(buffer_length) uint8_t *bufferp,
1826 __in size_t buffer_length,
1828 __in_bcount_opt(value_length) uint8_t *valuep,
1829 __in size_t value_length);
1831 extern __checkReturn efx_rc_t
1832 efx_dhcp_update_tag(
1833 __inout_bcount(buffer_length) uint8_t *bufferp,
1834 __in size_t buffer_length,
1836 __in uint8_t *value_locationp,
1837 __in_bcount_opt(value_length) uint8_t *valuep,
1838 __in size_t value_length);
1841 #endif /* EFSYS_OPT_BOOTCFG */
1843 #if EFSYS_OPT_IMAGE_LAYOUT
1845 #include "ef10_signed_image_layout.h"
1848 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1851 * The image header format is extensible. However, older drivers require an
1852 * exact match of image header version and header length when validating and
1853 * writing firmware images.
1855 * To avoid breaking backward compatibility, we use the upper bits of the
1856 * controller version fields to contain an extra version number used for
1857 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1858 * version). See bug39254 and SF-102785-PS for details.
1860 typedef struct efx_image_header_s {
1862 uint32_t eih_version;
1864 uint32_t eih_subtype;
1865 uint32_t eih_code_size;
1868 uint32_t eih_controller_version_min;
1870 uint16_t eih_controller_version_min_short;
1871 uint8_t eih_extra_version_a;
1872 uint8_t eih_extra_version_b;
1876 uint32_t eih_controller_version_max;
1878 uint16_t eih_controller_version_max_short;
1879 uint8_t eih_extra_version_c;
1880 uint8_t eih_extra_version_d;
1883 uint16_t eih_code_version_a;
1884 uint16_t eih_code_version_b;
1885 uint16_t eih_code_version_c;
1886 uint16_t eih_code_version_d;
1887 } efx_image_header_t;
1889 #define EFX_IMAGE_HEADER_SIZE (40)
1890 #define EFX_IMAGE_HEADER_VERSION (4)
1891 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1894 typedef struct efx_image_trailer_s {
1896 } efx_image_trailer_t;
1898 #define EFX_IMAGE_TRAILER_SIZE (4)
1900 typedef enum efx_image_format_e {
1901 EFX_IMAGE_FORMAT_NO_IMAGE,
1902 EFX_IMAGE_FORMAT_INVALID,
1903 EFX_IMAGE_FORMAT_UNSIGNED,
1904 EFX_IMAGE_FORMAT_SIGNED,
1905 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
1906 } efx_image_format_t;
1908 typedef struct efx_image_info_s {
1909 efx_image_format_t eii_format;
1910 uint8_t * eii_imagep;
1911 size_t eii_image_size;
1912 efx_image_header_t * eii_headerp;
1915 extern __checkReturn efx_rc_t
1916 efx_check_reflash_image(
1918 __in uint32_t buffer_size,
1919 __out efx_image_info_t *infop);
1921 extern __checkReturn efx_rc_t
1922 efx_build_signed_image_write_buffer(
1923 __out_bcount(buffer_size)
1925 __in uint32_t buffer_size,
1926 __in efx_image_info_t *infop,
1927 __out efx_image_header_t **headerpp);
1929 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1933 typedef enum efx_pattern_type_t {
1934 EFX_PATTERN_BYTE_INCREMENT = 0,
1935 EFX_PATTERN_ALL_THE_SAME,
1936 EFX_PATTERN_BIT_ALTERNATE,
1937 EFX_PATTERN_BYTE_ALTERNATE,
1938 EFX_PATTERN_BYTE_CHANGING,
1939 EFX_PATTERN_BIT_SWEEP,
1941 } efx_pattern_type_t;
1944 (*efx_sram_pattern_fn_t)(
1946 __in boolean_t negate,
1947 __out efx_qword_t *eqp);
1949 extern __checkReturn efx_rc_t
1951 __in efx_nic_t *enp,
1952 __in efx_pattern_type_t type);
1954 #endif /* EFSYS_OPT_DIAG */
1956 extern __checkReturn efx_rc_t
1957 efx_sram_buf_tbl_set(
1958 __in efx_nic_t *enp,
1960 __in efsys_mem_t *esmp,
1964 efx_sram_buf_tbl_clear(
1965 __in efx_nic_t *enp,
1969 #define EFX_BUF_TBL_SIZE 0x20000
1971 #define EFX_BUF_SIZE 4096
1975 typedef struct efx_evq_s efx_evq_t;
1977 #if EFSYS_OPT_QSTATS
1979 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
1980 typedef enum efx_ev_qstat_e {
1986 EV_RX_PAUSE_FRM_ERR,
1987 EV_RX_BUF_OWNER_ID_ERR,
1988 EV_RX_IPV4_HDR_CHKSUM_ERR,
1989 EV_RX_TCP_UDP_CHKSUM_ERR,
1993 EV_RX_MCAST_HASH_MATCH,
2010 EV_DRIVER_SRM_UPD_DONE,
2011 EV_DRIVER_TX_DESCQ_FLS_DONE,
2012 EV_DRIVER_RX_DESCQ_FLS_DONE,
2013 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2014 EV_DRIVER_RX_DSC_ERROR,
2015 EV_DRIVER_TX_DSC_ERROR,
2018 EV_RX_PARSE_INCOMPLETE,
2022 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2024 #endif /* EFSYS_OPT_QSTATS */
2026 extern __checkReturn efx_rc_t
2028 __in efx_nic_t *enp);
2032 __in efx_nic_t *enp);
2034 extern __checkReturn size_t
2036 __in const efx_nic_t *enp,
2037 __in unsigned int ndescs);
2039 extern __checkReturn unsigned int
2041 __in const efx_nic_t *enp,
2042 __in unsigned int ndescs);
2044 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2045 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2046 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2047 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2049 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2050 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2051 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2054 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2055 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2058 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2059 * which is the case when an event queue is set to THROUGHPUT mode.
2061 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2063 extern __checkReturn efx_rc_t
2065 __in efx_nic_t *enp,
2066 __in unsigned int index,
2067 __in efsys_mem_t *esmp,
2071 __in uint32_t flags,
2072 __deref_out efx_evq_t **eepp);
2076 __in efx_evq_t *eep,
2077 __in uint16_t data);
2079 typedef __checkReturn boolean_t
2080 (*efx_initialized_ev_t)(
2081 __in_opt void *arg);
2083 #define EFX_PKT_UNICAST 0x0004
2084 #define EFX_PKT_START 0x0008
2086 #define EFX_PKT_VLAN_TAGGED 0x0010
2087 #define EFX_CKSUM_TCPUDP 0x0020
2088 #define EFX_CKSUM_IPV4 0x0040
2089 #define EFX_PKT_CONT 0x0080
2091 #define EFX_CHECK_VLAN 0x0100
2092 #define EFX_PKT_TCP 0x0200
2093 #define EFX_PKT_UDP 0x0400
2094 #define EFX_PKT_IPV4 0x0800
2096 #define EFX_PKT_IPV6 0x1000
2097 #define EFX_PKT_PREFIX_LEN 0x2000
2098 #define EFX_ADDR_MISMATCH 0x4000
2099 #define EFX_DISCARD 0x8000
2102 * The following flags are used only for packed stream
2103 * mode. The values for the flags are reused to fit into 16 bit,
2104 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2105 * packed stream mode
2107 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2108 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2111 #define EFX_EV_RX_NLABELS 32
2112 #define EFX_EV_TX_NLABELS 32
2114 typedef __checkReturn boolean_t
2117 __in uint32_t label,
2120 __in uint16_t flags);
2122 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2125 * Packed stream mode is documented in SF-112241-TC.
2126 * The general idea is that, instead of putting each incoming
2127 * packet into a separate buffer which is specified in a RX
2128 * descriptor, a large buffer is provided to the hardware and
2129 * packets are put there in a continuous stream.
2130 * The main advantage of such an approach is that RX queue refilling
2131 * happens much less frequently.
2133 * Equal stride packed stream mode is documented in SF-119419-TC.
2134 * The general idea is to utilize advantages of the packed stream,
2135 * but avoid indirection in packets representation.
2136 * The main advantage of such an approach is that RX queue refilling
2137 * happens much less frequently and packets buffers are independent
2138 * from upper layers point of view.
2141 typedef __checkReturn boolean_t
2144 __in uint32_t label,
2146 __in uint32_t pkt_count,
2147 __in uint16_t flags);
2151 typedef __checkReturn boolean_t
2154 __in uint32_t label,
2157 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2158 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2159 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2160 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2161 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2162 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2163 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2164 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2165 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2167 typedef __checkReturn boolean_t
2168 (*efx_exception_ev_t)(
2170 __in uint32_t label,
2171 __in uint32_t data);
2173 typedef __checkReturn boolean_t
2174 (*efx_rxq_flush_done_ev_t)(
2176 __in uint32_t rxq_index);
2178 typedef __checkReturn boolean_t
2179 (*efx_rxq_flush_failed_ev_t)(
2181 __in uint32_t rxq_index);
2183 typedef __checkReturn boolean_t
2184 (*efx_txq_flush_done_ev_t)(
2186 __in uint32_t txq_index);
2188 typedef __checkReturn boolean_t
2189 (*efx_software_ev_t)(
2191 __in uint16_t magic);
2193 typedef __checkReturn boolean_t
2196 __in uint32_t code);
2198 #define EFX_SRAM_CLEAR 0
2199 #define EFX_SRAM_UPDATE 1
2200 #define EFX_SRAM_ILLEGAL_CLEAR 2
2202 typedef __checkReturn boolean_t
2203 (*efx_wake_up_ev_t)(
2205 __in uint32_t label);
2207 typedef __checkReturn boolean_t
2210 __in uint32_t label);
2212 typedef __checkReturn boolean_t
2213 (*efx_link_change_ev_t)(
2215 __in efx_link_mode_t link_mode);
2217 #if EFSYS_OPT_MON_STATS
2219 typedef __checkReturn boolean_t
2220 (*efx_monitor_ev_t)(
2222 __in efx_mon_stat_t id,
2223 __in efx_mon_stat_value_t value);
2225 #endif /* EFSYS_OPT_MON_STATS */
2227 #if EFSYS_OPT_MAC_STATS
2229 typedef __checkReturn boolean_t
2230 (*efx_mac_stats_ev_t)(
2232 __in uint32_t generation);
2234 #endif /* EFSYS_OPT_MAC_STATS */
2236 typedef struct efx_ev_callbacks_s {
2237 efx_initialized_ev_t eec_initialized;
2239 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2240 efx_rx_ps_ev_t eec_rx_ps;
2243 efx_exception_ev_t eec_exception;
2244 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2245 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2246 efx_txq_flush_done_ev_t eec_txq_flush_done;
2247 efx_software_ev_t eec_software;
2248 efx_sram_ev_t eec_sram;
2249 efx_wake_up_ev_t eec_wake_up;
2250 efx_timer_ev_t eec_timer;
2251 efx_link_change_ev_t eec_link_change;
2252 #if EFSYS_OPT_MON_STATS
2253 efx_monitor_ev_t eec_monitor;
2254 #endif /* EFSYS_OPT_MON_STATS */
2255 #if EFSYS_OPT_MAC_STATS
2256 efx_mac_stats_ev_t eec_mac_stats;
2257 #endif /* EFSYS_OPT_MAC_STATS */
2258 } efx_ev_callbacks_t;
2260 extern __checkReturn boolean_t
2262 __in efx_evq_t *eep,
2263 __in unsigned int count);
2265 #if EFSYS_OPT_EV_PREFETCH
2269 __in efx_evq_t *eep,
2270 __in unsigned int count);
2272 #endif /* EFSYS_OPT_EV_PREFETCH */
2276 __in efx_evq_t *eep,
2277 __inout unsigned int *countp,
2278 __in const efx_ev_callbacks_t *eecp,
2279 __in_opt void *arg);
2281 extern __checkReturn efx_rc_t
2282 efx_ev_usecs_to_ticks(
2283 __in efx_nic_t *enp,
2284 __in unsigned int usecs,
2285 __out unsigned int *ticksp);
2287 extern __checkReturn efx_rc_t
2289 __in efx_evq_t *eep,
2290 __in unsigned int us);
2292 extern __checkReturn efx_rc_t
2294 __in efx_evq_t *eep,
2295 __in unsigned int count);
2297 #if EFSYS_OPT_QSTATS
2303 __in efx_nic_t *enp,
2304 __in unsigned int id);
2306 #endif /* EFSYS_OPT_NAMES */
2309 efx_ev_qstats_update(
2310 __in efx_evq_t *eep,
2311 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2313 #endif /* EFSYS_OPT_QSTATS */
2317 __in efx_evq_t *eep);
2321 extern __checkReturn efx_rc_t
2323 __inout efx_nic_t *enp);
2327 __in efx_nic_t *enp);
2329 #if EFSYS_OPT_RX_SCATTER
2330 __checkReturn efx_rc_t
2331 efx_rx_scatter_enable(
2332 __in efx_nic_t *enp,
2333 __in unsigned int buf_size);
2334 #endif /* EFSYS_OPT_RX_SCATTER */
2336 /* Handle to represent use of the default RSS context. */
2337 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2339 #if EFSYS_OPT_RX_SCALE
2341 typedef enum efx_rx_hash_alg_e {
2342 EFX_RX_HASHALG_LFSR = 0,
2343 EFX_RX_HASHALG_TOEPLITZ,
2344 EFX_RX_HASHALG_PACKED_STREAM,
2346 } efx_rx_hash_alg_t;
2349 * Legacy hash type flags.
2351 * They represent standard tuples for distinct traffic classes.
2353 #define EFX_RX_HASH_IPV4 (1U << 0)
2354 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2355 #define EFX_RX_HASH_IPV6 (1U << 2)
2356 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2358 #define EFX_RX_HASH_LEGACY_MASK \
2359 (EFX_RX_HASH_IPV4 | \
2360 EFX_RX_HASH_TCPIPV4 | \
2361 EFX_RX_HASH_IPV6 | \
2362 EFX_RX_HASH_TCPIPV6)
2365 * The type of the argument used by efx_rx_scale_mode_set() to
2366 * provide a means for the client drivers to configure hashing.
2368 * A properly constructed value can either be:
2369 * - a combination of legacy flags
2370 * - a combination of EFX_RX_HASH() flags
2372 typedef uint32_t efx_rx_hash_type_t;
2374 typedef enum efx_rx_hash_support_e {
2375 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2376 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2377 } efx_rx_hash_support_t;
2379 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2380 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2381 #define EFX_MAXRSS 64 /* RX indirection entry range */
2382 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2384 typedef enum efx_rx_scale_context_type_e {
2385 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2386 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2387 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2388 } efx_rx_scale_context_type_t;
2391 * Traffic classes eligible for hash computation.
2393 * Select packet headers used in computing the receive hash.
2394 * This uses the same encoding as the RSS_MODES field of
2395 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2397 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2398 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2399 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2400 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2401 #define EFX_RX_CLASS_IPV4_LBN 16
2402 #define EFX_RX_CLASS_IPV4_WIDTH 4
2403 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2404 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2405 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2406 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2407 #define EFX_RX_CLASS_IPV6_LBN 28
2408 #define EFX_RX_CLASS_IPV6_WIDTH 4
2410 #define EFX_RX_NCLASSES 6
2413 * Ancillary flags used to construct generic hash tuples.
2414 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2416 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2417 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2418 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2419 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2422 * Generic hash tuples.
2424 * They express combinations of packet fields
2425 * which can contribute to the hash value for
2426 * a particular traffic class.
2428 #define EFX_RX_CLASS_HASH_DISABLE 0
2430 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2431 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2433 #define EFX_RX_CLASS_HASH_2TUPLE \
2434 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2435 EFX_RX_CLASS_HASH_DST_ADDR)
2437 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2438 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2439 EFX_RX_CLASS_HASH_SRC_PORT)
2441 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2442 (EFX_RX_CLASS_HASH_DST_ADDR | \
2443 EFX_RX_CLASS_HASH_DST_PORT)
2445 #define EFX_RX_CLASS_HASH_4TUPLE \
2446 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2447 EFX_RX_CLASS_HASH_DST_ADDR | \
2448 EFX_RX_CLASS_HASH_SRC_PORT | \
2449 EFX_RX_CLASS_HASH_DST_PORT)
2451 #define EFX_RX_CLASS_HASH_NTUPLES 7
2454 * Hash flag constructor.
2456 * Resulting flags encode hash tuples for specific traffic classes.
2457 * The client drivers are encouraged to use these flags to form
2458 * a hash type value.
2460 #define EFX_RX_HASH(_class, _tuple) \
2461 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2462 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2465 * The maximum number of EFX_RX_HASH() flags.
2467 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2469 extern __checkReturn efx_rc_t
2470 efx_rx_scale_hash_flags_get(
2471 __in efx_nic_t *enp,
2472 __in efx_rx_hash_alg_t hash_alg,
2473 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2474 __in unsigned int max_nflags,
2475 __out unsigned int *nflagsp);
2477 extern __checkReturn efx_rc_t
2478 efx_rx_hash_default_support_get(
2479 __in efx_nic_t *enp,
2480 __out efx_rx_hash_support_t *supportp);
2483 extern __checkReturn efx_rc_t
2484 efx_rx_scale_default_support_get(
2485 __in efx_nic_t *enp,
2486 __out efx_rx_scale_context_type_t *typep);
2488 extern __checkReturn efx_rc_t
2489 efx_rx_scale_context_alloc(
2490 __in efx_nic_t *enp,
2491 __in efx_rx_scale_context_type_t type,
2492 __in uint32_t num_queues,
2493 __out uint32_t *rss_contextp);
2495 extern __checkReturn efx_rc_t
2496 efx_rx_scale_context_free(
2497 __in efx_nic_t *enp,
2498 __in uint32_t rss_context);
2500 extern __checkReturn efx_rc_t
2501 efx_rx_scale_mode_set(
2502 __in efx_nic_t *enp,
2503 __in uint32_t rss_context,
2504 __in efx_rx_hash_alg_t alg,
2505 __in efx_rx_hash_type_t type,
2506 __in boolean_t insert);
2508 extern __checkReturn efx_rc_t
2509 efx_rx_scale_tbl_set(
2510 __in efx_nic_t *enp,
2511 __in uint32_t rss_context,
2512 __in_ecount(n) unsigned int *table,
2515 extern __checkReturn efx_rc_t
2516 efx_rx_scale_key_set(
2517 __in efx_nic_t *enp,
2518 __in uint32_t rss_context,
2519 __in_ecount(n) uint8_t *key,
2522 extern __checkReturn uint32_t
2523 efx_pseudo_hdr_hash_get(
2524 __in efx_rxq_t *erp,
2525 __in efx_rx_hash_alg_t func,
2526 __in uint8_t *buffer);
2528 #endif /* EFSYS_OPT_RX_SCALE */
2530 extern __checkReturn efx_rc_t
2531 efx_pseudo_hdr_pkt_length_get(
2532 __in efx_rxq_t *erp,
2533 __in uint8_t *buffer,
2534 __out uint16_t *pkt_lengthp);
2536 extern __checkReturn size_t
2538 __in const efx_nic_t *enp,
2539 __in unsigned int ndescs);
2541 extern __checkReturn unsigned int
2543 __in const efx_nic_t *enp,
2544 __in unsigned int ndescs);
2546 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2548 typedef enum efx_rxq_type_e {
2549 EFX_RXQ_TYPE_DEFAULT,
2550 EFX_RXQ_TYPE_PACKED_STREAM,
2551 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2556 * Dummy flag to be used instead of 0 to make it clear that the argument
2557 * is receive queue flags.
2559 #define EFX_RXQ_FLAG_NONE 0x0
2560 #define EFX_RXQ_FLAG_SCATTER 0x1
2562 * If tunnels are supported and Rx event can provide information about
2563 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2564 * full-feature firmware variant running), outer classes are requested by
2565 * default. However, if the driver supports tunnels, the flag allows to
2566 * request inner classes which are required to be able to interpret inner
2567 * Rx checksum offload results.
2569 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2571 extern __checkReturn efx_rc_t
2573 __in efx_nic_t *enp,
2574 __in unsigned int index,
2575 __in unsigned int label,
2576 __in efx_rxq_type_t type,
2577 __in size_t buf_size,
2578 __in efsys_mem_t *esmp,
2581 __in unsigned int flags,
2582 __in efx_evq_t *eep,
2583 __deref_out efx_rxq_t **erpp);
2585 #if EFSYS_OPT_RX_PACKED_STREAM
2587 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2588 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2589 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2590 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2591 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2593 extern __checkReturn efx_rc_t
2594 efx_rx_qcreate_packed_stream(
2595 __in efx_nic_t *enp,
2596 __in unsigned int index,
2597 __in unsigned int label,
2598 __in uint32_t ps_buf_size,
2599 __in efsys_mem_t *esmp,
2601 __in efx_evq_t *eep,
2602 __deref_out efx_rxq_t **erpp);
2606 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2608 /* Maximum head-of-line block timeout in nanoseconds */
2609 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2611 extern __checkReturn efx_rc_t
2612 efx_rx_qcreate_es_super_buffer(
2613 __in efx_nic_t *enp,
2614 __in unsigned int index,
2615 __in unsigned int label,
2616 __in uint32_t n_bufs_per_desc,
2617 __in uint32_t max_dma_len,
2618 __in uint32_t buf_stride,
2619 __in uint32_t hol_block_timeout,
2620 __in efsys_mem_t *esmp,
2622 __in unsigned int flags,
2623 __in efx_evq_t *eep,
2624 __deref_out efx_rxq_t **erpp);
2628 typedef struct efx_buffer_s {
2629 efsys_dma_addr_t eb_addr;
2634 typedef struct efx_desc_s {
2640 __in efx_rxq_t *erp,
2641 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2643 __in unsigned int ndescs,
2644 __in unsigned int completed,
2645 __in unsigned int added);
2649 __in efx_rxq_t *erp,
2650 __in unsigned int added,
2651 __inout unsigned int *pushedp);
2653 #if EFSYS_OPT_RX_PACKED_STREAM
2656 efx_rx_qpush_ps_credits(
2657 __in efx_rxq_t *erp);
2659 extern __checkReturn uint8_t *
2660 efx_rx_qps_packet_info(
2661 __in efx_rxq_t *erp,
2662 __in uint8_t *buffer,
2663 __in uint32_t buffer_length,
2664 __in uint32_t current_offset,
2665 __out uint16_t *lengthp,
2666 __out uint32_t *next_offsetp,
2667 __out uint32_t *timestamp);
2670 extern __checkReturn efx_rc_t
2672 __in efx_rxq_t *erp);
2676 __in efx_rxq_t *erp);
2680 __in efx_rxq_t *erp);
2684 typedef struct efx_txq_s efx_txq_t;
2686 #if EFSYS_OPT_QSTATS
2688 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2689 typedef enum efx_tx_qstat_e {
2695 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2697 #endif /* EFSYS_OPT_QSTATS */
2699 extern __checkReturn efx_rc_t
2701 __in efx_nic_t *enp);
2705 __in efx_nic_t *enp);
2707 extern __checkReturn size_t
2709 __in const efx_nic_t *enp,
2710 __in unsigned int ndescs);
2712 extern __checkReturn unsigned int
2714 __in const efx_nic_t *enp,
2715 __in unsigned int ndescs);
2717 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2719 #define EFX_TXQ_CKSUM_IPV4 0x0001
2720 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2721 #define EFX_TXQ_FATSOV2 0x0004
2722 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2723 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2725 extern __checkReturn efx_rc_t
2727 __in efx_nic_t *enp,
2728 __in unsigned int index,
2729 __in unsigned int label,
2730 __in efsys_mem_t *esmp,
2733 __in uint16_t flags,
2734 __in efx_evq_t *eep,
2735 __deref_out efx_txq_t **etpp,
2736 __out unsigned int *addedp);
2738 extern __checkReturn efx_rc_t
2740 __in efx_txq_t *etp,
2741 __in_ecount(ndescs) efx_buffer_t *eb,
2742 __in unsigned int ndescs,
2743 __in unsigned int completed,
2744 __inout unsigned int *addedp);
2746 extern __checkReturn efx_rc_t
2748 __in efx_txq_t *etp,
2749 __in unsigned int ns);
2753 __in efx_txq_t *etp,
2754 __in unsigned int added,
2755 __in unsigned int pushed);
2757 extern __checkReturn efx_rc_t
2759 __in efx_txq_t *etp);
2763 __in efx_txq_t *etp);
2765 extern __checkReturn efx_rc_t
2767 __in efx_txq_t *etp);
2770 efx_tx_qpio_disable(
2771 __in efx_txq_t *etp);
2773 extern __checkReturn efx_rc_t
2775 __in efx_txq_t *etp,
2776 __in_ecount(buf_length) uint8_t *buffer,
2777 __in size_t buf_length,
2778 __in size_t pio_buf_offset);
2780 extern __checkReturn efx_rc_t
2782 __in efx_txq_t *etp,
2783 __in size_t pkt_length,
2784 __in unsigned int completed,
2785 __inout unsigned int *addedp);
2787 extern __checkReturn efx_rc_t
2789 __in efx_txq_t *etp,
2790 __in_ecount(n) efx_desc_t *ed,
2791 __in unsigned int n,
2792 __in unsigned int completed,
2793 __inout unsigned int *addedp);
2796 efx_tx_qdesc_dma_create(
2797 __in efx_txq_t *etp,
2798 __in efsys_dma_addr_t addr,
2801 __out efx_desc_t *edp);
2804 efx_tx_qdesc_tso_create(
2805 __in efx_txq_t *etp,
2806 __in uint16_t ipv4_id,
2807 __in uint32_t tcp_seq,
2808 __in uint8_t tcp_flags,
2809 __out efx_desc_t *edp);
2811 /* Number of FATSOv2 option descriptors */
2812 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2814 /* Maximum number of DMA segments per TSO packet (not superframe) */
2815 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2818 efx_tx_qdesc_tso2_create(
2819 __in efx_txq_t *etp,
2820 __in uint16_t ipv4_id,
2821 __in uint16_t outer_ipv4_id,
2822 __in uint32_t tcp_seq,
2823 __in uint16_t tcp_mss,
2824 __out_ecount(count) efx_desc_t *edp,
2828 efx_tx_qdesc_vlantci_create(
2829 __in efx_txq_t *etp,
2831 __out efx_desc_t *edp);
2834 efx_tx_qdesc_checksum_create(
2835 __in efx_txq_t *etp,
2836 __in uint16_t flags,
2837 __out efx_desc_t *edp);
2839 #if EFSYS_OPT_QSTATS
2845 __in efx_nic_t *etp,
2846 __in unsigned int id);
2848 #endif /* EFSYS_OPT_NAMES */
2851 efx_tx_qstats_update(
2852 __in efx_txq_t *etp,
2853 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2855 #endif /* EFSYS_OPT_QSTATS */
2859 __in efx_txq_t *etp);
2864 #if EFSYS_OPT_FILTER
2866 #define EFX_ETHER_TYPE_IPV4 0x0800
2867 #define EFX_ETHER_TYPE_IPV6 0x86DD
2869 #define EFX_IPPROTO_TCP 6
2870 #define EFX_IPPROTO_UDP 17
2871 #define EFX_IPPROTO_GRE 47
2873 /* Use RSS to spread across multiple queues */
2874 #define EFX_FILTER_FLAG_RX_RSS 0x01
2875 /* Enable RX scatter */
2876 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2878 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2879 * May only be set by the filter implementation for each type.
2880 * A removal request will restore the automatic filter in its place.
2882 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2883 /* Filter is for RX */
2884 #define EFX_FILTER_FLAG_RX 0x08
2885 /* Filter is for TX */
2886 #define EFX_FILTER_FLAG_TX 0x10
2887 /* Set match flag on the received packet */
2888 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2889 /* Set match mark on the received packet */
2890 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2892 typedef uint8_t efx_filter_flags_t;
2895 * Flags which specify the fields to match on. The values are the same as in the
2896 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2899 /* Match by remote IP host address */
2900 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2901 /* Match by local IP host address */
2902 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2903 /* Match by remote MAC address */
2904 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2905 /* Match by remote TCP/UDP port */
2906 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2907 /* Match by remote TCP/UDP port */
2908 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2909 /* Match by local TCP/UDP port */
2910 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2911 /* Match by Ether-type */
2912 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2913 /* Match by inner VLAN ID */
2914 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2915 /* Match by outer VLAN ID */
2916 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2917 /* Match by IP transport protocol */
2918 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2919 /* Match by VNI or VSID */
2920 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2921 /* For encapsulated packets, match by inner frame local MAC address */
2922 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2923 /* For encapsulated packets, match all multicast inner frames */
2924 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2925 /* For encapsulated packets, match all unicast inner frames */
2926 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2928 * Match by encap type, this flag does not correspond to
2929 * the MCDI match flags and any unoccupied value may be used
2931 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2932 /* Match otherwise-unmatched multicast and broadcast packets */
2933 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2934 /* Match otherwise-unmatched unicast packets */
2935 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2937 typedef uint32_t efx_filter_match_flags_t;
2939 typedef enum efx_filter_priority_s {
2940 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2941 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2942 * address list or hardware
2943 * requirements. This may only be used
2944 * by the filter implementation for
2946 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2947 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2948 * client (e.g. SR-IOV, HyperV VMQ etc.)
2950 } efx_filter_priority_t;
2953 * FIXME: All these fields are assumed to be in little-endian byte order.
2954 * It may be better for some to be big-endian. See bug42804.
2957 typedef struct efx_filter_spec_s {
2958 efx_filter_match_flags_t efs_match_flags;
2959 uint8_t efs_priority;
2960 efx_filter_flags_t efs_flags;
2961 uint16_t efs_dmaq_id;
2962 uint32_t efs_rss_context;
2964 /* Fields below here are hashed for software filter lookup */
2965 uint16_t efs_outer_vid;
2966 uint16_t efs_inner_vid;
2967 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2968 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2969 uint16_t efs_ether_type;
2970 uint8_t efs_ip_proto;
2971 efx_tunnel_protocol_t efs_encap_type;
2972 uint16_t efs_loc_port;
2973 uint16_t efs_rem_port;
2974 efx_oword_t efs_rem_host;
2975 efx_oword_t efs_loc_host;
2976 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2977 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2978 } efx_filter_spec_t;
2981 /* Default values for use in filter specifications */
2982 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2983 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2985 extern __checkReturn efx_rc_t
2987 __in efx_nic_t *enp);
2991 __in efx_nic_t *enp);
2993 extern __checkReturn efx_rc_t
2995 __in efx_nic_t *enp,
2996 __inout efx_filter_spec_t *spec);
2998 extern __checkReturn efx_rc_t
3000 __in efx_nic_t *enp,
3001 __inout efx_filter_spec_t *spec);
3003 extern __checkReturn efx_rc_t
3005 __in efx_nic_t *enp);
3007 extern __checkReturn efx_rc_t
3008 efx_filter_supported_filters(
3009 __in efx_nic_t *enp,
3010 __out_ecount(buffer_length) uint32_t *buffer,
3011 __in size_t buffer_length,
3012 __out size_t *list_lengthp);
3015 efx_filter_spec_init_rx(
3016 __out efx_filter_spec_t *spec,
3017 __in efx_filter_priority_t priority,
3018 __in efx_filter_flags_t flags,
3019 __in efx_rxq_t *erp);
3022 efx_filter_spec_init_tx(
3023 __out efx_filter_spec_t *spec,
3024 __in efx_txq_t *etp);
3026 extern __checkReturn efx_rc_t
3027 efx_filter_spec_set_ipv4_local(
3028 __inout efx_filter_spec_t *spec,
3031 __in uint16_t port);
3033 extern __checkReturn efx_rc_t
3034 efx_filter_spec_set_ipv4_full(
3035 __inout efx_filter_spec_t *spec,
3037 __in uint32_t lhost,
3038 __in uint16_t lport,
3039 __in uint32_t rhost,
3040 __in uint16_t rport);
3042 extern __checkReturn efx_rc_t
3043 efx_filter_spec_set_eth_local(
3044 __inout efx_filter_spec_t *spec,
3046 __in const uint8_t *addr);
3049 efx_filter_spec_set_ether_type(
3050 __inout efx_filter_spec_t *spec,
3051 __in uint16_t ether_type);
3053 extern __checkReturn efx_rc_t
3054 efx_filter_spec_set_uc_def(
3055 __inout efx_filter_spec_t *spec);
3057 extern __checkReturn efx_rc_t
3058 efx_filter_spec_set_mc_def(
3059 __inout efx_filter_spec_t *spec);
3061 typedef enum efx_filter_inner_frame_match_e {
3062 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3063 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3064 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3065 } efx_filter_inner_frame_match_t;
3067 extern __checkReturn efx_rc_t
3068 efx_filter_spec_set_encap_type(
3069 __inout efx_filter_spec_t *spec,
3070 __in efx_tunnel_protocol_t encap_type,
3071 __in efx_filter_inner_frame_match_t inner_frame_match);
3073 extern __checkReturn efx_rc_t
3074 efx_filter_spec_set_vxlan(
3075 __inout efx_filter_spec_t *spec,
3076 __in const uint8_t *vni,
3077 __in const uint8_t *inner_addr,
3078 __in const uint8_t *outer_addr);
3080 extern __checkReturn efx_rc_t
3081 efx_filter_spec_set_geneve(
3082 __inout efx_filter_spec_t *spec,
3083 __in const uint8_t *vni,
3084 __in const uint8_t *inner_addr,
3085 __in const uint8_t *outer_addr);
3087 extern __checkReturn efx_rc_t
3088 efx_filter_spec_set_nvgre(
3089 __inout efx_filter_spec_t *spec,
3090 __in const uint8_t *vsid,
3091 __in const uint8_t *inner_addr,
3092 __in const uint8_t *outer_addr);
3094 #if EFSYS_OPT_RX_SCALE
3095 extern __checkReturn efx_rc_t
3096 efx_filter_spec_set_rss_context(
3097 __inout efx_filter_spec_t *spec,
3098 __in uint32_t rss_context);
3100 #endif /* EFSYS_OPT_FILTER */
3104 extern __checkReturn uint32_t
3106 __in_ecount(count) uint32_t const *input,
3108 __in uint32_t init);
3110 extern __checkReturn uint32_t
3112 __in_ecount(length) uint8_t const *input,
3114 __in uint32_t init);
3116 #if EFSYS_OPT_LICENSING
3120 typedef struct efx_key_stats_s {
3122 uint32_t eks_invalid;
3123 uint32_t eks_blacklisted;
3124 uint32_t eks_unverifiable;
3125 uint32_t eks_wrong_node;
3126 uint32_t eks_licensed_apps_lo;
3127 uint32_t eks_licensed_apps_hi;
3128 uint32_t eks_licensed_features_lo;
3129 uint32_t eks_licensed_features_hi;
3132 extern __checkReturn efx_rc_t
3134 __in efx_nic_t *enp);
3138 __in efx_nic_t *enp);
3140 extern __checkReturn boolean_t
3141 efx_lic_check_support(
3142 __in efx_nic_t *enp);
3144 extern __checkReturn efx_rc_t
3145 efx_lic_update_licenses(
3146 __in efx_nic_t *enp);
3148 extern __checkReturn efx_rc_t
3149 efx_lic_get_key_stats(
3150 __in efx_nic_t *enp,
3151 __out efx_key_stats_t *ksp);
3153 extern __checkReturn efx_rc_t
3155 __in efx_nic_t *enp,
3156 __in uint64_t app_id,
3157 __out boolean_t *licensedp);
3159 extern __checkReturn efx_rc_t
3161 __in efx_nic_t *enp,
3162 __in size_t buffer_size,
3163 __out uint32_t *typep,
3164 __out size_t *lengthp,
3165 __out_opt uint8_t *bufferp);
3168 extern __checkReturn efx_rc_t
3170 __in efx_nic_t *enp,
3171 __in_bcount(buffer_size)
3173 __in size_t buffer_size,
3174 __out uint32_t *startp);
3176 extern __checkReturn efx_rc_t
3178 __in efx_nic_t *enp,
3179 __in_bcount(buffer_size)
3181 __in size_t buffer_size,
3182 __in uint32_t offset,
3183 __out uint32_t *endp);
3185 extern __checkReturn __success(return != B_FALSE) boolean_t
3187 __in efx_nic_t *enp,
3188 __in_bcount(buffer_size)
3190 __in size_t buffer_size,
3191 __in uint32_t offset,
3192 __out uint32_t *startp,
3193 __out uint32_t *lengthp);
3195 extern __checkReturn __success(return != B_FALSE) boolean_t
3196 efx_lic_validate_key(
3197 __in efx_nic_t *enp,
3198 __in_bcount(length) caddr_t keyp,
3199 __in uint32_t length);
3201 extern __checkReturn efx_rc_t
3203 __in efx_nic_t *enp,
3204 __in_bcount(buffer_size)
3206 __in size_t buffer_size,
3207 __in uint32_t offset,
3208 __in uint32_t length,
3209 __out_bcount_part(key_max_size, *lengthp)
3211 __in size_t key_max_size,
3212 __out uint32_t *lengthp);
3214 extern __checkReturn efx_rc_t
3216 __in efx_nic_t *enp,
3217 __in_bcount(buffer_size)
3219 __in size_t buffer_size,
3220 __in uint32_t offset,
3221 __in_bcount(length) caddr_t keyp,
3222 __in uint32_t length,
3223 __out uint32_t *lengthp);
3225 __checkReturn efx_rc_t
3227 __in efx_nic_t *enp,
3228 __in_bcount(buffer_size)
3230 __in size_t buffer_size,
3231 __in uint32_t offset,
3232 __in uint32_t length,
3234 __out uint32_t *deltap);
3236 extern __checkReturn efx_rc_t
3237 efx_lic_create_partition(
3238 __in efx_nic_t *enp,
3239 __in_bcount(buffer_size)
3241 __in size_t buffer_size);
3243 extern __checkReturn efx_rc_t
3244 efx_lic_finish_partition(
3245 __in efx_nic_t *enp,
3246 __in_bcount(buffer_size)
3248 __in size_t buffer_size);
3250 #endif /* EFSYS_OPT_LICENSING */
3254 #if EFSYS_OPT_TUNNEL
3256 extern __checkReturn efx_rc_t
3258 __in efx_nic_t *enp);
3262 __in efx_nic_t *enp);
3265 * For overlay network encapsulation using UDP, the firmware needs to know
3266 * the configured UDP port for the overlay so it can decode encapsulated
3268 * The UDP port/protocol list is global.
3271 extern __checkReturn efx_rc_t
3272 efx_tunnel_config_udp_add(
3273 __in efx_nic_t *enp,
3274 __in uint16_t port /* host/cpu-endian */,
3275 __in efx_tunnel_protocol_t protocol);
3277 extern __checkReturn efx_rc_t
3278 efx_tunnel_config_udp_remove(
3279 __in efx_nic_t *enp,
3280 __in uint16_t port /* host/cpu-endian */,
3281 __in efx_tunnel_protocol_t protocol);
3284 efx_tunnel_config_clear(
3285 __in efx_nic_t *enp);
3288 * Apply tunnel UDP ports configuration to hardware.
3290 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3293 extern __checkReturn efx_rc_t
3294 efx_tunnel_reconfigure(
3295 __in efx_nic_t *enp);
3297 #endif /* EFSYS_OPT_TUNNEL */
3299 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3302 * Firmware subvariant choice options.
3304 * It may be switched to no Tx checksum if attached drivers are either
3305 * preboot or firmware subvariant aware and no VIS are allocated.
3306 * If may be always switched to default explicitly using set request or
3307 * implicitly if unaware driver is attaching. If switching is done when
3308 * a driver is attached, it gets MC_REBOOT event and should recreate its
3311 * See SF-119419-TC DPDK Firmware Driver Interface and
3312 * SF-109306-TC EF10 for Driver Writers for details.
3314 typedef enum efx_nic_fw_subvariant_e {
3315 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3316 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3317 EFX_NIC_FW_SUBVARIANT_NTYPES
3318 } efx_nic_fw_subvariant_t;
3320 extern __checkReturn efx_rc_t
3321 efx_nic_get_fw_subvariant(
3322 __in efx_nic_t *enp,
3323 __out efx_nic_fw_subvariant_t *subvariantp);
3325 extern __checkReturn efx_rc_t
3326 efx_nic_set_fw_subvariant(
3327 __in efx_nic_t *enp,
3328 __in efx_nic_fw_subvariant_t subvariant);
3330 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3332 typedef enum efx_phy_fec_type_e {
3333 EFX_PHY_FEC_NONE = 0,
3336 } efx_phy_fec_type_t;
3338 extern __checkReturn efx_rc_t
3339 efx_phy_fec_type_get(
3340 __in efx_nic_t *enp,
3341 __out efx_phy_fec_type_t *typep);
3343 typedef struct efx_phy_link_state_s {
3344 uint32_t epls_adv_cap_mask;
3345 uint32_t epls_lp_cap_mask;
3346 uint32_t epls_ld_cap_mask;
3347 unsigned int epls_fcntl;
3348 efx_phy_fec_type_t epls_fec;
3349 efx_link_mode_t epls_link_mode;
3350 } efx_phy_link_state_t;
3352 extern __checkReturn efx_rc_t
3353 efx_phy_link_state_get(
3354 __in efx_nic_t *enp,
3355 __out efx_phy_link_state_t *eplsp);
3360 typedef uint32_t efx_vswitch_id_t;
3361 typedef uint32_t efx_vport_id_t;
3363 typedef enum efx_vswitch_type_e {
3364 EFX_VSWITCH_TYPE_VLAN = 1,
3365 EFX_VSWITCH_TYPE_VEB,
3366 /* VSWITCH_TYPE_VEPA: obsolete */
3367 EFX_VSWITCH_TYPE_MUX = 4,
3368 } efx_vswitch_type_t;
3370 typedef enum efx_vport_type_e {
3371 EFX_VPORT_TYPE_NORMAL = 4,
3372 EFX_VPORT_TYPE_EXPANSION,
3373 EFX_VPORT_TYPE_TEST,
3376 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3377 #define EFX_FILTER_VID_UNSPEC 0xffff
3378 #define EFX_DEFAULT_VSWITCH_ID 1
3380 /* Default VF VLAN ID on creation */
3381 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3382 #define EFX_VPORT_ID_INVALID 0
3384 typedef struct efx_vport_config_s {
3385 /* Either VF index or 0xffff for PF */
3386 uint16_t evc_function;
3387 /* VLAN ID of the associated function */
3389 /* vport id shared with client driver */
3390 efx_vport_id_t evc_vport_id;
3391 /* MAC address of the associated function */
3392 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3394 * vports created with this flag set may only transfer traffic on the
3395 * VLANs permitted by the vport. Also, an attempt to install filter with
3396 * VLAN will be refused unless requesting function has VLAN privilege.
3398 boolean_t evc_vlan_restrict;
3399 /* Whether this function is assigned or not */
3400 boolean_t evc_vport_assigned;
3401 } efx_vport_config_t;
3403 typedef struct efx_vswitch_s efx_vswitch_t;
3405 extern __checkReturn efx_rc_t
3407 __in efx_nic_t *enp);
3411 __in efx_nic_t *enp);
3413 extern __checkReturn efx_rc_t
3414 efx_evb_vswitch_create(
3415 __in efx_nic_t *enp,
3416 __in uint32_t num_vports,
3417 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3418 __deref_out efx_vswitch_t **evpp);
3420 extern __checkReturn efx_rc_t
3421 efx_evb_vswitch_destroy(
3422 __in efx_nic_t *enp,
3423 __in efx_vswitch_t *evp);
3425 extern __checkReturn efx_rc_t
3426 efx_evb_vport_mac_set(
3427 __in efx_nic_t *enp,
3428 __in efx_vswitch_t *evp,
3429 __in efx_vport_id_t vport_id,
3430 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3432 extern __checkReturn efx_rc_t
3433 efx_evb_vport_vlan_set(
3434 __in efx_nic_t *enp,
3435 __in efx_vswitch_t *evp,
3436 __in efx_vport_id_t vport_id,
3439 extern __checkReturn efx_rc_t
3440 efx_evb_vport_reset(
3441 __in efx_nic_t *enp,
3442 __in efx_vswitch_t *evp,
3443 __in efx_vport_id_t vport_id,
3444 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3446 __out boolean_t *is_fn_resetp);
3448 extern __checkReturn efx_rc_t
3449 efx_evb_vport_stats(
3450 __in efx_nic_t *enp,
3451 __in efx_vswitch_t *evp,
3452 __in efx_vport_id_t vport_id,
3453 __out efsys_mem_t *stats_bufferp);
3455 #endif /* EFSYS_OPT_EVB */
3457 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3459 typedef struct efx_proxy_auth_config_s {
3460 efsys_mem_t *request_bufferp;
3461 efsys_mem_t *response_bufferp;
3462 efsys_mem_t *status_bufferp;
3466 uint32_t handled_privileges;
3467 } efx_proxy_auth_config_t;
3469 typedef struct efx_proxy_cmd_params_s {
3472 uint8_t *request_bufferp;
3473 size_t request_size;
3474 uint8_t *response_bufferp;
3475 size_t response_size;
3476 size_t *response_size_actualp;
3477 } efx_proxy_cmd_params_t;
3479 extern __checkReturn efx_rc_t
3480 efx_proxy_auth_init(
3481 __in efx_nic_t *enp);
3484 efx_proxy_auth_fini(
3485 __in efx_nic_t *enp);
3487 extern __checkReturn efx_rc_t
3488 efx_proxy_auth_configure(
3489 __in efx_nic_t *enp,
3490 __in efx_proxy_auth_config_t *configp);
3492 __checkReturn efx_rc_t
3493 efx_proxy_auth_destroy(
3494 __in efx_nic_t *enp,
3495 __in uint32_t handled_privileges);
3497 __checkReturn efx_rc_t
3498 efx_proxy_auth_complete_request(
3499 __in efx_nic_t *enp,
3500 __in uint32_t fn_index,
3501 __in uint32_t proxy_result,
3502 __in uint32_t handle);
3504 __checkReturn efx_rc_t
3505 efx_proxy_auth_exec_cmd(
3506 __in efx_nic_t *enp,
3507 __inout efx_proxy_cmd_params_t *paramsp);
3509 __checkReturn efx_rc_t
3510 efx_proxy_auth_set_privilege_mask(
3511 __in efx_nic_t *enp,
3512 __in uint32_t vf_index,
3514 __in uint32_t value);
3516 __checkReturn efx_rc_t
3517 efx_proxy_auth_privilege_mask_get(
3518 __in efx_nic_t *enp,
3519 __in uint32_t pf_index,
3520 __in uint32_t vf_index,
3521 __out uint32_t *maskp);
3523 __checkReturn efx_rc_t
3524 efx_proxy_auth_privilege_modify(
3525 __in efx_nic_t *enp,
3526 __in uint32_t pf_index,
3527 __in uint32_t vf_index,
3528 __in uint32_t add_privileges_mask,
3529 __in uint32_t remove_privileges_mask);
3531 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3537 #endif /* _SYS_EFX_H */