1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 extern __checkReturn efx_rc_t
134 __in efx_nic_t *enp);
136 extern __checkReturn efx_rc_t
138 __in efx_nic_t *enp);
140 extern __checkReturn efx_rc_t
142 __in efx_nic_t *enp);
146 extern __checkReturn efx_rc_t
147 efx_nic_register_test(
148 __in efx_nic_t *enp);
150 #endif /* EFSYS_OPT_DIAG */
154 __in efx_nic_t *enp);
158 __in efx_nic_t *enp);
162 __in efx_nic_t *enp);
164 #define EFX_PCIE_LINK_SPEED_GEN1 1
165 #define EFX_PCIE_LINK_SPEED_GEN2 2
166 #define EFX_PCIE_LINK_SPEED_GEN3 3
168 typedef enum efx_pcie_link_performance_e {
169 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
170 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
171 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
172 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
173 } efx_pcie_link_performance_t;
175 extern __checkReturn efx_rc_t
176 efx_nic_calculate_pcie_link_bandwidth(
177 __in uint32_t pcie_link_width,
178 __in uint32_t pcie_link_gen,
179 __out uint32_t *bandwidth_mbpsp);
181 extern __checkReturn efx_rc_t
182 efx_nic_check_pcie_link_speed(
184 __in uint32_t pcie_link_width,
185 __in uint32_t pcie_link_gen,
186 __out efx_pcie_link_performance_t *resultp);
190 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
191 /* Huntington and Medford require MCDIv2 commands */
192 #define WITH_MCDI_V2 1
195 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
197 typedef enum efx_mcdi_exception_e {
198 EFX_MCDI_EXCEPTION_MC_REBOOT,
199 EFX_MCDI_EXCEPTION_MC_BADASSERT,
200 } efx_mcdi_exception_t;
202 #if EFSYS_OPT_MCDI_LOGGING
203 typedef enum efx_log_msg_e {
205 EFX_LOG_MCDI_REQUEST,
206 EFX_LOG_MCDI_RESPONSE,
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
210 typedef struct efx_mcdi_transport_s {
212 efsys_mem_t *emt_dma_mem;
213 void (*emt_execute)(void *, efx_mcdi_req_t *);
214 void (*emt_ev_cpl)(void *);
215 void (*emt_exception)(void *, efx_mcdi_exception_t);
216 #if EFSYS_OPT_MCDI_LOGGING
217 void (*emt_logger)(void *, efx_log_msg_t,
218 void *, size_t, void *, size_t);
219 #endif /* EFSYS_OPT_MCDI_LOGGING */
220 #if EFSYS_OPT_MCDI_PROXY_AUTH
221 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
222 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
223 } efx_mcdi_transport_t;
225 extern __checkReturn efx_rc_t
228 __in const efx_mcdi_transport_t *mtp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
236 __in efx_nic_t *enp);
239 efx_mcdi_get_timeout(
241 __in efx_mcdi_req_t *emrp,
242 __out uint32_t *usec_timeoutp);
245 efx_mcdi_request_start(
247 __in efx_mcdi_req_t *emrp,
248 __in boolean_t ev_cpl);
250 extern __checkReturn boolean_t
251 efx_mcdi_request_poll(
252 __in efx_nic_t *enp);
254 extern __checkReturn boolean_t
255 efx_mcdi_request_abort(
256 __in efx_nic_t *enp);
260 __in efx_nic_t *enp);
262 #endif /* EFSYS_OPT_MCDI */
266 #define EFX_NINTR_SIENA 1024
268 typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
275 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
277 extern __checkReturn efx_rc_t
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
285 __in efx_nic_t *enp);
289 __in efx_nic_t *enp);
292 efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
295 #define EFX_INTR_NEVQS 32
297 extern __checkReturn efx_rc_t
300 __in unsigned int level);
303 efx_intr_status_line(
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
309 efx_intr_status_message(
311 __in unsigned int message,
312 __out boolean_t *fatalp);
316 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
324 #if EFSYS_OPT_MAC_STATS
326 /* START MKCONFIG GENERATED EfxHeaderMacBlock 7d59c0d68431a5d1 */
327 typedef enum efx_mac_stat_e {
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
409 EFX_MAC_FEC_UNCORRECTED_ERRORS,
410 EFX_MAC_FEC_CORRECTED_ERRORS,
411 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
412 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
413 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
414 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
415 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
416 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
417 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
418 EFX_MAC_CTPIO_OVERFLOW_FAIL,
419 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
420 EFX_MAC_CTPIO_TIMEOUT_FAIL,
421 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
422 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
423 EFX_MAC_CTPIO_INVALID_WR_FAIL,
424 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
425 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
426 EFX_MAC_CTPIO_RUNT_FALLBACK,
427 EFX_MAC_CTPIO_SUCCESS,
428 EFX_MAC_CTPIO_FALLBACK,
429 EFX_MAC_CTPIO_POISON,
434 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
436 #endif /* EFSYS_OPT_MAC_STATS */
438 typedef enum efx_link_mode_e {
439 EFX_LINK_UNKNOWN = 0,
455 #define EFX_MAC_ADDR_LEN 6
457 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
459 #define EFX_MAC_MULTICAST_LIST_MAX 256
461 #define EFX_MAC_SDU_MAX 9202
463 #define EFX_MAC_PDU_ADJUSTMENT \
467 + /* bug16011 */ 16) \
469 #define EFX_MAC_PDU(_sdu) \
470 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
473 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
474 * the SDU rounded up slightly.
476 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
478 #define EFX_MAC_PDU_MIN 60
479 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
481 extern __checkReturn efx_rc_t
486 extern __checkReturn efx_rc_t
491 extern __checkReturn efx_rc_t
496 extern __checkReturn efx_rc_t
499 __in boolean_t all_unicst,
500 __in boolean_t mulcst,
501 __in boolean_t all_mulcst,
502 __in boolean_t brdcst);
504 extern __checkReturn efx_rc_t
505 efx_mac_multicast_list_set(
507 __in_ecount(6*count) uint8_t const *addrs,
510 extern __checkReturn efx_rc_t
511 efx_mac_filter_default_rxq_set(
514 __in boolean_t using_rss);
517 efx_mac_filter_default_rxq_clear(
518 __in efx_nic_t *enp);
520 extern __checkReturn efx_rc_t
523 __in boolean_t enabled);
525 extern __checkReturn efx_rc_t
528 __out boolean_t *mac_upp);
530 #define EFX_FCNTL_RESPOND 0x00000001
531 #define EFX_FCNTL_GENERATE 0x00000002
533 extern __checkReturn efx_rc_t
536 __in unsigned int fcntl,
537 __in boolean_t autoneg);
542 __out unsigned int *fcntl_wantedp,
543 __out unsigned int *fcntl_linkp);
546 #if EFSYS_OPT_MAC_STATS
550 extern __checkReturn const char *
553 __in unsigned int id);
555 #endif /* EFSYS_OPT_NAMES */
557 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
559 #define EFX_MAC_STATS_MASK_NPAGES \
560 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
561 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
564 * Get mask of MAC statistics supported by the hardware.
566 * If mask_size is insufficient to return the mask, EINVAL error is
567 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
568 * (which is sizeof (uint32_t)) is sufficient.
570 extern __checkReturn efx_rc_t
571 efx_mac_stats_get_mask(
573 __out_bcount(mask_size) uint32_t *maskp,
574 __in size_t mask_size);
576 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
577 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
578 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
581 extern __checkReturn efx_rc_t
583 __in efx_nic_t *enp);
586 * Upload mac statistics supported by the hardware into the given buffer.
588 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
589 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
591 * The hardware will only DMA statistics that it understands (of course).
592 * Drivers should not make any assumptions about which statistics are
593 * supported, especially when the statistics are generated by firmware.
595 * Thus, drivers should zero this buffer before use, so that not-understood
596 * statistics read back as zero.
598 extern __checkReturn efx_rc_t
599 efx_mac_stats_upload(
601 __in efsys_mem_t *esmp);
603 extern __checkReturn efx_rc_t
604 efx_mac_stats_periodic(
606 __in efsys_mem_t *esmp,
607 __in uint16_t period_ms,
608 __in boolean_t events);
610 extern __checkReturn efx_rc_t
611 efx_mac_stats_update(
613 __in efsys_mem_t *esmp,
614 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
615 __inout_opt uint32_t *generationp);
617 #endif /* EFSYS_OPT_MAC_STATS */
621 typedef enum efx_mon_type_e {
633 __in efx_nic_t *enp);
635 #endif /* EFSYS_OPT_NAMES */
637 extern __checkReturn efx_rc_t
639 __in efx_nic_t *enp);
641 #if EFSYS_OPT_MON_STATS
643 #define EFX_MON_STATS_PAGE_SIZE 0x100
644 #define EFX_MON_MASK_ELEMENT_SIZE 32
646 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
647 typedef enum efx_mon_stat_e {
654 EFX_MON_STAT_EXT_TEMP,
655 EFX_MON_STAT_INT_TEMP,
658 EFX_MON_STAT_INT_COOLING,
659 EFX_MON_STAT_EXT_COOLING,
667 EFX_MON_STAT_AOE_TEMP,
668 EFX_MON_STAT_PSU_AOE_TEMP,
669 EFX_MON_STAT_PSU_TEMP,
675 EFX_MON_STAT_VAOE_IN,
677 EFX_MON_STAT_IAOE_IN,
678 EFX_MON_STAT_NIC_POWER,
682 EFX_MON_STAT_0_9V_ADC,
683 EFX_MON_STAT_INT_TEMP2,
684 EFX_MON_STAT_VREG_TEMP,
685 EFX_MON_STAT_VREG_0_9V_TEMP,
686 EFX_MON_STAT_VREG_1_2V_TEMP,
687 EFX_MON_STAT_INT_VPTAT,
688 EFX_MON_STAT_INT_ADC_TEMP,
689 EFX_MON_STAT_EXT_VPTAT,
690 EFX_MON_STAT_EXT_ADC_TEMP,
691 EFX_MON_STAT_AMBIENT_TEMP,
692 EFX_MON_STAT_AIRFLOW,
693 EFX_MON_STAT_VDD08D_VSS08D_CSR,
694 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
695 EFX_MON_STAT_HOTPOINT_TEMP,
696 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
697 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
698 EFX_MON_STAT_MUM_VCC,
701 EFX_MON_STAT_0V9_A_TEMP,
704 EFX_MON_STAT_0V9_B_TEMP,
705 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
706 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
707 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
708 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
709 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
710 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
711 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
712 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
713 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
714 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
715 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
716 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
717 EFX_MON_STAT_SODIMM_VOUT,
718 EFX_MON_STAT_SODIMM_0_TEMP,
719 EFX_MON_STAT_SODIMM_1_TEMP,
720 EFX_MON_STAT_PHY0_VCC,
721 EFX_MON_STAT_PHY1_VCC,
722 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
723 EFX_MON_STAT_BOARD_FRONT_TEMP,
724 EFX_MON_STAT_BOARD_BACK_TEMP,
734 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
736 typedef enum efx_mon_stat_state_e {
737 EFX_MON_STAT_STATE_OK = 0,
738 EFX_MON_STAT_STATE_WARNING = 1,
739 EFX_MON_STAT_STATE_FATAL = 2,
740 EFX_MON_STAT_STATE_BROKEN = 3,
741 EFX_MON_STAT_STATE_NO_READING = 4,
742 } efx_mon_stat_state_t;
744 typedef struct efx_mon_stat_value_s {
747 } efx_mon_stat_value_t;
754 __in efx_mon_stat_t id);
756 #endif /* EFSYS_OPT_NAMES */
758 extern __checkReturn efx_rc_t
759 efx_mon_stats_update(
761 __in efsys_mem_t *esmp,
762 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
764 #endif /* EFSYS_OPT_MON_STATS */
768 __in efx_nic_t *enp);
772 extern __checkReturn efx_rc_t
774 __in efx_nic_t *enp);
776 #if EFSYS_OPT_PHY_LED_CONTROL
778 typedef enum efx_phy_led_mode_e {
779 EFX_PHY_LED_DEFAULT = 0,
784 } efx_phy_led_mode_t;
786 extern __checkReturn efx_rc_t
789 __in efx_phy_led_mode_t mode);
791 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
793 extern __checkReturn efx_rc_t
795 __in efx_nic_t *enp);
797 #if EFSYS_OPT_LOOPBACK
799 typedef enum efx_loopback_type_e {
800 EFX_LOOPBACK_OFF = 0,
801 EFX_LOOPBACK_DATA = 1,
802 EFX_LOOPBACK_GMAC = 2,
803 EFX_LOOPBACK_XGMII = 3,
804 EFX_LOOPBACK_XGXS = 4,
805 EFX_LOOPBACK_XAUI = 5,
806 EFX_LOOPBACK_GMII = 6,
807 EFX_LOOPBACK_SGMII = 7,
808 EFX_LOOPBACK_XGBR = 8,
809 EFX_LOOPBACK_XFI = 9,
810 EFX_LOOPBACK_XAUI_FAR = 10,
811 EFX_LOOPBACK_GMII_FAR = 11,
812 EFX_LOOPBACK_SGMII_FAR = 12,
813 EFX_LOOPBACK_XFI_FAR = 13,
814 EFX_LOOPBACK_GPHY = 14,
815 EFX_LOOPBACK_PHY_XS = 15,
816 EFX_LOOPBACK_PCS = 16,
817 EFX_LOOPBACK_PMA_PMD = 17,
818 EFX_LOOPBACK_XPORT = 18,
819 EFX_LOOPBACK_XGMII_WS = 19,
820 EFX_LOOPBACK_XAUI_WS = 20,
821 EFX_LOOPBACK_XAUI_WS_FAR = 21,
822 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
823 EFX_LOOPBACK_GMII_WS = 23,
824 EFX_LOOPBACK_XFI_WS = 24,
825 EFX_LOOPBACK_XFI_WS_FAR = 25,
826 EFX_LOOPBACK_PHYXS_WS = 26,
827 EFX_LOOPBACK_PMA_INT = 27,
828 EFX_LOOPBACK_SD_NEAR = 28,
829 EFX_LOOPBACK_SD_FAR = 29,
830 EFX_LOOPBACK_PMA_INT_WS = 30,
831 EFX_LOOPBACK_SD_FEP2_WS = 31,
832 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
833 EFX_LOOPBACK_SD_FEP_WS = 33,
834 EFX_LOOPBACK_SD_FES_WS = 34,
835 EFX_LOOPBACK_AOE_INT_NEAR = 35,
836 EFX_LOOPBACK_DATA_WS = 36,
837 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
839 } efx_loopback_type_t;
841 typedef enum efx_loopback_kind_e {
842 EFX_LOOPBACK_KIND_OFF = 0,
843 EFX_LOOPBACK_KIND_ALL,
844 EFX_LOOPBACK_KIND_MAC,
845 EFX_LOOPBACK_KIND_PHY,
847 } efx_loopback_kind_t;
851 __in efx_loopback_kind_t loopback_kind,
852 __out efx_qword_t *maskp);
854 extern __checkReturn efx_rc_t
855 efx_port_loopback_set(
857 __in efx_link_mode_t link_mode,
858 __in efx_loopback_type_t type);
862 extern __checkReturn const char *
863 efx_loopback_type_name(
865 __in efx_loopback_type_t type);
867 #endif /* EFSYS_OPT_NAMES */
869 #endif /* EFSYS_OPT_LOOPBACK */
871 extern __checkReturn efx_rc_t
874 __out_opt efx_link_mode_t *link_modep);
878 __in efx_nic_t *enp);
880 typedef enum efx_phy_cap_type_e {
881 EFX_PHY_CAP_INVALID = 0,
888 EFX_PHY_CAP_10000FDX,
892 EFX_PHY_CAP_40000FDX,
894 EFX_PHY_CAP_100000FDX,
895 EFX_PHY_CAP_25000FDX,
896 EFX_PHY_CAP_50000FDX,
897 EFX_PHY_CAP_BASER_FEC,
898 EFX_PHY_CAP_BASER_FEC_REQUESTED,
900 EFX_PHY_CAP_RS_FEC_REQUESTED,
901 EFX_PHY_CAP_25G_BASER_FEC,
902 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
904 } efx_phy_cap_type_t;
907 #define EFX_PHY_CAP_CURRENT 0x00000000
908 #define EFX_PHY_CAP_DEFAULT 0x00000001
909 #define EFX_PHY_CAP_PERM 0x00000002
915 __out uint32_t *maskp);
917 extern __checkReturn efx_rc_t
925 __out uint32_t *maskp);
927 extern __checkReturn efx_rc_t
930 __out uint32_t *ouip);
932 typedef enum efx_phy_media_type_e {
933 EFX_PHY_MEDIA_INVALID = 0,
938 EFX_PHY_MEDIA_SFP_PLUS,
939 EFX_PHY_MEDIA_BASE_T,
940 EFX_PHY_MEDIA_QSFP_PLUS,
942 } efx_phy_media_type_t;
945 * Get the type of medium currently used. If the board has ports for
946 * modules, a module is present, and we recognise the media type of
947 * the module, then this will be the media type of the module.
948 * Otherwise it will be the media type of the port.
951 efx_phy_media_type_get(
953 __out efx_phy_media_type_t *typep);
955 extern __checkReturn efx_rc_t
956 efx_phy_module_get_info(
958 __in uint8_t dev_addr,
961 __out_bcount(len) uint8_t *data);
963 #if EFSYS_OPT_PHY_STATS
965 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
966 typedef enum efx_phy_stat_e {
968 EFX_PHY_STAT_PMA_PMD_LINK_UP,
969 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
970 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
971 EFX_PHY_STAT_PMA_PMD_REV_A,
972 EFX_PHY_STAT_PMA_PMD_REV_B,
973 EFX_PHY_STAT_PMA_PMD_REV_C,
974 EFX_PHY_STAT_PMA_PMD_REV_D,
975 EFX_PHY_STAT_PCS_LINK_UP,
976 EFX_PHY_STAT_PCS_RX_FAULT,
977 EFX_PHY_STAT_PCS_TX_FAULT,
978 EFX_PHY_STAT_PCS_BER,
979 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
980 EFX_PHY_STAT_PHY_XS_LINK_UP,
981 EFX_PHY_STAT_PHY_XS_RX_FAULT,
982 EFX_PHY_STAT_PHY_XS_TX_FAULT,
983 EFX_PHY_STAT_PHY_XS_ALIGN,
984 EFX_PHY_STAT_PHY_XS_SYNC_A,
985 EFX_PHY_STAT_PHY_XS_SYNC_B,
986 EFX_PHY_STAT_PHY_XS_SYNC_C,
987 EFX_PHY_STAT_PHY_XS_SYNC_D,
988 EFX_PHY_STAT_AN_LINK_UP,
989 EFX_PHY_STAT_AN_MASTER,
990 EFX_PHY_STAT_AN_LOCAL_RX_OK,
991 EFX_PHY_STAT_AN_REMOTE_RX_OK,
992 EFX_PHY_STAT_CL22EXT_LINK_UP,
997 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
998 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
999 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1000 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1001 EFX_PHY_STAT_AN_COMPLETE,
1002 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1003 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1004 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1005 EFX_PHY_STAT_PCS_FW_VERSION_0,
1006 EFX_PHY_STAT_PCS_FW_VERSION_1,
1007 EFX_PHY_STAT_PCS_FW_VERSION_2,
1008 EFX_PHY_STAT_PCS_FW_VERSION_3,
1009 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1010 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1011 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1012 EFX_PHY_STAT_PCS_OP_MODE,
1016 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1022 __in efx_nic_t *enp,
1023 __in efx_phy_stat_t stat);
1025 #endif /* EFSYS_OPT_NAMES */
1027 #define EFX_PHY_STATS_SIZE 0x100
1029 extern __checkReturn efx_rc_t
1030 efx_phy_stats_update(
1031 __in efx_nic_t *enp,
1032 __in efsys_mem_t *esmp,
1033 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1035 #endif /* EFSYS_OPT_PHY_STATS */
1040 typedef enum efx_bist_type_e {
1041 EFX_BIST_TYPE_UNKNOWN,
1042 EFX_BIST_TYPE_PHY_NORMAL,
1043 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1044 EFX_BIST_TYPE_PHY_CABLE_LONG,
1045 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1046 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1047 EFX_BIST_TYPE_REG, /* Test the register memories */
1048 EFX_BIST_TYPE_NTYPES,
1051 typedef enum efx_bist_result_e {
1052 EFX_BIST_RESULT_UNKNOWN,
1053 EFX_BIST_RESULT_RUNNING,
1054 EFX_BIST_RESULT_PASSED,
1055 EFX_BIST_RESULT_FAILED,
1056 } efx_bist_result_t;
1058 typedef enum efx_phy_cable_status_e {
1059 EFX_PHY_CABLE_STATUS_OK,
1060 EFX_PHY_CABLE_STATUS_INVALID,
1061 EFX_PHY_CABLE_STATUS_OPEN,
1062 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1063 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1064 EFX_PHY_CABLE_STATUS_BUSY,
1065 } efx_phy_cable_status_t;
1067 typedef enum efx_bist_value_e {
1068 EFX_BIST_PHY_CABLE_LENGTH_A,
1069 EFX_BIST_PHY_CABLE_LENGTH_B,
1070 EFX_BIST_PHY_CABLE_LENGTH_C,
1071 EFX_BIST_PHY_CABLE_LENGTH_D,
1072 EFX_BIST_PHY_CABLE_STATUS_A,
1073 EFX_BIST_PHY_CABLE_STATUS_B,
1074 EFX_BIST_PHY_CABLE_STATUS_C,
1075 EFX_BIST_PHY_CABLE_STATUS_D,
1076 EFX_BIST_FAULT_CODE,
1078 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1084 EFX_BIST_MEM_EXPECT,
1085 EFX_BIST_MEM_ACTUAL,
1087 EFX_BIST_MEM_ECC_PARITY,
1088 EFX_BIST_MEM_ECC_FATAL,
1092 extern __checkReturn efx_rc_t
1093 efx_bist_enable_offline(
1094 __in efx_nic_t *enp);
1096 extern __checkReturn efx_rc_t
1098 __in efx_nic_t *enp,
1099 __in efx_bist_type_t type);
1101 extern __checkReturn efx_rc_t
1103 __in efx_nic_t *enp,
1104 __in efx_bist_type_t type,
1105 __out efx_bist_result_t *resultp,
1106 __out_opt uint32_t *value_maskp,
1107 __out_ecount_opt(count) unsigned long *valuesp,
1112 __in efx_nic_t *enp,
1113 __in efx_bist_type_t type);
1115 #endif /* EFSYS_OPT_BIST */
1117 #define EFX_FEATURE_IPV6 0x00000001
1118 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1119 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1120 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1121 #define EFX_FEATURE_MCDI 0x00000020
1122 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1123 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1124 #define EFX_FEATURE_TURBO 0x00000100
1125 #define EFX_FEATURE_MCDI_DMA 0x00000200
1126 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1127 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1128 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1129 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1130 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1132 typedef enum efx_tunnel_protocol_e {
1133 EFX_TUNNEL_PROTOCOL_NONE = 0,
1134 EFX_TUNNEL_PROTOCOL_VXLAN,
1135 EFX_TUNNEL_PROTOCOL_GENEVE,
1136 EFX_TUNNEL_PROTOCOL_NVGRE,
1138 } efx_tunnel_protocol_t;
1140 typedef enum efx_vi_window_shift_e {
1141 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1142 EFX_VI_WINDOW_SHIFT_8K = 13,
1143 EFX_VI_WINDOW_SHIFT_16K = 14,
1144 EFX_VI_WINDOW_SHIFT_64K = 16,
1145 } efx_vi_window_shift_t;
1147 typedef struct efx_nic_cfg_s {
1148 uint32_t enc_board_type;
1149 uint32_t enc_phy_type;
1151 char enc_phy_name[21];
1153 char enc_phy_revision[21];
1154 efx_mon_type_t enc_mon_type;
1155 #if EFSYS_OPT_MON_STATS
1156 uint32_t enc_mon_stat_dma_buf_size;
1157 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1159 unsigned int enc_features;
1160 efx_vi_window_shift_t enc_vi_window_shift;
1161 uint8_t enc_mac_addr[6];
1162 uint8_t enc_port; /* PHY port number */
1163 uint32_t enc_intr_vec_base;
1164 uint32_t enc_intr_limit;
1165 uint32_t enc_evq_limit;
1166 uint32_t enc_txq_limit;
1167 uint32_t enc_rxq_limit;
1168 uint32_t enc_txq_max_ndescs;
1169 uint32_t enc_buftbl_limit;
1170 uint32_t enc_piobuf_limit;
1171 uint32_t enc_piobuf_size;
1172 uint32_t enc_piobuf_min_alloc_size;
1173 uint32_t enc_evq_timer_quantum_ns;
1174 uint32_t enc_evq_timer_max_us;
1175 uint32_t enc_clk_mult;
1176 uint32_t enc_rx_prefix_size;
1177 uint32_t enc_rx_buf_align_start;
1178 uint32_t enc_rx_buf_align_end;
1179 uint32_t enc_rx_scale_max_exclusive_contexts;
1180 #if EFSYS_OPT_LOOPBACK
1181 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1182 #endif /* EFSYS_OPT_LOOPBACK */
1183 #if EFSYS_OPT_PHY_FLAGS
1184 uint32_t enc_phy_flags_mask;
1185 #endif /* EFSYS_OPT_PHY_FLAGS */
1186 #if EFSYS_OPT_PHY_LED_CONTROL
1187 uint32_t enc_led_mask;
1188 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1189 #if EFSYS_OPT_PHY_STATS
1190 uint64_t enc_phy_stat_mask;
1191 #endif /* EFSYS_OPT_PHY_STATS */
1193 uint8_t enc_mcdi_mdio_channel;
1194 #if EFSYS_OPT_PHY_STATS
1195 uint32_t enc_mcdi_phy_stat_mask;
1196 #endif /* EFSYS_OPT_PHY_STATS */
1197 #if EFSYS_OPT_MON_STATS
1198 uint32_t *enc_mcdi_sensor_maskp;
1199 uint32_t enc_mcdi_sensor_mask_size;
1200 #endif /* EFSYS_OPT_MON_STATS */
1201 #endif /* EFSYS_OPT_MCDI */
1203 uint32_t enc_bist_mask;
1204 #endif /* EFSYS_OPT_BIST */
1205 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1208 uint32_t enc_privilege_mask;
1209 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1210 boolean_t enc_bug26807_workaround;
1211 boolean_t enc_bug35388_workaround;
1212 boolean_t enc_bug41750_workaround;
1213 boolean_t enc_bug61265_workaround;
1214 boolean_t enc_rx_batching_enabled;
1215 /* Maximum number of descriptors completed in an rx event. */
1216 uint32_t enc_rx_batch_max;
1217 /* Number of rx descriptors the hardware requires for a push. */
1218 uint32_t enc_rx_push_align;
1219 /* Maximum amount of data in DMA descriptor */
1220 uint32_t enc_tx_dma_desc_size_max;
1222 * Boundary which DMA descriptor data must not cross or 0 if no
1225 uint32_t enc_tx_dma_desc_boundary;
1227 * Maximum number of bytes into the packet the TCP header can start for
1228 * the hardware to apply TSO packet edits.
1230 uint32_t enc_tx_tso_tcp_header_offset_limit;
1231 boolean_t enc_fw_assisted_tso_enabled;
1232 boolean_t enc_fw_assisted_tso_v2_enabled;
1233 /* Number of TSO contexts on the NIC (FATSOv2) */
1234 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1235 boolean_t enc_hw_tx_insert_vlan_enabled;
1236 /* Number of PFs on the NIC */
1237 uint32_t enc_hw_pf_count;
1238 /* Datapath firmware vadapter/vport/vswitch support */
1239 boolean_t enc_datapath_cap_evb;
1240 boolean_t enc_rx_disable_scatter_supported;
1241 boolean_t enc_allow_set_mac_with_installed_filters;
1242 boolean_t enc_enhanced_set_mac_supported;
1243 boolean_t enc_init_evq_v2_supported;
1244 boolean_t enc_rx_packed_stream_supported;
1245 boolean_t enc_rx_var_packed_stream_supported;
1246 boolean_t enc_pm_and_rxdp_counters;
1247 boolean_t enc_mac_stats_40g_tx_size_bins;
1248 uint32_t enc_tunnel_encapsulations_supported;
1250 * NIC global maximum for unique UDP tunnel ports shared by all
1253 uint32_t enc_tunnel_config_udp_entries_max;
1254 /* External port identifier */
1255 uint8_t enc_external_port;
1256 uint32_t enc_mcdi_max_payload_length;
1257 /* VPD may be per-PF or global */
1258 boolean_t enc_vpd_is_global;
1259 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1260 uint32_t enc_required_pcie_bandwidth_mbps;
1261 uint32_t enc_max_pcie_link_gen;
1262 /* Firmware verifies integrity of NVRAM updates */
1263 uint32_t enc_nvram_update_verify_result_supported;
1264 /* Firmware support for extended MAC_STATS buffer */
1265 uint32_t enc_mac_stats_nstats;
1266 boolean_t enc_fec_counters;
1269 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1270 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1272 #define EFX_PCI_FUNCTION(_encp) \
1273 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1275 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1277 extern const efx_nic_cfg_t *
1279 __in efx_nic_t *enp);
1281 typedef struct efx_nic_fw_info_s {
1282 /* Basic FW version information */
1283 uint16_t enfi_mc_fw_version[4];
1285 * If datapath capabilities can be detected,
1286 * additional FW information is to be shown
1288 boolean_t enfi_dpcpu_fw_ids_valid;
1289 /* Rx and Tx datapath CPU FW IDs */
1290 uint16_t enfi_rx_dpcpu_fw_id;
1291 uint16_t enfi_tx_dpcpu_fw_id;
1292 } efx_nic_fw_info_t;
1294 extern __checkReturn efx_rc_t
1295 efx_nic_get_fw_version(
1296 __in efx_nic_t *enp,
1297 __out efx_nic_fw_info_t *enfip);
1299 /* Driver resource limits (minimum required/maximum usable). */
1300 typedef struct efx_drv_limits_s {
1301 uint32_t edl_min_evq_count;
1302 uint32_t edl_max_evq_count;
1304 uint32_t edl_min_rxq_count;
1305 uint32_t edl_max_rxq_count;
1307 uint32_t edl_min_txq_count;
1308 uint32_t edl_max_txq_count;
1310 /* PIO blocks (sub-allocated from piobuf) */
1311 uint32_t edl_min_pio_alloc_size;
1312 uint32_t edl_max_pio_alloc_count;
1315 extern __checkReturn efx_rc_t
1316 efx_nic_set_drv_limits(
1317 __inout efx_nic_t *enp,
1318 __in efx_drv_limits_t *edlp);
1320 typedef enum efx_nic_region_e {
1321 EFX_REGION_VI, /* Memory BAR UC mapping */
1322 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1325 extern __checkReturn efx_rc_t
1326 efx_nic_get_bar_region(
1327 __in efx_nic_t *enp,
1328 __in efx_nic_region_t region,
1329 __out uint32_t *offsetp,
1330 __out size_t *sizep);
1332 extern __checkReturn efx_rc_t
1333 efx_nic_get_vi_pool(
1334 __in efx_nic_t *enp,
1335 __out uint32_t *evq_countp,
1336 __out uint32_t *rxq_countp,
1337 __out uint32_t *txq_countp);
1342 typedef enum efx_vpd_tag_e {
1349 typedef uint16_t efx_vpd_keyword_t;
1351 typedef struct efx_vpd_value_s {
1352 efx_vpd_tag_t evv_tag;
1353 efx_vpd_keyword_t evv_keyword;
1355 uint8_t evv_value[0x100];
1359 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1361 extern __checkReturn efx_rc_t
1363 __in efx_nic_t *enp);
1365 extern __checkReturn efx_rc_t
1367 __in efx_nic_t *enp,
1368 __out size_t *sizep);
1370 extern __checkReturn efx_rc_t
1372 __in efx_nic_t *enp,
1373 __out_bcount(size) caddr_t data,
1376 extern __checkReturn efx_rc_t
1378 __in efx_nic_t *enp,
1379 __in_bcount(size) caddr_t data,
1382 extern __checkReturn efx_rc_t
1384 __in efx_nic_t *enp,
1385 __in_bcount(size) caddr_t data,
1388 extern __checkReturn efx_rc_t
1390 __in efx_nic_t *enp,
1391 __in_bcount(size) caddr_t data,
1393 __inout efx_vpd_value_t *evvp);
1395 extern __checkReturn efx_rc_t
1397 __in efx_nic_t *enp,
1398 __inout_bcount(size) caddr_t data,
1400 __in efx_vpd_value_t *evvp);
1402 extern __checkReturn efx_rc_t
1404 __in efx_nic_t *enp,
1405 __inout_bcount(size) caddr_t data,
1407 __out efx_vpd_value_t *evvp,
1408 __inout unsigned int *contp);
1410 extern __checkReturn efx_rc_t
1412 __in efx_nic_t *enp,
1413 __in_bcount(size) caddr_t data,
1418 __in efx_nic_t *enp);
1420 #endif /* EFSYS_OPT_VPD */
1426 typedef enum efx_nvram_type_e {
1427 EFX_NVRAM_INVALID = 0,
1429 EFX_NVRAM_BOOTROM_CFG,
1430 EFX_NVRAM_MC_FIRMWARE,
1431 EFX_NVRAM_MC_GOLDEN,
1437 EFX_NVRAM_FPGA_BACKUP,
1438 EFX_NVRAM_DYNAMIC_CFG,
1441 EFX_NVRAM_MUM_FIRMWARE,
1445 extern __checkReturn efx_rc_t
1447 __in efx_nic_t *enp);
1451 extern __checkReturn efx_rc_t
1453 __in efx_nic_t *enp);
1455 #endif /* EFSYS_OPT_DIAG */
1457 extern __checkReturn efx_rc_t
1459 __in efx_nic_t *enp,
1460 __in efx_nvram_type_t type,
1461 __out size_t *sizep);
1463 extern __checkReturn efx_rc_t
1465 __in efx_nic_t *enp,
1466 __in efx_nvram_type_t type,
1467 __out_opt size_t *pref_chunkp);
1469 extern __checkReturn efx_rc_t
1470 efx_nvram_rw_finish(
1471 __in efx_nic_t *enp,
1472 __in efx_nvram_type_t type,
1473 __out_opt uint32_t *verify_resultp);
1475 extern __checkReturn efx_rc_t
1476 efx_nvram_get_version(
1477 __in efx_nic_t *enp,
1478 __in efx_nvram_type_t type,
1479 __out uint32_t *subtypep,
1480 __out_ecount(4) uint16_t version[4]);
1482 extern __checkReturn efx_rc_t
1483 efx_nvram_read_chunk(
1484 __in efx_nic_t *enp,
1485 __in efx_nvram_type_t type,
1486 __in unsigned int offset,
1487 __out_bcount(size) caddr_t data,
1490 extern __checkReturn efx_rc_t
1491 efx_nvram_read_backup(
1492 __in efx_nic_t *enp,
1493 __in efx_nvram_type_t type,
1494 __in unsigned int offset,
1495 __out_bcount(size) caddr_t data,
1498 extern __checkReturn efx_rc_t
1499 efx_nvram_set_version(
1500 __in efx_nic_t *enp,
1501 __in efx_nvram_type_t type,
1502 __in_ecount(4) uint16_t version[4]);
1504 extern __checkReturn efx_rc_t
1506 __in efx_nic_t *enp,
1507 __in efx_nvram_type_t type,
1508 __in_bcount(partn_size) caddr_t partn_data,
1509 __in size_t partn_size);
1511 extern __checkReturn efx_rc_t
1513 __in efx_nic_t *enp,
1514 __in efx_nvram_type_t type);
1516 extern __checkReturn efx_rc_t
1517 efx_nvram_write_chunk(
1518 __in efx_nic_t *enp,
1519 __in efx_nvram_type_t type,
1520 __in unsigned int offset,
1521 __in_bcount(size) caddr_t data,
1526 __in efx_nic_t *enp);
1528 #endif /* EFSYS_OPT_NVRAM */
1530 #if EFSYS_OPT_BOOTCFG
1532 /* Report size and offset of bootcfg sector in NVRAM partition. */
1533 extern __checkReturn efx_rc_t
1534 efx_bootcfg_sector_info(
1535 __in efx_nic_t *enp,
1537 __out_opt uint32_t *sector_countp,
1538 __out size_t *offsetp,
1539 __out size_t *max_sizep);
1542 * Copy bootcfg sector data to a target buffer which may differ in size.
1543 * Optionally corrects format errors in source buffer.
1546 efx_bootcfg_copy_sector(
1547 __in efx_nic_t *enp,
1548 __inout_bcount(sector_length)
1550 __in size_t sector_length,
1551 __out_bcount(data_size) uint8_t *data,
1552 __in size_t data_size,
1553 __in boolean_t handle_format_errors);
1557 __in efx_nic_t *enp,
1558 __out_bcount(size) uint8_t *data,
1563 __in efx_nic_t *enp,
1564 __in_bcount(size) uint8_t *data,
1567 #endif /* EFSYS_OPT_BOOTCFG */
1571 typedef enum efx_pattern_type_t {
1572 EFX_PATTERN_BYTE_INCREMENT = 0,
1573 EFX_PATTERN_ALL_THE_SAME,
1574 EFX_PATTERN_BIT_ALTERNATE,
1575 EFX_PATTERN_BYTE_ALTERNATE,
1576 EFX_PATTERN_BYTE_CHANGING,
1577 EFX_PATTERN_BIT_SWEEP,
1579 } efx_pattern_type_t;
1582 (*efx_sram_pattern_fn_t)(
1584 __in boolean_t negate,
1585 __out efx_qword_t *eqp);
1587 extern __checkReturn efx_rc_t
1589 __in efx_nic_t *enp,
1590 __in efx_pattern_type_t type);
1592 #endif /* EFSYS_OPT_DIAG */
1594 extern __checkReturn efx_rc_t
1595 efx_sram_buf_tbl_set(
1596 __in efx_nic_t *enp,
1598 __in efsys_mem_t *esmp,
1602 efx_sram_buf_tbl_clear(
1603 __in efx_nic_t *enp,
1607 #define EFX_BUF_TBL_SIZE 0x20000
1609 #define EFX_BUF_SIZE 4096
1613 typedef struct efx_evq_s efx_evq_t;
1615 #if EFSYS_OPT_QSTATS
1617 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1618 typedef enum efx_ev_qstat_e {
1624 EV_RX_PAUSE_FRM_ERR,
1625 EV_RX_BUF_OWNER_ID_ERR,
1626 EV_RX_IPV4_HDR_CHKSUM_ERR,
1627 EV_RX_TCP_UDP_CHKSUM_ERR,
1631 EV_RX_MCAST_HASH_MATCH,
1648 EV_DRIVER_SRM_UPD_DONE,
1649 EV_DRIVER_TX_DESCQ_FLS_DONE,
1650 EV_DRIVER_RX_DESCQ_FLS_DONE,
1651 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1652 EV_DRIVER_RX_DSC_ERROR,
1653 EV_DRIVER_TX_DSC_ERROR,
1659 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1661 #endif /* EFSYS_OPT_QSTATS */
1663 extern __checkReturn efx_rc_t
1665 __in efx_nic_t *enp);
1669 __in efx_nic_t *enp);
1671 #define EFX_EVQ_MAXNEVS 32768
1672 #define EFX_EVQ_MINNEVS 512
1674 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1675 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1677 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1678 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1679 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1680 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1682 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1683 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1684 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1686 extern __checkReturn efx_rc_t
1688 __in efx_nic_t *enp,
1689 __in unsigned int index,
1690 __in efsys_mem_t *esmp,
1694 __in uint32_t flags,
1695 __deref_out efx_evq_t **eepp);
1699 __in efx_evq_t *eep,
1700 __in uint16_t data);
1702 typedef __checkReturn boolean_t
1703 (*efx_initialized_ev_t)(
1704 __in_opt void *arg);
1706 #define EFX_PKT_UNICAST 0x0004
1707 #define EFX_PKT_START 0x0008
1709 #define EFX_PKT_VLAN_TAGGED 0x0010
1710 #define EFX_CKSUM_TCPUDP 0x0020
1711 #define EFX_CKSUM_IPV4 0x0040
1712 #define EFX_PKT_CONT 0x0080
1714 #define EFX_CHECK_VLAN 0x0100
1715 #define EFX_PKT_TCP 0x0200
1716 #define EFX_PKT_UDP 0x0400
1717 #define EFX_PKT_IPV4 0x0800
1719 #define EFX_PKT_IPV6 0x1000
1720 #define EFX_PKT_PREFIX_LEN 0x2000
1721 #define EFX_ADDR_MISMATCH 0x4000
1722 #define EFX_DISCARD 0x8000
1725 * The following flags are used only for packed stream
1726 * mode. The values for the flags are reused to fit into 16 bit,
1727 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1728 * packed stream mode
1730 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1731 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1734 #define EFX_EV_RX_NLABELS 32
1735 #define EFX_EV_TX_NLABELS 32
1737 typedef __checkReturn boolean_t
1740 __in uint32_t label,
1743 __in uint16_t flags);
1745 #if EFSYS_OPT_RX_PACKED_STREAM
1748 * Packed stream mode is documented in SF-112241-TC.
1749 * The general idea is that, instead of putting each incoming
1750 * packet into a separate buffer which is specified in a RX
1751 * descriptor, a large buffer is provided to the hardware and
1752 * packets are put there in a continuous stream.
1753 * The main advantage of such an approach is that RX queue refilling
1754 * happens much less frequently.
1757 typedef __checkReturn boolean_t
1760 __in uint32_t label,
1762 __in uint32_t pkt_count,
1763 __in uint16_t flags);
1767 typedef __checkReturn boolean_t
1770 __in uint32_t label,
1773 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1774 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1775 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1776 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1777 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1778 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1779 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1780 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1781 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1783 typedef __checkReturn boolean_t
1784 (*efx_exception_ev_t)(
1786 __in uint32_t label,
1787 __in uint32_t data);
1789 typedef __checkReturn boolean_t
1790 (*efx_rxq_flush_done_ev_t)(
1792 __in uint32_t rxq_index);
1794 typedef __checkReturn boolean_t
1795 (*efx_rxq_flush_failed_ev_t)(
1797 __in uint32_t rxq_index);
1799 typedef __checkReturn boolean_t
1800 (*efx_txq_flush_done_ev_t)(
1802 __in uint32_t txq_index);
1804 typedef __checkReturn boolean_t
1805 (*efx_software_ev_t)(
1807 __in uint16_t magic);
1809 typedef __checkReturn boolean_t
1812 __in uint32_t code);
1814 #define EFX_SRAM_CLEAR 0
1815 #define EFX_SRAM_UPDATE 1
1816 #define EFX_SRAM_ILLEGAL_CLEAR 2
1818 typedef __checkReturn boolean_t
1819 (*efx_wake_up_ev_t)(
1821 __in uint32_t label);
1823 typedef __checkReturn boolean_t
1826 __in uint32_t label);
1828 typedef __checkReturn boolean_t
1829 (*efx_link_change_ev_t)(
1831 __in efx_link_mode_t link_mode);
1833 #if EFSYS_OPT_MON_STATS
1835 typedef __checkReturn boolean_t
1836 (*efx_monitor_ev_t)(
1838 __in efx_mon_stat_t id,
1839 __in efx_mon_stat_value_t value);
1841 #endif /* EFSYS_OPT_MON_STATS */
1843 #if EFSYS_OPT_MAC_STATS
1845 typedef __checkReturn boolean_t
1846 (*efx_mac_stats_ev_t)(
1848 __in uint32_t generation);
1850 #endif /* EFSYS_OPT_MAC_STATS */
1852 typedef struct efx_ev_callbacks_s {
1853 efx_initialized_ev_t eec_initialized;
1855 #if EFSYS_OPT_RX_PACKED_STREAM
1856 efx_rx_ps_ev_t eec_rx_ps;
1859 efx_exception_ev_t eec_exception;
1860 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1861 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1862 efx_txq_flush_done_ev_t eec_txq_flush_done;
1863 efx_software_ev_t eec_software;
1864 efx_sram_ev_t eec_sram;
1865 efx_wake_up_ev_t eec_wake_up;
1866 efx_timer_ev_t eec_timer;
1867 efx_link_change_ev_t eec_link_change;
1868 #if EFSYS_OPT_MON_STATS
1869 efx_monitor_ev_t eec_monitor;
1870 #endif /* EFSYS_OPT_MON_STATS */
1871 #if EFSYS_OPT_MAC_STATS
1872 efx_mac_stats_ev_t eec_mac_stats;
1873 #endif /* EFSYS_OPT_MAC_STATS */
1874 } efx_ev_callbacks_t;
1876 extern __checkReturn boolean_t
1878 __in efx_evq_t *eep,
1879 __in unsigned int count);
1881 #if EFSYS_OPT_EV_PREFETCH
1885 __in efx_evq_t *eep,
1886 __in unsigned int count);
1888 #endif /* EFSYS_OPT_EV_PREFETCH */
1892 __in efx_evq_t *eep,
1893 __inout unsigned int *countp,
1894 __in const efx_ev_callbacks_t *eecp,
1895 __in_opt void *arg);
1897 extern __checkReturn efx_rc_t
1898 efx_ev_usecs_to_ticks(
1899 __in efx_nic_t *enp,
1900 __in unsigned int usecs,
1901 __out unsigned int *ticksp);
1903 extern __checkReturn efx_rc_t
1905 __in efx_evq_t *eep,
1906 __in unsigned int us);
1908 extern __checkReturn efx_rc_t
1910 __in efx_evq_t *eep,
1911 __in unsigned int count);
1913 #if EFSYS_OPT_QSTATS
1919 __in efx_nic_t *enp,
1920 __in unsigned int id);
1922 #endif /* EFSYS_OPT_NAMES */
1925 efx_ev_qstats_update(
1926 __in efx_evq_t *eep,
1927 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1929 #endif /* EFSYS_OPT_QSTATS */
1933 __in efx_evq_t *eep);
1937 extern __checkReturn efx_rc_t
1939 __inout efx_nic_t *enp);
1943 __in efx_nic_t *enp);
1945 #if EFSYS_OPT_RX_SCATTER
1946 __checkReturn efx_rc_t
1947 efx_rx_scatter_enable(
1948 __in efx_nic_t *enp,
1949 __in unsigned int buf_size);
1950 #endif /* EFSYS_OPT_RX_SCATTER */
1952 /* Handle to represent use of the default RSS context. */
1953 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1955 #if EFSYS_OPT_RX_SCALE
1957 typedef enum efx_rx_hash_alg_e {
1958 EFX_RX_HASHALG_LFSR = 0,
1959 EFX_RX_HASHALG_TOEPLITZ
1960 } efx_rx_hash_alg_t;
1962 #define EFX_RX_HASH_IPV4 (1U << 0)
1963 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1964 #define EFX_RX_HASH_IPV6 (1U << 2)
1965 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1967 typedef unsigned int efx_rx_hash_type_t;
1969 typedef enum efx_rx_hash_support_e {
1970 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1971 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1972 } efx_rx_hash_support_t;
1974 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1975 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1976 #define EFX_MAXRSS 64 /* RX indirection entry range */
1977 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1979 typedef enum efx_rx_scale_context_type_e {
1980 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1981 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1982 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1983 } efx_rx_scale_context_type_t;
1985 extern __checkReturn efx_rc_t
1986 efx_rx_hash_default_support_get(
1987 __in efx_nic_t *enp,
1988 __out efx_rx_hash_support_t *supportp);
1991 extern __checkReturn efx_rc_t
1992 efx_rx_scale_default_support_get(
1993 __in efx_nic_t *enp,
1994 __out efx_rx_scale_context_type_t *typep);
1996 extern __checkReturn efx_rc_t
1997 efx_rx_scale_context_alloc(
1998 __in efx_nic_t *enp,
1999 __in efx_rx_scale_context_type_t type,
2000 __in uint32_t num_queues,
2001 __out uint32_t *rss_contextp);
2003 extern __checkReturn efx_rc_t
2004 efx_rx_scale_context_free(
2005 __in efx_nic_t *enp,
2006 __in uint32_t rss_context);
2008 extern __checkReturn efx_rc_t
2009 efx_rx_scale_mode_set(
2010 __in efx_nic_t *enp,
2011 __in uint32_t rss_context,
2012 __in efx_rx_hash_alg_t alg,
2013 __in efx_rx_hash_type_t type,
2014 __in boolean_t insert);
2016 extern __checkReturn efx_rc_t
2017 efx_rx_scale_tbl_set(
2018 __in efx_nic_t *enp,
2019 __in uint32_t rss_context,
2020 __in_ecount(n) unsigned int *table,
2023 extern __checkReturn efx_rc_t
2024 efx_rx_scale_key_set(
2025 __in efx_nic_t *enp,
2026 __in uint32_t rss_context,
2027 __in_ecount(n) uint8_t *key,
2030 extern __checkReturn uint32_t
2031 efx_pseudo_hdr_hash_get(
2032 __in efx_rxq_t *erp,
2033 __in efx_rx_hash_alg_t func,
2034 __in uint8_t *buffer);
2036 #endif /* EFSYS_OPT_RX_SCALE */
2038 extern __checkReturn efx_rc_t
2039 efx_pseudo_hdr_pkt_length_get(
2040 __in efx_rxq_t *erp,
2041 __in uint8_t *buffer,
2042 __out uint16_t *pkt_lengthp);
2044 #define EFX_RXQ_MAXNDESCS 4096
2045 #define EFX_RXQ_MINNDESCS 512
2047 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2048 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2049 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2050 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2052 typedef enum efx_rxq_type_e {
2053 EFX_RXQ_TYPE_DEFAULT,
2054 EFX_RXQ_TYPE_PACKED_STREAM,
2059 * Dummy flag to be used instead of 0 to make it clear that the argument
2060 * is receive queue flags.
2062 #define EFX_RXQ_FLAG_NONE 0x0
2063 #define EFX_RXQ_FLAG_SCATTER 0x1
2065 * If tunnels are supported and Rx event can provide information about
2066 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2067 * full-feature firmware variant running), outer classes are requested by
2068 * default. However, if the driver supports tunnels, the flag allows to
2069 * request inner classes which are required to be able to interpret inner
2070 * Rx checksum offload results.
2072 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2074 extern __checkReturn efx_rc_t
2076 __in efx_nic_t *enp,
2077 __in unsigned int index,
2078 __in unsigned int label,
2079 __in efx_rxq_type_t type,
2080 __in efsys_mem_t *esmp,
2083 __in unsigned int flags,
2084 __in efx_evq_t *eep,
2085 __deref_out efx_rxq_t **erpp);
2087 #if EFSYS_OPT_RX_PACKED_STREAM
2089 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2090 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2091 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2092 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2093 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2095 extern __checkReturn efx_rc_t
2096 efx_rx_qcreate_packed_stream(
2097 __in efx_nic_t *enp,
2098 __in unsigned int index,
2099 __in unsigned int label,
2100 __in uint32_t ps_buf_size,
2101 __in efsys_mem_t *esmp,
2103 __in efx_evq_t *eep,
2104 __deref_out efx_rxq_t **erpp);
2108 typedef struct efx_buffer_s {
2109 efsys_dma_addr_t eb_addr;
2114 typedef struct efx_desc_s {
2120 __in efx_rxq_t *erp,
2121 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2123 __in unsigned int ndescs,
2124 __in unsigned int completed,
2125 __in unsigned int added);
2129 __in efx_rxq_t *erp,
2130 __in unsigned int added,
2131 __inout unsigned int *pushedp);
2133 #if EFSYS_OPT_RX_PACKED_STREAM
2136 efx_rx_qpush_ps_credits(
2137 __in efx_rxq_t *erp);
2139 extern __checkReturn uint8_t *
2140 efx_rx_qps_packet_info(
2141 __in efx_rxq_t *erp,
2142 __in uint8_t *buffer,
2143 __in uint32_t buffer_length,
2144 __in uint32_t current_offset,
2145 __out uint16_t *lengthp,
2146 __out uint32_t *next_offsetp,
2147 __out uint32_t *timestamp);
2150 extern __checkReturn efx_rc_t
2152 __in efx_rxq_t *erp);
2156 __in efx_rxq_t *erp);
2160 __in efx_rxq_t *erp);
2164 typedef struct efx_txq_s efx_txq_t;
2166 #if EFSYS_OPT_QSTATS
2168 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2169 typedef enum efx_tx_qstat_e {
2175 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2177 #endif /* EFSYS_OPT_QSTATS */
2179 extern __checkReturn efx_rc_t
2181 __in efx_nic_t *enp);
2185 __in efx_nic_t *enp);
2187 #define EFX_TXQ_MINNDESCS 512
2189 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2190 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2191 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2193 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2195 #define EFX_TXQ_CKSUM_IPV4 0x0001
2196 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2197 #define EFX_TXQ_FATSOV2 0x0004
2198 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2199 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2201 extern __checkReturn efx_rc_t
2203 __in efx_nic_t *enp,
2204 __in unsigned int index,
2205 __in unsigned int label,
2206 __in efsys_mem_t *esmp,
2209 __in uint16_t flags,
2210 __in efx_evq_t *eep,
2211 __deref_out efx_txq_t **etpp,
2212 __out unsigned int *addedp);
2214 extern __checkReturn efx_rc_t
2216 __in efx_txq_t *etp,
2217 __in_ecount(ndescs) efx_buffer_t *eb,
2218 __in unsigned int ndescs,
2219 __in unsigned int completed,
2220 __inout unsigned int *addedp);
2222 extern __checkReturn efx_rc_t
2224 __in efx_txq_t *etp,
2225 __in unsigned int ns);
2229 __in efx_txq_t *etp,
2230 __in unsigned int added,
2231 __in unsigned int pushed);
2233 extern __checkReturn efx_rc_t
2235 __in efx_txq_t *etp);
2239 __in efx_txq_t *etp);
2241 extern __checkReturn efx_rc_t
2243 __in efx_txq_t *etp);
2246 efx_tx_qpio_disable(
2247 __in efx_txq_t *etp);
2249 extern __checkReturn efx_rc_t
2251 __in efx_txq_t *etp,
2252 __in_ecount(buf_length) uint8_t *buffer,
2253 __in size_t buf_length,
2254 __in size_t pio_buf_offset);
2256 extern __checkReturn efx_rc_t
2258 __in efx_txq_t *etp,
2259 __in size_t pkt_length,
2260 __in unsigned int completed,
2261 __inout unsigned int *addedp);
2263 extern __checkReturn efx_rc_t
2265 __in efx_txq_t *etp,
2266 __in_ecount(n) efx_desc_t *ed,
2267 __in unsigned int n,
2268 __in unsigned int completed,
2269 __inout unsigned int *addedp);
2272 efx_tx_qdesc_dma_create(
2273 __in efx_txq_t *etp,
2274 __in efsys_dma_addr_t addr,
2277 __out efx_desc_t *edp);
2280 efx_tx_qdesc_tso_create(
2281 __in efx_txq_t *etp,
2282 __in uint16_t ipv4_id,
2283 __in uint32_t tcp_seq,
2284 __in uint8_t tcp_flags,
2285 __out efx_desc_t *edp);
2287 /* Number of FATSOv2 option descriptors */
2288 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2290 /* Maximum number of DMA segments per TSO packet (not superframe) */
2291 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2294 efx_tx_qdesc_tso2_create(
2295 __in efx_txq_t *etp,
2296 __in uint16_t ipv4_id,
2297 __in uint32_t tcp_seq,
2298 __in uint16_t tcp_mss,
2299 __out_ecount(count) efx_desc_t *edp,
2303 efx_tx_qdesc_vlantci_create(
2304 __in efx_txq_t *etp,
2306 __out efx_desc_t *edp);
2309 efx_tx_qdesc_checksum_create(
2310 __in efx_txq_t *etp,
2311 __in uint16_t flags,
2312 __out efx_desc_t *edp);
2314 #if EFSYS_OPT_QSTATS
2320 __in efx_nic_t *etp,
2321 __in unsigned int id);
2323 #endif /* EFSYS_OPT_NAMES */
2326 efx_tx_qstats_update(
2327 __in efx_txq_t *etp,
2328 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2330 #endif /* EFSYS_OPT_QSTATS */
2334 __in efx_txq_t *etp);
2339 #if EFSYS_OPT_FILTER
2341 #define EFX_ETHER_TYPE_IPV4 0x0800
2342 #define EFX_ETHER_TYPE_IPV6 0x86DD
2344 #define EFX_IPPROTO_TCP 6
2345 #define EFX_IPPROTO_UDP 17
2346 #define EFX_IPPROTO_GRE 47
2348 /* Use RSS to spread across multiple queues */
2349 #define EFX_FILTER_FLAG_RX_RSS 0x01
2350 /* Enable RX scatter */
2351 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2353 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2354 * May only be set by the filter implementation for each type.
2355 * A removal request will restore the automatic filter in its place.
2357 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2358 /* Filter is for RX */
2359 #define EFX_FILTER_FLAG_RX 0x08
2360 /* Filter is for TX */
2361 #define EFX_FILTER_FLAG_TX 0x10
2363 typedef uint8_t efx_filter_flags_t;
2366 * Flags which specify the fields to match on. The values are the same as in the
2367 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2370 /* Match by remote IP host address */
2371 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2372 /* Match by local IP host address */
2373 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2374 /* Match by remote MAC address */
2375 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2376 /* Match by remote TCP/UDP port */
2377 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2378 /* Match by remote TCP/UDP port */
2379 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2380 /* Match by local TCP/UDP port */
2381 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2382 /* Match by Ether-type */
2383 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2384 /* Match by inner VLAN ID */
2385 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2386 /* Match by outer VLAN ID */
2387 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2388 /* Match by IP transport protocol */
2389 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2390 /* For encapsulated packets, match all multicast inner frames */
2391 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2392 /* For encapsulated packets, match all unicast inner frames */
2393 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2394 /* Match otherwise-unmatched multicast and broadcast packets */
2395 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2396 /* Match otherwise-unmatched unicast packets */
2397 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2399 typedef uint32_t efx_filter_match_flags_t;
2401 typedef enum efx_filter_priority_s {
2402 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2403 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2404 * address list or hardware
2405 * requirements. This may only be used
2406 * by the filter implementation for
2408 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2409 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2410 * client (e.g. SR-IOV, HyperV VMQ etc.)
2412 } efx_filter_priority_t;
2415 * FIXME: All these fields are assumed to be in little-endian byte order.
2416 * It may be better for some to be big-endian. See bug42804.
2419 typedef struct efx_filter_spec_s {
2420 efx_filter_match_flags_t efs_match_flags;
2421 uint8_t efs_priority;
2422 efx_filter_flags_t efs_flags;
2423 uint16_t efs_dmaq_id;
2424 uint32_t efs_rss_context;
2425 uint16_t efs_outer_vid;
2426 uint16_t efs_inner_vid;
2427 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2428 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2429 uint16_t efs_ether_type;
2430 uint8_t efs_ip_proto;
2431 efx_tunnel_protocol_t efs_encap_type;
2432 uint16_t efs_loc_port;
2433 uint16_t efs_rem_port;
2434 efx_oword_t efs_rem_host;
2435 efx_oword_t efs_loc_host;
2436 } efx_filter_spec_t;
2439 /* Default values for use in filter specifications */
2440 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2441 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2443 extern __checkReturn efx_rc_t
2445 __in efx_nic_t *enp);
2449 __in efx_nic_t *enp);
2451 extern __checkReturn efx_rc_t
2453 __in efx_nic_t *enp,
2454 __inout efx_filter_spec_t *spec);
2456 extern __checkReturn efx_rc_t
2458 __in efx_nic_t *enp,
2459 __inout efx_filter_spec_t *spec);
2461 extern __checkReturn efx_rc_t
2463 __in efx_nic_t *enp);
2465 extern __checkReturn efx_rc_t
2466 efx_filter_supported_filters(
2467 __in efx_nic_t *enp,
2468 __out_ecount(buffer_length) uint32_t *buffer,
2469 __in size_t buffer_length,
2470 __out size_t *list_lengthp);
2473 efx_filter_spec_init_rx(
2474 __out efx_filter_spec_t *spec,
2475 __in efx_filter_priority_t priority,
2476 __in efx_filter_flags_t flags,
2477 __in efx_rxq_t *erp);
2480 efx_filter_spec_init_tx(
2481 __out efx_filter_spec_t *spec,
2482 __in efx_txq_t *etp);
2484 extern __checkReturn efx_rc_t
2485 efx_filter_spec_set_ipv4_local(
2486 __inout efx_filter_spec_t *spec,
2489 __in uint16_t port);
2491 extern __checkReturn efx_rc_t
2492 efx_filter_spec_set_ipv4_full(
2493 __inout efx_filter_spec_t *spec,
2495 __in uint32_t lhost,
2496 __in uint16_t lport,
2497 __in uint32_t rhost,
2498 __in uint16_t rport);
2500 extern __checkReturn efx_rc_t
2501 efx_filter_spec_set_eth_local(
2502 __inout efx_filter_spec_t *spec,
2504 __in const uint8_t *addr);
2507 efx_filter_spec_set_ether_type(
2508 __inout efx_filter_spec_t *spec,
2509 __in uint16_t ether_type);
2511 extern __checkReturn efx_rc_t
2512 efx_filter_spec_set_uc_def(
2513 __inout efx_filter_spec_t *spec);
2515 extern __checkReturn efx_rc_t
2516 efx_filter_spec_set_mc_def(
2517 __inout efx_filter_spec_t *spec);
2519 typedef enum efx_filter_inner_frame_match_e {
2520 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2521 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2522 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2523 } efx_filter_inner_frame_match_t;
2525 extern __checkReturn efx_rc_t
2526 efx_filter_spec_set_encap_type(
2527 __inout efx_filter_spec_t *spec,
2528 __in efx_tunnel_protocol_t encap_type,
2529 __in efx_filter_inner_frame_match_t inner_frame_match);
2531 #if EFSYS_OPT_RX_SCALE
2532 extern __checkReturn efx_rc_t
2533 efx_filter_spec_set_rss_context(
2534 __inout efx_filter_spec_t *spec,
2535 __in uint32_t rss_context);
2537 #endif /* EFSYS_OPT_FILTER */
2541 extern __checkReturn uint32_t
2543 __in_ecount(count) uint32_t const *input,
2545 __in uint32_t init);
2547 extern __checkReturn uint32_t
2549 __in_ecount(length) uint8_t const *input,
2551 __in uint32_t init);
2553 #if EFSYS_OPT_LICENSING
2557 typedef struct efx_key_stats_s {
2559 uint32_t eks_invalid;
2560 uint32_t eks_blacklisted;
2561 uint32_t eks_unverifiable;
2562 uint32_t eks_wrong_node;
2563 uint32_t eks_licensed_apps_lo;
2564 uint32_t eks_licensed_apps_hi;
2565 uint32_t eks_licensed_features_lo;
2566 uint32_t eks_licensed_features_hi;
2569 extern __checkReturn efx_rc_t
2571 __in efx_nic_t *enp);
2575 __in efx_nic_t *enp);
2577 extern __checkReturn boolean_t
2578 efx_lic_check_support(
2579 __in efx_nic_t *enp);
2581 extern __checkReturn efx_rc_t
2582 efx_lic_update_licenses(
2583 __in efx_nic_t *enp);
2585 extern __checkReturn efx_rc_t
2586 efx_lic_get_key_stats(
2587 __in efx_nic_t *enp,
2588 __out efx_key_stats_t *ksp);
2590 extern __checkReturn efx_rc_t
2592 __in efx_nic_t *enp,
2593 __in uint64_t app_id,
2594 __out boolean_t *licensedp);
2596 extern __checkReturn efx_rc_t
2598 __in efx_nic_t *enp,
2599 __in size_t buffer_size,
2600 __out uint32_t *typep,
2601 __out size_t *lengthp,
2602 __out_opt uint8_t *bufferp);
2605 extern __checkReturn efx_rc_t
2607 __in efx_nic_t *enp,
2608 __in_bcount(buffer_size)
2610 __in size_t buffer_size,
2611 __out uint32_t *startp);
2613 extern __checkReturn efx_rc_t
2615 __in efx_nic_t *enp,
2616 __in_bcount(buffer_size)
2618 __in size_t buffer_size,
2619 __in uint32_t offset,
2620 __out uint32_t *endp);
2622 extern __checkReturn __success(return != B_FALSE) boolean_t
2624 __in efx_nic_t *enp,
2625 __in_bcount(buffer_size)
2627 __in size_t buffer_size,
2628 __in uint32_t offset,
2629 __out uint32_t *startp,
2630 __out uint32_t *lengthp);
2632 extern __checkReturn __success(return != B_FALSE) boolean_t
2633 efx_lic_validate_key(
2634 __in efx_nic_t *enp,
2635 __in_bcount(length) caddr_t keyp,
2636 __in uint32_t length);
2638 extern __checkReturn efx_rc_t
2640 __in efx_nic_t *enp,
2641 __in_bcount(buffer_size)
2643 __in size_t buffer_size,
2644 __in uint32_t offset,
2645 __in uint32_t length,
2646 __out_bcount_part(key_max_size, *lengthp)
2648 __in size_t key_max_size,
2649 __out uint32_t *lengthp);
2651 extern __checkReturn efx_rc_t
2653 __in efx_nic_t *enp,
2654 __in_bcount(buffer_size)
2656 __in size_t buffer_size,
2657 __in uint32_t offset,
2658 __in_bcount(length) caddr_t keyp,
2659 __in uint32_t length,
2660 __out uint32_t *lengthp);
2662 __checkReturn efx_rc_t
2664 __in efx_nic_t *enp,
2665 __in_bcount(buffer_size)
2667 __in size_t buffer_size,
2668 __in uint32_t offset,
2669 __in uint32_t length,
2671 __out uint32_t *deltap);
2673 extern __checkReturn efx_rc_t
2674 efx_lic_create_partition(
2675 __in efx_nic_t *enp,
2676 __in_bcount(buffer_size)
2678 __in size_t buffer_size);
2680 extern __checkReturn efx_rc_t
2681 efx_lic_finish_partition(
2682 __in efx_nic_t *enp,
2683 __in_bcount(buffer_size)
2685 __in size_t buffer_size);
2687 #endif /* EFSYS_OPT_LICENSING */
2691 #if EFSYS_OPT_TUNNEL
2693 extern __checkReturn efx_rc_t
2695 __in efx_nic_t *enp);
2699 __in efx_nic_t *enp);
2702 * For overlay network encapsulation using UDP, the firmware needs to know
2703 * the configured UDP port for the overlay so it can decode encapsulated
2705 * The UDP port/protocol list is global.
2708 extern __checkReturn efx_rc_t
2709 efx_tunnel_config_udp_add(
2710 __in efx_nic_t *enp,
2711 __in uint16_t port /* host/cpu-endian */,
2712 __in efx_tunnel_protocol_t protocol);
2714 extern __checkReturn efx_rc_t
2715 efx_tunnel_config_udp_remove(
2716 __in efx_nic_t *enp,
2717 __in uint16_t port /* host/cpu-endian */,
2718 __in efx_tunnel_protocol_t protocol);
2721 efx_tunnel_config_clear(
2722 __in efx_nic_t *enp);
2725 * Apply tunnel UDP ports configuration to hardware.
2727 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2730 extern __checkReturn efx_rc_t
2731 efx_tunnel_reconfigure(
2732 __in efx_nic_t *enp);
2734 #endif /* EFSYS_OPT_TUNNEL */
2741 #endif /* _SYS_EFX_H */