1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 extern __checkReturn efx_rc_t
134 __in efx_nic_t *enp);
136 extern __checkReturn efx_rc_t
138 __in efx_nic_t *enp);
140 extern __checkReturn efx_rc_t
142 __in efx_nic_t *enp);
146 extern __checkReturn efx_rc_t
147 efx_nic_register_test(
148 __in efx_nic_t *enp);
150 #endif /* EFSYS_OPT_DIAG */
154 __in efx_nic_t *enp);
158 __in efx_nic_t *enp);
162 __in efx_nic_t *enp);
164 #define EFX_PCIE_LINK_SPEED_GEN1 1
165 #define EFX_PCIE_LINK_SPEED_GEN2 2
166 #define EFX_PCIE_LINK_SPEED_GEN3 3
168 typedef enum efx_pcie_link_performance_e {
169 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
170 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
171 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
172 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
173 } efx_pcie_link_performance_t;
175 extern __checkReturn efx_rc_t
176 efx_nic_calculate_pcie_link_bandwidth(
177 __in uint32_t pcie_link_width,
178 __in uint32_t pcie_link_gen,
179 __out uint32_t *bandwidth_mbpsp);
181 extern __checkReturn efx_rc_t
182 efx_nic_check_pcie_link_speed(
184 __in uint32_t pcie_link_width,
185 __in uint32_t pcie_link_gen,
186 __out efx_pcie_link_performance_t *resultp);
190 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
191 /* Huntington and Medford require MCDIv2 commands */
192 #define WITH_MCDI_V2 1
195 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
197 typedef enum efx_mcdi_exception_e {
198 EFX_MCDI_EXCEPTION_MC_REBOOT,
199 EFX_MCDI_EXCEPTION_MC_BADASSERT,
200 } efx_mcdi_exception_t;
202 #if EFSYS_OPT_MCDI_LOGGING
203 typedef enum efx_log_msg_e {
205 EFX_LOG_MCDI_REQUEST,
206 EFX_LOG_MCDI_RESPONSE,
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
210 typedef struct efx_mcdi_transport_s {
212 efsys_mem_t *emt_dma_mem;
213 void (*emt_execute)(void *, efx_mcdi_req_t *);
214 void (*emt_ev_cpl)(void *);
215 void (*emt_exception)(void *, efx_mcdi_exception_t);
216 #if EFSYS_OPT_MCDI_LOGGING
217 void (*emt_logger)(void *, efx_log_msg_t,
218 void *, size_t, void *, size_t);
219 #endif /* EFSYS_OPT_MCDI_LOGGING */
220 #if EFSYS_OPT_MCDI_PROXY_AUTH
221 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
222 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
223 } efx_mcdi_transport_t;
225 extern __checkReturn efx_rc_t
228 __in const efx_mcdi_transport_t *mtp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
236 __in efx_nic_t *enp);
239 efx_mcdi_get_timeout(
241 __in efx_mcdi_req_t *emrp,
242 __out uint32_t *usec_timeoutp);
245 efx_mcdi_request_start(
247 __in efx_mcdi_req_t *emrp,
248 __in boolean_t ev_cpl);
250 extern __checkReturn boolean_t
251 efx_mcdi_request_poll(
252 __in efx_nic_t *enp);
254 extern __checkReturn boolean_t
255 efx_mcdi_request_abort(
256 __in efx_nic_t *enp);
260 __in efx_nic_t *enp);
262 #endif /* EFSYS_OPT_MCDI */
266 #define EFX_NINTR_SIENA 1024
268 typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
275 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
277 extern __checkReturn efx_rc_t
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
285 __in efx_nic_t *enp);
289 __in efx_nic_t *enp);
292 efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
295 #define EFX_INTR_NEVQS 32
297 extern __checkReturn efx_rc_t
300 __in unsigned int level);
303 efx_intr_status_line(
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
309 efx_intr_status_message(
311 __in unsigned int message,
312 __out boolean_t *fatalp);
316 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
324 #if EFSYS_OPT_MAC_STATS
326 /* START MKCONFIG GENERATED EfxHeaderMacBlock 7b5f45054a3b45bc */
327 typedef enum efx_mac_stat_e {
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
409 EFX_MAC_FEC_UNCORRECTED_ERRORS,
410 EFX_MAC_FEC_CORRECTED_ERRORS,
411 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
412 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
413 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
414 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
418 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
420 #endif /* EFSYS_OPT_MAC_STATS */
422 typedef enum efx_link_mode_e {
423 EFX_LINK_UNKNOWN = 0,
439 #define EFX_MAC_ADDR_LEN 6
441 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
443 #define EFX_MAC_MULTICAST_LIST_MAX 256
445 #define EFX_MAC_SDU_MAX 9202
447 #define EFX_MAC_PDU_ADJUSTMENT \
451 + /* bug16011 */ 16) \
453 #define EFX_MAC_PDU(_sdu) \
454 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
457 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
458 * the SDU rounded up slightly.
460 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
462 #define EFX_MAC_PDU_MIN 60
463 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
465 extern __checkReturn efx_rc_t
470 extern __checkReturn efx_rc_t
475 extern __checkReturn efx_rc_t
480 extern __checkReturn efx_rc_t
483 __in boolean_t all_unicst,
484 __in boolean_t mulcst,
485 __in boolean_t all_mulcst,
486 __in boolean_t brdcst);
488 extern __checkReturn efx_rc_t
489 efx_mac_multicast_list_set(
491 __in_ecount(6*count) uint8_t const *addrs,
494 extern __checkReturn efx_rc_t
495 efx_mac_filter_default_rxq_set(
498 __in boolean_t using_rss);
501 efx_mac_filter_default_rxq_clear(
502 __in efx_nic_t *enp);
504 extern __checkReturn efx_rc_t
507 __in boolean_t enabled);
509 extern __checkReturn efx_rc_t
512 __out boolean_t *mac_upp);
514 #define EFX_FCNTL_RESPOND 0x00000001
515 #define EFX_FCNTL_GENERATE 0x00000002
517 extern __checkReturn efx_rc_t
520 __in unsigned int fcntl,
521 __in boolean_t autoneg);
526 __out unsigned int *fcntl_wantedp,
527 __out unsigned int *fcntl_linkp);
530 #if EFSYS_OPT_MAC_STATS
534 extern __checkReturn const char *
537 __in unsigned int id);
539 #endif /* EFSYS_OPT_NAMES */
541 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
543 #define EFX_MAC_STATS_MASK_NPAGES \
544 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
545 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
548 * Get mask of MAC statistics supported by the hardware.
550 * If mask_size is insufficient to return the mask, EINVAL error is
551 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
552 * (which is sizeof (uint32_t)) is sufficient.
554 extern __checkReturn efx_rc_t
555 efx_mac_stats_get_mask(
557 __out_bcount(mask_size) uint32_t *maskp,
558 __in size_t mask_size);
560 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
561 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
562 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
565 extern __checkReturn efx_rc_t
567 __in efx_nic_t *enp);
570 * Upload mac statistics supported by the hardware into the given buffer.
572 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
573 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
575 * The hardware will only DMA statistics that it understands (of course).
576 * Drivers should not make any assumptions about which statistics are
577 * supported, especially when the statistics are generated by firmware.
579 * Thus, drivers should zero this buffer before use, so that not-understood
580 * statistics read back as zero.
582 extern __checkReturn efx_rc_t
583 efx_mac_stats_upload(
585 __in efsys_mem_t *esmp);
587 extern __checkReturn efx_rc_t
588 efx_mac_stats_periodic(
590 __in efsys_mem_t *esmp,
591 __in uint16_t period_ms,
592 __in boolean_t events);
594 extern __checkReturn efx_rc_t
595 efx_mac_stats_update(
597 __in efsys_mem_t *esmp,
598 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
599 __inout_opt uint32_t *generationp);
601 #endif /* EFSYS_OPT_MAC_STATS */
605 typedef enum efx_mon_type_e {
617 __in efx_nic_t *enp);
619 #endif /* EFSYS_OPT_NAMES */
621 extern __checkReturn efx_rc_t
623 __in efx_nic_t *enp);
625 #if EFSYS_OPT_MON_STATS
627 #define EFX_MON_STATS_PAGE_SIZE 0x100
628 #define EFX_MON_MASK_ELEMENT_SIZE 32
630 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock fcc1b6748432e1ac */
631 typedef enum efx_mon_stat_e {
638 EFX_MON_STAT_EXT_TEMP,
639 EFX_MON_STAT_INT_TEMP,
642 EFX_MON_STAT_INT_COOLING,
643 EFX_MON_STAT_EXT_COOLING,
651 EFX_MON_STAT_AOE_TEMP,
652 EFX_MON_STAT_PSU_AOE_TEMP,
653 EFX_MON_STAT_PSU_TEMP,
659 EFX_MON_STAT_VAOE_IN,
661 EFX_MON_STAT_IAOE_IN,
662 EFX_MON_STAT_NIC_POWER,
666 EFX_MON_STAT_0_9V_ADC,
667 EFX_MON_STAT_INT_TEMP2,
668 EFX_MON_STAT_VREG_TEMP,
669 EFX_MON_STAT_VREG_0_9V_TEMP,
670 EFX_MON_STAT_VREG_1_2V_TEMP,
671 EFX_MON_STAT_INT_VPTAT,
672 EFX_MON_STAT_INT_ADC_TEMP,
673 EFX_MON_STAT_EXT_VPTAT,
674 EFX_MON_STAT_EXT_ADC_TEMP,
675 EFX_MON_STAT_AMBIENT_TEMP,
676 EFX_MON_STAT_AIRFLOW,
677 EFX_MON_STAT_VDD08D_VSS08D_CSR,
678 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
679 EFX_MON_STAT_HOTPOINT_TEMP,
680 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
681 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
682 EFX_MON_STAT_MUM_VCC,
685 EFX_MON_STAT_0V9_A_TEMP,
688 EFX_MON_STAT_0V9_B_TEMP,
689 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
690 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
691 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
692 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
693 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
694 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
695 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
696 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
697 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
698 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
699 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
700 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
701 EFX_MON_STAT_SODIMM_VOUT,
702 EFX_MON_STAT_SODIMM_0_TEMP,
703 EFX_MON_STAT_SODIMM_1_TEMP,
704 EFX_MON_STAT_PHY0_VCC,
705 EFX_MON_STAT_PHY1_VCC,
706 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
707 EFX_MON_STAT_BOARD_FRONT_TEMP,
708 EFX_MON_STAT_BOARD_BACK_TEMP,
716 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
718 typedef enum efx_mon_stat_state_e {
719 EFX_MON_STAT_STATE_OK = 0,
720 EFX_MON_STAT_STATE_WARNING = 1,
721 EFX_MON_STAT_STATE_FATAL = 2,
722 EFX_MON_STAT_STATE_BROKEN = 3,
723 EFX_MON_STAT_STATE_NO_READING = 4,
724 } efx_mon_stat_state_t;
726 typedef struct efx_mon_stat_value_s {
729 } efx_mon_stat_value_t;
736 __in efx_mon_stat_t id);
738 #endif /* EFSYS_OPT_NAMES */
740 extern __checkReturn efx_rc_t
741 efx_mon_stats_update(
743 __in efsys_mem_t *esmp,
744 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
746 #endif /* EFSYS_OPT_MON_STATS */
750 __in efx_nic_t *enp);
754 extern __checkReturn efx_rc_t
756 __in efx_nic_t *enp);
758 #if EFSYS_OPT_PHY_LED_CONTROL
760 typedef enum efx_phy_led_mode_e {
761 EFX_PHY_LED_DEFAULT = 0,
766 } efx_phy_led_mode_t;
768 extern __checkReturn efx_rc_t
771 __in efx_phy_led_mode_t mode);
773 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
775 extern __checkReturn efx_rc_t
777 __in efx_nic_t *enp);
779 #if EFSYS_OPT_LOOPBACK
781 typedef enum efx_loopback_type_e {
782 EFX_LOOPBACK_OFF = 0,
783 EFX_LOOPBACK_DATA = 1,
784 EFX_LOOPBACK_GMAC = 2,
785 EFX_LOOPBACK_XGMII = 3,
786 EFX_LOOPBACK_XGXS = 4,
787 EFX_LOOPBACK_XAUI = 5,
788 EFX_LOOPBACK_GMII = 6,
789 EFX_LOOPBACK_SGMII = 7,
790 EFX_LOOPBACK_XGBR = 8,
791 EFX_LOOPBACK_XFI = 9,
792 EFX_LOOPBACK_XAUI_FAR = 10,
793 EFX_LOOPBACK_GMII_FAR = 11,
794 EFX_LOOPBACK_SGMII_FAR = 12,
795 EFX_LOOPBACK_XFI_FAR = 13,
796 EFX_LOOPBACK_GPHY = 14,
797 EFX_LOOPBACK_PHY_XS = 15,
798 EFX_LOOPBACK_PCS = 16,
799 EFX_LOOPBACK_PMA_PMD = 17,
800 EFX_LOOPBACK_XPORT = 18,
801 EFX_LOOPBACK_XGMII_WS = 19,
802 EFX_LOOPBACK_XAUI_WS = 20,
803 EFX_LOOPBACK_XAUI_WS_FAR = 21,
804 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
805 EFX_LOOPBACK_GMII_WS = 23,
806 EFX_LOOPBACK_XFI_WS = 24,
807 EFX_LOOPBACK_XFI_WS_FAR = 25,
808 EFX_LOOPBACK_PHYXS_WS = 26,
809 EFX_LOOPBACK_PMA_INT = 27,
810 EFX_LOOPBACK_SD_NEAR = 28,
811 EFX_LOOPBACK_SD_FAR = 29,
812 EFX_LOOPBACK_PMA_INT_WS = 30,
813 EFX_LOOPBACK_SD_FEP2_WS = 31,
814 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
815 EFX_LOOPBACK_SD_FEP_WS = 33,
816 EFX_LOOPBACK_SD_FES_WS = 34,
817 EFX_LOOPBACK_AOE_INT_NEAR = 35,
818 EFX_LOOPBACK_DATA_WS = 36,
819 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
821 } efx_loopback_type_t;
823 typedef enum efx_loopback_kind_e {
824 EFX_LOOPBACK_KIND_OFF = 0,
825 EFX_LOOPBACK_KIND_ALL,
826 EFX_LOOPBACK_KIND_MAC,
827 EFX_LOOPBACK_KIND_PHY,
829 } efx_loopback_kind_t;
833 __in efx_loopback_kind_t loopback_kind,
834 __out efx_qword_t *maskp);
836 extern __checkReturn efx_rc_t
837 efx_port_loopback_set(
839 __in efx_link_mode_t link_mode,
840 __in efx_loopback_type_t type);
844 extern __checkReturn const char *
845 efx_loopback_type_name(
847 __in efx_loopback_type_t type);
849 #endif /* EFSYS_OPT_NAMES */
851 #endif /* EFSYS_OPT_LOOPBACK */
853 extern __checkReturn efx_rc_t
856 __out_opt efx_link_mode_t *link_modep);
860 __in efx_nic_t *enp);
862 typedef enum efx_phy_cap_type_e {
863 EFX_PHY_CAP_INVALID = 0,
870 EFX_PHY_CAP_10000FDX,
874 EFX_PHY_CAP_40000FDX,
876 EFX_PHY_CAP_100000FDX,
877 EFX_PHY_CAP_25000FDX,
878 EFX_PHY_CAP_50000FDX,
880 } efx_phy_cap_type_t;
883 #define EFX_PHY_CAP_CURRENT 0x00000000
884 #define EFX_PHY_CAP_DEFAULT 0x00000001
885 #define EFX_PHY_CAP_PERM 0x00000002
891 __out uint32_t *maskp);
893 extern __checkReturn efx_rc_t
901 __out uint32_t *maskp);
903 extern __checkReturn efx_rc_t
906 __out uint32_t *ouip);
908 typedef enum efx_phy_media_type_e {
909 EFX_PHY_MEDIA_INVALID = 0,
914 EFX_PHY_MEDIA_SFP_PLUS,
915 EFX_PHY_MEDIA_BASE_T,
916 EFX_PHY_MEDIA_QSFP_PLUS,
918 } efx_phy_media_type_t;
921 * Get the type of medium currently used. If the board has ports for
922 * modules, a module is present, and we recognise the media type of
923 * the module, then this will be the media type of the module.
924 * Otherwise it will be the media type of the port.
927 efx_phy_media_type_get(
929 __out efx_phy_media_type_t *typep);
931 extern __checkReturn efx_rc_t
932 efx_phy_module_get_info(
934 __in uint8_t dev_addr,
937 __out_bcount(len) uint8_t *data);
939 #if EFSYS_OPT_PHY_STATS
941 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
942 typedef enum efx_phy_stat_e {
944 EFX_PHY_STAT_PMA_PMD_LINK_UP,
945 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
946 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
947 EFX_PHY_STAT_PMA_PMD_REV_A,
948 EFX_PHY_STAT_PMA_PMD_REV_B,
949 EFX_PHY_STAT_PMA_PMD_REV_C,
950 EFX_PHY_STAT_PMA_PMD_REV_D,
951 EFX_PHY_STAT_PCS_LINK_UP,
952 EFX_PHY_STAT_PCS_RX_FAULT,
953 EFX_PHY_STAT_PCS_TX_FAULT,
954 EFX_PHY_STAT_PCS_BER,
955 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
956 EFX_PHY_STAT_PHY_XS_LINK_UP,
957 EFX_PHY_STAT_PHY_XS_RX_FAULT,
958 EFX_PHY_STAT_PHY_XS_TX_FAULT,
959 EFX_PHY_STAT_PHY_XS_ALIGN,
960 EFX_PHY_STAT_PHY_XS_SYNC_A,
961 EFX_PHY_STAT_PHY_XS_SYNC_B,
962 EFX_PHY_STAT_PHY_XS_SYNC_C,
963 EFX_PHY_STAT_PHY_XS_SYNC_D,
964 EFX_PHY_STAT_AN_LINK_UP,
965 EFX_PHY_STAT_AN_MASTER,
966 EFX_PHY_STAT_AN_LOCAL_RX_OK,
967 EFX_PHY_STAT_AN_REMOTE_RX_OK,
968 EFX_PHY_STAT_CL22EXT_LINK_UP,
973 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
974 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
975 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
976 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
977 EFX_PHY_STAT_AN_COMPLETE,
978 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
979 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
980 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
981 EFX_PHY_STAT_PCS_FW_VERSION_0,
982 EFX_PHY_STAT_PCS_FW_VERSION_1,
983 EFX_PHY_STAT_PCS_FW_VERSION_2,
984 EFX_PHY_STAT_PCS_FW_VERSION_3,
985 EFX_PHY_STAT_PCS_FW_BUILD_YY,
986 EFX_PHY_STAT_PCS_FW_BUILD_MM,
987 EFX_PHY_STAT_PCS_FW_BUILD_DD,
988 EFX_PHY_STAT_PCS_OP_MODE,
992 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
999 __in efx_phy_stat_t stat);
1001 #endif /* EFSYS_OPT_NAMES */
1003 #define EFX_PHY_STATS_SIZE 0x100
1005 extern __checkReturn efx_rc_t
1006 efx_phy_stats_update(
1007 __in efx_nic_t *enp,
1008 __in efsys_mem_t *esmp,
1009 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1011 #endif /* EFSYS_OPT_PHY_STATS */
1016 typedef enum efx_bist_type_e {
1017 EFX_BIST_TYPE_UNKNOWN,
1018 EFX_BIST_TYPE_PHY_NORMAL,
1019 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1020 EFX_BIST_TYPE_PHY_CABLE_LONG,
1021 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1022 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1023 EFX_BIST_TYPE_REG, /* Test the register memories */
1024 EFX_BIST_TYPE_NTYPES,
1027 typedef enum efx_bist_result_e {
1028 EFX_BIST_RESULT_UNKNOWN,
1029 EFX_BIST_RESULT_RUNNING,
1030 EFX_BIST_RESULT_PASSED,
1031 EFX_BIST_RESULT_FAILED,
1032 } efx_bist_result_t;
1034 typedef enum efx_phy_cable_status_e {
1035 EFX_PHY_CABLE_STATUS_OK,
1036 EFX_PHY_CABLE_STATUS_INVALID,
1037 EFX_PHY_CABLE_STATUS_OPEN,
1038 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1039 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1040 EFX_PHY_CABLE_STATUS_BUSY,
1041 } efx_phy_cable_status_t;
1043 typedef enum efx_bist_value_e {
1044 EFX_BIST_PHY_CABLE_LENGTH_A,
1045 EFX_BIST_PHY_CABLE_LENGTH_B,
1046 EFX_BIST_PHY_CABLE_LENGTH_C,
1047 EFX_BIST_PHY_CABLE_LENGTH_D,
1048 EFX_BIST_PHY_CABLE_STATUS_A,
1049 EFX_BIST_PHY_CABLE_STATUS_B,
1050 EFX_BIST_PHY_CABLE_STATUS_C,
1051 EFX_BIST_PHY_CABLE_STATUS_D,
1052 EFX_BIST_FAULT_CODE,
1054 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1060 EFX_BIST_MEM_EXPECT,
1061 EFX_BIST_MEM_ACTUAL,
1063 EFX_BIST_MEM_ECC_PARITY,
1064 EFX_BIST_MEM_ECC_FATAL,
1068 extern __checkReturn efx_rc_t
1069 efx_bist_enable_offline(
1070 __in efx_nic_t *enp);
1072 extern __checkReturn efx_rc_t
1074 __in efx_nic_t *enp,
1075 __in efx_bist_type_t type);
1077 extern __checkReturn efx_rc_t
1079 __in efx_nic_t *enp,
1080 __in efx_bist_type_t type,
1081 __out efx_bist_result_t *resultp,
1082 __out_opt uint32_t *value_maskp,
1083 __out_ecount_opt(count) unsigned long *valuesp,
1088 __in efx_nic_t *enp,
1089 __in efx_bist_type_t type);
1091 #endif /* EFSYS_OPT_BIST */
1093 #define EFX_FEATURE_IPV6 0x00000001
1094 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1095 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1096 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1097 #define EFX_FEATURE_MCDI 0x00000020
1098 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1099 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1100 #define EFX_FEATURE_TURBO 0x00000100
1101 #define EFX_FEATURE_MCDI_DMA 0x00000200
1102 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1103 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1104 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1105 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1106 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1108 typedef enum efx_tunnel_protocol_e {
1109 EFX_TUNNEL_PROTOCOL_NONE = 0,
1110 EFX_TUNNEL_PROTOCOL_VXLAN,
1111 EFX_TUNNEL_PROTOCOL_GENEVE,
1112 EFX_TUNNEL_PROTOCOL_NVGRE,
1114 } efx_tunnel_protocol_t;
1116 typedef enum efx_vi_window_shift_e {
1117 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1118 EFX_VI_WINDOW_SHIFT_8K = 13,
1119 EFX_VI_WINDOW_SHIFT_16K = 14,
1120 EFX_VI_WINDOW_SHIFT_64K = 16,
1121 } efx_vi_window_shift_t;
1123 typedef struct efx_nic_cfg_s {
1124 uint32_t enc_board_type;
1125 uint32_t enc_phy_type;
1127 char enc_phy_name[21];
1129 char enc_phy_revision[21];
1130 efx_mon_type_t enc_mon_type;
1131 #if EFSYS_OPT_MON_STATS
1132 uint32_t enc_mon_stat_dma_buf_size;
1133 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1135 unsigned int enc_features;
1136 efx_vi_window_shift_t enc_vi_window_shift;
1137 uint8_t enc_mac_addr[6];
1138 uint8_t enc_port; /* PHY port number */
1139 uint32_t enc_intr_vec_base;
1140 uint32_t enc_intr_limit;
1141 uint32_t enc_evq_limit;
1142 uint32_t enc_txq_limit;
1143 uint32_t enc_rxq_limit;
1144 uint32_t enc_txq_max_ndescs;
1145 uint32_t enc_buftbl_limit;
1146 uint32_t enc_piobuf_limit;
1147 uint32_t enc_piobuf_size;
1148 uint32_t enc_piobuf_min_alloc_size;
1149 uint32_t enc_evq_timer_quantum_ns;
1150 uint32_t enc_evq_timer_max_us;
1151 uint32_t enc_clk_mult;
1152 uint32_t enc_rx_prefix_size;
1153 uint32_t enc_rx_buf_align_start;
1154 uint32_t enc_rx_buf_align_end;
1155 uint32_t enc_rx_scale_max_exclusive_contexts;
1156 #if EFSYS_OPT_LOOPBACK
1157 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1158 #endif /* EFSYS_OPT_LOOPBACK */
1159 #if EFSYS_OPT_PHY_FLAGS
1160 uint32_t enc_phy_flags_mask;
1161 #endif /* EFSYS_OPT_PHY_FLAGS */
1162 #if EFSYS_OPT_PHY_LED_CONTROL
1163 uint32_t enc_led_mask;
1164 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1165 #if EFSYS_OPT_PHY_STATS
1166 uint64_t enc_phy_stat_mask;
1167 #endif /* EFSYS_OPT_PHY_STATS */
1169 uint8_t enc_mcdi_mdio_channel;
1170 #if EFSYS_OPT_PHY_STATS
1171 uint32_t enc_mcdi_phy_stat_mask;
1172 #endif /* EFSYS_OPT_PHY_STATS */
1173 #if EFSYS_OPT_MON_STATS
1174 uint32_t *enc_mcdi_sensor_maskp;
1175 uint32_t enc_mcdi_sensor_mask_size;
1176 #endif /* EFSYS_OPT_MON_STATS */
1177 #endif /* EFSYS_OPT_MCDI */
1179 uint32_t enc_bist_mask;
1180 #endif /* EFSYS_OPT_BIST */
1181 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1184 uint32_t enc_privilege_mask;
1185 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1186 boolean_t enc_bug26807_workaround;
1187 boolean_t enc_bug35388_workaround;
1188 boolean_t enc_bug41750_workaround;
1189 boolean_t enc_bug61265_workaround;
1190 boolean_t enc_rx_batching_enabled;
1191 /* Maximum number of descriptors completed in an rx event. */
1192 uint32_t enc_rx_batch_max;
1193 /* Number of rx descriptors the hardware requires for a push. */
1194 uint32_t enc_rx_push_align;
1195 /* Maximum amount of data in DMA descriptor */
1196 uint32_t enc_tx_dma_desc_size_max;
1198 * Boundary which DMA descriptor data must not cross or 0 if no
1201 uint32_t enc_tx_dma_desc_boundary;
1203 * Maximum number of bytes into the packet the TCP header can start for
1204 * the hardware to apply TSO packet edits.
1206 uint32_t enc_tx_tso_tcp_header_offset_limit;
1207 boolean_t enc_fw_assisted_tso_enabled;
1208 boolean_t enc_fw_assisted_tso_v2_enabled;
1209 /* Number of TSO contexts on the NIC (FATSOv2) */
1210 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1211 boolean_t enc_hw_tx_insert_vlan_enabled;
1212 /* Number of PFs on the NIC */
1213 uint32_t enc_hw_pf_count;
1214 /* Datapath firmware vadapter/vport/vswitch support */
1215 boolean_t enc_datapath_cap_evb;
1216 boolean_t enc_rx_disable_scatter_supported;
1217 boolean_t enc_allow_set_mac_with_installed_filters;
1218 boolean_t enc_enhanced_set_mac_supported;
1219 boolean_t enc_init_evq_v2_supported;
1220 boolean_t enc_rx_packed_stream_supported;
1221 boolean_t enc_rx_var_packed_stream_supported;
1222 boolean_t enc_pm_and_rxdp_counters;
1223 boolean_t enc_mac_stats_40g_tx_size_bins;
1224 uint32_t enc_tunnel_encapsulations_supported;
1226 * NIC global maximum for unique UDP tunnel ports shared by all
1229 uint32_t enc_tunnel_config_udp_entries_max;
1230 /* External port identifier */
1231 uint8_t enc_external_port;
1232 uint32_t enc_mcdi_max_payload_length;
1233 /* VPD may be per-PF or global */
1234 boolean_t enc_vpd_is_global;
1235 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1236 uint32_t enc_required_pcie_bandwidth_mbps;
1237 uint32_t enc_max_pcie_link_gen;
1238 /* Firmware verifies integrity of NVRAM updates */
1239 uint32_t enc_nvram_update_verify_result_supported;
1240 /* Firmware support for extended MAC_STATS buffer */
1241 uint32_t enc_mac_stats_nstats;
1242 boolean_t enc_fec_counters;
1245 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1246 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1248 #define EFX_PCI_FUNCTION(_encp) \
1249 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1251 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1253 extern const efx_nic_cfg_t *
1255 __in efx_nic_t *enp);
1257 typedef struct efx_nic_fw_info_s {
1258 /* Basic FW version information */
1259 uint16_t enfi_mc_fw_version[4];
1261 * If datapath capabilities can be detected,
1262 * additional FW information is to be shown
1264 boolean_t enfi_dpcpu_fw_ids_valid;
1265 /* Rx and Tx datapath CPU FW IDs */
1266 uint16_t enfi_rx_dpcpu_fw_id;
1267 uint16_t enfi_tx_dpcpu_fw_id;
1268 } efx_nic_fw_info_t;
1270 extern __checkReturn efx_rc_t
1271 efx_nic_get_fw_version(
1272 __in efx_nic_t *enp,
1273 __out efx_nic_fw_info_t *enfip);
1275 /* Driver resource limits (minimum required/maximum usable). */
1276 typedef struct efx_drv_limits_s {
1277 uint32_t edl_min_evq_count;
1278 uint32_t edl_max_evq_count;
1280 uint32_t edl_min_rxq_count;
1281 uint32_t edl_max_rxq_count;
1283 uint32_t edl_min_txq_count;
1284 uint32_t edl_max_txq_count;
1286 /* PIO blocks (sub-allocated from piobuf) */
1287 uint32_t edl_min_pio_alloc_size;
1288 uint32_t edl_max_pio_alloc_count;
1291 extern __checkReturn efx_rc_t
1292 efx_nic_set_drv_limits(
1293 __inout efx_nic_t *enp,
1294 __in efx_drv_limits_t *edlp);
1296 typedef enum efx_nic_region_e {
1297 EFX_REGION_VI, /* Memory BAR UC mapping */
1298 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1301 extern __checkReturn efx_rc_t
1302 efx_nic_get_bar_region(
1303 __in efx_nic_t *enp,
1304 __in efx_nic_region_t region,
1305 __out uint32_t *offsetp,
1306 __out size_t *sizep);
1308 extern __checkReturn efx_rc_t
1309 efx_nic_get_vi_pool(
1310 __in efx_nic_t *enp,
1311 __out uint32_t *evq_countp,
1312 __out uint32_t *rxq_countp,
1313 __out uint32_t *txq_countp);
1318 typedef enum efx_vpd_tag_e {
1325 typedef uint16_t efx_vpd_keyword_t;
1327 typedef struct efx_vpd_value_s {
1328 efx_vpd_tag_t evv_tag;
1329 efx_vpd_keyword_t evv_keyword;
1331 uint8_t evv_value[0x100];
1335 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1337 extern __checkReturn efx_rc_t
1339 __in efx_nic_t *enp);
1341 extern __checkReturn efx_rc_t
1343 __in efx_nic_t *enp,
1344 __out size_t *sizep);
1346 extern __checkReturn efx_rc_t
1348 __in efx_nic_t *enp,
1349 __out_bcount(size) caddr_t data,
1352 extern __checkReturn efx_rc_t
1354 __in efx_nic_t *enp,
1355 __in_bcount(size) caddr_t data,
1358 extern __checkReturn efx_rc_t
1360 __in efx_nic_t *enp,
1361 __in_bcount(size) caddr_t data,
1364 extern __checkReturn efx_rc_t
1366 __in efx_nic_t *enp,
1367 __in_bcount(size) caddr_t data,
1369 __inout efx_vpd_value_t *evvp);
1371 extern __checkReturn efx_rc_t
1373 __in efx_nic_t *enp,
1374 __inout_bcount(size) caddr_t data,
1376 __in efx_vpd_value_t *evvp);
1378 extern __checkReturn efx_rc_t
1380 __in efx_nic_t *enp,
1381 __inout_bcount(size) caddr_t data,
1383 __out efx_vpd_value_t *evvp,
1384 __inout unsigned int *contp);
1386 extern __checkReturn efx_rc_t
1388 __in efx_nic_t *enp,
1389 __in_bcount(size) caddr_t data,
1394 __in efx_nic_t *enp);
1396 #endif /* EFSYS_OPT_VPD */
1402 typedef enum efx_nvram_type_e {
1403 EFX_NVRAM_INVALID = 0,
1405 EFX_NVRAM_BOOTROM_CFG,
1406 EFX_NVRAM_MC_FIRMWARE,
1407 EFX_NVRAM_MC_GOLDEN,
1413 EFX_NVRAM_FPGA_BACKUP,
1414 EFX_NVRAM_DYNAMIC_CFG,
1417 EFX_NVRAM_MUM_FIRMWARE,
1421 extern __checkReturn efx_rc_t
1423 __in efx_nic_t *enp);
1427 extern __checkReturn efx_rc_t
1429 __in efx_nic_t *enp);
1431 #endif /* EFSYS_OPT_DIAG */
1433 extern __checkReturn efx_rc_t
1435 __in efx_nic_t *enp,
1436 __in efx_nvram_type_t type,
1437 __out size_t *sizep);
1439 extern __checkReturn efx_rc_t
1441 __in efx_nic_t *enp,
1442 __in efx_nvram_type_t type,
1443 __out_opt size_t *pref_chunkp);
1445 extern __checkReturn efx_rc_t
1446 efx_nvram_rw_finish(
1447 __in efx_nic_t *enp,
1448 __in efx_nvram_type_t type,
1449 __out_opt uint32_t *verify_resultp);
1451 extern __checkReturn efx_rc_t
1452 efx_nvram_get_version(
1453 __in efx_nic_t *enp,
1454 __in efx_nvram_type_t type,
1455 __out uint32_t *subtypep,
1456 __out_ecount(4) uint16_t version[4]);
1458 extern __checkReturn efx_rc_t
1459 efx_nvram_read_chunk(
1460 __in efx_nic_t *enp,
1461 __in efx_nvram_type_t type,
1462 __in unsigned int offset,
1463 __out_bcount(size) caddr_t data,
1466 extern __checkReturn efx_rc_t
1467 efx_nvram_read_backup(
1468 __in efx_nic_t *enp,
1469 __in efx_nvram_type_t type,
1470 __in unsigned int offset,
1471 __out_bcount(size) caddr_t data,
1474 extern __checkReturn efx_rc_t
1475 efx_nvram_set_version(
1476 __in efx_nic_t *enp,
1477 __in efx_nvram_type_t type,
1478 __in_ecount(4) uint16_t version[4]);
1480 extern __checkReturn efx_rc_t
1482 __in efx_nic_t *enp,
1483 __in efx_nvram_type_t type,
1484 __in_bcount(partn_size) caddr_t partn_data,
1485 __in size_t partn_size);
1487 extern __checkReturn efx_rc_t
1489 __in efx_nic_t *enp,
1490 __in efx_nvram_type_t type);
1492 extern __checkReturn efx_rc_t
1493 efx_nvram_write_chunk(
1494 __in efx_nic_t *enp,
1495 __in efx_nvram_type_t type,
1496 __in unsigned int offset,
1497 __in_bcount(size) caddr_t data,
1502 __in efx_nic_t *enp);
1504 #endif /* EFSYS_OPT_NVRAM */
1506 #if EFSYS_OPT_BOOTCFG
1508 /* Report size and offset of bootcfg sector in NVRAM partition. */
1509 extern __checkReturn efx_rc_t
1510 efx_bootcfg_sector_info(
1511 __in efx_nic_t *enp,
1513 __out_opt uint32_t *sector_countp,
1514 __out size_t *offsetp,
1515 __out size_t *max_sizep);
1518 * Copy bootcfg sector data to a target buffer which may differ in size.
1519 * Optionally corrects format errors in source buffer.
1522 efx_bootcfg_copy_sector(
1523 __in efx_nic_t *enp,
1524 __inout_bcount(sector_length)
1526 __in size_t sector_length,
1527 __out_bcount(data_size) uint8_t *data,
1528 __in size_t data_size,
1529 __in boolean_t handle_format_errors);
1533 __in efx_nic_t *enp,
1534 __out_bcount(size) uint8_t *data,
1539 __in efx_nic_t *enp,
1540 __in_bcount(size) uint8_t *data,
1543 #endif /* EFSYS_OPT_BOOTCFG */
1547 typedef enum efx_pattern_type_t {
1548 EFX_PATTERN_BYTE_INCREMENT = 0,
1549 EFX_PATTERN_ALL_THE_SAME,
1550 EFX_PATTERN_BIT_ALTERNATE,
1551 EFX_PATTERN_BYTE_ALTERNATE,
1552 EFX_PATTERN_BYTE_CHANGING,
1553 EFX_PATTERN_BIT_SWEEP,
1555 } efx_pattern_type_t;
1558 (*efx_sram_pattern_fn_t)(
1560 __in boolean_t negate,
1561 __out efx_qword_t *eqp);
1563 extern __checkReturn efx_rc_t
1565 __in efx_nic_t *enp,
1566 __in efx_pattern_type_t type);
1568 #endif /* EFSYS_OPT_DIAG */
1570 extern __checkReturn efx_rc_t
1571 efx_sram_buf_tbl_set(
1572 __in efx_nic_t *enp,
1574 __in efsys_mem_t *esmp,
1578 efx_sram_buf_tbl_clear(
1579 __in efx_nic_t *enp,
1583 #define EFX_BUF_TBL_SIZE 0x20000
1585 #define EFX_BUF_SIZE 4096
1589 typedef struct efx_evq_s efx_evq_t;
1591 #if EFSYS_OPT_QSTATS
1593 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1594 typedef enum efx_ev_qstat_e {
1600 EV_RX_PAUSE_FRM_ERR,
1601 EV_RX_BUF_OWNER_ID_ERR,
1602 EV_RX_IPV4_HDR_CHKSUM_ERR,
1603 EV_RX_TCP_UDP_CHKSUM_ERR,
1607 EV_RX_MCAST_HASH_MATCH,
1624 EV_DRIVER_SRM_UPD_DONE,
1625 EV_DRIVER_TX_DESCQ_FLS_DONE,
1626 EV_DRIVER_RX_DESCQ_FLS_DONE,
1627 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1628 EV_DRIVER_RX_DSC_ERROR,
1629 EV_DRIVER_TX_DSC_ERROR,
1635 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1637 #endif /* EFSYS_OPT_QSTATS */
1639 extern __checkReturn efx_rc_t
1641 __in efx_nic_t *enp);
1645 __in efx_nic_t *enp);
1647 #define EFX_EVQ_MAXNEVS 32768
1648 #define EFX_EVQ_MINNEVS 512
1650 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1651 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1653 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1654 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1655 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1656 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1658 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1659 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1660 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1662 extern __checkReturn efx_rc_t
1664 __in efx_nic_t *enp,
1665 __in unsigned int index,
1666 __in efsys_mem_t *esmp,
1670 __in uint32_t flags,
1671 __deref_out efx_evq_t **eepp);
1675 __in efx_evq_t *eep,
1676 __in uint16_t data);
1678 typedef __checkReturn boolean_t
1679 (*efx_initialized_ev_t)(
1680 __in_opt void *arg);
1682 #define EFX_PKT_UNICAST 0x0004
1683 #define EFX_PKT_START 0x0008
1685 #define EFX_PKT_VLAN_TAGGED 0x0010
1686 #define EFX_CKSUM_TCPUDP 0x0020
1687 #define EFX_CKSUM_IPV4 0x0040
1688 #define EFX_PKT_CONT 0x0080
1690 #define EFX_CHECK_VLAN 0x0100
1691 #define EFX_PKT_TCP 0x0200
1692 #define EFX_PKT_UDP 0x0400
1693 #define EFX_PKT_IPV4 0x0800
1695 #define EFX_PKT_IPV6 0x1000
1696 #define EFX_PKT_PREFIX_LEN 0x2000
1697 #define EFX_ADDR_MISMATCH 0x4000
1698 #define EFX_DISCARD 0x8000
1701 * The following flags are used only for packed stream
1702 * mode. The values for the flags are reused to fit into 16 bit,
1703 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1704 * packed stream mode
1706 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1707 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1710 #define EFX_EV_RX_NLABELS 32
1711 #define EFX_EV_TX_NLABELS 32
1713 typedef __checkReturn boolean_t
1716 __in uint32_t label,
1719 __in uint16_t flags);
1721 #if EFSYS_OPT_RX_PACKED_STREAM
1724 * Packed stream mode is documented in SF-112241-TC.
1725 * The general idea is that, instead of putting each incoming
1726 * packet into a separate buffer which is specified in a RX
1727 * descriptor, a large buffer is provided to the hardware and
1728 * packets are put there in a continuous stream.
1729 * The main advantage of such an approach is that RX queue refilling
1730 * happens much less frequently.
1733 typedef __checkReturn boolean_t
1736 __in uint32_t label,
1738 __in uint32_t pkt_count,
1739 __in uint16_t flags);
1743 typedef __checkReturn boolean_t
1746 __in uint32_t label,
1749 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1750 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1751 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1752 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1753 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1754 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1755 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1756 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1757 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1759 typedef __checkReturn boolean_t
1760 (*efx_exception_ev_t)(
1762 __in uint32_t label,
1763 __in uint32_t data);
1765 typedef __checkReturn boolean_t
1766 (*efx_rxq_flush_done_ev_t)(
1768 __in uint32_t rxq_index);
1770 typedef __checkReturn boolean_t
1771 (*efx_rxq_flush_failed_ev_t)(
1773 __in uint32_t rxq_index);
1775 typedef __checkReturn boolean_t
1776 (*efx_txq_flush_done_ev_t)(
1778 __in uint32_t txq_index);
1780 typedef __checkReturn boolean_t
1781 (*efx_software_ev_t)(
1783 __in uint16_t magic);
1785 typedef __checkReturn boolean_t
1788 __in uint32_t code);
1790 #define EFX_SRAM_CLEAR 0
1791 #define EFX_SRAM_UPDATE 1
1792 #define EFX_SRAM_ILLEGAL_CLEAR 2
1794 typedef __checkReturn boolean_t
1795 (*efx_wake_up_ev_t)(
1797 __in uint32_t label);
1799 typedef __checkReturn boolean_t
1802 __in uint32_t label);
1804 typedef __checkReturn boolean_t
1805 (*efx_link_change_ev_t)(
1807 __in efx_link_mode_t link_mode);
1809 #if EFSYS_OPT_MON_STATS
1811 typedef __checkReturn boolean_t
1812 (*efx_monitor_ev_t)(
1814 __in efx_mon_stat_t id,
1815 __in efx_mon_stat_value_t value);
1817 #endif /* EFSYS_OPT_MON_STATS */
1819 #if EFSYS_OPT_MAC_STATS
1821 typedef __checkReturn boolean_t
1822 (*efx_mac_stats_ev_t)(
1824 __in uint32_t generation);
1826 #endif /* EFSYS_OPT_MAC_STATS */
1828 typedef struct efx_ev_callbacks_s {
1829 efx_initialized_ev_t eec_initialized;
1831 #if EFSYS_OPT_RX_PACKED_STREAM
1832 efx_rx_ps_ev_t eec_rx_ps;
1835 efx_exception_ev_t eec_exception;
1836 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1837 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1838 efx_txq_flush_done_ev_t eec_txq_flush_done;
1839 efx_software_ev_t eec_software;
1840 efx_sram_ev_t eec_sram;
1841 efx_wake_up_ev_t eec_wake_up;
1842 efx_timer_ev_t eec_timer;
1843 efx_link_change_ev_t eec_link_change;
1844 #if EFSYS_OPT_MON_STATS
1845 efx_monitor_ev_t eec_monitor;
1846 #endif /* EFSYS_OPT_MON_STATS */
1847 #if EFSYS_OPT_MAC_STATS
1848 efx_mac_stats_ev_t eec_mac_stats;
1849 #endif /* EFSYS_OPT_MAC_STATS */
1850 } efx_ev_callbacks_t;
1852 extern __checkReturn boolean_t
1854 __in efx_evq_t *eep,
1855 __in unsigned int count);
1857 #if EFSYS_OPT_EV_PREFETCH
1861 __in efx_evq_t *eep,
1862 __in unsigned int count);
1864 #endif /* EFSYS_OPT_EV_PREFETCH */
1868 __in efx_evq_t *eep,
1869 __inout unsigned int *countp,
1870 __in const efx_ev_callbacks_t *eecp,
1871 __in_opt void *arg);
1873 extern __checkReturn efx_rc_t
1874 efx_ev_usecs_to_ticks(
1875 __in efx_nic_t *enp,
1876 __in unsigned int usecs,
1877 __out unsigned int *ticksp);
1879 extern __checkReturn efx_rc_t
1881 __in efx_evq_t *eep,
1882 __in unsigned int us);
1884 extern __checkReturn efx_rc_t
1886 __in efx_evq_t *eep,
1887 __in unsigned int count);
1889 #if EFSYS_OPT_QSTATS
1895 __in efx_nic_t *enp,
1896 __in unsigned int id);
1898 #endif /* EFSYS_OPT_NAMES */
1901 efx_ev_qstats_update(
1902 __in efx_evq_t *eep,
1903 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1905 #endif /* EFSYS_OPT_QSTATS */
1909 __in efx_evq_t *eep);
1913 extern __checkReturn efx_rc_t
1915 __inout efx_nic_t *enp);
1919 __in efx_nic_t *enp);
1921 #if EFSYS_OPT_RX_SCATTER
1922 __checkReturn efx_rc_t
1923 efx_rx_scatter_enable(
1924 __in efx_nic_t *enp,
1925 __in unsigned int buf_size);
1926 #endif /* EFSYS_OPT_RX_SCATTER */
1928 /* Handle to represent use of the default RSS context. */
1929 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1931 #if EFSYS_OPT_RX_SCALE
1933 typedef enum efx_rx_hash_alg_e {
1934 EFX_RX_HASHALG_LFSR = 0,
1935 EFX_RX_HASHALG_TOEPLITZ
1936 } efx_rx_hash_alg_t;
1938 #define EFX_RX_HASH_IPV4 (1U << 0)
1939 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1940 #define EFX_RX_HASH_IPV6 (1U << 2)
1941 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1943 typedef unsigned int efx_rx_hash_type_t;
1945 typedef enum efx_rx_hash_support_e {
1946 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1947 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1948 } efx_rx_hash_support_t;
1950 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1951 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1952 #define EFX_MAXRSS 64 /* RX indirection entry range */
1953 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1955 typedef enum efx_rx_scale_context_type_e {
1956 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1957 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1958 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1959 } efx_rx_scale_context_type_t;
1961 extern __checkReturn efx_rc_t
1962 efx_rx_hash_default_support_get(
1963 __in efx_nic_t *enp,
1964 __out efx_rx_hash_support_t *supportp);
1967 extern __checkReturn efx_rc_t
1968 efx_rx_scale_default_support_get(
1969 __in efx_nic_t *enp,
1970 __out efx_rx_scale_context_type_t *typep);
1972 extern __checkReturn efx_rc_t
1973 efx_rx_scale_context_alloc(
1974 __in efx_nic_t *enp,
1975 __in efx_rx_scale_context_type_t type,
1976 __in uint32_t num_queues,
1977 __out uint32_t *rss_contextp);
1979 extern __checkReturn efx_rc_t
1980 efx_rx_scale_context_free(
1981 __in efx_nic_t *enp,
1982 __in uint32_t rss_context);
1984 extern __checkReturn efx_rc_t
1985 efx_rx_scale_mode_set(
1986 __in efx_nic_t *enp,
1987 __in uint32_t rss_context,
1988 __in efx_rx_hash_alg_t alg,
1989 __in efx_rx_hash_type_t type,
1990 __in boolean_t insert);
1992 extern __checkReturn efx_rc_t
1993 efx_rx_scale_tbl_set(
1994 __in efx_nic_t *enp,
1995 __in uint32_t rss_context,
1996 __in_ecount(n) unsigned int *table,
1999 extern __checkReturn efx_rc_t
2000 efx_rx_scale_key_set(
2001 __in efx_nic_t *enp,
2002 __in uint32_t rss_context,
2003 __in_ecount(n) uint8_t *key,
2006 extern __checkReturn uint32_t
2007 efx_pseudo_hdr_hash_get(
2008 __in efx_rxq_t *erp,
2009 __in efx_rx_hash_alg_t func,
2010 __in uint8_t *buffer);
2012 #endif /* EFSYS_OPT_RX_SCALE */
2014 extern __checkReturn efx_rc_t
2015 efx_pseudo_hdr_pkt_length_get(
2016 __in efx_rxq_t *erp,
2017 __in uint8_t *buffer,
2018 __out uint16_t *pkt_lengthp);
2020 #define EFX_RXQ_MAXNDESCS 4096
2021 #define EFX_RXQ_MINNDESCS 512
2023 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2024 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2025 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2026 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2028 typedef enum efx_rxq_type_e {
2029 EFX_RXQ_TYPE_DEFAULT,
2030 EFX_RXQ_TYPE_PACKED_STREAM,
2035 * Dummy flag to be used instead of 0 to make it clear that the argument
2036 * is receive queue flags.
2038 #define EFX_RXQ_FLAG_NONE 0x0
2039 #define EFX_RXQ_FLAG_SCATTER 0x1
2041 * If tunnels are supported and Rx event can provide information about
2042 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2043 * full-feature firmware variant running), outer classes are requested by
2044 * default. However, if the driver supports tunnels, the flag allows to
2045 * request inner classes which are required to be able to interpret inner
2046 * Rx checksum offload results.
2048 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2050 extern __checkReturn efx_rc_t
2052 __in efx_nic_t *enp,
2053 __in unsigned int index,
2054 __in unsigned int label,
2055 __in efx_rxq_type_t type,
2056 __in efsys_mem_t *esmp,
2059 __in unsigned int flags,
2060 __in efx_evq_t *eep,
2061 __deref_out efx_rxq_t **erpp);
2063 #if EFSYS_OPT_RX_PACKED_STREAM
2065 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2066 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2067 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2068 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2069 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2071 extern __checkReturn efx_rc_t
2072 efx_rx_qcreate_packed_stream(
2073 __in efx_nic_t *enp,
2074 __in unsigned int index,
2075 __in unsigned int label,
2076 __in uint32_t ps_buf_size,
2077 __in efsys_mem_t *esmp,
2079 __in efx_evq_t *eep,
2080 __deref_out efx_rxq_t **erpp);
2084 typedef struct efx_buffer_s {
2085 efsys_dma_addr_t eb_addr;
2090 typedef struct efx_desc_s {
2096 __in efx_rxq_t *erp,
2097 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2099 __in unsigned int ndescs,
2100 __in unsigned int completed,
2101 __in unsigned int added);
2105 __in efx_rxq_t *erp,
2106 __in unsigned int added,
2107 __inout unsigned int *pushedp);
2109 #if EFSYS_OPT_RX_PACKED_STREAM
2112 efx_rx_qpush_ps_credits(
2113 __in efx_rxq_t *erp);
2115 extern __checkReturn uint8_t *
2116 efx_rx_qps_packet_info(
2117 __in efx_rxq_t *erp,
2118 __in uint8_t *buffer,
2119 __in uint32_t buffer_length,
2120 __in uint32_t current_offset,
2121 __out uint16_t *lengthp,
2122 __out uint32_t *next_offsetp,
2123 __out uint32_t *timestamp);
2126 extern __checkReturn efx_rc_t
2128 __in efx_rxq_t *erp);
2132 __in efx_rxq_t *erp);
2136 __in efx_rxq_t *erp);
2140 typedef struct efx_txq_s efx_txq_t;
2142 #if EFSYS_OPT_QSTATS
2144 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2145 typedef enum efx_tx_qstat_e {
2151 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2153 #endif /* EFSYS_OPT_QSTATS */
2155 extern __checkReturn efx_rc_t
2157 __in efx_nic_t *enp);
2161 __in efx_nic_t *enp);
2163 #define EFX_TXQ_MINNDESCS 512
2165 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2166 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2167 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2169 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2171 #define EFX_TXQ_CKSUM_IPV4 0x0001
2172 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2173 #define EFX_TXQ_FATSOV2 0x0004
2174 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2175 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2177 extern __checkReturn efx_rc_t
2179 __in efx_nic_t *enp,
2180 __in unsigned int index,
2181 __in unsigned int label,
2182 __in efsys_mem_t *esmp,
2185 __in uint16_t flags,
2186 __in efx_evq_t *eep,
2187 __deref_out efx_txq_t **etpp,
2188 __out unsigned int *addedp);
2190 extern __checkReturn efx_rc_t
2192 __in efx_txq_t *etp,
2193 __in_ecount(ndescs) efx_buffer_t *eb,
2194 __in unsigned int ndescs,
2195 __in unsigned int completed,
2196 __inout unsigned int *addedp);
2198 extern __checkReturn efx_rc_t
2200 __in efx_txq_t *etp,
2201 __in unsigned int ns);
2205 __in efx_txq_t *etp,
2206 __in unsigned int added,
2207 __in unsigned int pushed);
2209 extern __checkReturn efx_rc_t
2211 __in efx_txq_t *etp);
2215 __in efx_txq_t *etp);
2217 extern __checkReturn efx_rc_t
2219 __in efx_txq_t *etp);
2222 efx_tx_qpio_disable(
2223 __in efx_txq_t *etp);
2225 extern __checkReturn efx_rc_t
2227 __in efx_txq_t *etp,
2228 __in_ecount(buf_length) uint8_t *buffer,
2229 __in size_t buf_length,
2230 __in size_t pio_buf_offset);
2232 extern __checkReturn efx_rc_t
2234 __in efx_txq_t *etp,
2235 __in size_t pkt_length,
2236 __in unsigned int completed,
2237 __inout unsigned int *addedp);
2239 extern __checkReturn efx_rc_t
2241 __in efx_txq_t *etp,
2242 __in_ecount(n) efx_desc_t *ed,
2243 __in unsigned int n,
2244 __in unsigned int completed,
2245 __inout unsigned int *addedp);
2248 efx_tx_qdesc_dma_create(
2249 __in efx_txq_t *etp,
2250 __in efsys_dma_addr_t addr,
2253 __out efx_desc_t *edp);
2256 efx_tx_qdesc_tso_create(
2257 __in efx_txq_t *etp,
2258 __in uint16_t ipv4_id,
2259 __in uint32_t tcp_seq,
2260 __in uint8_t tcp_flags,
2261 __out efx_desc_t *edp);
2263 /* Number of FATSOv2 option descriptors */
2264 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2266 /* Maximum number of DMA segments per TSO packet (not superframe) */
2267 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2270 efx_tx_qdesc_tso2_create(
2271 __in efx_txq_t *etp,
2272 __in uint16_t ipv4_id,
2273 __in uint32_t tcp_seq,
2274 __in uint16_t tcp_mss,
2275 __out_ecount(count) efx_desc_t *edp,
2279 efx_tx_qdesc_vlantci_create(
2280 __in efx_txq_t *etp,
2282 __out efx_desc_t *edp);
2285 efx_tx_qdesc_checksum_create(
2286 __in efx_txq_t *etp,
2287 __in uint16_t flags,
2288 __out efx_desc_t *edp);
2290 #if EFSYS_OPT_QSTATS
2296 __in efx_nic_t *etp,
2297 __in unsigned int id);
2299 #endif /* EFSYS_OPT_NAMES */
2302 efx_tx_qstats_update(
2303 __in efx_txq_t *etp,
2304 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2306 #endif /* EFSYS_OPT_QSTATS */
2310 __in efx_txq_t *etp);
2315 #if EFSYS_OPT_FILTER
2317 #define EFX_ETHER_TYPE_IPV4 0x0800
2318 #define EFX_ETHER_TYPE_IPV6 0x86DD
2320 #define EFX_IPPROTO_TCP 6
2321 #define EFX_IPPROTO_UDP 17
2322 #define EFX_IPPROTO_GRE 47
2324 /* Use RSS to spread across multiple queues */
2325 #define EFX_FILTER_FLAG_RX_RSS 0x01
2326 /* Enable RX scatter */
2327 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2329 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2330 * May only be set by the filter implementation for each type.
2331 * A removal request will restore the automatic filter in its place.
2333 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2334 /* Filter is for RX */
2335 #define EFX_FILTER_FLAG_RX 0x08
2336 /* Filter is for TX */
2337 #define EFX_FILTER_FLAG_TX 0x10
2339 typedef uint8_t efx_filter_flags_t;
2342 * Flags which specify the fields to match on. The values are the same as in the
2343 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2346 /* Match by remote IP host address */
2347 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2348 /* Match by local IP host address */
2349 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2350 /* Match by remote MAC address */
2351 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2352 /* Match by remote TCP/UDP port */
2353 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2354 /* Match by remote TCP/UDP port */
2355 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2356 /* Match by local TCP/UDP port */
2357 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2358 /* Match by Ether-type */
2359 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2360 /* Match by inner VLAN ID */
2361 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2362 /* Match by outer VLAN ID */
2363 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2364 /* Match by IP transport protocol */
2365 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2366 /* For encapsulated packets, match all multicast inner frames */
2367 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2368 /* For encapsulated packets, match all unicast inner frames */
2369 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2370 /* Match otherwise-unmatched multicast and broadcast packets */
2371 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2372 /* Match otherwise-unmatched unicast packets */
2373 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2375 typedef uint32_t efx_filter_match_flags_t;
2377 typedef enum efx_filter_priority_s {
2378 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2379 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2380 * address list or hardware
2381 * requirements. This may only be used
2382 * by the filter implementation for
2384 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2385 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2386 * client (e.g. SR-IOV, HyperV VMQ etc.)
2388 } efx_filter_priority_t;
2391 * FIXME: All these fields are assumed to be in little-endian byte order.
2392 * It may be better for some to be big-endian. See bug42804.
2395 typedef struct efx_filter_spec_s {
2396 efx_filter_match_flags_t efs_match_flags;
2397 uint8_t efs_priority;
2398 efx_filter_flags_t efs_flags;
2399 uint16_t efs_dmaq_id;
2400 uint32_t efs_rss_context;
2401 uint16_t efs_outer_vid;
2402 uint16_t efs_inner_vid;
2403 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2404 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2405 uint16_t efs_ether_type;
2406 uint8_t efs_ip_proto;
2407 efx_tunnel_protocol_t efs_encap_type;
2408 uint16_t efs_loc_port;
2409 uint16_t efs_rem_port;
2410 efx_oword_t efs_rem_host;
2411 efx_oword_t efs_loc_host;
2412 } efx_filter_spec_t;
2415 /* Default values for use in filter specifications */
2416 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2417 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2419 extern __checkReturn efx_rc_t
2421 __in efx_nic_t *enp);
2425 __in efx_nic_t *enp);
2427 extern __checkReturn efx_rc_t
2429 __in efx_nic_t *enp,
2430 __inout efx_filter_spec_t *spec);
2432 extern __checkReturn efx_rc_t
2434 __in efx_nic_t *enp,
2435 __inout efx_filter_spec_t *spec);
2437 extern __checkReturn efx_rc_t
2439 __in efx_nic_t *enp);
2441 extern __checkReturn efx_rc_t
2442 efx_filter_supported_filters(
2443 __in efx_nic_t *enp,
2444 __out_ecount(buffer_length) uint32_t *buffer,
2445 __in size_t buffer_length,
2446 __out size_t *list_lengthp);
2449 efx_filter_spec_init_rx(
2450 __out efx_filter_spec_t *spec,
2451 __in efx_filter_priority_t priority,
2452 __in efx_filter_flags_t flags,
2453 __in efx_rxq_t *erp);
2456 efx_filter_spec_init_tx(
2457 __out efx_filter_spec_t *spec,
2458 __in efx_txq_t *etp);
2460 extern __checkReturn efx_rc_t
2461 efx_filter_spec_set_ipv4_local(
2462 __inout efx_filter_spec_t *spec,
2465 __in uint16_t port);
2467 extern __checkReturn efx_rc_t
2468 efx_filter_spec_set_ipv4_full(
2469 __inout efx_filter_spec_t *spec,
2471 __in uint32_t lhost,
2472 __in uint16_t lport,
2473 __in uint32_t rhost,
2474 __in uint16_t rport);
2476 extern __checkReturn efx_rc_t
2477 efx_filter_spec_set_eth_local(
2478 __inout efx_filter_spec_t *spec,
2480 __in const uint8_t *addr);
2483 efx_filter_spec_set_ether_type(
2484 __inout efx_filter_spec_t *spec,
2485 __in uint16_t ether_type);
2487 extern __checkReturn efx_rc_t
2488 efx_filter_spec_set_uc_def(
2489 __inout efx_filter_spec_t *spec);
2491 extern __checkReturn efx_rc_t
2492 efx_filter_spec_set_mc_def(
2493 __inout efx_filter_spec_t *spec);
2495 typedef enum efx_filter_inner_frame_match_e {
2496 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2497 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2498 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2499 } efx_filter_inner_frame_match_t;
2501 extern __checkReturn efx_rc_t
2502 efx_filter_spec_set_encap_type(
2503 __inout efx_filter_spec_t *spec,
2504 __in efx_tunnel_protocol_t encap_type,
2505 __in efx_filter_inner_frame_match_t inner_frame_match);
2507 #if EFSYS_OPT_RX_SCALE
2508 extern __checkReturn efx_rc_t
2509 efx_filter_spec_set_rss_context(
2510 __inout efx_filter_spec_t *spec,
2511 __in uint32_t rss_context);
2513 #endif /* EFSYS_OPT_FILTER */
2517 extern __checkReturn uint32_t
2519 __in_ecount(count) uint32_t const *input,
2521 __in uint32_t init);
2523 extern __checkReturn uint32_t
2525 __in_ecount(length) uint8_t const *input,
2527 __in uint32_t init);
2529 #if EFSYS_OPT_LICENSING
2533 typedef struct efx_key_stats_s {
2535 uint32_t eks_invalid;
2536 uint32_t eks_blacklisted;
2537 uint32_t eks_unverifiable;
2538 uint32_t eks_wrong_node;
2539 uint32_t eks_licensed_apps_lo;
2540 uint32_t eks_licensed_apps_hi;
2541 uint32_t eks_licensed_features_lo;
2542 uint32_t eks_licensed_features_hi;
2545 extern __checkReturn efx_rc_t
2547 __in efx_nic_t *enp);
2551 __in efx_nic_t *enp);
2553 extern __checkReturn boolean_t
2554 efx_lic_check_support(
2555 __in efx_nic_t *enp);
2557 extern __checkReturn efx_rc_t
2558 efx_lic_update_licenses(
2559 __in efx_nic_t *enp);
2561 extern __checkReturn efx_rc_t
2562 efx_lic_get_key_stats(
2563 __in efx_nic_t *enp,
2564 __out efx_key_stats_t *ksp);
2566 extern __checkReturn efx_rc_t
2568 __in efx_nic_t *enp,
2569 __in uint64_t app_id,
2570 __out boolean_t *licensedp);
2572 extern __checkReturn efx_rc_t
2574 __in efx_nic_t *enp,
2575 __in size_t buffer_size,
2576 __out uint32_t *typep,
2577 __out size_t *lengthp,
2578 __out_opt uint8_t *bufferp);
2581 extern __checkReturn efx_rc_t
2583 __in efx_nic_t *enp,
2584 __in_bcount(buffer_size)
2586 __in size_t buffer_size,
2587 __out uint32_t *startp);
2589 extern __checkReturn efx_rc_t
2591 __in efx_nic_t *enp,
2592 __in_bcount(buffer_size)
2594 __in size_t buffer_size,
2595 __in uint32_t offset,
2596 __out uint32_t *endp);
2598 extern __checkReturn __success(return != B_FALSE) boolean_t
2600 __in efx_nic_t *enp,
2601 __in_bcount(buffer_size)
2603 __in size_t buffer_size,
2604 __in uint32_t offset,
2605 __out uint32_t *startp,
2606 __out uint32_t *lengthp);
2608 extern __checkReturn __success(return != B_FALSE) boolean_t
2609 efx_lic_validate_key(
2610 __in efx_nic_t *enp,
2611 __in_bcount(length) caddr_t keyp,
2612 __in uint32_t length);
2614 extern __checkReturn efx_rc_t
2616 __in efx_nic_t *enp,
2617 __in_bcount(buffer_size)
2619 __in size_t buffer_size,
2620 __in uint32_t offset,
2621 __in uint32_t length,
2622 __out_bcount_part(key_max_size, *lengthp)
2624 __in size_t key_max_size,
2625 __out uint32_t *lengthp);
2627 extern __checkReturn efx_rc_t
2629 __in efx_nic_t *enp,
2630 __in_bcount(buffer_size)
2632 __in size_t buffer_size,
2633 __in uint32_t offset,
2634 __in_bcount(length) caddr_t keyp,
2635 __in uint32_t length,
2636 __out uint32_t *lengthp);
2638 __checkReturn efx_rc_t
2640 __in efx_nic_t *enp,
2641 __in_bcount(buffer_size)
2643 __in size_t buffer_size,
2644 __in uint32_t offset,
2645 __in uint32_t length,
2647 __out uint32_t *deltap);
2649 extern __checkReturn efx_rc_t
2650 efx_lic_create_partition(
2651 __in efx_nic_t *enp,
2652 __in_bcount(buffer_size)
2654 __in size_t buffer_size);
2656 extern __checkReturn efx_rc_t
2657 efx_lic_finish_partition(
2658 __in efx_nic_t *enp,
2659 __in_bcount(buffer_size)
2661 __in size_t buffer_size);
2663 #endif /* EFSYS_OPT_LICENSING */
2667 #if EFSYS_OPT_TUNNEL
2669 extern __checkReturn efx_rc_t
2671 __in efx_nic_t *enp);
2675 __in efx_nic_t *enp);
2678 * For overlay network encapsulation using UDP, the firmware needs to know
2679 * the configured UDP port for the overlay so it can decode encapsulated
2681 * The UDP port/protocol list is global.
2684 extern __checkReturn efx_rc_t
2685 efx_tunnel_config_udp_add(
2686 __in efx_nic_t *enp,
2687 __in uint16_t port /* host/cpu-endian */,
2688 __in efx_tunnel_protocol_t protocol);
2690 extern __checkReturn efx_rc_t
2691 efx_tunnel_config_udp_remove(
2692 __in efx_nic_t *enp,
2693 __in uint16_t port /* host/cpu-endian */,
2694 __in efx_tunnel_protocol_t protocol);
2697 efx_tunnel_config_clear(
2698 __in efx_nic_t *enp);
2701 * Apply tunnel UDP ports configuration to hardware.
2703 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2706 extern __checkReturn efx_rc_t
2707 efx_tunnel_reconfigure(
2708 __in efx_nic_t *enp);
2710 #endif /* EFSYS_OPT_TUNNEL */
2717 #endif /* _SYS_EFX_H */