2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 extern __checkReturn efx_rc_t
152 efx_nic_register_test(
153 __in efx_nic_t *enp);
155 #endif /* EFSYS_OPT_DIAG */
159 __in efx_nic_t *enp);
163 __in efx_nic_t *enp);
167 __in efx_nic_t *enp);
169 #define EFX_PCIE_LINK_SPEED_GEN1 1
170 #define EFX_PCIE_LINK_SPEED_GEN2 2
171 #define EFX_PCIE_LINK_SPEED_GEN3 3
173 typedef enum efx_pcie_link_performance_e {
174 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
175 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
176 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
177 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
178 } efx_pcie_link_performance_t;
180 extern __checkReturn efx_rc_t
181 efx_nic_calculate_pcie_link_bandwidth(
182 __in uint32_t pcie_link_width,
183 __in uint32_t pcie_link_gen,
184 __out uint32_t *bandwidth_mbpsp);
186 extern __checkReturn efx_rc_t
187 efx_nic_check_pcie_link_speed(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out efx_pcie_link_performance_t *resultp);
195 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
196 /* Huntington and Medford require MCDIv2 commands */
197 #define WITH_MCDI_V2 1
200 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
202 typedef enum efx_mcdi_exception_e {
203 EFX_MCDI_EXCEPTION_MC_REBOOT,
204 EFX_MCDI_EXCEPTION_MC_BADASSERT,
205 } efx_mcdi_exception_t;
207 #if EFSYS_OPT_MCDI_LOGGING
208 typedef enum efx_log_msg_e {
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_get_timeout(
246 __in efx_mcdi_req_t *emrp,
247 __out uint32_t *usec_timeoutp);
250 efx_mcdi_request_start(
252 __in efx_mcdi_req_t *emrp,
253 __in boolean_t ev_cpl);
255 extern __checkReturn boolean_t
256 efx_mcdi_request_poll(
257 __in efx_nic_t *enp);
259 extern __checkReturn boolean_t
260 efx_mcdi_request_abort(
261 __in efx_nic_t *enp);
265 __in efx_nic_t *enp);
267 #endif /* EFSYS_OPT_MCDI */
271 #define EFX_NINTR_SIENA 1024
273 typedef enum efx_intr_type_e {
274 EFX_INTR_INVALID = 0,
280 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
282 extern __checkReturn efx_rc_t
285 __in efx_intr_type_t type,
286 __in efsys_mem_t *esmp);
290 __in efx_nic_t *enp);
294 __in efx_nic_t *enp);
297 efx_intr_disable_unlocked(
298 __in efx_nic_t *enp);
300 #define EFX_INTR_NEVQS 32
302 extern __checkReturn efx_rc_t
305 __in unsigned int level);
308 efx_intr_status_line(
310 __out boolean_t *fatalp,
311 __out uint32_t *maskp);
314 efx_intr_status_message(
316 __in unsigned int message,
317 __out boolean_t *fatalp);
321 __in efx_nic_t *enp);
325 __in efx_nic_t *enp);
329 #if EFSYS_OPT_MAC_STATS
331 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
332 typedef enum efx_mac_stat_e {
335 EFX_MAC_RX_UNICST_PKTS,
336 EFX_MAC_RX_MULTICST_PKTS,
337 EFX_MAC_RX_BRDCST_PKTS,
338 EFX_MAC_RX_PAUSE_PKTS,
339 EFX_MAC_RX_LE_64_PKTS,
340 EFX_MAC_RX_65_TO_127_PKTS,
341 EFX_MAC_RX_128_TO_255_PKTS,
342 EFX_MAC_RX_256_TO_511_PKTS,
343 EFX_MAC_RX_512_TO_1023_PKTS,
344 EFX_MAC_RX_1024_TO_15XX_PKTS,
345 EFX_MAC_RX_GE_15XX_PKTS,
347 EFX_MAC_RX_FCS_ERRORS,
348 EFX_MAC_RX_DROP_EVENTS,
349 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
350 EFX_MAC_RX_SYMBOL_ERRORS,
351 EFX_MAC_RX_ALIGN_ERRORS,
352 EFX_MAC_RX_INTERNAL_ERRORS,
353 EFX_MAC_RX_JABBER_PKTS,
354 EFX_MAC_RX_LANE0_CHAR_ERR,
355 EFX_MAC_RX_LANE1_CHAR_ERR,
356 EFX_MAC_RX_LANE2_CHAR_ERR,
357 EFX_MAC_RX_LANE3_CHAR_ERR,
358 EFX_MAC_RX_LANE0_DISP_ERR,
359 EFX_MAC_RX_LANE1_DISP_ERR,
360 EFX_MAC_RX_LANE2_DISP_ERR,
361 EFX_MAC_RX_LANE3_DISP_ERR,
362 EFX_MAC_RX_MATCH_FAULT,
363 EFX_MAC_RX_NODESC_DROP_CNT,
366 EFX_MAC_TX_UNICST_PKTS,
367 EFX_MAC_TX_MULTICST_PKTS,
368 EFX_MAC_TX_BRDCST_PKTS,
369 EFX_MAC_TX_PAUSE_PKTS,
370 EFX_MAC_TX_LE_64_PKTS,
371 EFX_MAC_TX_65_TO_127_PKTS,
372 EFX_MAC_TX_128_TO_255_PKTS,
373 EFX_MAC_TX_256_TO_511_PKTS,
374 EFX_MAC_TX_512_TO_1023_PKTS,
375 EFX_MAC_TX_1024_TO_15XX_PKTS,
376 EFX_MAC_TX_GE_15XX_PKTS,
378 EFX_MAC_TX_SGL_COL_PKTS,
379 EFX_MAC_TX_MULT_COL_PKTS,
380 EFX_MAC_TX_EX_COL_PKTS,
381 EFX_MAC_TX_LATE_COL_PKTS,
383 EFX_MAC_TX_EX_DEF_PKTS,
384 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
385 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
386 EFX_MAC_PM_TRUNC_VFIFO_FULL,
387 EFX_MAC_PM_DISCARD_VFIFO_FULL,
388 EFX_MAC_PM_TRUNC_QBB,
389 EFX_MAC_PM_DISCARD_QBB,
390 EFX_MAC_PM_DISCARD_MAPPING,
391 EFX_MAC_RXDP_Q_DISABLED_PKTS,
392 EFX_MAC_RXDP_DI_DROPPED_PKTS,
393 EFX_MAC_RXDP_STREAMING_PKTS,
394 EFX_MAC_RXDP_HLB_FETCH,
395 EFX_MAC_RXDP_HLB_WAIT,
396 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
397 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
398 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
399 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
400 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
401 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
402 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
403 EFX_MAC_VADAPTER_RX_BAD_BYTES,
404 EFX_MAC_VADAPTER_RX_OVERFLOW,
405 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
406 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
407 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
408 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
409 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
410 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
411 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
412 EFX_MAC_VADAPTER_TX_BAD_BYTES,
413 EFX_MAC_VADAPTER_TX_OVERFLOW,
417 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
419 #endif /* EFSYS_OPT_MAC_STATS */
421 typedef enum efx_link_mode_e {
422 EFX_LINK_UNKNOWN = 0,
435 #define EFX_MAC_ADDR_LEN 6
437 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
439 #define EFX_MAC_MULTICAST_LIST_MAX 256
441 #define EFX_MAC_SDU_MAX 9202
443 #define EFX_MAC_PDU_ADJUSTMENT \
447 + /* bug16011 */ 16) \
449 #define EFX_MAC_PDU(_sdu) \
450 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
453 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
454 * the SDU rounded up slightly.
456 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
458 #define EFX_MAC_PDU_MIN 60
459 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
461 extern __checkReturn efx_rc_t
466 extern __checkReturn efx_rc_t
471 extern __checkReturn efx_rc_t
476 extern __checkReturn efx_rc_t
479 __in boolean_t all_unicst,
480 __in boolean_t mulcst,
481 __in boolean_t all_mulcst,
482 __in boolean_t brdcst);
484 extern __checkReturn efx_rc_t
485 efx_mac_multicast_list_set(
487 __in_ecount(6*count) uint8_t const *addrs,
490 extern __checkReturn efx_rc_t
491 efx_mac_filter_default_rxq_set(
494 __in boolean_t using_rss);
497 efx_mac_filter_default_rxq_clear(
498 __in efx_nic_t *enp);
500 extern __checkReturn efx_rc_t
503 __in boolean_t enabled);
505 extern __checkReturn efx_rc_t
508 __out boolean_t *mac_upp);
510 #define EFX_FCNTL_RESPOND 0x00000001
511 #define EFX_FCNTL_GENERATE 0x00000002
513 extern __checkReturn efx_rc_t
516 __in unsigned int fcntl,
517 __in boolean_t autoneg);
522 __out unsigned int *fcntl_wantedp,
523 __out unsigned int *fcntl_linkp);
526 #if EFSYS_OPT_MAC_STATS
530 extern __checkReturn const char *
533 __in unsigned int id);
535 #endif /* EFSYS_OPT_NAMES */
537 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
539 #define EFX_MAC_STATS_MASK_NPAGES \
540 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
541 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
544 * Get mask of MAC statistics supported by the hardware.
546 * If mask_size is insufficient to return the mask, EINVAL error is
547 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
548 * (which is sizeof (uint32_t)) is sufficient.
550 extern __checkReturn efx_rc_t
551 efx_mac_stats_get_mask(
553 __out_bcount(mask_size) uint32_t *maskp,
554 __in size_t mask_size);
556 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
557 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
558 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
560 #define EFX_MAC_STATS_SIZE 0x400
562 extern __checkReturn efx_rc_t
564 __in efx_nic_t *enp);
567 * Upload mac statistics supported by the hardware into the given buffer.
569 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
572 * The hardware will only DMA statistics that it understands (of course).
573 * Drivers should not make any assumptions about which statistics are
574 * supported, especially when the statistics are generated by firmware.
576 * Thus, drivers should zero this buffer before use, so that not-understood
577 * statistics read back as zero.
579 extern __checkReturn efx_rc_t
580 efx_mac_stats_upload(
582 __in efsys_mem_t *esmp);
584 extern __checkReturn efx_rc_t
585 efx_mac_stats_periodic(
587 __in efsys_mem_t *esmp,
588 __in uint16_t period_ms,
589 __in boolean_t events);
591 extern __checkReturn efx_rc_t
592 efx_mac_stats_update(
594 __in efsys_mem_t *esmp,
595 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
596 __inout_opt uint32_t *generationp);
598 #endif /* EFSYS_OPT_MAC_STATS */
602 typedef enum efx_mon_type_e {
614 __in efx_nic_t *enp);
616 #endif /* EFSYS_OPT_NAMES */
618 extern __checkReturn efx_rc_t
620 __in efx_nic_t *enp);
622 #if EFSYS_OPT_MON_STATS
624 #define EFX_MON_STATS_PAGE_SIZE 0x100
625 #define EFX_MON_MASK_ELEMENT_SIZE 32
627 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
628 typedef enum efx_mon_stat_e {
635 EFX_MON_STAT_EXT_TEMP,
636 EFX_MON_STAT_INT_TEMP,
639 EFX_MON_STAT_INT_COOLING,
640 EFX_MON_STAT_EXT_COOLING,
648 EFX_MON_STAT_AOE_TEMP,
649 EFX_MON_STAT_PSU_AOE_TEMP,
650 EFX_MON_STAT_PSU_TEMP,
656 EFX_MON_STAT_VAOE_IN,
658 EFX_MON_STAT_IAOE_IN,
659 EFX_MON_STAT_NIC_POWER,
663 EFX_MON_STAT_0_9V_ADC,
664 EFX_MON_STAT_INT_TEMP2,
665 EFX_MON_STAT_VREG_TEMP,
666 EFX_MON_STAT_VREG_0_9V_TEMP,
667 EFX_MON_STAT_VREG_1_2V_TEMP,
668 EFX_MON_STAT_INT_VPTAT,
669 EFX_MON_STAT_INT_ADC_TEMP,
670 EFX_MON_STAT_EXT_VPTAT,
671 EFX_MON_STAT_EXT_ADC_TEMP,
672 EFX_MON_STAT_AMBIENT_TEMP,
673 EFX_MON_STAT_AIRFLOW,
674 EFX_MON_STAT_VDD08D_VSS08D_CSR,
675 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
676 EFX_MON_STAT_HOTPOINT_TEMP,
677 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
678 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
679 EFX_MON_STAT_MUM_VCC,
682 EFX_MON_STAT_0V9_A_TEMP,
685 EFX_MON_STAT_0V9_B_TEMP,
686 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
687 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
688 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
689 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
690 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
691 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
692 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
693 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
694 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
695 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
696 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
697 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
698 EFX_MON_STAT_SODIMM_VOUT,
699 EFX_MON_STAT_SODIMM_0_TEMP,
700 EFX_MON_STAT_SODIMM_1_TEMP,
701 EFX_MON_STAT_PHY0_VCC,
702 EFX_MON_STAT_PHY1_VCC,
703 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
704 EFX_MON_STAT_BOARD_FRONT_TEMP,
705 EFX_MON_STAT_BOARD_BACK_TEMP,
709 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
711 typedef enum efx_mon_stat_state_e {
712 EFX_MON_STAT_STATE_OK = 0,
713 EFX_MON_STAT_STATE_WARNING = 1,
714 EFX_MON_STAT_STATE_FATAL = 2,
715 EFX_MON_STAT_STATE_BROKEN = 3,
716 EFX_MON_STAT_STATE_NO_READING = 4,
717 } efx_mon_stat_state_t;
719 typedef struct efx_mon_stat_value_s {
722 } efx_mon_stat_value_t;
729 __in efx_mon_stat_t id);
731 #endif /* EFSYS_OPT_NAMES */
733 extern __checkReturn efx_rc_t
734 efx_mon_stats_update(
736 __in efsys_mem_t *esmp,
737 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
739 #endif /* EFSYS_OPT_MON_STATS */
743 __in efx_nic_t *enp);
747 extern __checkReturn efx_rc_t
749 __in efx_nic_t *enp);
751 #if EFSYS_OPT_PHY_LED_CONTROL
753 typedef enum efx_phy_led_mode_e {
754 EFX_PHY_LED_DEFAULT = 0,
759 } efx_phy_led_mode_t;
761 extern __checkReturn efx_rc_t
764 __in efx_phy_led_mode_t mode);
766 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
768 extern __checkReturn efx_rc_t
770 __in efx_nic_t *enp);
772 #if EFSYS_OPT_LOOPBACK
774 typedef enum efx_loopback_type_e {
775 EFX_LOOPBACK_OFF = 0,
776 EFX_LOOPBACK_DATA = 1,
777 EFX_LOOPBACK_GMAC = 2,
778 EFX_LOOPBACK_XGMII = 3,
779 EFX_LOOPBACK_XGXS = 4,
780 EFX_LOOPBACK_XAUI = 5,
781 EFX_LOOPBACK_GMII = 6,
782 EFX_LOOPBACK_SGMII = 7,
783 EFX_LOOPBACK_XGBR = 8,
784 EFX_LOOPBACK_XFI = 9,
785 EFX_LOOPBACK_XAUI_FAR = 10,
786 EFX_LOOPBACK_GMII_FAR = 11,
787 EFX_LOOPBACK_SGMII_FAR = 12,
788 EFX_LOOPBACK_XFI_FAR = 13,
789 EFX_LOOPBACK_GPHY = 14,
790 EFX_LOOPBACK_PHY_XS = 15,
791 EFX_LOOPBACK_PCS = 16,
792 EFX_LOOPBACK_PMA_PMD = 17,
793 EFX_LOOPBACK_XPORT = 18,
794 EFX_LOOPBACK_XGMII_WS = 19,
795 EFX_LOOPBACK_XAUI_WS = 20,
796 EFX_LOOPBACK_XAUI_WS_FAR = 21,
797 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
798 EFX_LOOPBACK_GMII_WS = 23,
799 EFX_LOOPBACK_XFI_WS = 24,
800 EFX_LOOPBACK_XFI_WS_FAR = 25,
801 EFX_LOOPBACK_PHYXS_WS = 26,
802 EFX_LOOPBACK_PMA_INT = 27,
803 EFX_LOOPBACK_SD_NEAR = 28,
804 EFX_LOOPBACK_SD_FAR = 29,
805 EFX_LOOPBACK_PMA_INT_WS = 30,
806 EFX_LOOPBACK_SD_FEP2_WS = 31,
807 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
808 EFX_LOOPBACK_SD_FEP_WS = 33,
809 EFX_LOOPBACK_SD_FES_WS = 34,
811 } efx_loopback_type_t;
813 typedef enum efx_loopback_kind_e {
814 EFX_LOOPBACK_KIND_OFF = 0,
815 EFX_LOOPBACK_KIND_ALL,
816 EFX_LOOPBACK_KIND_MAC,
817 EFX_LOOPBACK_KIND_PHY,
819 } efx_loopback_kind_t;
823 __in efx_loopback_kind_t loopback_kind,
824 __out efx_qword_t *maskp);
826 extern __checkReturn efx_rc_t
827 efx_port_loopback_set(
829 __in efx_link_mode_t link_mode,
830 __in efx_loopback_type_t type);
834 extern __checkReturn const char *
835 efx_loopback_type_name(
837 __in efx_loopback_type_t type);
839 #endif /* EFSYS_OPT_NAMES */
841 #endif /* EFSYS_OPT_LOOPBACK */
843 extern __checkReturn efx_rc_t
846 __out_opt efx_link_mode_t *link_modep);
850 __in efx_nic_t *enp);
852 typedef enum efx_phy_cap_type_e {
853 EFX_PHY_CAP_INVALID = 0,
860 EFX_PHY_CAP_10000FDX,
864 EFX_PHY_CAP_40000FDX,
866 } efx_phy_cap_type_t;
869 #define EFX_PHY_CAP_CURRENT 0x00000000
870 #define EFX_PHY_CAP_DEFAULT 0x00000001
871 #define EFX_PHY_CAP_PERM 0x00000002
877 __out uint32_t *maskp);
879 extern __checkReturn efx_rc_t
887 __out uint32_t *maskp);
889 extern __checkReturn efx_rc_t
892 __out uint32_t *ouip);
894 typedef enum efx_phy_media_type_e {
895 EFX_PHY_MEDIA_INVALID = 0,
900 EFX_PHY_MEDIA_SFP_PLUS,
901 EFX_PHY_MEDIA_BASE_T,
902 EFX_PHY_MEDIA_QSFP_PLUS,
904 } efx_phy_media_type_t;
906 /* Get the type of medium currently used. If the board has ports for
907 * modules, a module is present, and we recognise the media type of
908 * the module, then this will be the media type of the module.
909 * Otherwise it will be the media type of the port.
912 efx_phy_media_type_get(
914 __out efx_phy_media_type_t *typep);
917 efx_phy_module_get_info(
919 __in uint8_t dev_addr,
922 __out_bcount(len) uint8_t *data);
924 #if EFSYS_OPT_PHY_STATS
926 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
927 typedef enum efx_phy_stat_e {
929 EFX_PHY_STAT_PMA_PMD_LINK_UP,
930 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
931 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
932 EFX_PHY_STAT_PMA_PMD_REV_A,
933 EFX_PHY_STAT_PMA_PMD_REV_B,
934 EFX_PHY_STAT_PMA_PMD_REV_C,
935 EFX_PHY_STAT_PMA_PMD_REV_D,
936 EFX_PHY_STAT_PCS_LINK_UP,
937 EFX_PHY_STAT_PCS_RX_FAULT,
938 EFX_PHY_STAT_PCS_TX_FAULT,
939 EFX_PHY_STAT_PCS_BER,
940 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
941 EFX_PHY_STAT_PHY_XS_LINK_UP,
942 EFX_PHY_STAT_PHY_XS_RX_FAULT,
943 EFX_PHY_STAT_PHY_XS_TX_FAULT,
944 EFX_PHY_STAT_PHY_XS_ALIGN,
945 EFX_PHY_STAT_PHY_XS_SYNC_A,
946 EFX_PHY_STAT_PHY_XS_SYNC_B,
947 EFX_PHY_STAT_PHY_XS_SYNC_C,
948 EFX_PHY_STAT_PHY_XS_SYNC_D,
949 EFX_PHY_STAT_AN_LINK_UP,
950 EFX_PHY_STAT_AN_MASTER,
951 EFX_PHY_STAT_AN_LOCAL_RX_OK,
952 EFX_PHY_STAT_AN_REMOTE_RX_OK,
953 EFX_PHY_STAT_CL22EXT_LINK_UP,
958 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
959 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
960 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
961 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
962 EFX_PHY_STAT_AN_COMPLETE,
963 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
964 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
965 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
966 EFX_PHY_STAT_PCS_FW_VERSION_0,
967 EFX_PHY_STAT_PCS_FW_VERSION_1,
968 EFX_PHY_STAT_PCS_FW_VERSION_2,
969 EFX_PHY_STAT_PCS_FW_VERSION_3,
970 EFX_PHY_STAT_PCS_FW_BUILD_YY,
971 EFX_PHY_STAT_PCS_FW_BUILD_MM,
972 EFX_PHY_STAT_PCS_FW_BUILD_DD,
973 EFX_PHY_STAT_PCS_OP_MODE,
977 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
984 __in efx_phy_stat_t stat);
986 #endif /* EFSYS_OPT_NAMES */
988 #define EFX_PHY_STATS_SIZE 0x100
990 extern __checkReturn efx_rc_t
991 efx_phy_stats_update(
993 __in efsys_mem_t *esmp,
994 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
996 #endif /* EFSYS_OPT_PHY_STATS */
1001 typedef enum efx_bist_type_e {
1002 EFX_BIST_TYPE_UNKNOWN,
1003 EFX_BIST_TYPE_PHY_NORMAL,
1004 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1005 EFX_BIST_TYPE_PHY_CABLE_LONG,
1006 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1007 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
1008 EFX_BIST_TYPE_REG, /* Test the register memories */
1009 EFX_BIST_TYPE_NTYPES,
1012 typedef enum efx_bist_result_e {
1013 EFX_BIST_RESULT_UNKNOWN,
1014 EFX_BIST_RESULT_RUNNING,
1015 EFX_BIST_RESULT_PASSED,
1016 EFX_BIST_RESULT_FAILED,
1017 } efx_bist_result_t;
1019 typedef enum efx_phy_cable_status_e {
1020 EFX_PHY_CABLE_STATUS_OK,
1021 EFX_PHY_CABLE_STATUS_INVALID,
1022 EFX_PHY_CABLE_STATUS_OPEN,
1023 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1024 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1025 EFX_PHY_CABLE_STATUS_BUSY,
1026 } efx_phy_cable_status_t;
1028 typedef enum efx_bist_value_e {
1029 EFX_BIST_PHY_CABLE_LENGTH_A,
1030 EFX_BIST_PHY_CABLE_LENGTH_B,
1031 EFX_BIST_PHY_CABLE_LENGTH_C,
1032 EFX_BIST_PHY_CABLE_LENGTH_D,
1033 EFX_BIST_PHY_CABLE_STATUS_A,
1034 EFX_BIST_PHY_CABLE_STATUS_B,
1035 EFX_BIST_PHY_CABLE_STATUS_C,
1036 EFX_BIST_PHY_CABLE_STATUS_D,
1037 EFX_BIST_FAULT_CODE,
1038 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1043 EFX_BIST_MEM_EXPECT,
1044 EFX_BIST_MEM_ACTUAL,
1046 EFX_BIST_MEM_ECC_PARITY,
1047 EFX_BIST_MEM_ECC_FATAL,
1051 extern __checkReturn efx_rc_t
1052 efx_bist_enable_offline(
1053 __in efx_nic_t *enp);
1055 extern __checkReturn efx_rc_t
1057 __in efx_nic_t *enp,
1058 __in efx_bist_type_t type);
1060 extern __checkReturn efx_rc_t
1062 __in efx_nic_t *enp,
1063 __in efx_bist_type_t type,
1064 __out efx_bist_result_t *resultp,
1065 __out_opt uint32_t *value_maskp,
1066 __out_ecount_opt(count) unsigned long *valuesp,
1071 __in efx_nic_t *enp,
1072 __in efx_bist_type_t type);
1074 #endif /* EFSYS_OPT_BIST */
1076 #define EFX_FEATURE_IPV6 0x00000001
1077 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1078 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1079 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1080 #define EFX_FEATURE_MCDI 0x00000020
1081 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1082 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1083 #define EFX_FEATURE_TURBO 0x00000100
1084 #define EFX_FEATURE_MCDI_DMA 0x00000200
1085 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1086 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1087 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1088 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1089 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1091 typedef struct efx_nic_cfg_s {
1092 uint32_t enc_board_type;
1093 uint32_t enc_phy_type;
1095 char enc_phy_name[21];
1097 char enc_phy_revision[21];
1098 efx_mon_type_t enc_mon_type;
1099 #if EFSYS_OPT_MON_STATS
1100 uint32_t enc_mon_stat_dma_buf_size;
1101 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1103 unsigned int enc_features;
1104 uint8_t enc_mac_addr[6];
1105 uint8_t enc_port; /* PHY port number */
1106 uint32_t enc_intr_vec_base;
1107 uint32_t enc_intr_limit;
1108 uint32_t enc_evq_limit;
1109 uint32_t enc_txq_limit;
1110 uint32_t enc_rxq_limit;
1111 uint32_t enc_txq_max_ndescs;
1112 uint32_t enc_buftbl_limit;
1113 uint32_t enc_piobuf_limit;
1114 uint32_t enc_piobuf_size;
1115 uint32_t enc_piobuf_min_alloc_size;
1116 uint32_t enc_evq_timer_quantum_ns;
1117 uint32_t enc_evq_timer_max_us;
1118 uint32_t enc_clk_mult;
1119 uint32_t enc_rx_prefix_size;
1120 uint32_t enc_rx_buf_align_start;
1121 uint32_t enc_rx_buf_align_end;
1122 #if EFSYS_OPT_LOOPBACK
1123 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1124 #endif /* EFSYS_OPT_LOOPBACK */
1125 #if EFSYS_OPT_PHY_FLAGS
1126 uint32_t enc_phy_flags_mask;
1127 #endif /* EFSYS_OPT_PHY_FLAGS */
1128 #if EFSYS_OPT_PHY_LED_CONTROL
1129 uint32_t enc_led_mask;
1130 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1131 #if EFSYS_OPT_PHY_STATS
1132 uint64_t enc_phy_stat_mask;
1133 #endif /* EFSYS_OPT_PHY_STATS */
1135 uint8_t enc_mcdi_mdio_channel;
1136 #if EFSYS_OPT_PHY_STATS
1137 uint32_t enc_mcdi_phy_stat_mask;
1138 #endif /* EFSYS_OPT_PHY_STATS */
1139 #if EFSYS_OPT_MON_STATS
1140 uint32_t *enc_mcdi_sensor_maskp;
1141 uint32_t enc_mcdi_sensor_mask_size;
1142 #endif /* EFSYS_OPT_MON_STATS */
1143 #endif /* EFSYS_OPT_MCDI */
1145 uint32_t enc_bist_mask;
1146 #endif /* EFSYS_OPT_BIST */
1147 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1150 uint32_t enc_privilege_mask;
1151 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1152 boolean_t enc_bug26807_workaround;
1153 boolean_t enc_bug35388_workaround;
1154 boolean_t enc_bug41750_workaround;
1155 boolean_t enc_bug61265_workaround;
1156 boolean_t enc_rx_batching_enabled;
1157 /* Maximum number of descriptors completed in an rx event. */
1158 uint32_t enc_rx_batch_max;
1159 /* Number of rx descriptors the hardware requires for a push. */
1160 uint32_t enc_rx_push_align;
1161 /* Maximum amount of data in DMA descriptor */
1162 uint32_t enc_tx_dma_desc_size_max;
1164 * Boundary which DMA descriptor data must not cross or 0 if no
1167 uint32_t enc_tx_dma_desc_boundary;
1169 * Maximum number of bytes into the packet the TCP header can start for
1170 * the hardware to apply TSO packet edits.
1172 uint32_t enc_tx_tso_tcp_header_offset_limit;
1173 boolean_t enc_fw_assisted_tso_enabled;
1174 boolean_t enc_fw_assisted_tso_v2_enabled;
1175 /* Number of TSO contexts on the NIC (FATSOv2) */
1176 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1177 boolean_t enc_hw_tx_insert_vlan_enabled;
1178 /* Number of PFs on the NIC */
1179 uint32_t enc_hw_pf_count;
1180 /* Datapath firmware vadapter/vport/vswitch support */
1181 boolean_t enc_datapath_cap_evb;
1182 boolean_t enc_rx_disable_scatter_supported;
1183 boolean_t enc_allow_set_mac_with_installed_filters;
1184 boolean_t enc_enhanced_set_mac_supported;
1185 boolean_t enc_init_evq_v2_supported;
1186 boolean_t enc_rx_packed_stream_supported;
1187 boolean_t enc_rx_var_packed_stream_supported;
1188 boolean_t enc_pm_and_rxdp_counters;
1189 boolean_t enc_mac_stats_40g_tx_size_bins;
1190 /* External port identifier */
1191 uint8_t enc_external_port;
1192 uint32_t enc_mcdi_max_payload_length;
1193 /* VPD may be per-PF or global */
1194 boolean_t enc_vpd_is_global;
1195 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1196 uint32_t enc_required_pcie_bandwidth_mbps;
1197 uint32_t enc_max_pcie_link_gen;
1198 /* Firmware verifies integrity of NVRAM updates */
1199 uint32_t enc_fw_verified_nvram_update_required;
1202 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1203 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1205 #define EFX_PCI_FUNCTION(_encp) \
1206 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1208 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1210 extern const efx_nic_cfg_t *
1212 __in efx_nic_t *enp);
1214 /* Driver resource limits (minimum required/maximum usable). */
1215 typedef struct efx_drv_limits_s {
1216 uint32_t edl_min_evq_count;
1217 uint32_t edl_max_evq_count;
1219 uint32_t edl_min_rxq_count;
1220 uint32_t edl_max_rxq_count;
1222 uint32_t edl_min_txq_count;
1223 uint32_t edl_max_txq_count;
1225 /* PIO blocks (sub-allocated from piobuf) */
1226 uint32_t edl_min_pio_alloc_size;
1227 uint32_t edl_max_pio_alloc_count;
1230 extern __checkReturn efx_rc_t
1231 efx_nic_set_drv_limits(
1232 __inout efx_nic_t *enp,
1233 __in efx_drv_limits_t *edlp);
1235 typedef enum efx_nic_region_e {
1236 EFX_REGION_VI, /* Memory BAR UC mapping */
1237 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1240 extern __checkReturn efx_rc_t
1241 efx_nic_get_bar_region(
1242 __in efx_nic_t *enp,
1243 __in efx_nic_region_t region,
1244 __out uint32_t *offsetp,
1245 __out size_t *sizep);
1247 extern __checkReturn efx_rc_t
1248 efx_nic_get_vi_pool(
1249 __in efx_nic_t *enp,
1250 __out uint32_t *evq_countp,
1251 __out uint32_t *rxq_countp,
1252 __out uint32_t *txq_countp);
1257 typedef enum efx_vpd_tag_e {
1264 typedef uint16_t efx_vpd_keyword_t;
1266 typedef struct efx_vpd_value_s {
1267 efx_vpd_tag_t evv_tag;
1268 efx_vpd_keyword_t evv_keyword;
1270 uint8_t evv_value[0x100];
1274 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1276 extern __checkReturn efx_rc_t
1278 __in efx_nic_t *enp);
1280 extern __checkReturn efx_rc_t
1282 __in efx_nic_t *enp,
1283 __out size_t *sizep);
1285 extern __checkReturn efx_rc_t
1287 __in efx_nic_t *enp,
1288 __out_bcount(size) caddr_t data,
1291 extern __checkReturn efx_rc_t
1293 __in efx_nic_t *enp,
1294 __in_bcount(size) caddr_t data,
1297 extern __checkReturn efx_rc_t
1299 __in efx_nic_t *enp,
1300 __in_bcount(size) caddr_t data,
1303 extern __checkReturn efx_rc_t
1305 __in efx_nic_t *enp,
1306 __in_bcount(size) caddr_t data,
1308 __inout efx_vpd_value_t *evvp);
1310 extern __checkReturn efx_rc_t
1312 __in efx_nic_t *enp,
1313 __inout_bcount(size) caddr_t data,
1315 __in efx_vpd_value_t *evvp);
1317 extern __checkReturn efx_rc_t
1319 __in efx_nic_t *enp,
1320 __inout_bcount(size) caddr_t data,
1322 __out efx_vpd_value_t *evvp,
1323 __inout unsigned int *contp);
1325 extern __checkReturn efx_rc_t
1327 __in efx_nic_t *enp,
1328 __in_bcount(size) caddr_t data,
1333 __in efx_nic_t *enp);
1335 #endif /* EFSYS_OPT_VPD */
1341 typedef enum efx_nvram_type_e {
1342 EFX_NVRAM_INVALID = 0,
1344 EFX_NVRAM_BOOTROM_CFG,
1345 EFX_NVRAM_MC_FIRMWARE,
1346 EFX_NVRAM_MC_GOLDEN,
1352 EFX_NVRAM_FPGA_BACKUP,
1353 EFX_NVRAM_DYNAMIC_CFG,
1359 extern __checkReturn efx_rc_t
1361 __in efx_nic_t *enp);
1365 extern __checkReturn efx_rc_t
1367 __in efx_nic_t *enp);
1369 #endif /* EFSYS_OPT_DIAG */
1371 extern __checkReturn efx_rc_t
1373 __in efx_nic_t *enp,
1374 __in efx_nvram_type_t type,
1375 __out size_t *sizep);
1377 extern __checkReturn efx_rc_t
1379 __in efx_nic_t *enp,
1380 __in efx_nvram_type_t type,
1381 __out_opt size_t *pref_chunkp);
1383 extern __checkReturn efx_rc_t
1384 efx_nvram_rw_finish(
1385 __in efx_nic_t *enp,
1386 __in efx_nvram_type_t type);
1388 extern __checkReturn efx_rc_t
1389 efx_nvram_get_version(
1390 __in efx_nic_t *enp,
1391 __in efx_nvram_type_t type,
1392 __out uint32_t *subtypep,
1393 __out_ecount(4) uint16_t version[4]);
1395 extern __checkReturn efx_rc_t
1396 efx_nvram_read_chunk(
1397 __in efx_nic_t *enp,
1398 __in efx_nvram_type_t type,
1399 __in unsigned int offset,
1400 __out_bcount(size) caddr_t data,
1403 extern __checkReturn efx_rc_t
1404 efx_nvram_set_version(
1405 __in efx_nic_t *enp,
1406 __in efx_nvram_type_t type,
1407 __in_ecount(4) uint16_t version[4]);
1409 extern __checkReturn efx_rc_t
1411 __in efx_nic_t *enp,
1412 __in efx_nvram_type_t type,
1413 __in_bcount(partn_size) caddr_t partn_data,
1414 __in size_t partn_size);
1416 extern __checkReturn efx_rc_t
1418 __in efx_nic_t *enp,
1419 __in efx_nvram_type_t type);
1421 extern __checkReturn efx_rc_t
1422 efx_nvram_write_chunk(
1423 __in efx_nic_t *enp,
1424 __in efx_nvram_type_t type,
1425 __in unsigned int offset,
1426 __in_bcount(size) caddr_t data,
1431 __in efx_nic_t *enp);
1433 #endif /* EFSYS_OPT_NVRAM */
1435 #if EFSYS_OPT_BOOTCFG
1437 /* Report size and offset of bootcfg sector in NVRAM partition. */
1438 extern __checkReturn efx_rc_t
1439 efx_bootcfg_sector_info(
1440 __in efx_nic_t *enp,
1442 __out_opt uint32_t *sector_countp,
1443 __out size_t *offsetp,
1444 __out size_t *max_sizep);
1447 * Copy bootcfg sector data to a target buffer which may differ in size.
1448 * Optionally corrects format errors in source buffer.
1451 efx_bootcfg_copy_sector(
1452 __in efx_nic_t *enp,
1453 __inout_bcount(sector_length)
1455 __in size_t sector_length,
1456 __out_bcount(data_size) uint8_t *data,
1457 __in size_t data_size,
1458 __in boolean_t handle_format_errors);
1462 __in efx_nic_t *enp,
1463 __out_bcount(size) caddr_t data,
1468 __in efx_nic_t *enp,
1469 __in_bcount(size) caddr_t data,
1472 #endif /* EFSYS_OPT_BOOTCFG */
1476 typedef enum efx_pattern_type_t {
1477 EFX_PATTERN_BYTE_INCREMENT = 0,
1478 EFX_PATTERN_ALL_THE_SAME,
1479 EFX_PATTERN_BIT_ALTERNATE,
1480 EFX_PATTERN_BYTE_ALTERNATE,
1481 EFX_PATTERN_BYTE_CHANGING,
1482 EFX_PATTERN_BIT_SWEEP,
1484 } efx_pattern_type_t;
1487 (*efx_sram_pattern_fn_t)(
1489 __in boolean_t negate,
1490 __out efx_qword_t *eqp);
1492 extern __checkReturn efx_rc_t
1494 __in efx_nic_t *enp,
1495 __in efx_pattern_type_t type);
1497 #endif /* EFSYS_OPT_DIAG */
1499 extern __checkReturn efx_rc_t
1500 efx_sram_buf_tbl_set(
1501 __in efx_nic_t *enp,
1503 __in efsys_mem_t *esmp,
1507 efx_sram_buf_tbl_clear(
1508 __in efx_nic_t *enp,
1512 #define EFX_BUF_TBL_SIZE 0x20000
1514 #define EFX_BUF_SIZE 4096
1518 typedef struct efx_evq_s efx_evq_t;
1520 #if EFSYS_OPT_QSTATS
1522 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1523 typedef enum efx_ev_qstat_e {
1529 EV_RX_PAUSE_FRM_ERR,
1530 EV_RX_BUF_OWNER_ID_ERR,
1531 EV_RX_IPV4_HDR_CHKSUM_ERR,
1532 EV_RX_TCP_UDP_CHKSUM_ERR,
1536 EV_RX_MCAST_HASH_MATCH,
1553 EV_DRIVER_SRM_UPD_DONE,
1554 EV_DRIVER_TX_DESCQ_FLS_DONE,
1555 EV_DRIVER_RX_DESCQ_FLS_DONE,
1556 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1557 EV_DRIVER_RX_DSC_ERROR,
1558 EV_DRIVER_TX_DSC_ERROR,
1564 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1566 #endif /* EFSYS_OPT_QSTATS */
1568 extern __checkReturn efx_rc_t
1570 __in efx_nic_t *enp);
1574 __in efx_nic_t *enp);
1576 #define EFX_EVQ_MAXNEVS 32768
1577 #define EFX_EVQ_MINNEVS 512
1579 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1580 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1582 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1583 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1584 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1585 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1587 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1588 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1589 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1591 extern __checkReturn efx_rc_t
1593 __in efx_nic_t *enp,
1594 __in unsigned int index,
1595 __in efsys_mem_t *esmp,
1599 __in uint32_t flags,
1600 __deref_out efx_evq_t **eepp);
1604 __in efx_evq_t *eep,
1605 __in uint16_t data);
1607 typedef __checkReturn boolean_t
1608 (*efx_initialized_ev_t)(
1609 __in_opt void *arg);
1611 #define EFX_PKT_UNICAST 0x0004
1612 #define EFX_PKT_START 0x0008
1614 #define EFX_PKT_VLAN_TAGGED 0x0010
1615 #define EFX_CKSUM_TCPUDP 0x0020
1616 #define EFX_CKSUM_IPV4 0x0040
1617 #define EFX_PKT_CONT 0x0080
1619 #define EFX_CHECK_VLAN 0x0100
1620 #define EFX_PKT_TCP 0x0200
1621 #define EFX_PKT_UDP 0x0400
1622 #define EFX_PKT_IPV4 0x0800
1624 #define EFX_PKT_IPV6 0x1000
1625 #define EFX_PKT_PREFIX_LEN 0x2000
1626 #define EFX_ADDR_MISMATCH 0x4000
1627 #define EFX_DISCARD 0x8000
1630 * The following flags are used only for packed stream
1631 * mode. The values for the flags are reused to fit into 16 bit,
1632 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1633 * packed stream mode
1635 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1636 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1639 #define EFX_EV_RX_NLABELS 32
1640 #define EFX_EV_TX_NLABELS 32
1642 typedef __checkReturn boolean_t
1645 __in uint32_t label,
1648 __in uint16_t flags);
1650 #if EFSYS_OPT_RX_PACKED_STREAM
1653 * Packed stream mode is documented in SF-112241-TC.
1654 * The general idea is that, instead of putting each incoming
1655 * packet into a separate buffer which is specified in a RX
1656 * descriptor, a large buffer is provided to the hardware and
1657 * packets are put there in a continuous stream.
1658 * The main advantage of such an approach is that RX queue refilling
1659 * happens much less frequently.
1662 typedef __checkReturn boolean_t
1665 __in uint32_t label,
1667 __in uint32_t pkt_count,
1668 __in uint16_t flags);
1672 typedef __checkReturn boolean_t
1675 __in uint32_t label,
1678 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1679 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1680 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1681 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1682 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1683 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1684 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1685 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1686 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1688 typedef __checkReturn boolean_t
1689 (*efx_exception_ev_t)(
1691 __in uint32_t label,
1692 __in uint32_t data);
1694 typedef __checkReturn boolean_t
1695 (*efx_rxq_flush_done_ev_t)(
1697 __in uint32_t rxq_index);
1699 typedef __checkReturn boolean_t
1700 (*efx_rxq_flush_failed_ev_t)(
1702 __in uint32_t rxq_index);
1704 typedef __checkReturn boolean_t
1705 (*efx_txq_flush_done_ev_t)(
1707 __in uint32_t txq_index);
1709 typedef __checkReturn boolean_t
1710 (*efx_software_ev_t)(
1712 __in uint16_t magic);
1714 typedef __checkReturn boolean_t
1717 __in uint32_t code);
1719 #define EFX_SRAM_CLEAR 0
1720 #define EFX_SRAM_UPDATE 1
1721 #define EFX_SRAM_ILLEGAL_CLEAR 2
1723 typedef __checkReturn boolean_t
1724 (*efx_wake_up_ev_t)(
1726 __in uint32_t label);
1728 typedef __checkReturn boolean_t
1731 __in uint32_t label);
1733 typedef __checkReturn boolean_t
1734 (*efx_link_change_ev_t)(
1736 __in efx_link_mode_t link_mode);
1738 #if EFSYS_OPT_MON_STATS
1740 typedef __checkReturn boolean_t
1741 (*efx_monitor_ev_t)(
1743 __in efx_mon_stat_t id,
1744 __in efx_mon_stat_value_t value);
1746 #endif /* EFSYS_OPT_MON_STATS */
1748 #if EFSYS_OPT_MAC_STATS
1750 typedef __checkReturn boolean_t
1751 (*efx_mac_stats_ev_t)(
1753 __in uint32_t generation
1756 #endif /* EFSYS_OPT_MAC_STATS */
1758 typedef struct efx_ev_callbacks_s {
1759 efx_initialized_ev_t eec_initialized;
1761 #if EFSYS_OPT_RX_PACKED_STREAM
1762 efx_rx_ps_ev_t eec_rx_ps;
1765 efx_exception_ev_t eec_exception;
1766 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1767 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1768 efx_txq_flush_done_ev_t eec_txq_flush_done;
1769 efx_software_ev_t eec_software;
1770 efx_sram_ev_t eec_sram;
1771 efx_wake_up_ev_t eec_wake_up;
1772 efx_timer_ev_t eec_timer;
1773 efx_link_change_ev_t eec_link_change;
1774 #if EFSYS_OPT_MON_STATS
1775 efx_monitor_ev_t eec_monitor;
1776 #endif /* EFSYS_OPT_MON_STATS */
1777 #if EFSYS_OPT_MAC_STATS
1778 efx_mac_stats_ev_t eec_mac_stats;
1779 #endif /* EFSYS_OPT_MAC_STATS */
1780 } efx_ev_callbacks_t;
1782 extern __checkReturn boolean_t
1784 __in efx_evq_t *eep,
1785 __in unsigned int count);
1787 #if EFSYS_OPT_EV_PREFETCH
1791 __in efx_evq_t *eep,
1792 __in unsigned int count);
1794 #endif /* EFSYS_OPT_EV_PREFETCH */
1798 __in efx_evq_t *eep,
1799 __inout unsigned int *countp,
1800 __in const efx_ev_callbacks_t *eecp,
1801 __in_opt void *arg);
1803 extern __checkReturn efx_rc_t
1804 efx_ev_usecs_to_ticks(
1805 __in efx_nic_t *enp,
1806 __in unsigned int usecs,
1807 __out unsigned int *ticksp);
1809 extern __checkReturn efx_rc_t
1811 __in efx_evq_t *eep,
1812 __in unsigned int us);
1814 extern __checkReturn efx_rc_t
1816 __in efx_evq_t *eep,
1817 __in unsigned int count);
1819 #if EFSYS_OPT_QSTATS
1825 __in efx_nic_t *enp,
1826 __in unsigned int id);
1828 #endif /* EFSYS_OPT_NAMES */
1831 efx_ev_qstats_update(
1832 __in efx_evq_t *eep,
1833 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1835 #endif /* EFSYS_OPT_QSTATS */
1839 __in efx_evq_t *eep);
1843 extern __checkReturn efx_rc_t
1845 __inout efx_nic_t *enp);
1849 __in efx_nic_t *enp);
1851 #if EFSYS_OPT_RX_SCATTER
1852 __checkReturn efx_rc_t
1853 efx_rx_scatter_enable(
1854 __in efx_nic_t *enp,
1855 __in unsigned int buf_size);
1856 #endif /* EFSYS_OPT_RX_SCATTER */
1858 #if EFSYS_OPT_RX_SCALE
1860 typedef enum efx_rx_hash_alg_e {
1861 EFX_RX_HASHALG_LFSR = 0,
1862 EFX_RX_HASHALG_TOEPLITZ
1863 } efx_rx_hash_alg_t;
1865 #define EFX_RX_HASH_IPV4 (1U << 0)
1866 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1867 #define EFX_RX_HASH_IPV6 (1U << 2)
1868 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1870 typedef unsigned int efx_rx_hash_type_t;
1872 typedef enum efx_rx_hash_support_e {
1873 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1874 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1875 } efx_rx_hash_support_t;
1877 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1878 #define EFX_MAXRSS 64 /* RX indirection entry range */
1879 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1881 typedef enum efx_rx_scale_support_e {
1882 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1883 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1884 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1885 } efx_rx_scale_support_t;
1887 extern __checkReturn efx_rc_t
1888 efx_rx_hash_support_get(
1889 __in efx_nic_t *enp,
1890 __out efx_rx_hash_support_t *supportp);
1893 extern __checkReturn efx_rc_t
1894 efx_rx_scale_support_get(
1895 __in efx_nic_t *enp,
1896 __out efx_rx_scale_support_t *supportp);
1898 extern __checkReturn efx_rc_t
1899 efx_rx_scale_mode_set(
1900 __in efx_nic_t *enp,
1901 __in efx_rx_hash_alg_t alg,
1902 __in efx_rx_hash_type_t type,
1903 __in boolean_t insert);
1905 extern __checkReturn efx_rc_t
1906 efx_rx_scale_tbl_set(
1907 __in efx_nic_t *enp,
1908 __in_ecount(n) unsigned int *table,
1911 extern __checkReturn efx_rc_t
1912 efx_rx_scale_key_set(
1913 __in efx_nic_t *enp,
1914 __in_ecount(n) uint8_t *key,
1917 extern __checkReturn uint32_t
1918 efx_pseudo_hdr_hash_get(
1919 __in efx_rxq_t *erp,
1920 __in efx_rx_hash_alg_t func,
1921 __in uint8_t *buffer);
1923 #endif /* EFSYS_OPT_RX_SCALE */
1925 extern __checkReturn efx_rc_t
1926 efx_pseudo_hdr_pkt_length_get(
1927 __in efx_rxq_t *erp,
1928 __in uint8_t *buffer,
1929 __out uint16_t *pkt_lengthp);
1931 #define EFX_RXQ_MAXNDESCS 4096
1932 #define EFX_RXQ_MINNDESCS 512
1934 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1935 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1936 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1937 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1939 typedef enum efx_rxq_type_e {
1940 EFX_RXQ_TYPE_DEFAULT,
1941 EFX_RXQ_TYPE_SCATTER,
1942 EFX_RXQ_TYPE_PACKED_STREAM_1M,
1943 EFX_RXQ_TYPE_PACKED_STREAM_512K,
1944 EFX_RXQ_TYPE_PACKED_STREAM_256K,
1945 EFX_RXQ_TYPE_PACKED_STREAM_128K,
1946 EFX_RXQ_TYPE_PACKED_STREAM_64K,
1950 extern __checkReturn efx_rc_t
1952 __in efx_nic_t *enp,
1953 __in unsigned int index,
1954 __in unsigned int label,
1955 __in efx_rxq_type_t type,
1956 __in efsys_mem_t *esmp,
1959 __in efx_evq_t *eep,
1960 __deref_out efx_rxq_t **erpp);
1962 typedef struct efx_buffer_s {
1963 efsys_dma_addr_t eb_addr;
1968 typedef struct efx_desc_s {
1974 __in efx_rxq_t *erp,
1975 __in_ecount(n) efsys_dma_addr_t *addrp,
1977 __in unsigned int n,
1978 __in unsigned int completed,
1979 __in unsigned int added);
1983 __in efx_rxq_t *erp,
1984 __in unsigned int added,
1985 __inout unsigned int *pushedp);
1987 #if EFSYS_OPT_RX_PACKED_STREAM
1990 * Fake length for RXQ descriptors in packed stream mode
1991 * to make hardware happy
1993 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
1996 efx_rx_qps_update_credits(
1997 __in efx_rxq_t *erp);
1999 extern __checkReturn uint8_t *
2000 efx_rx_qps_packet_info(
2001 __in efx_rxq_t *erp,
2002 __in uint8_t *buffer,
2003 __in uint32_t buffer_length,
2004 __in uint32_t current_offset,
2005 __out uint16_t *lengthp,
2006 __out uint32_t *next_offsetp,
2007 __out uint32_t *timestamp);
2010 extern __checkReturn efx_rc_t
2012 __in efx_rxq_t *erp);
2016 __in efx_rxq_t *erp);
2020 __in efx_rxq_t *erp);
2024 typedef struct efx_txq_s efx_txq_t;
2026 #if EFSYS_OPT_QSTATS
2028 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2029 typedef enum efx_tx_qstat_e {
2035 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2037 #endif /* EFSYS_OPT_QSTATS */
2039 extern __checkReturn efx_rc_t
2041 __in efx_nic_t *enp);
2045 __in efx_nic_t *enp);
2047 #define EFX_TXQ_MINNDESCS 512
2049 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2050 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2051 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2052 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2054 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2056 #define EFX_TXQ_CKSUM_IPV4 0x0001
2057 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2058 #define EFX_TXQ_FATSOV2 0x0004
2060 extern __checkReturn efx_rc_t
2062 __in efx_nic_t *enp,
2063 __in unsigned int index,
2064 __in unsigned int label,
2065 __in efsys_mem_t *esmp,
2068 __in uint16_t flags,
2069 __in efx_evq_t *eep,
2070 __deref_out efx_txq_t **etpp,
2071 __out unsigned int *addedp);
2073 extern __checkReturn efx_rc_t
2075 __in efx_txq_t *etp,
2076 __in_ecount(n) efx_buffer_t *eb,
2077 __in unsigned int n,
2078 __in unsigned int completed,
2079 __inout unsigned int *addedp);
2081 extern __checkReturn efx_rc_t
2083 __in efx_txq_t *etp,
2084 __in unsigned int ns);
2088 __in efx_txq_t *etp,
2089 __in unsigned int added,
2090 __in unsigned int pushed);
2092 extern __checkReturn efx_rc_t
2094 __in efx_txq_t *etp);
2098 __in efx_txq_t *etp);
2100 extern __checkReturn efx_rc_t
2102 __in efx_txq_t *etp);
2105 efx_tx_qpio_disable(
2106 __in efx_txq_t *etp);
2108 extern __checkReturn efx_rc_t
2110 __in efx_txq_t *etp,
2111 __in_ecount(buf_length) uint8_t *buffer,
2112 __in size_t buf_length,
2113 __in size_t pio_buf_offset);
2115 extern __checkReturn efx_rc_t
2117 __in efx_txq_t *etp,
2118 __in size_t pkt_length,
2119 __in unsigned int completed,
2120 __inout unsigned int *addedp);
2122 extern __checkReturn efx_rc_t
2124 __in efx_txq_t *etp,
2125 __in_ecount(n) efx_desc_t *ed,
2126 __in unsigned int n,
2127 __in unsigned int completed,
2128 __inout unsigned int *addedp);
2131 efx_tx_qdesc_dma_create(
2132 __in efx_txq_t *etp,
2133 __in efsys_dma_addr_t addr,
2136 __out efx_desc_t *edp);
2139 efx_tx_qdesc_tso_create(
2140 __in efx_txq_t *etp,
2141 __in uint16_t ipv4_id,
2142 __in uint32_t tcp_seq,
2143 __in uint8_t tcp_flags,
2144 __out efx_desc_t *edp);
2146 /* Number of FATSOv2 option descriptors */
2147 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2149 /* Maximum number of DMA segments per TSO packet (not superframe) */
2150 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2153 efx_tx_qdesc_tso2_create(
2154 __in efx_txq_t *etp,
2155 __in uint16_t ipv4_id,
2156 __in uint32_t tcp_seq,
2157 __in uint16_t tcp_mss,
2158 __out_ecount(count) efx_desc_t *edp,
2162 efx_tx_qdesc_vlantci_create(
2163 __in efx_txq_t *etp,
2165 __out efx_desc_t *edp);
2167 #if EFSYS_OPT_QSTATS
2173 __in efx_nic_t *etp,
2174 __in unsigned int id);
2176 #endif /* EFSYS_OPT_NAMES */
2179 efx_tx_qstats_update(
2180 __in efx_txq_t *etp,
2181 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2183 #endif /* EFSYS_OPT_QSTATS */
2187 __in efx_txq_t *etp);
2192 #if EFSYS_OPT_FILTER
2194 #define EFX_ETHER_TYPE_IPV4 0x0800
2195 #define EFX_ETHER_TYPE_IPV6 0x86DD
2197 #define EFX_IPPROTO_TCP 6
2198 #define EFX_IPPROTO_UDP 17
2200 /* Use RSS to spread across multiple queues */
2201 #define EFX_FILTER_FLAG_RX_RSS 0x01
2202 /* Enable RX scatter */
2203 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2205 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2206 * May only be set by the filter implementation for each type.
2207 * A removal request will restore the automatic filter in its place.
2209 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2210 /* Filter is for RX */
2211 #define EFX_FILTER_FLAG_RX 0x08
2212 /* Filter is for TX */
2213 #define EFX_FILTER_FLAG_TX 0x10
2215 typedef unsigned int efx_filter_flags_t;
2217 typedef enum efx_filter_match_flags_e {
2218 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
2220 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
2222 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
2223 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
2224 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
2225 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
2226 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
2227 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2228 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2229 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2231 /* Match otherwise-unmatched multicast and broadcast packets */
2232 EFX_FILTER_MATCH_UNKNOWN_MCAST_DST = 0x40000000,
2233 /* Match otherwise-unmatched unicast packets */
2234 EFX_FILTER_MATCH_UNKNOWN_UCAST_DST = 0x80000000,
2235 } efx_filter_match_flags_t;
2237 typedef enum efx_filter_priority_s {
2238 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2239 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2240 * address list or hardware
2241 * requirements. This may only be used
2242 * by the filter implementation for
2244 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2245 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2246 * client (e.g. SR-IOV, HyperV VMQ etc.)
2248 } efx_filter_priority_t;
2251 * FIXME: All these fields are assumed to be in little-endian byte order.
2252 * It may be better for some to be big-endian. See bug42804.
2255 typedef struct efx_filter_spec_s {
2256 uint32_t efs_match_flags;
2257 uint32_t efs_priority:2;
2258 uint32_t efs_flags:6;
2259 uint32_t efs_dmaq_id:12;
2260 uint32_t efs_rss_context;
2261 uint16_t efs_outer_vid;
2262 uint16_t efs_inner_vid;
2263 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2264 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2265 uint16_t efs_ether_type;
2266 uint8_t efs_ip_proto;
2267 uint16_t efs_loc_port;
2268 uint16_t efs_rem_port;
2269 efx_oword_t efs_rem_host;
2270 efx_oword_t efs_loc_host;
2271 } efx_filter_spec_t;
2274 /* Default values for use in filter specifications */
2275 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2276 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2277 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2279 extern __checkReturn efx_rc_t
2281 __in efx_nic_t *enp);
2285 __in efx_nic_t *enp);
2287 extern __checkReturn efx_rc_t
2289 __in efx_nic_t *enp,
2290 __inout efx_filter_spec_t *spec);
2292 extern __checkReturn efx_rc_t
2294 __in efx_nic_t *enp,
2295 __inout efx_filter_spec_t *spec);
2297 extern __checkReturn efx_rc_t
2299 __in efx_nic_t *enp);
2301 extern __checkReturn efx_rc_t
2302 efx_filter_supported_filters(
2303 __in efx_nic_t *enp,
2304 __out_ecount(buffer_length) uint32_t *buffer,
2305 __in size_t buffer_length,
2306 __out size_t *list_lengthp);
2309 efx_filter_spec_init_rx(
2310 __out efx_filter_spec_t *spec,
2311 __in efx_filter_priority_t priority,
2312 __in efx_filter_flags_t flags,
2313 __in efx_rxq_t *erp);
2316 efx_filter_spec_init_tx(
2317 __out efx_filter_spec_t *spec,
2318 __in efx_txq_t *etp);
2320 extern __checkReturn efx_rc_t
2321 efx_filter_spec_set_ipv4_local(
2322 __inout efx_filter_spec_t *spec,
2325 __in uint16_t port);
2327 extern __checkReturn efx_rc_t
2328 efx_filter_spec_set_ipv4_full(
2329 __inout efx_filter_spec_t *spec,
2331 __in uint32_t lhost,
2332 __in uint16_t lport,
2333 __in uint32_t rhost,
2334 __in uint16_t rport);
2336 extern __checkReturn efx_rc_t
2337 efx_filter_spec_set_eth_local(
2338 __inout efx_filter_spec_t *spec,
2340 __in const uint8_t *addr);
2342 extern __checkReturn efx_rc_t
2343 efx_filter_spec_set_uc_def(
2344 __inout efx_filter_spec_t *spec);
2346 extern __checkReturn efx_rc_t
2347 efx_filter_spec_set_mc_def(
2348 __inout efx_filter_spec_t *spec);
2350 #endif /* EFSYS_OPT_FILTER */
2354 extern __checkReturn uint32_t
2356 __in_ecount(count) uint32_t const *input,
2358 __in uint32_t init);
2360 extern __checkReturn uint32_t
2362 __in_ecount(length) uint8_t const *input,
2364 __in uint32_t init);
2366 #if EFSYS_OPT_LICENSING
2370 typedef struct efx_key_stats_s {
2372 uint32_t eks_invalid;
2373 uint32_t eks_blacklisted;
2374 uint32_t eks_unverifiable;
2375 uint32_t eks_wrong_node;
2376 uint32_t eks_licensed_apps_lo;
2377 uint32_t eks_licensed_apps_hi;
2378 uint32_t eks_licensed_features_lo;
2379 uint32_t eks_licensed_features_hi;
2382 extern __checkReturn efx_rc_t
2384 __in efx_nic_t *enp);
2388 __in efx_nic_t *enp);
2390 extern __checkReturn boolean_t
2391 efx_lic_check_support(
2392 __in efx_nic_t *enp);
2394 extern __checkReturn efx_rc_t
2395 efx_lic_update_licenses(
2396 __in efx_nic_t *enp);
2398 extern __checkReturn efx_rc_t
2399 efx_lic_get_key_stats(
2400 __in efx_nic_t *enp,
2401 __out efx_key_stats_t *ksp);
2403 extern __checkReturn efx_rc_t
2405 __in efx_nic_t *enp,
2406 __in uint64_t app_id,
2407 __out boolean_t *licensedp);
2409 extern __checkReturn efx_rc_t
2411 __in efx_nic_t *enp,
2412 __in size_t buffer_size,
2413 __out uint32_t *typep,
2414 __out size_t *lengthp,
2415 __out_opt uint8_t *bufferp);
2418 extern __checkReturn efx_rc_t
2420 __in efx_nic_t *enp,
2421 __in_bcount(buffer_size)
2423 __in size_t buffer_size,
2424 __out uint32_t *startp
2427 extern __checkReturn efx_rc_t
2429 __in efx_nic_t *enp,
2430 __in_bcount(buffer_size)
2432 __in size_t buffer_size,
2433 __in uint32_t offset,
2434 __out uint32_t *endp
2437 extern __checkReturn __success(return != B_FALSE) boolean_t
2439 __in efx_nic_t *enp,
2440 __in_bcount(buffer_size)
2442 __in size_t buffer_size,
2443 __in uint32_t offset,
2444 __out uint32_t *startp,
2445 __out uint32_t *lengthp
2448 extern __checkReturn __success(return != B_FALSE) boolean_t
2449 efx_lic_validate_key(
2450 __in efx_nic_t *enp,
2451 __in_bcount(length) caddr_t keyp,
2452 __in uint32_t length
2455 extern __checkReturn efx_rc_t
2457 __in efx_nic_t *enp,
2458 __in_bcount(buffer_size)
2460 __in size_t buffer_size,
2461 __in uint32_t offset,
2462 __in uint32_t length,
2463 __out_bcount_part(key_max_size, *lengthp)
2465 __in size_t key_max_size,
2466 __out uint32_t *lengthp
2469 extern __checkReturn efx_rc_t
2471 __in efx_nic_t *enp,
2472 __in_bcount(buffer_size)
2474 __in size_t buffer_size,
2475 __in uint32_t offset,
2476 __in_bcount(length) caddr_t keyp,
2477 __in uint32_t length,
2478 __out uint32_t *lengthp
2481 __checkReturn efx_rc_t
2483 __in efx_nic_t *enp,
2484 __in_bcount(buffer_size)
2486 __in size_t buffer_size,
2487 __in uint32_t offset,
2488 __in uint32_t length,
2490 __out uint32_t *deltap
2493 extern __checkReturn efx_rc_t
2494 efx_lic_create_partition(
2495 __in efx_nic_t *enp,
2496 __in_bcount(buffer_size)
2498 __in size_t buffer_size
2501 extern __checkReturn efx_rc_t
2502 efx_lic_finish_partition(
2503 __in efx_nic_t *enp,
2504 __in_bcount(buffer_size)
2506 __in size_t buffer_size
2509 #endif /* EFSYS_OPT_LICENSING */
2517 #endif /* _SYS_EFX_H */