1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
42 typedef __success(return == 0) int efx_rc_t;
47 typedef enum efx_family_e {
49 EFX_FAMILY_FALCON, /* Obsolete and not supported */
51 EFX_FAMILY_HUNTINGTON,
57 extern __checkReturn efx_rc_t
61 __out efx_family_t *efp,
62 __out unsigned int *membarp);
65 #define EFX_PCI_VENID_SFC 0x1924
67 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
69 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
70 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
71 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
73 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
74 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
75 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
77 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
78 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
80 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
81 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
82 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
84 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
85 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
86 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
89 #define EFX_MEM_BAR_SIENA 2
91 #define EFX_MEM_BAR_HUNTINGTON_PF 2
92 #define EFX_MEM_BAR_HUNTINGTON_VF 0
94 #define EFX_MEM_BAR_MEDFORD_PF 2
95 #define EFX_MEM_BAR_MEDFORD_VF 0
97 #define EFX_MEM_BAR_MEDFORD2 0
105 EFX_ERR_BUFID_DC_OOB,
118 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
119 extern __checkReturn uint32_t
121 __in uint32_t crc_init,
122 __in_ecount(length) uint8_t const *input,
126 /* Type prototypes */
128 typedef struct efx_rxq_s efx_rxq_t;
132 typedef struct efx_nic_s efx_nic_t;
134 extern __checkReturn efx_rc_t
136 __in efx_family_t family,
137 __in efsys_identifier_t *esip,
138 __in efsys_bar_t *esbp,
139 __in efsys_lock_t *eslp,
140 __deref_out efx_nic_t **enpp);
142 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
143 typedef enum efx_fw_variant_e {
144 EFX_FW_VARIANT_FULL_FEATURED,
145 EFX_FW_VARIANT_LOW_LATENCY,
146 EFX_FW_VARIANT_PACKED_STREAM,
147 EFX_FW_VARIANT_HIGH_TX_RATE,
148 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
149 EFX_FW_VARIANT_RULES_ENGINE,
151 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
154 extern __checkReturn efx_rc_t
157 __in efx_fw_variant_t efv);
159 extern __checkReturn efx_rc_t
161 __in efx_nic_t *enp);
163 extern __checkReturn efx_rc_t
165 __in efx_nic_t *enp);
167 extern __checkReturn boolean_t
168 efx_nic_hw_unavailable(
169 __in efx_nic_t *enp);
172 efx_nic_set_hw_unavailable(
173 __in efx_nic_t *enp);
177 extern __checkReturn efx_rc_t
178 efx_nic_register_test(
179 __in efx_nic_t *enp);
181 #endif /* EFSYS_OPT_DIAG */
185 __in efx_nic_t *enp);
189 __in efx_nic_t *enp);
193 __in efx_nic_t *enp);
195 #define EFX_PCIE_LINK_SPEED_GEN1 1
196 #define EFX_PCIE_LINK_SPEED_GEN2 2
197 #define EFX_PCIE_LINK_SPEED_GEN3 3
199 typedef enum efx_pcie_link_performance_e {
200 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
201 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
202 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
203 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
204 } efx_pcie_link_performance_t;
206 extern __checkReturn efx_rc_t
207 efx_nic_calculate_pcie_link_bandwidth(
208 __in uint32_t pcie_link_width,
209 __in uint32_t pcie_link_gen,
210 __out uint32_t *bandwidth_mbpsp);
212 extern __checkReturn efx_rc_t
213 efx_nic_check_pcie_link_speed(
215 __in uint32_t pcie_link_width,
216 __in uint32_t pcie_link_gen,
217 __out efx_pcie_link_performance_t *resultp);
222 /* EF10 architecture NICs require MCDIv2 commands */
223 #define WITH_MCDI_V2 1
226 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
228 typedef enum efx_mcdi_exception_e {
229 EFX_MCDI_EXCEPTION_MC_REBOOT,
230 EFX_MCDI_EXCEPTION_MC_BADASSERT,
231 } efx_mcdi_exception_t;
233 #if EFSYS_OPT_MCDI_LOGGING
234 typedef enum efx_log_msg_e {
236 EFX_LOG_MCDI_REQUEST,
237 EFX_LOG_MCDI_RESPONSE,
239 #endif /* EFSYS_OPT_MCDI_LOGGING */
241 typedef struct efx_mcdi_transport_s {
243 efsys_mem_t *emt_dma_mem;
244 void (*emt_execute)(void *, efx_mcdi_req_t *);
245 void (*emt_ev_cpl)(void *);
246 void (*emt_exception)(void *, efx_mcdi_exception_t);
247 #if EFSYS_OPT_MCDI_LOGGING
248 void (*emt_logger)(void *, efx_log_msg_t,
249 void *, size_t, void *, size_t);
250 #endif /* EFSYS_OPT_MCDI_LOGGING */
251 #if EFSYS_OPT_MCDI_PROXY_AUTH
252 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
253 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
254 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
255 void (*emt_ev_proxy_request)(void *, uint32_t);
256 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
257 } efx_mcdi_transport_t;
259 extern __checkReturn efx_rc_t
262 __in const efx_mcdi_transport_t *mtp);
264 extern __checkReturn efx_rc_t
266 __in efx_nic_t *enp);
270 __in efx_nic_t *enp);
273 efx_mcdi_get_timeout(
275 __in efx_mcdi_req_t *emrp,
276 __out uint32_t *usec_timeoutp);
279 efx_mcdi_request_start(
281 __in efx_mcdi_req_t *emrp,
282 __in boolean_t ev_cpl);
284 extern __checkReturn boolean_t
285 efx_mcdi_request_poll(
286 __in efx_nic_t *enp);
288 extern __checkReturn boolean_t
289 efx_mcdi_request_abort(
290 __in efx_nic_t *enp);
294 __in efx_nic_t *enp);
296 #endif /* EFSYS_OPT_MCDI */
300 #define EFX_NINTR_SIENA 1024
302 typedef enum efx_intr_type_e {
303 EFX_INTR_INVALID = 0,
309 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
311 extern __checkReturn efx_rc_t
314 __in efx_intr_type_t type,
315 __in_opt efsys_mem_t *esmp);
319 __in efx_nic_t *enp);
323 __in efx_nic_t *enp);
326 efx_intr_disable_unlocked(
327 __in efx_nic_t *enp);
329 #define EFX_INTR_NEVQS 32
331 extern __checkReturn efx_rc_t
334 __in unsigned int level);
337 efx_intr_status_line(
339 __out boolean_t *fatalp,
340 __out uint32_t *maskp);
343 efx_intr_status_message(
345 __in unsigned int message,
346 __out boolean_t *fatalp);
350 __in efx_nic_t *enp);
354 __in efx_nic_t *enp);
358 #if EFSYS_OPT_MAC_STATS
360 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
361 typedef enum efx_mac_stat_e {
364 EFX_MAC_RX_UNICST_PKTS,
365 EFX_MAC_RX_MULTICST_PKTS,
366 EFX_MAC_RX_BRDCST_PKTS,
367 EFX_MAC_RX_PAUSE_PKTS,
368 EFX_MAC_RX_LE_64_PKTS,
369 EFX_MAC_RX_65_TO_127_PKTS,
370 EFX_MAC_RX_128_TO_255_PKTS,
371 EFX_MAC_RX_256_TO_511_PKTS,
372 EFX_MAC_RX_512_TO_1023_PKTS,
373 EFX_MAC_RX_1024_TO_15XX_PKTS,
374 EFX_MAC_RX_GE_15XX_PKTS,
376 EFX_MAC_RX_FCS_ERRORS,
377 EFX_MAC_RX_DROP_EVENTS,
378 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
379 EFX_MAC_RX_SYMBOL_ERRORS,
380 EFX_MAC_RX_ALIGN_ERRORS,
381 EFX_MAC_RX_INTERNAL_ERRORS,
382 EFX_MAC_RX_JABBER_PKTS,
383 EFX_MAC_RX_LANE0_CHAR_ERR,
384 EFX_MAC_RX_LANE1_CHAR_ERR,
385 EFX_MAC_RX_LANE2_CHAR_ERR,
386 EFX_MAC_RX_LANE3_CHAR_ERR,
387 EFX_MAC_RX_LANE0_DISP_ERR,
388 EFX_MAC_RX_LANE1_DISP_ERR,
389 EFX_MAC_RX_LANE2_DISP_ERR,
390 EFX_MAC_RX_LANE3_DISP_ERR,
391 EFX_MAC_RX_MATCH_FAULT,
392 EFX_MAC_RX_NODESC_DROP_CNT,
395 EFX_MAC_TX_UNICST_PKTS,
396 EFX_MAC_TX_MULTICST_PKTS,
397 EFX_MAC_TX_BRDCST_PKTS,
398 EFX_MAC_TX_PAUSE_PKTS,
399 EFX_MAC_TX_LE_64_PKTS,
400 EFX_MAC_TX_65_TO_127_PKTS,
401 EFX_MAC_TX_128_TO_255_PKTS,
402 EFX_MAC_TX_256_TO_511_PKTS,
403 EFX_MAC_TX_512_TO_1023_PKTS,
404 EFX_MAC_TX_1024_TO_15XX_PKTS,
405 EFX_MAC_TX_GE_15XX_PKTS,
407 EFX_MAC_TX_SGL_COL_PKTS,
408 EFX_MAC_TX_MULT_COL_PKTS,
409 EFX_MAC_TX_EX_COL_PKTS,
410 EFX_MAC_TX_LATE_COL_PKTS,
412 EFX_MAC_TX_EX_DEF_PKTS,
413 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
414 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
415 EFX_MAC_PM_TRUNC_VFIFO_FULL,
416 EFX_MAC_PM_DISCARD_VFIFO_FULL,
417 EFX_MAC_PM_TRUNC_QBB,
418 EFX_MAC_PM_DISCARD_QBB,
419 EFX_MAC_PM_DISCARD_MAPPING,
420 EFX_MAC_RXDP_Q_DISABLED_PKTS,
421 EFX_MAC_RXDP_DI_DROPPED_PKTS,
422 EFX_MAC_RXDP_STREAMING_PKTS,
423 EFX_MAC_RXDP_HLB_FETCH,
424 EFX_MAC_RXDP_HLB_WAIT,
425 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
426 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
427 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
428 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
429 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
430 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
431 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
432 EFX_MAC_VADAPTER_RX_BAD_BYTES,
433 EFX_MAC_VADAPTER_RX_OVERFLOW,
434 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
435 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
436 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
437 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
438 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
439 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
440 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
441 EFX_MAC_VADAPTER_TX_BAD_BYTES,
442 EFX_MAC_VADAPTER_TX_OVERFLOW,
443 EFX_MAC_FEC_UNCORRECTED_ERRORS,
444 EFX_MAC_FEC_CORRECTED_ERRORS,
445 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
446 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
447 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
448 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
449 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
450 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
451 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
452 EFX_MAC_CTPIO_OVERFLOW_FAIL,
453 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
454 EFX_MAC_CTPIO_TIMEOUT_FAIL,
455 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
456 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
457 EFX_MAC_CTPIO_INVALID_WR_FAIL,
458 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
459 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
460 EFX_MAC_CTPIO_RUNT_FALLBACK,
461 EFX_MAC_CTPIO_SUCCESS,
462 EFX_MAC_CTPIO_FALLBACK,
463 EFX_MAC_CTPIO_POISON,
465 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
466 EFX_MAC_RXDP_HLB_IDLE,
467 EFX_MAC_RXDP_HLB_TIMEOUT,
471 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
473 #endif /* EFSYS_OPT_MAC_STATS */
475 typedef enum efx_link_mode_e {
476 EFX_LINK_UNKNOWN = 0,
492 #define EFX_MAC_ADDR_LEN 6
494 #define EFX_VNI_OR_VSID_LEN 3
496 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
498 #define EFX_MAC_MULTICAST_LIST_MAX 256
500 #define EFX_MAC_SDU_MAX 9202
502 #define EFX_MAC_PDU_ADJUSTMENT \
506 + /* bug16011 */ 16) \
508 #define EFX_MAC_PDU(_sdu) \
509 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
512 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
513 * the SDU rounded up slightly.
515 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
517 #define EFX_MAC_PDU_MIN 60
518 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
520 extern __checkReturn efx_rc_t
525 extern __checkReturn efx_rc_t
530 extern __checkReturn efx_rc_t
535 extern __checkReturn efx_rc_t
538 __in boolean_t all_unicst,
539 __in boolean_t mulcst,
540 __in boolean_t all_mulcst,
541 __in boolean_t brdcst);
543 extern __checkReturn efx_rc_t
544 efx_mac_multicast_list_set(
546 __in_ecount(6*count) uint8_t const *addrs,
549 extern __checkReturn efx_rc_t
550 efx_mac_filter_default_rxq_set(
553 __in boolean_t using_rss);
556 efx_mac_filter_default_rxq_clear(
557 __in efx_nic_t *enp);
559 extern __checkReturn efx_rc_t
562 __in boolean_t enabled);
564 extern __checkReturn efx_rc_t
567 __out boolean_t *mac_upp);
569 #define EFX_FCNTL_RESPOND 0x00000001
570 #define EFX_FCNTL_GENERATE 0x00000002
572 extern __checkReturn efx_rc_t
575 __in unsigned int fcntl,
576 __in boolean_t autoneg);
581 __out unsigned int *fcntl_wantedp,
582 __out unsigned int *fcntl_linkp);
585 #if EFSYS_OPT_MAC_STATS
589 extern __checkReturn const char *
592 __in unsigned int id);
594 #endif /* EFSYS_OPT_NAMES */
596 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
598 #define EFX_MAC_STATS_MASK_NPAGES \
599 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
600 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
601 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
604 * Get mask of MAC statistics supported by the hardware.
606 * If mask_size is insufficient to return the mask, EINVAL error is
607 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
608 * (which is sizeof (uint32_t)) is sufficient.
610 extern __checkReturn efx_rc_t
611 efx_mac_stats_get_mask(
613 __out_bcount(mask_size) uint32_t *maskp,
614 __in size_t mask_size);
616 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
617 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
618 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
621 extern __checkReturn efx_rc_t
623 __in efx_nic_t *enp);
626 * Upload mac statistics supported by the hardware into the given buffer.
628 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
629 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
631 * The hardware will only DMA statistics that it understands (of course).
632 * Drivers should not make any assumptions about which statistics are
633 * supported, especially when the statistics are generated by firmware.
635 * Thus, drivers should zero this buffer before use, so that not-understood
636 * statistics read back as zero.
638 extern __checkReturn efx_rc_t
639 efx_mac_stats_upload(
641 __in efsys_mem_t *esmp);
643 extern __checkReturn efx_rc_t
644 efx_mac_stats_periodic(
646 __in efsys_mem_t *esmp,
647 __in uint16_t period_ms,
648 __in boolean_t events);
650 extern __checkReturn efx_rc_t
651 efx_mac_stats_update(
653 __in efsys_mem_t *esmp,
654 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
655 __inout_opt uint32_t *generationp);
657 #endif /* EFSYS_OPT_MAC_STATS */
661 typedef enum efx_mon_type_e {
673 __in efx_nic_t *enp);
675 #endif /* EFSYS_OPT_NAMES */
677 extern __checkReturn efx_rc_t
679 __in efx_nic_t *enp);
681 #if EFSYS_OPT_MON_STATS
683 #define EFX_MON_STATS_PAGE_SIZE 0x100
684 #define EFX_MON_MASK_ELEMENT_SIZE 32
686 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
687 typedef enum efx_mon_stat_e {
688 EFX_MON_STAT_CONTROLLER_TEMP,
689 EFX_MON_STAT_PHY_COMMON_TEMP,
690 EFX_MON_STAT_CONTROLLER_COOLING,
691 EFX_MON_STAT_PHY0_TEMP,
692 EFX_MON_STAT_PHY0_COOLING,
693 EFX_MON_STAT_PHY1_TEMP,
694 EFX_MON_STAT_PHY1_COOLING,
700 EFX_MON_STAT_IN_12V0,
701 EFX_MON_STAT_IN_1V2A,
702 EFX_MON_STAT_IN_VREF,
703 EFX_MON_STAT_OUT_VAOE,
704 EFX_MON_STAT_AOE_TEMP,
705 EFX_MON_STAT_PSU_AOE_TEMP,
706 EFX_MON_STAT_PSU_TEMP,
712 EFX_MON_STAT_IN_VAOE,
713 EFX_MON_STAT_OUT_IAOE,
714 EFX_MON_STAT_IN_IAOE,
715 EFX_MON_STAT_NIC_POWER,
717 EFX_MON_STAT_IN_I0V9,
718 EFX_MON_STAT_IN_I1V2,
719 EFX_MON_STAT_IN_0V9_ADC,
720 EFX_MON_STAT_CONTROLLER_2_TEMP,
721 EFX_MON_STAT_VREG_INTERNAL_TEMP,
722 EFX_MON_STAT_VREG_0V9_TEMP,
723 EFX_MON_STAT_VREG_1V2_TEMP,
724 EFX_MON_STAT_CONTROLLER_VPTAT,
725 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
726 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
727 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
728 EFX_MON_STAT_AMBIENT_TEMP,
729 EFX_MON_STAT_AIRFLOW,
730 EFX_MON_STAT_VDD08D_VSS08D_CSR,
731 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
732 EFX_MON_STAT_HOTPOINT_TEMP,
733 EFX_MON_STAT_PHY_POWER_PORT0,
734 EFX_MON_STAT_PHY_POWER_PORT1,
735 EFX_MON_STAT_MUM_VCC,
736 EFX_MON_STAT_IN_0V9_A,
737 EFX_MON_STAT_IN_I0V9_A,
738 EFX_MON_STAT_VREG_0V9_A_TEMP,
739 EFX_MON_STAT_IN_0V9_B,
740 EFX_MON_STAT_IN_I0V9_B,
741 EFX_MON_STAT_VREG_0V9_B_TEMP,
742 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
743 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
744 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
745 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
746 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
747 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
748 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
749 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
750 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
751 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
752 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
753 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
754 EFX_MON_STAT_SODIMM_VOUT,
755 EFX_MON_STAT_SODIMM_0_TEMP,
756 EFX_MON_STAT_SODIMM_1_TEMP,
757 EFX_MON_STAT_PHY0_VCC,
758 EFX_MON_STAT_PHY1_VCC,
759 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
760 EFX_MON_STAT_BOARD_FRONT_TEMP,
761 EFX_MON_STAT_BOARD_BACK_TEMP,
762 EFX_MON_STAT_IN_I1V8,
763 EFX_MON_STAT_IN_I2V5,
764 EFX_MON_STAT_IN_I3V3,
765 EFX_MON_STAT_IN_I12V0,
767 EFX_MON_STAT_IN_I1V3,
771 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
773 typedef enum efx_mon_stat_state_e {
774 EFX_MON_STAT_STATE_OK = 0,
775 EFX_MON_STAT_STATE_WARNING = 1,
776 EFX_MON_STAT_STATE_FATAL = 2,
777 EFX_MON_STAT_STATE_BROKEN = 3,
778 EFX_MON_STAT_STATE_NO_READING = 4,
779 } efx_mon_stat_state_t;
781 typedef enum efx_mon_stat_unit_e {
782 EFX_MON_STAT_UNIT_UNKNOWN = 0,
783 EFX_MON_STAT_UNIT_BOOL,
784 EFX_MON_STAT_UNIT_TEMP_C,
785 EFX_MON_STAT_UNIT_VOLTAGE_MV,
786 EFX_MON_STAT_UNIT_CURRENT_MA,
787 EFX_MON_STAT_UNIT_POWER_W,
788 EFX_MON_STAT_UNIT_RPM,
790 } efx_mon_stat_unit_t;
792 typedef struct efx_mon_stat_value_s {
794 efx_mon_stat_state_t emsv_state;
795 efx_mon_stat_unit_t emsv_unit;
796 } efx_mon_stat_value_t;
798 typedef struct efx_mon_limit_value_s {
799 uint16_t emlv_warning_min;
800 uint16_t emlv_warning_max;
801 uint16_t emlv_fatal_min;
802 uint16_t emlv_fatal_max;
803 } efx_mon_stat_limits_t;
805 typedef enum efx_mon_stat_portmask_e {
806 EFX_MON_STAT_PORTMAP_NONE = 0,
807 EFX_MON_STAT_PORTMAP_PORT0 = 1,
808 EFX_MON_STAT_PORTMAP_PORT1 = 2,
809 EFX_MON_STAT_PORTMAP_PORT2 = 3,
810 EFX_MON_STAT_PORTMAP_PORT3 = 4,
811 EFX_MON_STAT_PORTMAP_ALL = (-1),
812 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
813 } efx_mon_stat_portmask_t;
820 __in efx_mon_stat_t id);
823 efx_mon_stat_description(
825 __in efx_mon_stat_t id);
827 #endif /* EFSYS_OPT_NAMES */
829 extern __checkReturn boolean_t
830 efx_mon_mcdi_to_efx_stat(
832 __out efx_mon_stat_t *statp);
834 extern __checkReturn boolean_t
835 efx_mon_get_stat_unit(
836 __in efx_mon_stat_t stat,
837 __out efx_mon_stat_unit_t *unitp);
839 extern __checkReturn boolean_t
840 efx_mon_get_stat_portmap(
841 __in efx_mon_stat_t stat,
842 __out efx_mon_stat_portmask_t *maskp);
844 extern __checkReturn efx_rc_t
845 efx_mon_stats_update(
847 __in efsys_mem_t *esmp,
848 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
850 extern __checkReturn efx_rc_t
851 efx_mon_limits_update(
853 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
855 #endif /* EFSYS_OPT_MON_STATS */
859 __in efx_nic_t *enp);
863 extern __checkReturn efx_rc_t
865 __in efx_nic_t *enp);
867 #if EFSYS_OPT_PHY_LED_CONTROL
869 typedef enum efx_phy_led_mode_e {
870 EFX_PHY_LED_DEFAULT = 0,
875 } efx_phy_led_mode_t;
877 extern __checkReturn efx_rc_t
880 __in efx_phy_led_mode_t mode);
882 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
884 extern __checkReturn efx_rc_t
886 __in efx_nic_t *enp);
888 #if EFSYS_OPT_LOOPBACK
890 typedef enum efx_loopback_type_e {
891 EFX_LOOPBACK_OFF = 0,
892 EFX_LOOPBACK_DATA = 1,
893 EFX_LOOPBACK_GMAC = 2,
894 EFX_LOOPBACK_XGMII = 3,
895 EFX_LOOPBACK_XGXS = 4,
896 EFX_LOOPBACK_XAUI = 5,
897 EFX_LOOPBACK_GMII = 6,
898 EFX_LOOPBACK_SGMII = 7,
899 EFX_LOOPBACK_XGBR = 8,
900 EFX_LOOPBACK_XFI = 9,
901 EFX_LOOPBACK_XAUI_FAR = 10,
902 EFX_LOOPBACK_GMII_FAR = 11,
903 EFX_LOOPBACK_SGMII_FAR = 12,
904 EFX_LOOPBACK_XFI_FAR = 13,
905 EFX_LOOPBACK_GPHY = 14,
906 EFX_LOOPBACK_PHY_XS = 15,
907 EFX_LOOPBACK_PCS = 16,
908 EFX_LOOPBACK_PMA_PMD = 17,
909 EFX_LOOPBACK_XPORT = 18,
910 EFX_LOOPBACK_XGMII_WS = 19,
911 EFX_LOOPBACK_XAUI_WS = 20,
912 EFX_LOOPBACK_XAUI_WS_FAR = 21,
913 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
914 EFX_LOOPBACK_GMII_WS = 23,
915 EFX_LOOPBACK_XFI_WS = 24,
916 EFX_LOOPBACK_XFI_WS_FAR = 25,
917 EFX_LOOPBACK_PHYXS_WS = 26,
918 EFX_LOOPBACK_PMA_INT = 27,
919 EFX_LOOPBACK_SD_NEAR = 28,
920 EFX_LOOPBACK_SD_FAR = 29,
921 EFX_LOOPBACK_PMA_INT_WS = 30,
922 EFX_LOOPBACK_SD_FEP2_WS = 31,
923 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
924 EFX_LOOPBACK_SD_FEP_WS = 33,
925 EFX_LOOPBACK_SD_FES_WS = 34,
926 EFX_LOOPBACK_AOE_INT_NEAR = 35,
927 EFX_LOOPBACK_DATA_WS = 36,
928 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
930 } efx_loopback_type_t;
932 typedef enum efx_loopback_kind_e {
933 EFX_LOOPBACK_KIND_OFF = 0,
934 EFX_LOOPBACK_KIND_ALL,
935 EFX_LOOPBACK_KIND_MAC,
936 EFX_LOOPBACK_KIND_PHY,
938 } efx_loopback_kind_t;
942 __in efx_loopback_kind_t loopback_kind,
943 __out efx_qword_t *maskp);
945 extern __checkReturn efx_rc_t
946 efx_port_loopback_set(
948 __in efx_link_mode_t link_mode,
949 __in efx_loopback_type_t type);
953 extern __checkReturn const char *
954 efx_loopback_type_name(
956 __in efx_loopback_type_t type);
958 #endif /* EFSYS_OPT_NAMES */
960 #endif /* EFSYS_OPT_LOOPBACK */
962 extern __checkReturn efx_rc_t
965 __out_opt efx_link_mode_t *link_modep);
969 __in efx_nic_t *enp);
971 typedef enum efx_phy_cap_type_e {
972 EFX_PHY_CAP_INVALID = 0,
979 EFX_PHY_CAP_10000FDX,
983 EFX_PHY_CAP_40000FDX,
985 EFX_PHY_CAP_100000FDX,
986 EFX_PHY_CAP_25000FDX,
987 EFX_PHY_CAP_50000FDX,
988 EFX_PHY_CAP_BASER_FEC,
989 EFX_PHY_CAP_BASER_FEC_REQUESTED,
991 EFX_PHY_CAP_RS_FEC_REQUESTED,
992 EFX_PHY_CAP_25G_BASER_FEC,
993 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
995 } efx_phy_cap_type_t;
998 #define EFX_PHY_CAP_CURRENT 0x00000000
999 #define EFX_PHY_CAP_DEFAULT 0x00000001
1000 #define EFX_PHY_CAP_PERM 0x00000002
1003 efx_phy_adv_cap_get(
1004 __in efx_nic_t *enp,
1006 __out uint32_t *maskp);
1008 extern __checkReturn efx_rc_t
1009 efx_phy_adv_cap_set(
1010 __in efx_nic_t *enp,
1011 __in uint32_t mask);
1015 __in efx_nic_t *enp,
1016 __out uint32_t *maskp);
1018 extern __checkReturn efx_rc_t
1020 __in efx_nic_t *enp,
1021 __out uint32_t *ouip);
1023 typedef enum efx_phy_media_type_e {
1024 EFX_PHY_MEDIA_INVALID = 0,
1029 EFX_PHY_MEDIA_SFP_PLUS,
1030 EFX_PHY_MEDIA_BASE_T,
1031 EFX_PHY_MEDIA_QSFP_PLUS,
1032 EFX_PHY_MEDIA_NTYPES
1033 } efx_phy_media_type_t;
1036 * Get the type of medium currently used. If the board has ports for
1037 * modules, a module is present, and we recognise the media type of
1038 * the module, then this will be the media type of the module.
1039 * Otherwise it will be the media type of the port.
1042 efx_phy_media_type_get(
1043 __in efx_nic_t *enp,
1044 __out efx_phy_media_type_t *typep);
1047 * 2-wire device address of the base information in accordance with SFF-8472
1048 * Diagnostic Monitoring Interface for Optical Transceivers section
1049 * 4 Memory Organization.
1051 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1054 * 2-wire device address of the digital diagnostics monitoring interface
1055 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1056 * Transceivers section 4 Memory Organization.
1058 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1061 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1062 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1065 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1068 * Maximum accessible data offset for PHY module information.
1070 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1073 extern __checkReturn efx_rc_t
1074 efx_phy_module_get_info(
1075 __in efx_nic_t *enp,
1076 __in uint8_t dev_addr,
1079 __out_bcount(len) uint8_t *data);
1081 #if EFSYS_OPT_PHY_STATS
1083 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1084 typedef enum efx_phy_stat_e {
1086 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1087 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1088 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1089 EFX_PHY_STAT_PMA_PMD_REV_A,
1090 EFX_PHY_STAT_PMA_PMD_REV_B,
1091 EFX_PHY_STAT_PMA_PMD_REV_C,
1092 EFX_PHY_STAT_PMA_PMD_REV_D,
1093 EFX_PHY_STAT_PCS_LINK_UP,
1094 EFX_PHY_STAT_PCS_RX_FAULT,
1095 EFX_PHY_STAT_PCS_TX_FAULT,
1096 EFX_PHY_STAT_PCS_BER,
1097 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1098 EFX_PHY_STAT_PHY_XS_LINK_UP,
1099 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1100 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1101 EFX_PHY_STAT_PHY_XS_ALIGN,
1102 EFX_PHY_STAT_PHY_XS_SYNC_A,
1103 EFX_PHY_STAT_PHY_XS_SYNC_B,
1104 EFX_PHY_STAT_PHY_XS_SYNC_C,
1105 EFX_PHY_STAT_PHY_XS_SYNC_D,
1106 EFX_PHY_STAT_AN_LINK_UP,
1107 EFX_PHY_STAT_AN_MASTER,
1108 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1109 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1110 EFX_PHY_STAT_CL22EXT_LINK_UP,
1115 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1116 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1117 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1118 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1119 EFX_PHY_STAT_AN_COMPLETE,
1120 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1121 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1122 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1123 EFX_PHY_STAT_PCS_FW_VERSION_0,
1124 EFX_PHY_STAT_PCS_FW_VERSION_1,
1125 EFX_PHY_STAT_PCS_FW_VERSION_2,
1126 EFX_PHY_STAT_PCS_FW_VERSION_3,
1127 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1128 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1129 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1130 EFX_PHY_STAT_PCS_OP_MODE,
1134 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1140 __in efx_nic_t *enp,
1141 __in efx_phy_stat_t stat);
1143 #endif /* EFSYS_OPT_NAMES */
1145 #define EFX_PHY_STATS_SIZE 0x100
1147 extern __checkReturn efx_rc_t
1148 efx_phy_stats_update(
1149 __in efx_nic_t *enp,
1150 __in efsys_mem_t *esmp,
1151 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1153 #endif /* EFSYS_OPT_PHY_STATS */
1158 typedef enum efx_bist_type_e {
1159 EFX_BIST_TYPE_UNKNOWN,
1160 EFX_BIST_TYPE_PHY_NORMAL,
1161 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1162 EFX_BIST_TYPE_PHY_CABLE_LONG,
1163 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1164 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1165 EFX_BIST_TYPE_REG, /* Test the register memories */
1166 EFX_BIST_TYPE_NTYPES,
1169 typedef enum efx_bist_result_e {
1170 EFX_BIST_RESULT_UNKNOWN,
1171 EFX_BIST_RESULT_RUNNING,
1172 EFX_BIST_RESULT_PASSED,
1173 EFX_BIST_RESULT_FAILED,
1174 } efx_bist_result_t;
1176 typedef enum efx_phy_cable_status_e {
1177 EFX_PHY_CABLE_STATUS_OK,
1178 EFX_PHY_CABLE_STATUS_INVALID,
1179 EFX_PHY_CABLE_STATUS_OPEN,
1180 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1181 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1182 EFX_PHY_CABLE_STATUS_BUSY,
1183 } efx_phy_cable_status_t;
1185 typedef enum efx_bist_value_e {
1186 EFX_BIST_PHY_CABLE_LENGTH_A,
1187 EFX_BIST_PHY_CABLE_LENGTH_B,
1188 EFX_BIST_PHY_CABLE_LENGTH_C,
1189 EFX_BIST_PHY_CABLE_LENGTH_D,
1190 EFX_BIST_PHY_CABLE_STATUS_A,
1191 EFX_BIST_PHY_CABLE_STATUS_B,
1192 EFX_BIST_PHY_CABLE_STATUS_C,
1193 EFX_BIST_PHY_CABLE_STATUS_D,
1194 EFX_BIST_FAULT_CODE,
1196 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1202 EFX_BIST_MEM_EXPECT,
1203 EFX_BIST_MEM_ACTUAL,
1205 EFX_BIST_MEM_ECC_PARITY,
1206 EFX_BIST_MEM_ECC_FATAL,
1210 extern __checkReturn efx_rc_t
1211 efx_bist_enable_offline(
1212 __in efx_nic_t *enp);
1214 extern __checkReturn efx_rc_t
1216 __in efx_nic_t *enp,
1217 __in efx_bist_type_t type);
1219 extern __checkReturn efx_rc_t
1221 __in efx_nic_t *enp,
1222 __in efx_bist_type_t type,
1223 __out efx_bist_result_t *resultp,
1224 __out_opt uint32_t *value_maskp,
1225 __out_ecount_opt(count) unsigned long *valuesp,
1230 __in efx_nic_t *enp,
1231 __in efx_bist_type_t type);
1233 #endif /* EFSYS_OPT_BIST */
1235 #define EFX_FEATURE_IPV6 0x00000001
1236 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1237 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1238 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1239 #define EFX_FEATURE_MCDI 0x00000020
1240 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1241 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1242 #define EFX_FEATURE_TURBO 0x00000100
1243 #define EFX_FEATURE_MCDI_DMA 0x00000200
1244 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1245 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1246 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1247 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1248 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1249 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1251 typedef enum efx_tunnel_protocol_e {
1252 EFX_TUNNEL_PROTOCOL_NONE = 0,
1253 EFX_TUNNEL_PROTOCOL_VXLAN,
1254 EFX_TUNNEL_PROTOCOL_GENEVE,
1255 EFX_TUNNEL_PROTOCOL_NVGRE,
1257 } efx_tunnel_protocol_t;
1259 typedef enum efx_vi_window_shift_e {
1260 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1261 EFX_VI_WINDOW_SHIFT_8K = 13,
1262 EFX_VI_WINDOW_SHIFT_16K = 14,
1263 EFX_VI_WINDOW_SHIFT_64K = 16,
1264 } efx_vi_window_shift_t;
1266 typedef struct efx_nic_cfg_s {
1267 uint32_t enc_board_type;
1268 uint32_t enc_phy_type;
1270 char enc_phy_name[21];
1272 char enc_phy_revision[21];
1273 efx_mon_type_t enc_mon_type;
1274 #if EFSYS_OPT_MON_STATS
1275 uint32_t enc_mon_stat_dma_buf_size;
1276 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1278 unsigned int enc_features;
1279 efx_vi_window_shift_t enc_vi_window_shift;
1280 uint8_t enc_mac_addr[6];
1281 uint8_t enc_port; /* PHY port number */
1282 uint32_t enc_intr_vec_base;
1283 uint32_t enc_intr_limit;
1284 uint32_t enc_evq_limit;
1285 uint32_t enc_txq_limit;
1286 uint32_t enc_rxq_limit;
1287 uint32_t enc_evq_max_nevs;
1288 uint32_t enc_evq_min_nevs;
1289 uint32_t enc_rxq_max_ndescs;
1290 uint32_t enc_rxq_min_ndescs;
1291 uint32_t enc_txq_max_ndescs;
1292 uint32_t enc_txq_min_ndescs;
1293 uint32_t enc_buftbl_limit;
1294 uint32_t enc_piobuf_limit;
1295 uint32_t enc_piobuf_size;
1296 uint32_t enc_piobuf_min_alloc_size;
1297 uint32_t enc_evq_timer_quantum_ns;
1298 uint32_t enc_evq_timer_max_us;
1299 uint32_t enc_clk_mult;
1300 uint32_t enc_ev_desc_size;
1301 uint32_t enc_rx_desc_size;
1302 uint32_t enc_tx_desc_size;
1303 uint32_t enc_rx_prefix_size;
1304 uint32_t enc_rx_buf_align_start;
1305 uint32_t enc_rx_buf_align_end;
1306 #if EFSYS_OPT_RX_SCALE
1307 uint32_t enc_rx_scale_max_exclusive_contexts;
1309 * Mask of supported hash algorithms.
1310 * Hash algorithm types are used as the bit indices.
1312 uint32_t enc_rx_scale_hash_alg_mask;
1314 * Indicates whether port numbers can be included to the
1315 * input data for hash computation.
1317 boolean_t enc_rx_scale_l4_hash_supported;
1318 boolean_t enc_rx_scale_additional_modes_supported;
1319 #endif /* EFSYS_OPT_RX_SCALE */
1320 #if EFSYS_OPT_LOOPBACK
1321 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1322 #endif /* EFSYS_OPT_LOOPBACK */
1323 #if EFSYS_OPT_PHY_FLAGS
1324 uint32_t enc_phy_flags_mask;
1325 #endif /* EFSYS_OPT_PHY_FLAGS */
1326 #if EFSYS_OPT_PHY_LED_CONTROL
1327 uint32_t enc_led_mask;
1328 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1329 #if EFSYS_OPT_PHY_STATS
1330 uint64_t enc_phy_stat_mask;
1331 #endif /* EFSYS_OPT_PHY_STATS */
1333 uint8_t enc_mcdi_mdio_channel;
1334 #if EFSYS_OPT_PHY_STATS
1335 uint32_t enc_mcdi_phy_stat_mask;
1336 #endif /* EFSYS_OPT_PHY_STATS */
1337 #if EFSYS_OPT_MON_STATS
1338 uint32_t *enc_mcdi_sensor_maskp;
1339 uint32_t enc_mcdi_sensor_mask_size;
1340 #endif /* EFSYS_OPT_MON_STATS */
1341 #endif /* EFSYS_OPT_MCDI */
1343 uint32_t enc_bist_mask;
1344 #endif /* EFSYS_OPT_BIST */
1348 uint32_t enc_privilege_mask;
1349 #endif /* EFX_OPTS_EF10() */
1350 boolean_t enc_bug26807_workaround;
1351 boolean_t enc_bug35388_workaround;
1352 boolean_t enc_bug41750_workaround;
1353 boolean_t enc_bug61265_workaround;
1354 boolean_t enc_bug61297_workaround;
1355 boolean_t enc_rx_batching_enabled;
1356 /* Maximum number of descriptors completed in an rx event. */
1357 uint32_t enc_rx_batch_max;
1358 /* Number of rx descriptors the hardware requires for a push. */
1359 uint32_t enc_rx_push_align;
1360 /* Maximum amount of data in DMA descriptor */
1361 uint32_t enc_tx_dma_desc_size_max;
1363 * Boundary which DMA descriptor data must not cross or 0 if no
1366 uint32_t enc_tx_dma_desc_boundary;
1368 * Maximum number of bytes into the packet the TCP header can start for
1369 * the hardware to apply TSO packet edits.
1371 uint32_t enc_tx_tso_tcp_header_offset_limit;
1372 boolean_t enc_fw_assisted_tso_enabled;
1373 boolean_t enc_fw_assisted_tso_v2_enabled;
1374 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1375 /* Number of TSO contexts on the NIC (FATSOv2) */
1376 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1377 boolean_t enc_hw_tx_insert_vlan_enabled;
1378 /* Number of PFs on the NIC */
1379 uint32_t enc_hw_pf_count;
1380 /* Datapath firmware vadapter/vport/vswitch support */
1381 boolean_t enc_datapath_cap_evb;
1382 /* Datapath firmware vport reconfigure support */
1383 boolean_t enc_vport_reconfigure_supported;
1384 boolean_t enc_rx_disable_scatter_supported;
1385 boolean_t enc_allow_set_mac_with_installed_filters;
1386 boolean_t enc_enhanced_set_mac_supported;
1387 boolean_t enc_init_evq_v2_supported;
1388 boolean_t enc_no_cont_ev_mode_supported;
1389 boolean_t enc_init_rxq_with_buffer_size;
1390 boolean_t enc_rx_packed_stream_supported;
1391 boolean_t enc_rx_var_packed_stream_supported;
1392 boolean_t enc_rx_es_super_buffer_supported;
1393 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1394 boolean_t enc_pm_and_rxdp_counters;
1395 boolean_t enc_mac_stats_40g_tx_size_bins;
1396 uint32_t enc_tunnel_encapsulations_supported;
1398 * NIC global maximum for unique UDP tunnel ports shared by all
1401 uint32_t enc_tunnel_config_udp_entries_max;
1402 /* External port identifier */
1403 uint8_t enc_external_port;
1404 uint32_t enc_mcdi_max_payload_length;
1405 /* VPD may be per-PF or global */
1406 boolean_t enc_vpd_is_global;
1407 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1408 uint32_t enc_required_pcie_bandwidth_mbps;
1409 uint32_t enc_max_pcie_link_gen;
1410 /* Firmware verifies integrity of NVRAM updates */
1411 boolean_t enc_nvram_update_verify_result_supported;
1412 /* Firmware supports polled NVRAM updates on select partitions */
1413 boolean_t enc_nvram_update_poll_verify_result_supported;
1414 /* Firmware accepts updates via the BUNDLE partition */
1415 boolean_t enc_nvram_bundle_update_supported;
1416 /* Firmware support for extended MAC_STATS buffer */
1417 uint32_t enc_mac_stats_nstats;
1418 boolean_t enc_fec_counters;
1419 boolean_t enc_hlb_counters;
1420 /* Firmware support for "FLAG" and "MARK" filter actions */
1421 boolean_t enc_filter_action_flag_supported;
1422 boolean_t enc_filter_action_mark_supported;
1423 uint32_t enc_filter_action_mark_max;
1424 /* Port assigned to this PCI function */
1425 uint32_t enc_assigned_port;
1428 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1429 ((configp)->evc_function == 0xffff)
1431 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1432 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1434 #define EFX_PCI_FUNCTION(_encp) \
1435 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1437 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1439 extern const efx_nic_cfg_t *
1441 __in const efx_nic_t *enp);
1443 /* RxDPCPU firmware id values by which FW variant can be identified */
1444 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1445 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1446 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1447 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1448 #define EFX_RXDP_DPDK_FW_ID 0x6
1450 typedef struct efx_nic_fw_info_s {
1451 /* Basic FW version information */
1452 uint16_t enfi_mc_fw_version[4];
1454 * If datapath capabilities can be detected,
1455 * additional FW information is to be shown
1457 boolean_t enfi_dpcpu_fw_ids_valid;
1458 /* Rx and Tx datapath CPU FW IDs */
1459 uint16_t enfi_rx_dpcpu_fw_id;
1460 uint16_t enfi_tx_dpcpu_fw_id;
1461 } efx_nic_fw_info_t;
1463 extern __checkReturn efx_rc_t
1464 efx_nic_get_fw_version(
1465 __in efx_nic_t *enp,
1466 __out efx_nic_fw_info_t *enfip);
1468 /* Driver resource limits (minimum required/maximum usable). */
1469 typedef struct efx_drv_limits_s {
1470 uint32_t edl_min_evq_count;
1471 uint32_t edl_max_evq_count;
1473 uint32_t edl_min_rxq_count;
1474 uint32_t edl_max_rxq_count;
1476 uint32_t edl_min_txq_count;
1477 uint32_t edl_max_txq_count;
1479 /* PIO blocks (sub-allocated from piobuf) */
1480 uint32_t edl_min_pio_alloc_size;
1481 uint32_t edl_max_pio_alloc_count;
1484 extern __checkReturn efx_rc_t
1485 efx_nic_set_drv_limits(
1486 __inout efx_nic_t *enp,
1487 __in efx_drv_limits_t *edlp);
1490 * Register the OS driver version string for management agents
1491 * (e.g. via NC-SI). The content length is provided (i.e. no
1492 * NUL terminator). Use length 0 to indicate no version string
1493 * should be advertised. It is valid to set the version string
1494 * only before efx_nic_probe() is called.
1496 extern __checkReturn efx_rc_t
1497 efx_nic_set_drv_version(
1498 __inout efx_nic_t *enp,
1499 __in_ecount(length) char const *verp,
1500 __in size_t length);
1502 typedef enum efx_nic_region_e {
1503 EFX_REGION_VI, /* Memory BAR UC mapping */
1504 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1507 extern __checkReturn efx_rc_t
1508 efx_nic_get_bar_region(
1509 __in efx_nic_t *enp,
1510 __in efx_nic_region_t region,
1511 __out uint32_t *offsetp,
1512 __out size_t *sizep);
1514 extern __checkReturn efx_rc_t
1515 efx_nic_get_vi_pool(
1516 __in efx_nic_t *enp,
1517 __out uint32_t *evq_countp,
1518 __out uint32_t *rxq_countp,
1519 __out uint32_t *txq_countp);
1524 typedef enum efx_vpd_tag_e {
1531 typedef uint16_t efx_vpd_keyword_t;
1533 typedef struct efx_vpd_value_s {
1534 efx_vpd_tag_t evv_tag;
1535 efx_vpd_keyword_t evv_keyword;
1537 uint8_t evv_value[0x100];
1541 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1543 extern __checkReturn efx_rc_t
1545 __in efx_nic_t *enp);
1547 extern __checkReturn efx_rc_t
1549 __in efx_nic_t *enp,
1550 __out size_t *sizep);
1552 extern __checkReturn efx_rc_t
1554 __in efx_nic_t *enp,
1555 __out_bcount(size) caddr_t data,
1558 extern __checkReturn efx_rc_t
1560 __in efx_nic_t *enp,
1561 __in_bcount(size) caddr_t data,
1564 extern __checkReturn efx_rc_t
1566 __in efx_nic_t *enp,
1567 __in_bcount(size) caddr_t data,
1570 extern __checkReturn efx_rc_t
1572 __in efx_nic_t *enp,
1573 __in_bcount(size) caddr_t data,
1575 __inout efx_vpd_value_t *evvp);
1577 extern __checkReturn efx_rc_t
1579 __in efx_nic_t *enp,
1580 __inout_bcount(size) caddr_t data,
1582 __in efx_vpd_value_t *evvp);
1584 extern __checkReturn efx_rc_t
1586 __in efx_nic_t *enp,
1587 __inout_bcount(size) caddr_t data,
1589 __out efx_vpd_value_t *evvp,
1590 __inout unsigned int *contp);
1592 extern __checkReturn efx_rc_t
1594 __in efx_nic_t *enp,
1595 __in_bcount(size) caddr_t data,
1600 __in efx_nic_t *enp);
1602 #endif /* EFSYS_OPT_VPD */
1608 typedef enum efx_nvram_type_e {
1609 EFX_NVRAM_INVALID = 0,
1611 EFX_NVRAM_BOOTROM_CFG,
1612 EFX_NVRAM_MC_FIRMWARE,
1613 EFX_NVRAM_MC_GOLDEN,
1619 EFX_NVRAM_FPGA_BACKUP,
1620 EFX_NVRAM_DYNAMIC_CFG,
1623 EFX_NVRAM_MUM_FIRMWARE,
1624 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1625 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1627 EFX_NVRAM_BUNDLE_METADATA,
1631 typedef struct efx_nvram_info_s {
1633 uint32_t eni_partn_size;
1634 uint32_t eni_address;
1635 uint32_t eni_erase_size;
1636 uint32_t eni_write_size;
1639 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1641 extern __checkReturn efx_rc_t
1643 __in efx_nic_t *enp);
1647 extern __checkReturn efx_rc_t
1649 __in efx_nic_t *enp);
1651 #endif /* EFSYS_OPT_DIAG */
1653 extern __checkReturn efx_rc_t
1655 __in efx_nic_t *enp,
1656 __in efx_nvram_type_t type,
1657 __out size_t *sizep);
1659 extern __checkReturn efx_rc_t
1661 __in efx_nic_t *enp,
1662 __in efx_nvram_type_t type,
1663 __out efx_nvram_info_t *enip);
1665 extern __checkReturn efx_rc_t
1667 __in efx_nic_t *enp,
1668 __in efx_nvram_type_t type,
1669 __out_opt size_t *pref_chunkp);
1671 extern __checkReturn efx_rc_t
1672 efx_nvram_rw_finish(
1673 __in efx_nic_t *enp,
1674 __in efx_nvram_type_t type,
1675 __out_opt uint32_t *verify_resultp);
1677 extern __checkReturn efx_rc_t
1678 efx_nvram_get_version(
1679 __in efx_nic_t *enp,
1680 __in efx_nvram_type_t type,
1681 __out uint32_t *subtypep,
1682 __out_ecount(4) uint16_t version[4]);
1684 extern __checkReturn efx_rc_t
1685 efx_nvram_read_chunk(
1686 __in efx_nic_t *enp,
1687 __in efx_nvram_type_t type,
1688 __in unsigned int offset,
1689 __out_bcount(size) caddr_t data,
1692 extern __checkReturn efx_rc_t
1693 efx_nvram_read_backup(
1694 __in efx_nic_t *enp,
1695 __in efx_nvram_type_t type,
1696 __in unsigned int offset,
1697 __out_bcount(size) caddr_t data,
1700 extern __checkReturn efx_rc_t
1701 efx_nvram_set_version(
1702 __in efx_nic_t *enp,
1703 __in efx_nvram_type_t type,
1704 __in_ecount(4) uint16_t version[4]);
1706 extern __checkReturn efx_rc_t
1708 __in efx_nic_t *enp,
1709 __in efx_nvram_type_t type,
1710 __in_bcount(partn_size) caddr_t partn_data,
1711 __in size_t partn_size);
1713 extern __checkReturn efx_rc_t
1715 __in efx_nic_t *enp,
1716 __in efx_nvram_type_t type);
1718 extern __checkReturn efx_rc_t
1719 efx_nvram_write_chunk(
1720 __in efx_nic_t *enp,
1721 __in efx_nvram_type_t type,
1722 __in unsigned int offset,
1723 __in_bcount(size) caddr_t data,
1728 __in efx_nic_t *enp);
1730 #endif /* EFSYS_OPT_NVRAM */
1732 #if EFSYS_OPT_BOOTCFG
1734 /* Report size and offset of bootcfg sector in NVRAM partition. */
1735 extern __checkReturn efx_rc_t
1736 efx_bootcfg_sector_info(
1737 __in efx_nic_t *enp,
1739 __out_opt uint32_t *sector_countp,
1740 __out size_t *offsetp,
1741 __out size_t *max_sizep);
1744 * Copy bootcfg sector data to a target buffer which may differ in size.
1745 * Optionally corrects format errors in source buffer.
1748 efx_bootcfg_copy_sector(
1749 __in efx_nic_t *enp,
1750 __inout_bcount(sector_length)
1752 __in size_t sector_length,
1753 __out_bcount(data_size) uint8_t *data,
1754 __in size_t data_size,
1755 __in boolean_t handle_format_errors);
1759 __in efx_nic_t *enp,
1760 __out_bcount(size) uint8_t *data,
1765 __in efx_nic_t *enp,
1766 __in_bcount(size) uint8_t *data,
1771 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1772 * (see https://tools.ietf.org/html/rfc1533)
1774 * Summarising the format: the buffer is a sequence of options. All options
1775 * begin with a tag octet, which uniquely identifies the option. Fixed-
1776 * length options without data consist of only a tag octet. Only options PAD
1777 * (0) and END (255) are fixed length. All other options are variable-length
1778 * with a length octet following the tag octet. The value of the length
1779 * octet does not include the two octets specifying the tag and length. The
1780 * length octet is followed by "length" octets of data.
1782 * Option data may be a sequence of sub-options in the same format. The data
1783 * content of the encapsulating option is one or more encapsulated sub-options,
1784 * with no terminating END tag is required.
1786 * To be valid, the top-level sequence of options should be terminated by an
1787 * END tag. The buffer should be padded with the PAD byte.
1789 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1790 * checksum octet. The full buffer (including after the END tag) contributes
1791 * to the checksum, hence the need to fill the buffer to the end with PAD.
1794 #define EFX_DHCP_END ((uint8_t)0xff)
1795 #define EFX_DHCP_PAD ((uint8_t)0)
1797 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1798 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1800 extern __checkReturn uint8_t
1802 __in_bcount(size) uint8_t const *data,
1805 extern __checkReturn efx_rc_t
1807 __in_bcount(size) uint8_t const *data,
1809 __out_opt size_t *usedp);
1811 extern __checkReturn efx_rc_t
1813 __in_bcount(buffer_length) uint8_t *bufferp,
1814 __in size_t buffer_length,
1816 __deref_out uint8_t **valuepp,
1817 __out size_t *value_lengthp);
1819 extern __checkReturn efx_rc_t
1821 __in_bcount(buffer_length) uint8_t *bufferp,
1822 __in size_t buffer_length,
1823 __deref_out uint8_t **endpp);
1826 extern __checkReturn efx_rc_t
1827 efx_dhcp_delete_tag(
1828 __inout_bcount(buffer_length) uint8_t *bufferp,
1829 __in size_t buffer_length,
1832 extern __checkReturn efx_rc_t
1834 __inout_bcount(buffer_length) uint8_t *bufferp,
1835 __in size_t buffer_length,
1837 __in_bcount_opt(value_length) uint8_t *valuep,
1838 __in size_t value_length);
1840 extern __checkReturn efx_rc_t
1841 efx_dhcp_update_tag(
1842 __inout_bcount(buffer_length) uint8_t *bufferp,
1843 __in size_t buffer_length,
1845 __in uint8_t *value_locationp,
1846 __in_bcount_opt(value_length) uint8_t *valuep,
1847 __in size_t value_length);
1850 #endif /* EFSYS_OPT_BOOTCFG */
1852 #if EFSYS_OPT_IMAGE_LAYOUT
1854 #include "ef10_signed_image_layout.h"
1857 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1860 * The image header format is extensible. However, older drivers require an
1861 * exact match of image header version and header length when validating and
1862 * writing firmware images.
1864 * To avoid breaking backward compatibility, we use the upper bits of the
1865 * controller version fields to contain an extra version number used for
1866 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1867 * version). See bug39254 and SF-102785-PS for details.
1869 typedef struct efx_image_header_s {
1871 uint32_t eih_version;
1873 uint32_t eih_subtype;
1874 uint32_t eih_code_size;
1877 uint32_t eih_controller_version_min;
1879 uint16_t eih_controller_version_min_short;
1880 uint8_t eih_extra_version_a;
1881 uint8_t eih_extra_version_b;
1885 uint32_t eih_controller_version_max;
1887 uint16_t eih_controller_version_max_short;
1888 uint8_t eih_extra_version_c;
1889 uint8_t eih_extra_version_d;
1892 uint16_t eih_code_version_a;
1893 uint16_t eih_code_version_b;
1894 uint16_t eih_code_version_c;
1895 uint16_t eih_code_version_d;
1896 } efx_image_header_t;
1898 #define EFX_IMAGE_HEADER_SIZE (40)
1899 #define EFX_IMAGE_HEADER_VERSION (4)
1900 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1903 typedef struct efx_image_trailer_s {
1905 } efx_image_trailer_t;
1907 #define EFX_IMAGE_TRAILER_SIZE (4)
1909 typedef enum efx_image_format_e {
1910 EFX_IMAGE_FORMAT_NO_IMAGE,
1911 EFX_IMAGE_FORMAT_INVALID,
1912 EFX_IMAGE_FORMAT_UNSIGNED,
1913 EFX_IMAGE_FORMAT_SIGNED,
1914 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
1915 } efx_image_format_t;
1917 typedef struct efx_image_info_s {
1918 efx_image_format_t eii_format;
1919 uint8_t * eii_imagep;
1920 size_t eii_image_size;
1921 efx_image_header_t * eii_headerp;
1924 extern __checkReturn efx_rc_t
1925 efx_check_reflash_image(
1927 __in uint32_t buffer_size,
1928 __out efx_image_info_t *infop);
1930 extern __checkReturn efx_rc_t
1931 efx_build_signed_image_write_buffer(
1932 __out_bcount(buffer_size)
1934 __in uint32_t buffer_size,
1935 __in efx_image_info_t *infop,
1936 __out efx_image_header_t **headerpp);
1938 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1942 typedef enum efx_pattern_type_t {
1943 EFX_PATTERN_BYTE_INCREMENT = 0,
1944 EFX_PATTERN_ALL_THE_SAME,
1945 EFX_PATTERN_BIT_ALTERNATE,
1946 EFX_PATTERN_BYTE_ALTERNATE,
1947 EFX_PATTERN_BYTE_CHANGING,
1948 EFX_PATTERN_BIT_SWEEP,
1950 } efx_pattern_type_t;
1953 (*efx_sram_pattern_fn_t)(
1955 __in boolean_t negate,
1956 __out efx_qword_t *eqp);
1958 extern __checkReturn efx_rc_t
1960 __in efx_nic_t *enp,
1961 __in efx_pattern_type_t type);
1963 #endif /* EFSYS_OPT_DIAG */
1965 extern __checkReturn efx_rc_t
1966 efx_sram_buf_tbl_set(
1967 __in efx_nic_t *enp,
1969 __in efsys_mem_t *esmp,
1973 efx_sram_buf_tbl_clear(
1974 __in efx_nic_t *enp,
1978 #define EFX_BUF_TBL_SIZE 0x20000
1980 #define EFX_BUF_SIZE 4096
1984 typedef struct efx_evq_s efx_evq_t;
1986 #if EFSYS_OPT_QSTATS
1988 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
1989 typedef enum efx_ev_qstat_e {
1995 EV_RX_PAUSE_FRM_ERR,
1996 EV_RX_BUF_OWNER_ID_ERR,
1997 EV_RX_IPV4_HDR_CHKSUM_ERR,
1998 EV_RX_TCP_UDP_CHKSUM_ERR,
2002 EV_RX_MCAST_HASH_MATCH,
2019 EV_DRIVER_SRM_UPD_DONE,
2020 EV_DRIVER_TX_DESCQ_FLS_DONE,
2021 EV_DRIVER_RX_DESCQ_FLS_DONE,
2022 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2023 EV_DRIVER_RX_DSC_ERROR,
2024 EV_DRIVER_TX_DSC_ERROR,
2027 EV_RX_PARSE_INCOMPLETE,
2031 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2033 #endif /* EFSYS_OPT_QSTATS */
2035 extern __checkReturn efx_rc_t
2037 __in efx_nic_t *enp);
2041 __in efx_nic_t *enp);
2043 extern __checkReturn size_t
2045 __in const efx_nic_t *enp,
2046 __in unsigned int ndescs);
2048 extern __checkReturn unsigned int
2050 __in const efx_nic_t *enp,
2051 __in unsigned int ndescs);
2053 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2054 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2055 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2056 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2058 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2059 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2060 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2063 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2064 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2067 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2068 * which is the case when an event queue is set to THROUGHPUT mode.
2070 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2072 extern __checkReturn efx_rc_t
2074 __in efx_nic_t *enp,
2075 __in unsigned int index,
2076 __in efsys_mem_t *esmp,
2080 __in uint32_t flags,
2081 __deref_out efx_evq_t **eepp);
2085 __in efx_evq_t *eep,
2086 __in uint16_t data);
2088 typedef __checkReturn boolean_t
2089 (*efx_initialized_ev_t)(
2090 __in_opt void *arg);
2092 #define EFX_PKT_UNICAST 0x0004
2093 #define EFX_PKT_START 0x0008
2095 #define EFX_PKT_VLAN_TAGGED 0x0010
2096 #define EFX_CKSUM_TCPUDP 0x0020
2097 #define EFX_CKSUM_IPV4 0x0040
2098 #define EFX_PKT_CONT 0x0080
2100 #define EFX_CHECK_VLAN 0x0100
2101 #define EFX_PKT_TCP 0x0200
2102 #define EFX_PKT_UDP 0x0400
2103 #define EFX_PKT_IPV4 0x0800
2105 #define EFX_PKT_IPV6 0x1000
2106 #define EFX_PKT_PREFIX_LEN 0x2000
2107 #define EFX_ADDR_MISMATCH 0x4000
2108 #define EFX_DISCARD 0x8000
2111 * The following flags are used only for packed stream
2112 * mode. The values for the flags are reused to fit into 16 bit,
2113 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2114 * packed stream mode
2116 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2117 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2120 #define EFX_EV_RX_NLABELS 32
2121 #define EFX_EV_TX_NLABELS 32
2123 typedef __checkReturn boolean_t
2126 __in uint32_t label,
2129 __in uint16_t flags);
2131 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2134 * Packed stream mode is documented in SF-112241-TC.
2135 * The general idea is that, instead of putting each incoming
2136 * packet into a separate buffer which is specified in a RX
2137 * descriptor, a large buffer is provided to the hardware and
2138 * packets are put there in a continuous stream.
2139 * The main advantage of such an approach is that RX queue refilling
2140 * happens much less frequently.
2142 * Equal stride packed stream mode is documented in SF-119419-TC.
2143 * The general idea is to utilize advantages of the packed stream,
2144 * but avoid indirection in packets representation.
2145 * The main advantage of such an approach is that RX queue refilling
2146 * happens much less frequently and packets buffers are independent
2147 * from upper layers point of view.
2150 typedef __checkReturn boolean_t
2153 __in uint32_t label,
2155 __in uint32_t pkt_count,
2156 __in uint16_t flags);
2160 typedef __checkReturn boolean_t
2163 __in uint32_t label,
2166 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2167 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2168 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2169 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2170 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2171 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2172 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2173 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2174 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2176 typedef __checkReturn boolean_t
2177 (*efx_exception_ev_t)(
2179 __in uint32_t label,
2180 __in uint32_t data);
2182 typedef __checkReturn boolean_t
2183 (*efx_rxq_flush_done_ev_t)(
2185 __in uint32_t rxq_index);
2187 typedef __checkReturn boolean_t
2188 (*efx_rxq_flush_failed_ev_t)(
2190 __in uint32_t rxq_index);
2192 typedef __checkReturn boolean_t
2193 (*efx_txq_flush_done_ev_t)(
2195 __in uint32_t txq_index);
2197 typedef __checkReturn boolean_t
2198 (*efx_software_ev_t)(
2200 __in uint16_t magic);
2202 typedef __checkReturn boolean_t
2205 __in uint32_t code);
2207 #define EFX_SRAM_CLEAR 0
2208 #define EFX_SRAM_UPDATE 1
2209 #define EFX_SRAM_ILLEGAL_CLEAR 2
2211 typedef __checkReturn boolean_t
2212 (*efx_wake_up_ev_t)(
2214 __in uint32_t label);
2216 typedef __checkReturn boolean_t
2219 __in uint32_t label);
2221 typedef __checkReturn boolean_t
2222 (*efx_link_change_ev_t)(
2224 __in efx_link_mode_t link_mode);
2226 #if EFSYS_OPT_MON_STATS
2228 typedef __checkReturn boolean_t
2229 (*efx_monitor_ev_t)(
2231 __in efx_mon_stat_t id,
2232 __in efx_mon_stat_value_t value);
2234 #endif /* EFSYS_OPT_MON_STATS */
2236 #if EFSYS_OPT_MAC_STATS
2238 typedef __checkReturn boolean_t
2239 (*efx_mac_stats_ev_t)(
2241 __in uint32_t generation);
2243 #endif /* EFSYS_OPT_MAC_STATS */
2245 typedef struct efx_ev_callbacks_s {
2246 efx_initialized_ev_t eec_initialized;
2248 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2249 efx_rx_ps_ev_t eec_rx_ps;
2252 efx_exception_ev_t eec_exception;
2253 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2254 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2255 efx_txq_flush_done_ev_t eec_txq_flush_done;
2256 efx_software_ev_t eec_software;
2257 efx_sram_ev_t eec_sram;
2258 efx_wake_up_ev_t eec_wake_up;
2259 efx_timer_ev_t eec_timer;
2260 efx_link_change_ev_t eec_link_change;
2261 #if EFSYS_OPT_MON_STATS
2262 efx_monitor_ev_t eec_monitor;
2263 #endif /* EFSYS_OPT_MON_STATS */
2264 #if EFSYS_OPT_MAC_STATS
2265 efx_mac_stats_ev_t eec_mac_stats;
2266 #endif /* EFSYS_OPT_MAC_STATS */
2267 } efx_ev_callbacks_t;
2269 extern __checkReturn boolean_t
2271 __in efx_evq_t *eep,
2272 __in unsigned int count);
2274 #if EFSYS_OPT_EV_PREFETCH
2278 __in efx_evq_t *eep,
2279 __in unsigned int count);
2281 #endif /* EFSYS_OPT_EV_PREFETCH */
2285 __in efx_evq_t *eep,
2286 __inout unsigned int *countp,
2287 __in const efx_ev_callbacks_t *eecp,
2288 __in_opt void *arg);
2290 extern __checkReturn efx_rc_t
2291 efx_ev_usecs_to_ticks(
2292 __in efx_nic_t *enp,
2293 __in unsigned int usecs,
2294 __out unsigned int *ticksp);
2296 extern __checkReturn efx_rc_t
2298 __in efx_evq_t *eep,
2299 __in unsigned int us);
2301 extern __checkReturn efx_rc_t
2303 __in efx_evq_t *eep,
2304 __in unsigned int count);
2306 #if EFSYS_OPT_QSTATS
2312 __in efx_nic_t *enp,
2313 __in unsigned int id);
2315 #endif /* EFSYS_OPT_NAMES */
2318 efx_ev_qstats_update(
2319 __in efx_evq_t *eep,
2320 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2322 #endif /* EFSYS_OPT_QSTATS */
2326 __in efx_evq_t *eep);
2330 extern __checkReturn efx_rc_t
2332 __inout efx_nic_t *enp);
2336 __in efx_nic_t *enp);
2338 #if EFSYS_OPT_RX_SCATTER
2339 __checkReturn efx_rc_t
2340 efx_rx_scatter_enable(
2341 __in efx_nic_t *enp,
2342 __in unsigned int buf_size);
2343 #endif /* EFSYS_OPT_RX_SCATTER */
2345 /* Handle to represent use of the default RSS context. */
2346 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2348 #if EFSYS_OPT_RX_SCALE
2350 typedef enum efx_rx_hash_alg_e {
2351 EFX_RX_HASHALG_LFSR = 0,
2352 EFX_RX_HASHALG_TOEPLITZ,
2353 EFX_RX_HASHALG_PACKED_STREAM,
2355 } efx_rx_hash_alg_t;
2358 * Legacy hash type flags.
2360 * They represent standard tuples for distinct traffic classes.
2362 #define EFX_RX_HASH_IPV4 (1U << 0)
2363 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2364 #define EFX_RX_HASH_IPV6 (1U << 2)
2365 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2367 #define EFX_RX_HASH_LEGACY_MASK \
2368 (EFX_RX_HASH_IPV4 | \
2369 EFX_RX_HASH_TCPIPV4 | \
2370 EFX_RX_HASH_IPV6 | \
2371 EFX_RX_HASH_TCPIPV6)
2374 * The type of the argument used by efx_rx_scale_mode_set() to
2375 * provide a means for the client drivers to configure hashing.
2377 * A properly constructed value can either be:
2378 * - a combination of legacy flags
2379 * - a combination of EFX_RX_HASH() flags
2381 typedef uint32_t efx_rx_hash_type_t;
2383 typedef enum efx_rx_hash_support_e {
2384 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2385 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2386 } efx_rx_hash_support_t;
2388 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2389 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2390 #define EFX_MAXRSS 64 /* RX indirection entry range */
2391 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2393 typedef enum efx_rx_scale_context_type_e {
2394 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2395 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2396 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2397 } efx_rx_scale_context_type_t;
2400 * Traffic classes eligible for hash computation.
2402 * Select packet headers used in computing the receive hash.
2403 * This uses the same encoding as the RSS_MODES field of
2404 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2406 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2407 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2408 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2409 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2410 #define EFX_RX_CLASS_IPV4_LBN 16
2411 #define EFX_RX_CLASS_IPV4_WIDTH 4
2412 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2413 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2414 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2415 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2416 #define EFX_RX_CLASS_IPV6_LBN 28
2417 #define EFX_RX_CLASS_IPV6_WIDTH 4
2419 #define EFX_RX_NCLASSES 6
2422 * Ancillary flags used to construct generic hash tuples.
2423 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2425 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2426 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2427 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2428 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2431 * Generic hash tuples.
2433 * They express combinations of packet fields
2434 * which can contribute to the hash value for
2435 * a particular traffic class.
2437 #define EFX_RX_CLASS_HASH_DISABLE 0
2439 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2440 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2442 #define EFX_RX_CLASS_HASH_2TUPLE \
2443 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2444 EFX_RX_CLASS_HASH_DST_ADDR)
2446 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2447 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2448 EFX_RX_CLASS_HASH_SRC_PORT)
2450 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2451 (EFX_RX_CLASS_HASH_DST_ADDR | \
2452 EFX_RX_CLASS_HASH_DST_PORT)
2454 #define EFX_RX_CLASS_HASH_4TUPLE \
2455 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2456 EFX_RX_CLASS_HASH_DST_ADDR | \
2457 EFX_RX_CLASS_HASH_SRC_PORT | \
2458 EFX_RX_CLASS_HASH_DST_PORT)
2460 #define EFX_RX_CLASS_HASH_NTUPLES 7
2463 * Hash flag constructor.
2465 * Resulting flags encode hash tuples for specific traffic classes.
2466 * The client drivers are encouraged to use these flags to form
2467 * a hash type value.
2469 #define EFX_RX_HASH(_class, _tuple) \
2470 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2471 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2474 * The maximum number of EFX_RX_HASH() flags.
2476 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2478 extern __checkReturn efx_rc_t
2479 efx_rx_scale_hash_flags_get(
2480 __in efx_nic_t *enp,
2481 __in efx_rx_hash_alg_t hash_alg,
2482 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2483 __in unsigned int max_nflags,
2484 __out unsigned int *nflagsp);
2486 extern __checkReturn efx_rc_t
2487 efx_rx_hash_default_support_get(
2488 __in efx_nic_t *enp,
2489 __out efx_rx_hash_support_t *supportp);
2492 extern __checkReturn efx_rc_t
2493 efx_rx_scale_default_support_get(
2494 __in efx_nic_t *enp,
2495 __out efx_rx_scale_context_type_t *typep);
2497 extern __checkReturn efx_rc_t
2498 efx_rx_scale_context_alloc(
2499 __in efx_nic_t *enp,
2500 __in efx_rx_scale_context_type_t type,
2501 __in uint32_t num_queues,
2502 __out uint32_t *rss_contextp);
2504 extern __checkReturn efx_rc_t
2505 efx_rx_scale_context_free(
2506 __in efx_nic_t *enp,
2507 __in uint32_t rss_context);
2509 extern __checkReturn efx_rc_t
2510 efx_rx_scale_mode_set(
2511 __in efx_nic_t *enp,
2512 __in uint32_t rss_context,
2513 __in efx_rx_hash_alg_t alg,
2514 __in efx_rx_hash_type_t type,
2515 __in boolean_t insert);
2517 extern __checkReturn efx_rc_t
2518 efx_rx_scale_tbl_set(
2519 __in efx_nic_t *enp,
2520 __in uint32_t rss_context,
2521 __in_ecount(n) unsigned int *table,
2524 extern __checkReturn efx_rc_t
2525 efx_rx_scale_key_set(
2526 __in efx_nic_t *enp,
2527 __in uint32_t rss_context,
2528 __in_ecount(n) uint8_t *key,
2531 extern __checkReturn uint32_t
2532 efx_pseudo_hdr_hash_get(
2533 __in efx_rxq_t *erp,
2534 __in efx_rx_hash_alg_t func,
2535 __in uint8_t *buffer);
2537 #endif /* EFSYS_OPT_RX_SCALE */
2539 extern __checkReturn efx_rc_t
2540 efx_pseudo_hdr_pkt_length_get(
2541 __in efx_rxq_t *erp,
2542 __in uint8_t *buffer,
2543 __out uint16_t *pkt_lengthp);
2545 extern __checkReturn size_t
2547 __in const efx_nic_t *enp,
2548 __in unsigned int ndescs);
2550 extern __checkReturn unsigned int
2552 __in const efx_nic_t *enp,
2553 __in unsigned int ndescs);
2555 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2557 typedef enum efx_rxq_type_e {
2558 EFX_RXQ_TYPE_DEFAULT,
2559 EFX_RXQ_TYPE_PACKED_STREAM,
2560 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2565 * Dummy flag to be used instead of 0 to make it clear that the argument
2566 * is receive queue flags.
2568 #define EFX_RXQ_FLAG_NONE 0x0
2569 #define EFX_RXQ_FLAG_SCATTER 0x1
2571 * If tunnels are supported and Rx event can provide information about
2572 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2573 * full-feature firmware variant running), outer classes are requested by
2574 * default. However, if the driver supports tunnels, the flag allows to
2575 * request inner classes which are required to be able to interpret inner
2576 * Rx checksum offload results.
2578 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2580 extern __checkReturn efx_rc_t
2582 __in efx_nic_t *enp,
2583 __in unsigned int index,
2584 __in unsigned int label,
2585 __in efx_rxq_type_t type,
2586 __in size_t buf_size,
2587 __in efsys_mem_t *esmp,
2590 __in unsigned int flags,
2591 __in efx_evq_t *eep,
2592 __deref_out efx_rxq_t **erpp);
2594 #if EFSYS_OPT_RX_PACKED_STREAM
2596 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2597 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2598 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2599 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2600 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2602 extern __checkReturn efx_rc_t
2603 efx_rx_qcreate_packed_stream(
2604 __in efx_nic_t *enp,
2605 __in unsigned int index,
2606 __in unsigned int label,
2607 __in uint32_t ps_buf_size,
2608 __in efsys_mem_t *esmp,
2610 __in efx_evq_t *eep,
2611 __deref_out efx_rxq_t **erpp);
2615 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2617 /* Maximum head-of-line block timeout in nanoseconds */
2618 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2620 extern __checkReturn efx_rc_t
2621 efx_rx_qcreate_es_super_buffer(
2622 __in efx_nic_t *enp,
2623 __in unsigned int index,
2624 __in unsigned int label,
2625 __in uint32_t n_bufs_per_desc,
2626 __in uint32_t max_dma_len,
2627 __in uint32_t buf_stride,
2628 __in uint32_t hol_block_timeout,
2629 __in efsys_mem_t *esmp,
2631 __in unsigned int flags,
2632 __in efx_evq_t *eep,
2633 __deref_out efx_rxq_t **erpp);
2637 typedef struct efx_buffer_s {
2638 efsys_dma_addr_t eb_addr;
2643 typedef struct efx_desc_s {
2649 __in efx_rxq_t *erp,
2650 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2652 __in unsigned int ndescs,
2653 __in unsigned int completed,
2654 __in unsigned int added);
2658 __in efx_rxq_t *erp,
2659 __in unsigned int added,
2660 __inout unsigned int *pushedp);
2662 #if EFSYS_OPT_RX_PACKED_STREAM
2665 efx_rx_qpush_ps_credits(
2666 __in efx_rxq_t *erp);
2668 extern __checkReturn uint8_t *
2669 efx_rx_qps_packet_info(
2670 __in efx_rxq_t *erp,
2671 __in uint8_t *buffer,
2672 __in uint32_t buffer_length,
2673 __in uint32_t current_offset,
2674 __out uint16_t *lengthp,
2675 __out uint32_t *next_offsetp,
2676 __out uint32_t *timestamp);
2679 extern __checkReturn efx_rc_t
2681 __in efx_rxq_t *erp);
2685 __in efx_rxq_t *erp);
2689 __in efx_rxq_t *erp);
2693 typedef struct efx_txq_s efx_txq_t;
2695 #if EFSYS_OPT_QSTATS
2697 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2698 typedef enum efx_tx_qstat_e {
2704 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2706 #endif /* EFSYS_OPT_QSTATS */
2708 extern __checkReturn efx_rc_t
2710 __in efx_nic_t *enp);
2714 __in efx_nic_t *enp);
2716 extern __checkReturn size_t
2718 __in const efx_nic_t *enp,
2719 __in unsigned int ndescs);
2721 extern __checkReturn unsigned int
2723 __in const efx_nic_t *enp,
2724 __in unsigned int ndescs);
2726 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2728 #define EFX_TXQ_CKSUM_IPV4 0x0001
2729 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2730 #define EFX_TXQ_FATSOV2 0x0004
2731 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2732 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2734 extern __checkReturn efx_rc_t
2736 __in efx_nic_t *enp,
2737 __in unsigned int index,
2738 __in unsigned int label,
2739 __in efsys_mem_t *esmp,
2742 __in uint16_t flags,
2743 __in efx_evq_t *eep,
2744 __deref_out efx_txq_t **etpp,
2745 __out unsigned int *addedp);
2747 extern __checkReturn efx_rc_t
2749 __in efx_txq_t *etp,
2750 __in_ecount(ndescs) efx_buffer_t *eb,
2751 __in unsigned int ndescs,
2752 __in unsigned int completed,
2753 __inout unsigned int *addedp);
2755 extern __checkReturn efx_rc_t
2757 __in efx_txq_t *etp,
2758 __in unsigned int ns);
2762 __in efx_txq_t *etp,
2763 __in unsigned int added,
2764 __in unsigned int pushed);
2766 extern __checkReturn efx_rc_t
2768 __in efx_txq_t *etp);
2772 __in efx_txq_t *etp);
2774 extern __checkReturn efx_rc_t
2776 __in efx_txq_t *etp);
2779 efx_tx_qpio_disable(
2780 __in efx_txq_t *etp);
2782 extern __checkReturn efx_rc_t
2784 __in efx_txq_t *etp,
2785 __in_ecount(buf_length) uint8_t *buffer,
2786 __in size_t buf_length,
2787 __in size_t pio_buf_offset);
2789 extern __checkReturn efx_rc_t
2791 __in efx_txq_t *etp,
2792 __in size_t pkt_length,
2793 __in unsigned int completed,
2794 __inout unsigned int *addedp);
2796 extern __checkReturn efx_rc_t
2798 __in efx_txq_t *etp,
2799 __in_ecount(n) efx_desc_t *ed,
2800 __in unsigned int n,
2801 __in unsigned int completed,
2802 __inout unsigned int *addedp);
2805 efx_tx_qdesc_dma_create(
2806 __in efx_txq_t *etp,
2807 __in efsys_dma_addr_t addr,
2810 __out efx_desc_t *edp);
2813 efx_tx_qdesc_tso_create(
2814 __in efx_txq_t *etp,
2815 __in uint16_t ipv4_id,
2816 __in uint32_t tcp_seq,
2817 __in uint8_t tcp_flags,
2818 __out efx_desc_t *edp);
2820 /* Number of FATSOv2 option descriptors */
2821 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2823 /* Maximum number of DMA segments per TSO packet (not superframe) */
2824 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2827 efx_tx_qdesc_tso2_create(
2828 __in efx_txq_t *etp,
2829 __in uint16_t ipv4_id,
2830 __in uint16_t outer_ipv4_id,
2831 __in uint32_t tcp_seq,
2832 __in uint16_t tcp_mss,
2833 __out_ecount(count) efx_desc_t *edp,
2837 efx_tx_qdesc_vlantci_create(
2838 __in efx_txq_t *etp,
2840 __out efx_desc_t *edp);
2843 efx_tx_qdesc_checksum_create(
2844 __in efx_txq_t *etp,
2845 __in uint16_t flags,
2846 __out efx_desc_t *edp);
2848 #if EFSYS_OPT_QSTATS
2854 __in efx_nic_t *etp,
2855 __in unsigned int id);
2857 #endif /* EFSYS_OPT_NAMES */
2860 efx_tx_qstats_update(
2861 __in efx_txq_t *etp,
2862 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2864 #endif /* EFSYS_OPT_QSTATS */
2868 __in efx_txq_t *etp);
2873 #if EFSYS_OPT_FILTER
2875 #define EFX_ETHER_TYPE_IPV4 0x0800
2876 #define EFX_ETHER_TYPE_IPV6 0x86DD
2878 #define EFX_IPPROTO_TCP 6
2879 #define EFX_IPPROTO_UDP 17
2880 #define EFX_IPPROTO_GRE 47
2882 /* Use RSS to spread across multiple queues */
2883 #define EFX_FILTER_FLAG_RX_RSS 0x01
2884 /* Enable RX scatter */
2885 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2887 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2888 * May only be set by the filter implementation for each type.
2889 * A removal request will restore the automatic filter in its place.
2891 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2892 /* Filter is for RX */
2893 #define EFX_FILTER_FLAG_RX 0x08
2894 /* Filter is for TX */
2895 #define EFX_FILTER_FLAG_TX 0x10
2896 /* Set match flag on the received packet */
2897 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2898 /* Set match mark on the received packet */
2899 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2901 typedef uint8_t efx_filter_flags_t;
2904 * Flags which specify the fields to match on. The values are the same as in the
2905 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2908 /* Match by remote IP host address */
2909 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2910 /* Match by local IP host address */
2911 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2912 /* Match by remote MAC address */
2913 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2914 /* Match by remote TCP/UDP port */
2915 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2916 /* Match by remote TCP/UDP port */
2917 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2918 /* Match by local TCP/UDP port */
2919 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2920 /* Match by Ether-type */
2921 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2922 /* Match by inner VLAN ID */
2923 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2924 /* Match by outer VLAN ID */
2925 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2926 /* Match by IP transport protocol */
2927 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2928 /* Match by VNI or VSID */
2929 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2930 /* For encapsulated packets, match by inner frame local MAC address */
2931 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2932 /* For encapsulated packets, match all multicast inner frames */
2933 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2934 /* For encapsulated packets, match all unicast inner frames */
2935 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2937 * Match by encap type, this flag does not correspond to
2938 * the MCDI match flags and any unoccupied value may be used
2940 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2941 /* Match otherwise-unmatched multicast and broadcast packets */
2942 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2943 /* Match otherwise-unmatched unicast packets */
2944 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2946 typedef uint32_t efx_filter_match_flags_t;
2948 typedef enum efx_filter_priority_s {
2949 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2950 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2951 * address list or hardware
2952 * requirements. This may only be used
2953 * by the filter implementation for
2955 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2956 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2957 * client (e.g. SR-IOV, HyperV VMQ etc.)
2959 } efx_filter_priority_t;
2962 * FIXME: All these fields are assumed to be in little-endian byte order.
2963 * It may be better for some to be big-endian. See bug42804.
2966 typedef struct efx_filter_spec_s {
2967 efx_filter_match_flags_t efs_match_flags;
2968 uint8_t efs_priority;
2969 efx_filter_flags_t efs_flags;
2970 uint16_t efs_dmaq_id;
2971 uint32_t efs_rss_context;
2973 /* Fields below here are hashed for software filter lookup */
2974 uint16_t efs_outer_vid;
2975 uint16_t efs_inner_vid;
2976 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2977 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2978 uint16_t efs_ether_type;
2979 uint8_t efs_ip_proto;
2980 efx_tunnel_protocol_t efs_encap_type;
2981 uint16_t efs_loc_port;
2982 uint16_t efs_rem_port;
2983 efx_oword_t efs_rem_host;
2984 efx_oword_t efs_loc_host;
2985 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2986 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2987 } efx_filter_spec_t;
2990 /* Default values for use in filter specifications */
2991 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2992 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2994 extern __checkReturn efx_rc_t
2996 __in efx_nic_t *enp);
3000 __in efx_nic_t *enp);
3002 extern __checkReturn efx_rc_t
3004 __in efx_nic_t *enp,
3005 __inout efx_filter_spec_t *spec);
3007 extern __checkReturn efx_rc_t
3009 __in efx_nic_t *enp,
3010 __inout efx_filter_spec_t *spec);
3012 extern __checkReturn efx_rc_t
3014 __in efx_nic_t *enp);
3016 extern __checkReturn efx_rc_t
3017 efx_filter_supported_filters(
3018 __in efx_nic_t *enp,
3019 __out_ecount(buffer_length) uint32_t *buffer,
3020 __in size_t buffer_length,
3021 __out size_t *list_lengthp);
3024 efx_filter_spec_init_rx(
3025 __out efx_filter_spec_t *spec,
3026 __in efx_filter_priority_t priority,
3027 __in efx_filter_flags_t flags,
3028 __in efx_rxq_t *erp);
3031 efx_filter_spec_init_tx(
3032 __out efx_filter_spec_t *spec,
3033 __in efx_txq_t *etp);
3035 extern __checkReturn efx_rc_t
3036 efx_filter_spec_set_ipv4_local(
3037 __inout efx_filter_spec_t *spec,
3040 __in uint16_t port);
3042 extern __checkReturn efx_rc_t
3043 efx_filter_spec_set_ipv4_full(
3044 __inout efx_filter_spec_t *spec,
3046 __in uint32_t lhost,
3047 __in uint16_t lport,
3048 __in uint32_t rhost,
3049 __in uint16_t rport);
3051 extern __checkReturn efx_rc_t
3052 efx_filter_spec_set_eth_local(
3053 __inout efx_filter_spec_t *spec,
3055 __in const uint8_t *addr);
3058 efx_filter_spec_set_ether_type(
3059 __inout efx_filter_spec_t *spec,
3060 __in uint16_t ether_type);
3062 extern __checkReturn efx_rc_t
3063 efx_filter_spec_set_uc_def(
3064 __inout efx_filter_spec_t *spec);
3066 extern __checkReturn efx_rc_t
3067 efx_filter_spec_set_mc_def(
3068 __inout efx_filter_spec_t *spec);
3070 typedef enum efx_filter_inner_frame_match_e {
3071 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3072 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3073 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3074 } efx_filter_inner_frame_match_t;
3076 extern __checkReturn efx_rc_t
3077 efx_filter_spec_set_encap_type(
3078 __inout efx_filter_spec_t *spec,
3079 __in efx_tunnel_protocol_t encap_type,
3080 __in efx_filter_inner_frame_match_t inner_frame_match);
3082 extern __checkReturn efx_rc_t
3083 efx_filter_spec_set_vxlan(
3084 __inout efx_filter_spec_t *spec,
3085 __in const uint8_t *vni,
3086 __in const uint8_t *inner_addr,
3087 __in const uint8_t *outer_addr);
3089 extern __checkReturn efx_rc_t
3090 efx_filter_spec_set_geneve(
3091 __inout efx_filter_spec_t *spec,
3092 __in const uint8_t *vni,
3093 __in const uint8_t *inner_addr,
3094 __in const uint8_t *outer_addr);
3096 extern __checkReturn efx_rc_t
3097 efx_filter_spec_set_nvgre(
3098 __inout efx_filter_spec_t *spec,
3099 __in const uint8_t *vsid,
3100 __in const uint8_t *inner_addr,
3101 __in const uint8_t *outer_addr);
3103 #if EFSYS_OPT_RX_SCALE
3104 extern __checkReturn efx_rc_t
3105 efx_filter_spec_set_rss_context(
3106 __inout efx_filter_spec_t *spec,
3107 __in uint32_t rss_context);
3109 #endif /* EFSYS_OPT_FILTER */
3113 extern __checkReturn uint32_t
3115 __in_ecount(count) uint32_t const *input,
3117 __in uint32_t init);
3119 extern __checkReturn uint32_t
3121 __in_ecount(length) uint8_t const *input,
3123 __in uint32_t init);
3125 #if EFSYS_OPT_LICENSING
3129 typedef struct efx_key_stats_s {
3131 uint32_t eks_invalid;
3132 uint32_t eks_blacklisted;
3133 uint32_t eks_unverifiable;
3134 uint32_t eks_wrong_node;
3135 uint32_t eks_licensed_apps_lo;
3136 uint32_t eks_licensed_apps_hi;
3137 uint32_t eks_licensed_features_lo;
3138 uint32_t eks_licensed_features_hi;
3141 extern __checkReturn efx_rc_t
3143 __in efx_nic_t *enp);
3147 __in efx_nic_t *enp);
3149 extern __checkReturn boolean_t
3150 efx_lic_check_support(
3151 __in efx_nic_t *enp);
3153 extern __checkReturn efx_rc_t
3154 efx_lic_update_licenses(
3155 __in efx_nic_t *enp);
3157 extern __checkReturn efx_rc_t
3158 efx_lic_get_key_stats(
3159 __in efx_nic_t *enp,
3160 __out efx_key_stats_t *ksp);
3162 extern __checkReturn efx_rc_t
3164 __in efx_nic_t *enp,
3165 __in uint64_t app_id,
3166 __out boolean_t *licensedp);
3168 extern __checkReturn efx_rc_t
3170 __in efx_nic_t *enp,
3171 __in size_t buffer_size,
3172 __out uint32_t *typep,
3173 __out size_t *lengthp,
3174 __out_opt uint8_t *bufferp);
3177 extern __checkReturn efx_rc_t
3179 __in efx_nic_t *enp,
3180 __in_bcount(buffer_size)
3182 __in size_t buffer_size,
3183 __out uint32_t *startp);
3185 extern __checkReturn efx_rc_t
3187 __in efx_nic_t *enp,
3188 __in_bcount(buffer_size)
3190 __in size_t buffer_size,
3191 __in uint32_t offset,
3192 __out uint32_t *endp);
3194 extern __checkReturn __success(return != B_FALSE) boolean_t
3196 __in efx_nic_t *enp,
3197 __in_bcount(buffer_size)
3199 __in size_t buffer_size,
3200 __in uint32_t offset,
3201 __out uint32_t *startp,
3202 __out uint32_t *lengthp);
3204 extern __checkReturn __success(return != B_FALSE) boolean_t
3205 efx_lic_validate_key(
3206 __in efx_nic_t *enp,
3207 __in_bcount(length) caddr_t keyp,
3208 __in uint32_t length);
3210 extern __checkReturn efx_rc_t
3212 __in efx_nic_t *enp,
3213 __in_bcount(buffer_size)
3215 __in size_t buffer_size,
3216 __in uint32_t offset,
3217 __in uint32_t length,
3218 __out_bcount_part(key_max_size, *lengthp)
3220 __in size_t key_max_size,
3221 __out uint32_t *lengthp);
3223 extern __checkReturn efx_rc_t
3225 __in efx_nic_t *enp,
3226 __in_bcount(buffer_size)
3228 __in size_t buffer_size,
3229 __in uint32_t offset,
3230 __in_bcount(length) caddr_t keyp,
3231 __in uint32_t length,
3232 __out uint32_t *lengthp);
3234 __checkReturn efx_rc_t
3236 __in efx_nic_t *enp,
3237 __in_bcount(buffer_size)
3239 __in size_t buffer_size,
3240 __in uint32_t offset,
3241 __in uint32_t length,
3243 __out uint32_t *deltap);
3245 extern __checkReturn efx_rc_t
3246 efx_lic_create_partition(
3247 __in efx_nic_t *enp,
3248 __in_bcount(buffer_size)
3250 __in size_t buffer_size);
3252 extern __checkReturn efx_rc_t
3253 efx_lic_finish_partition(
3254 __in efx_nic_t *enp,
3255 __in_bcount(buffer_size)
3257 __in size_t buffer_size);
3259 #endif /* EFSYS_OPT_LICENSING */
3263 #if EFSYS_OPT_TUNNEL
3265 extern __checkReturn efx_rc_t
3267 __in efx_nic_t *enp);
3271 __in efx_nic_t *enp);
3274 * For overlay network encapsulation using UDP, the firmware needs to know
3275 * the configured UDP port for the overlay so it can decode encapsulated
3277 * The UDP port/protocol list is global.
3280 extern __checkReturn efx_rc_t
3281 efx_tunnel_config_udp_add(
3282 __in efx_nic_t *enp,
3283 __in uint16_t port /* host/cpu-endian */,
3284 __in efx_tunnel_protocol_t protocol);
3286 extern __checkReturn efx_rc_t
3287 efx_tunnel_config_udp_remove(
3288 __in efx_nic_t *enp,
3289 __in uint16_t port /* host/cpu-endian */,
3290 __in efx_tunnel_protocol_t protocol);
3293 efx_tunnel_config_clear(
3294 __in efx_nic_t *enp);
3297 * Apply tunnel UDP ports configuration to hardware.
3299 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3302 extern __checkReturn efx_rc_t
3303 efx_tunnel_reconfigure(
3304 __in efx_nic_t *enp);
3306 #endif /* EFSYS_OPT_TUNNEL */
3308 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3311 * Firmware subvariant choice options.
3313 * It may be switched to no Tx checksum if attached drivers are either
3314 * preboot or firmware subvariant aware and no VIS are allocated.
3315 * If may be always switched to default explicitly using set request or
3316 * implicitly if unaware driver is attaching. If switching is done when
3317 * a driver is attached, it gets MC_REBOOT event and should recreate its
3320 * See SF-119419-TC DPDK Firmware Driver Interface and
3321 * SF-109306-TC EF10 for Driver Writers for details.
3323 typedef enum efx_nic_fw_subvariant_e {
3324 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3325 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3326 EFX_NIC_FW_SUBVARIANT_NTYPES
3327 } efx_nic_fw_subvariant_t;
3329 extern __checkReturn efx_rc_t
3330 efx_nic_get_fw_subvariant(
3331 __in efx_nic_t *enp,
3332 __out efx_nic_fw_subvariant_t *subvariantp);
3334 extern __checkReturn efx_rc_t
3335 efx_nic_set_fw_subvariant(
3336 __in efx_nic_t *enp,
3337 __in efx_nic_fw_subvariant_t subvariant);
3339 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3341 typedef enum efx_phy_fec_type_e {
3342 EFX_PHY_FEC_NONE = 0,
3345 } efx_phy_fec_type_t;
3347 extern __checkReturn efx_rc_t
3348 efx_phy_fec_type_get(
3349 __in efx_nic_t *enp,
3350 __out efx_phy_fec_type_t *typep);
3352 typedef struct efx_phy_link_state_s {
3353 uint32_t epls_adv_cap_mask;
3354 uint32_t epls_lp_cap_mask;
3355 uint32_t epls_ld_cap_mask;
3356 unsigned int epls_fcntl;
3357 efx_phy_fec_type_t epls_fec;
3358 efx_link_mode_t epls_link_mode;
3359 } efx_phy_link_state_t;
3361 extern __checkReturn efx_rc_t
3362 efx_phy_link_state_get(
3363 __in efx_nic_t *enp,
3364 __out efx_phy_link_state_t *eplsp);
3369 typedef uint32_t efx_vswitch_id_t;
3370 typedef uint32_t efx_vport_id_t;
3372 typedef enum efx_vswitch_type_e {
3373 EFX_VSWITCH_TYPE_VLAN = 1,
3374 EFX_VSWITCH_TYPE_VEB,
3375 /* VSWITCH_TYPE_VEPA: obsolete */
3376 EFX_VSWITCH_TYPE_MUX = 4,
3377 } efx_vswitch_type_t;
3379 typedef enum efx_vport_type_e {
3380 EFX_VPORT_TYPE_NORMAL = 4,
3381 EFX_VPORT_TYPE_EXPANSION,
3382 EFX_VPORT_TYPE_TEST,
3385 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3386 #define EFX_FILTER_VID_UNSPEC 0xffff
3387 #define EFX_DEFAULT_VSWITCH_ID 1
3389 /* Default VF VLAN ID on creation */
3390 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3391 #define EFX_VPORT_ID_INVALID 0
3393 typedef struct efx_vport_config_s {
3394 /* Either VF index or 0xffff for PF */
3395 uint16_t evc_function;
3396 /* VLAN ID of the associated function */
3398 /* vport id shared with client driver */
3399 efx_vport_id_t evc_vport_id;
3400 /* MAC address of the associated function */
3401 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3403 * vports created with this flag set may only transfer traffic on the
3404 * VLANs permitted by the vport. Also, an attempt to install filter with
3405 * VLAN will be refused unless requesting function has VLAN privilege.
3407 boolean_t evc_vlan_restrict;
3408 /* Whether this function is assigned or not */
3409 boolean_t evc_vport_assigned;
3410 } efx_vport_config_t;
3412 typedef struct efx_vswitch_s efx_vswitch_t;
3414 extern __checkReturn efx_rc_t
3416 __in efx_nic_t *enp);
3420 __in efx_nic_t *enp);
3422 extern __checkReturn efx_rc_t
3423 efx_evb_vswitch_create(
3424 __in efx_nic_t *enp,
3425 __in uint32_t num_vports,
3426 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3427 __deref_out efx_vswitch_t **evpp);
3429 extern __checkReturn efx_rc_t
3430 efx_evb_vswitch_destroy(
3431 __in efx_nic_t *enp,
3432 __in efx_vswitch_t *evp);
3434 extern __checkReturn efx_rc_t
3435 efx_evb_vport_mac_set(
3436 __in efx_nic_t *enp,
3437 __in efx_vswitch_t *evp,
3438 __in efx_vport_id_t vport_id,
3439 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3441 extern __checkReturn efx_rc_t
3442 efx_evb_vport_vlan_set(
3443 __in efx_nic_t *enp,
3444 __in efx_vswitch_t *evp,
3445 __in efx_vport_id_t vport_id,
3448 extern __checkReturn efx_rc_t
3449 efx_evb_vport_reset(
3450 __in efx_nic_t *enp,
3451 __in efx_vswitch_t *evp,
3452 __in efx_vport_id_t vport_id,
3453 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3455 __out boolean_t *is_fn_resetp);
3457 extern __checkReturn efx_rc_t
3458 efx_evb_vport_stats(
3459 __in efx_nic_t *enp,
3460 __in efx_vswitch_t *evp,
3461 __in efx_vport_id_t vport_id,
3462 __out efsys_mem_t *stats_bufferp);
3464 #endif /* EFSYS_OPT_EVB */
3466 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3468 typedef struct efx_proxy_auth_config_s {
3469 efsys_mem_t *request_bufferp;
3470 efsys_mem_t *response_bufferp;
3471 efsys_mem_t *status_bufferp;
3475 uint32_t handled_privileges;
3476 } efx_proxy_auth_config_t;
3478 typedef struct efx_proxy_cmd_params_s {
3481 uint8_t *request_bufferp;
3482 size_t request_size;
3483 uint8_t *response_bufferp;
3484 size_t response_size;
3485 size_t *response_size_actualp;
3486 } efx_proxy_cmd_params_t;
3488 extern __checkReturn efx_rc_t
3489 efx_proxy_auth_init(
3490 __in efx_nic_t *enp);
3493 efx_proxy_auth_fini(
3494 __in efx_nic_t *enp);
3496 extern __checkReturn efx_rc_t
3497 efx_proxy_auth_configure(
3498 __in efx_nic_t *enp,
3499 __in efx_proxy_auth_config_t *configp);
3501 __checkReturn efx_rc_t
3502 efx_proxy_auth_destroy(
3503 __in efx_nic_t *enp,
3504 __in uint32_t handled_privileges);
3506 __checkReturn efx_rc_t
3507 efx_proxy_auth_complete_request(
3508 __in efx_nic_t *enp,
3509 __in uint32_t fn_index,
3510 __in uint32_t proxy_result,
3511 __in uint32_t handle);
3513 __checkReturn efx_rc_t
3514 efx_proxy_auth_exec_cmd(
3515 __in efx_nic_t *enp,
3516 __inout efx_proxy_cmd_params_t *paramsp);
3518 __checkReturn efx_rc_t
3519 efx_proxy_auth_set_privilege_mask(
3520 __in efx_nic_t *enp,
3521 __in uint32_t vf_index,
3523 __in uint32_t value);
3525 __checkReturn efx_rc_t
3526 efx_proxy_auth_privilege_mask_get(
3527 __in efx_nic_t *enp,
3528 __in uint32_t pf_index,
3529 __in uint32_t vf_index,
3530 __out uint32_t *maskp);
3532 __checkReturn efx_rc_t
3533 efx_proxy_auth_privilege_modify(
3534 __in efx_nic_t *enp,
3535 __in uint32_t pf_index,
3536 __in uint32_t vf_index,
3537 __in uint32_t add_privileges_mask,
3538 __in uint32_t remove_privileges_mask);
3540 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
3546 #endif /* _SYS_EFX_H */