1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
133 typedef enum efx_fw_variant_e {
134 EFX_FW_VARIANT_FULL_FEATURED,
135 EFX_FW_VARIANT_LOW_LATENCY,
136 EFX_FW_VARIANT_PACKED_STREAM,
137 EFX_FW_VARIANT_HIGH_TX_RATE,
138 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
139 EFX_FW_VARIANT_RULES_ENGINE,
141 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
144 extern __checkReturn efx_rc_t
147 __in efx_fw_variant_t efv);
149 extern __checkReturn efx_rc_t
151 __in efx_nic_t *enp);
153 extern __checkReturn efx_rc_t
155 __in efx_nic_t *enp);
159 extern __checkReturn efx_rc_t
160 efx_nic_register_test(
161 __in efx_nic_t *enp);
163 #endif /* EFSYS_OPT_DIAG */
167 __in efx_nic_t *enp);
171 __in efx_nic_t *enp);
175 __in efx_nic_t *enp);
177 #define EFX_PCIE_LINK_SPEED_GEN1 1
178 #define EFX_PCIE_LINK_SPEED_GEN2 2
179 #define EFX_PCIE_LINK_SPEED_GEN3 3
181 typedef enum efx_pcie_link_performance_e {
182 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
183 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
184 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
185 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
186 } efx_pcie_link_performance_t;
188 extern __checkReturn efx_rc_t
189 efx_nic_calculate_pcie_link_bandwidth(
190 __in uint32_t pcie_link_width,
191 __in uint32_t pcie_link_gen,
192 __out uint32_t *bandwidth_mbpsp);
194 extern __checkReturn efx_rc_t
195 efx_nic_check_pcie_link_speed(
197 __in uint32_t pcie_link_width,
198 __in uint32_t pcie_link_gen,
199 __out efx_pcie_link_performance_t *resultp);
203 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
204 /* Huntington and Medford require MCDIv2 commands */
205 #define WITH_MCDI_V2 1
208 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
210 typedef enum efx_mcdi_exception_e {
211 EFX_MCDI_EXCEPTION_MC_REBOOT,
212 EFX_MCDI_EXCEPTION_MC_BADASSERT,
213 } efx_mcdi_exception_t;
215 #if EFSYS_OPT_MCDI_LOGGING
216 typedef enum efx_log_msg_e {
218 EFX_LOG_MCDI_REQUEST,
219 EFX_LOG_MCDI_RESPONSE,
221 #endif /* EFSYS_OPT_MCDI_LOGGING */
223 typedef struct efx_mcdi_transport_s {
225 efsys_mem_t *emt_dma_mem;
226 void (*emt_execute)(void *, efx_mcdi_req_t *);
227 void (*emt_ev_cpl)(void *);
228 void (*emt_exception)(void *, efx_mcdi_exception_t);
229 #if EFSYS_OPT_MCDI_LOGGING
230 void (*emt_logger)(void *, efx_log_msg_t,
231 void *, size_t, void *, size_t);
232 #endif /* EFSYS_OPT_MCDI_LOGGING */
233 #if EFSYS_OPT_MCDI_PROXY_AUTH
234 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
235 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
236 } efx_mcdi_transport_t;
238 extern __checkReturn efx_rc_t
241 __in const efx_mcdi_transport_t *mtp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
249 __in efx_nic_t *enp);
252 efx_mcdi_get_timeout(
254 __in efx_mcdi_req_t *emrp,
255 __out uint32_t *usec_timeoutp);
258 efx_mcdi_request_start(
260 __in efx_mcdi_req_t *emrp,
261 __in boolean_t ev_cpl);
263 extern __checkReturn boolean_t
264 efx_mcdi_request_poll(
265 __in efx_nic_t *enp);
267 extern __checkReturn boolean_t
268 efx_mcdi_request_abort(
269 __in efx_nic_t *enp);
273 __in efx_nic_t *enp);
275 #endif /* EFSYS_OPT_MCDI */
279 #define EFX_NINTR_SIENA 1024
281 typedef enum efx_intr_type_e {
282 EFX_INTR_INVALID = 0,
288 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
290 extern __checkReturn efx_rc_t
293 __in efx_intr_type_t type,
294 __in efsys_mem_t *esmp);
298 __in efx_nic_t *enp);
302 __in efx_nic_t *enp);
305 efx_intr_disable_unlocked(
306 __in efx_nic_t *enp);
308 #define EFX_INTR_NEVQS 32
310 extern __checkReturn efx_rc_t
313 __in unsigned int level);
316 efx_intr_status_line(
318 __out boolean_t *fatalp,
319 __out uint32_t *maskp);
322 efx_intr_status_message(
324 __in unsigned int message,
325 __out boolean_t *fatalp);
329 __in efx_nic_t *enp);
333 __in efx_nic_t *enp);
337 #if EFSYS_OPT_MAC_STATS
339 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
340 typedef enum efx_mac_stat_e {
343 EFX_MAC_RX_UNICST_PKTS,
344 EFX_MAC_RX_MULTICST_PKTS,
345 EFX_MAC_RX_BRDCST_PKTS,
346 EFX_MAC_RX_PAUSE_PKTS,
347 EFX_MAC_RX_LE_64_PKTS,
348 EFX_MAC_RX_65_TO_127_PKTS,
349 EFX_MAC_RX_128_TO_255_PKTS,
350 EFX_MAC_RX_256_TO_511_PKTS,
351 EFX_MAC_RX_512_TO_1023_PKTS,
352 EFX_MAC_RX_1024_TO_15XX_PKTS,
353 EFX_MAC_RX_GE_15XX_PKTS,
355 EFX_MAC_RX_FCS_ERRORS,
356 EFX_MAC_RX_DROP_EVENTS,
357 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
358 EFX_MAC_RX_SYMBOL_ERRORS,
359 EFX_MAC_RX_ALIGN_ERRORS,
360 EFX_MAC_RX_INTERNAL_ERRORS,
361 EFX_MAC_RX_JABBER_PKTS,
362 EFX_MAC_RX_LANE0_CHAR_ERR,
363 EFX_MAC_RX_LANE1_CHAR_ERR,
364 EFX_MAC_RX_LANE2_CHAR_ERR,
365 EFX_MAC_RX_LANE3_CHAR_ERR,
366 EFX_MAC_RX_LANE0_DISP_ERR,
367 EFX_MAC_RX_LANE1_DISP_ERR,
368 EFX_MAC_RX_LANE2_DISP_ERR,
369 EFX_MAC_RX_LANE3_DISP_ERR,
370 EFX_MAC_RX_MATCH_FAULT,
371 EFX_MAC_RX_NODESC_DROP_CNT,
374 EFX_MAC_TX_UNICST_PKTS,
375 EFX_MAC_TX_MULTICST_PKTS,
376 EFX_MAC_TX_BRDCST_PKTS,
377 EFX_MAC_TX_PAUSE_PKTS,
378 EFX_MAC_TX_LE_64_PKTS,
379 EFX_MAC_TX_65_TO_127_PKTS,
380 EFX_MAC_TX_128_TO_255_PKTS,
381 EFX_MAC_TX_256_TO_511_PKTS,
382 EFX_MAC_TX_512_TO_1023_PKTS,
383 EFX_MAC_TX_1024_TO_15XX_PKTS,
384 EFX_MAC_TX_GE_15XX_PKTS,
386 EFX_MAC_TX_SGL_COL_PKTS,
387 EFX_MAC_TX_MULT_COL_PKTS,
388 EFX_MAC_TX_EX_COL_PKTS,
389 EFX_MAC_TX_LATE_COL_PKTS,
391 EFX_MAC_TX_EX_DEF_PKTS,
392 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
393 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
394 EFX_MAC_PM_TRUNC_VFIFO_FULL,
395 EFX_MAC_PM_DISCARD_VFIFO_FULL,
396 EFX_MAC_PM_TRUNC_QBB,
397 EFX_MAC_PM_DISCARD_QBB,
398 EFX_MAC_PM_DISCARD_MAPPING,
399 EFX_MAC_RXDP_Q_DISABLED_PKTS,
400 EFX_MAC_RXDP_DI_DROPPED_PKTS,
401 EFX_MAC_RXDP_STREAMING_PKTS,
402 EFX_MAC_RXDP_HLB_FETCH,
403 EFX_MAC_RXDP_HLB_WAIT,
404 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
405 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
406 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
407 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
408 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
409 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
410 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
411 EFX_MAC_VADAPTER_RX_BAD_BYTES,
412 EFX_MAC_VADAPTER_RX_OVERFLOW,
413 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
414 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
415 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
416 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
417 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
418 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
419 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
420 EFX_MAC_VADAPTER_TX_BAD_BYTES,
421 EFX_MAC_VADAPTER_TX_OVERFLOW,
422 EFX_MAC_FEC_UNCORRECTED_ERRORS,
423 EFX_MAC_FEC_CORRECTED_ERRORS,
424 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
425 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
426 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
427 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
428 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
429 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
430 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
431 EFX_MAC_CTPIO_OVERFLOW_FAIL,
432 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
433 EFX_MAC_CTPIO_TIMEOUT_FAIL,
434 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
435 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
436 EFX_MAC_CTPIO_INVALID_WR_FAIL,
437 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
438 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
439 EFX_MAC_CTPIO_RUNT_FALLBACK,
440 EFX_MAC_CTPIO_SUCCESS,
441 EFX_MAC_CTPIO_FALLBACK,
442 EFX_MAC_CTPIO_POISON,
444 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
445 EFX_MAC_RXDP_HLB_IDLE,
446 EFX_MAC_RXDP_HLB_TIMEOUT,
450 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
452 #endif /* EFSYS_OPT_MAC_STATS */
454 typedef enum efx_link_mode_e {
455 EFX_LINK_UNKNOWN = 0,
471 #define EFX_MAC_ADDR_LEN 6
473 #define EFX_VNI_OR_VSID_LEN 3
475 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
477 #define EFX_MAC_MULTICAST_LIST_MAX 256
479 #define EFX_MAC_SDU_MAX 9202
481 #define EFX_MAC_PDU_ADJUSTMENT \
485 + /* bug16011 */ 16) \
487 #define EFX_MAC_PDU(_sdu) \
488 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
491 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
492 * the SDU rounded up slightly.
494 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
496 #define EFX_MAC_PDU_MIN 60
497 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
499 extern __checkReturn efx_rc_t
504 extern __checkReturn efx_rc_t
509 extern __checkReturn efx_rc_t
514 extern __checkReturn efx_rc_t
517 __in boolean_t all_unicst,
518 __in boolean_t mulcst,
519 __in boolean_t all_mulcst,
520 __in boolean_t brdcst);
522 extern __checkReturn efx_rc_t
523 efx_mac_multicast_list_set(
525 __in_ecount(6*count) uint8_t const *addrs,
528 extern __checkReturn efx_rc_t
529 efx_mac_filter_default_rxq_set(
532 __in boolean_t using_rss);
535 efx_mac_filter_default_rxq_clear(
536 __in efx_nic_t *enp);
538 extern __checkReturn efx_rc_t
541 __in boolean_t enabled);
543 extern __checkReturn efx_rc_t
546 __out boolean_t *mac_upp);
548 #define EFX_FCNTL_RESPOND 0x00000001
549 #define EFX_FCNTL_GENERATE 0x00000002
551 extern __checkReturn efx_rc_t
554 __in unsigned int fcntl,
555 __in boolean_t autoneg);
560 __out unsigned int *fcntl_wantedp,
561 __out unsigned int *fcntl_linkp);
564 #if EFSYS_OPT_MAC_STATS
568 extern __checkReturn const char *
571 __in unsigned int id);
573 #endif /* EFSYS_OPT_NAMES */
575 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
577 #define EFX_MAC_STATS_MASK_NPAGES \
578 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
579 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
582 * Get mask of MAC statistics supported by the hardware.
584 * If mask_size is insufficient to return the mask, EINVAL error is
585 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
586 * (which is sizeof (uint32_t)) is sufficient.
588 extern __checkReturn efx_rc_t
589 efx_mac_stats_get_mask(
591 __out_bcount(mask_size) uint32_t *maskp,
592 __in size_t mask_size);
594 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
595 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
596 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
599 extern __checkReturn efx_rc_t
601 __in efx_nic_t *enp);
604 * Upload mac statistics supported by the hardware into the given buffer.
606 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
607 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
609 * The hardware will only DMA statistics that it understands (of course).
610 * Drivers should not make any assumptions about which statistics are
611 * supported, especially when the statistics are generated by firmware.
613 * Thus, drivers should zero this buffer before use, so that not-understood
614 * statistics read back as zero.
616 extern __checkReturn efx_rc_t
617 efx_mac_stats_upload(
619 __in efsys_mem_t *esmp);
621 extern __checkReturn efx_rc_t
622 efx_mac_stats_periodic(
624 __in efsys_mem_t *esmp,
625 __in uint16_t period_ms,
626 __in boolean_t events);
628 extern __checkReturn efx_rc_t
629 efx_mac_stats_update(
631 __in efsys_mem_t *esmp,
632 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
633 __inout_opt uint32_t *generationp);
635 #endif /* EFSYS_OPT_MAC_STATS */
639 typedef enum efx_mon_type_e {
651 __in efx_nic_t *enp);
653 #endif /* EFSYS_OPT_NAMES */
655 extern __checkReturn efx_rc_t
657 __in efx_nic_t *enp);
659 #if EFSYS_OPT_MON_STATS
661 #define EFX_MON_STATS_PAGE_SIZE 0x100
662 #define EFX_MON_MASK_ELEMENT_SIZE 32
664 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
665 typedef enum efx_mon_stat_e {
672 EFX_MON_STAT_EXT_TEMP,
673 EFX_MON_STAT_INT_TEMP,
676 EFX_MON_STAT_INT_COOLING,
677 EFX_MON_STAT_EXT_COOLING,
685 EFX_MON_STAT_AOE_TEMP,
686 EFX_MON_STAT_PSU_AOE_TEMP,
687 EFX_MON_STAT_PSU_TEMP,
693 EFX_MON_STAT_VAOE_IN,
695 EFX_MON_STAT_IAOE_IN,
696 EFX_MON_STAT_NIC_POWER,
700 EFX_MON_STAT_0_9V_ADC,
701 EFX_MON_STAT_INT_TEMP2,
702 EFX_MON_STAT_VREG_TEMP,
703 EFX_MON_STAT_VREG_0_9V_TEMP,
704 EFX_MON_STAT_VREG_1_2V_TEMP,
705 EFX_MON_STAT_INT_VPTAT,
706 EFX_MON_STAT_INT_ADC_TEMP,
707 EFX_MON_STAT_EXT_VPTAT,
708 EFX_MON_STAT_EXT_ADC_TEMP,
709 EFX_MON_STAT_AMBIENT_TEMP,
710 EFX_MON_STAT_AIRFLOW,
711 EFX_MON_STAT_VDD08D_VSS08D_CSR,
712 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
713 EFX_MON_STAT_HOTPOINT_TEMP,
714 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
715 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
716 EFX_MON_STAT_MUM_VCC,
719 EFX_MON_STAT_0V9_A_TEMP,
722 EFX_MON_STAT_0V9_B_TEMP,
723 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
724 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
725 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
726 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
727 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
728 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
729 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
730 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
731 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
732 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
733 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
734 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
735 EFX_MON_STAT_SODIMM_VOUT,
736 EFX_MON_STAT_SODIMM_0_TEMP,
737 EFX_MON_STAT_SODIMM_1_TEMP,
738 EFX_MON_STAT_PHY0_VCC,
739 EFX_MON_STAT_PHY1_VCC,
740 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
741 EFX_MON_STAT_BOARD_FRONT_TEMP,
742 EFX_MON_STAT_BOARD_BACK_TEMP,
752 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
754 typedef enum efx_mon_stat_state_e {
755 EFX_MON_STAT_STATE_OK = 0,
756 EFX_MON_STAT_STATE_WARNING = 1,
757 EFX_MON_STAT_STATE_FATAL = 2,
758 EFX_MON_STAT_STATE_BROKEN = 3,
759 EFX_MON_STAT_STATE_NO_READING = 4,
760 } efx_mon_stat_state_t;
762 typedef struct efx_mon_stat_value_s {
765 } efx_mon_stat_value_t;
772 __in efx_mon_stat_t id);
774 #endif /* EFSYS_OPT_NAMES */
776 extern __checkReturn efx_rc_t
777 efx_mon_stats_update(
779 __in efsys_mem_t *esmp,
780 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
782 #endif /* EFSYS_OPT_MON_STATS */
786 __in efx_nic_t *enp);
790 extern __checkReturn efx_rc_t
792 __in efx_nic_t *enp);
794 #if EFSYS_OPT_PHY_LED_CONTROL
796 typedef enum efx_phy_led_mode_e {
797 EFX_PHY_LED_DEFAULT = 0,
802 } efx_phy_led_mode_t;
804 extern __checkReturn efx_rc_t
807 __in efx_phy_led_mode_t mode);
809 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
811 extern __checkReturn efx_rc_t
813 __in efx_nic_t *enp);
815 #if EFSYS_OPT_LOOPBACK
817 typedef enum efx_loopback_type_e {
818 EFX_LOOPBACK_OFF = 0,
819 EFX_LOOPBACK_DATA = 1,
820 EFX_LOOPBACK_GMAC = 2,
821 EFX_LOOPBACK_XGMII = 3,
822 EFX_LOOPBACK_XGXS = 4,
823 EFX_LOOPBACK_XAUI = 5,
824 EFX_LOOPBACK_GMII = 6,
825 EFX_LOOPBACK_SGMII = 7,
826 EFX_LOOPBACK_XGBR = 8,
827 EFX_LOOPBACK_XFI = 9,
828 EFX_LOOPBACK_XAUI_FAR = 10,
829 EFX_LOOPBACK_GMII_FAR = 11,
830 EFX_LOOPBACK_SGMII_FAR = 12,
831 EFX_LOOPBACK_XFI_FAR = 13,
832 EFX_LOOPBACK_GPHY = 14,
833 EFX_LOOPBACK_PHY_XS = 15,
834 EFX_LOOPBACK_PCS = 16,
835 EFX_LOOPBACK_PMA_PMD = 17,
836 EFX_LOOPBACK_XPORT = 18,
837 EFX_LOOPBACK_XGMII_WS = 19,
838 EFX_LOOPBACK_XAUI_WS = 20,
839 EFX_LOOPBACK_XAUI_WS_FAR = 21,
840 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
841 EFX_LOOPBACK_GMII_WS = 23,
842 EFX_LOOPBACK_XFI_WS = 24,
843 EFX_LOOPBACK_XFI_WS_FAR = 25,
844 EFX_LOOPBACK_PHYXS_WS = 26,
845 EFX_LOOPBACK_PMA_INT = 27,
846 EFX_LOOPBACK_SD_NEAR = 28,
847 EFX_LOOPBACK_SD_FAR = 29,
848 EFX_LOOPBACK_PMA_INT_WS = 30,
849 EFX_LOOPBACK_SD_FEP2_WS = 31,
850 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
851 EFX_LOOPBACK_SD_FEP_WS = 33,
852 EFX_LOOPBACK_SD_FES_WS = 34,
853 EFX_LOOPBACK_AOE_INT_NEAR = 35,
854 EFX_LOOPBACK_DATA_WS = 36,
855 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
857 } efx_loopback_type_t;
859 typedef enum efx_loopback_kind_e {
860 EFX_LOOPBACK_KIND_OFF = 0,
861 EFX_LOOPBACK_KIND_ALL,
862 EFX_LOOPBACK_KIND_MAC,
863 EFX_LOOPBACK_KIND_PHY,
865 } efx_loopback_kind_t;
869 __in efx_loopback_kind_t loopback_kind,
870 __out efx_qword_t *maskp);
872 extern __checkReturn efx_rc_t
873 efx_port_loopback_set(
875 __in efx_link_mode_t link_mode,
876 __in efx_loopback_type_t type);
880 extern __checkReturn const char *
881 efx_loopback_type_name(
883 __in efx_loopback_type_t type);
885 #endif /* EFSYS_OPT_NAMES */
887 #endif /* EFSYS_OPT_LOOPBACK */
889 extern __checkReturn efx_rc_t
892 __out_opt efx_link_mode_t *link_modep);
896 __in efx_nic_t *enp);
898 typedef enum efx_phy_cap_type_e {
899 EFX_PHY_CAP_INVALID = 0,
906 EFX_PHY_CAP_10000FDX,
910 EFX_PHY_CAP_40000FDX,
912 EFX_PHY_CAP_100000FDX,
913 EFX_PHY_CAP_25000FDX,
914 EFX_PHY_CAP_50000FDX,
915 EFX_PHY_CAP_BASER_FEC,
916 EFX_PHY_CAP_BASER_FEC_REQUESTED,
918 EFX_PHY_CAP_RS_FEC_REQUESTED,
919 EFX_PHY_CAP_25G_BASER_FEC,
920 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
922 } efx_phy_cap_type_t;
925 #define EFX_PHY_CAP_CURRENT 0x00000000
926 #define EFX_PHY_CAP_DEFAULT 0x00000001
927 #define EFX_PHY_CAP_PERM 0x00000002
933 __out uint32_t *maskp);
935 extern __checkReturn efx_rc_t
943 __out uint32_t *maskp);
945 extern __checkReturn efx_rc_t
948 __out uint32_t *ouip);
950 typedef enum efx_phy_media_type_e {
951 EFX_PHY_MEDIA_INVALID = 0,
956 EFX_PHY_MEDIA_SFP_PLUS,
957 EFX_PHY_MEDIA_BASE_T,
958 EFX_PHY_MEDIA_QSFP_PLUS,
960 } efx_phy_media_type_t;
963 * Get the type of medium currently used. If the board has ports for
964 * modules, a module is present, and we recognise the media type of
965 * the module, then this will be the media type of the module.
966 * Otherwise it will be the media type of the port.
969 efx_phy_media_type_get(
971 __out efx_phy_media_type_t *typep);
973 extern __checkReturn efx_rc_t
974 efx_phy_module_get_info(
976 __in uint8_t dev_addr,
979 __out_bcount(len) uint8_t *data);
981 #if EFSYS_OPT_PHY_STATS
983 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
984 typedef enum efx_phy_stat_e {
986 EFX_PHY_STAT_PMA_PMD_LINK_UP,
987 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
988 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
989 EFX_PHY_STAT_PMA_PMD_REV_A,
990 EFX_PHY_STAT_PMA_PMD_REV_B,
991 EFX_PHY_STAT_PMA_PMD_REV_C,
992 EFX_PHY_STAT_PMA_PMD_REV_D,
993 EFX_PHY_STAT_PCS_LINK_UP,
994 EFX_PHY_STAT_PCS_RX_FAULT,
995 EFX_PHY_STAT_PCS_TX_FAULT,
996 EFX_PHY_STAT_PCS_BER,
997 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
998 EFX_PHY_STAT_PHY_XS_LINK_UP,
999 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1000 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1001 EFX_PHY_STAT_PHY_XS_ALIGN,
1002 EFX_PHY_STAT_PHY_XS_SYNC_A,
1003 EFX_PHY_STAT_PHY_XS_SYNC_B,
1004 EFX_PHY_STAT_PHY_XS_SYNC_C,
1005 EFX_PHY_STAT_PHY_XS_SYNC_D,
1006 EFX_PHY_STAT_AN_LINK_UP,
1007 EFX_PHY_STAT_AN_MASTER,
1008 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1009 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1010 EFX_PHY_STAT_CL22EXT_LINK_UP,
1015 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1016 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1017 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1018 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1019 EFX_PHY_STAT_AN_COMPLETE,
1020 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1021 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1022 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1023 EFX_PHY_STAT_PCS_FW_VERSION_0,
1024 EFX_PHY_STAT_PCS_FW_VERSION_1,
1025 EFX_PHY_STAT_PCS_FW_VERSION_2,
1026 EFX_PHY_STAT_PCS_FW_VERSION_3,
1027 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1028 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1029 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1030 EFX_PHY_STAT_PCS_OP_MODE,
1034 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1040 __in efx_nic_t *enp,
1041 __in efx_phy_stat_t stat);
1043 #endif /* EFSYS_OPT_NAMES */
1045 #define EFX_PHY_STATS_SIZE 0x100
1047 extern __checkReturn efx_rc_t
1048 efx_phy_stats_update(
1049 __in efx_nic_t *enp,
1050 __in efsys_mem_t *esmp,
1051 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1053 #endif /* EFSYS_OPT_PHY_STATS */
1058 typedef enum efx_bist_type_e {
1059 EFX_BIST_TYPE_UNKNOWN,
1060 EFX_BIST_TYPE_PHY_NORMAL,
1061 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1062 EFX_BIST_TYPE_PHY_CABLE_LONG,
1063 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1064 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1065 EFX_BIST_TYPE_REG, /* Test the register memories */
1066 EFX_BIST_TYPE_NTYPES,
1069 typedef enum efx_bist_result_e {
1070 EFX_BIST_RESULT_UNKNOWN,
1071 EFX_BIST_RESULT_RUNNING,
1072 EFX_BIST_RESULT_PASSED,
1073 EFX_BIST_RESULT_FAILED,
1074 } efx_bist_result_t;
1076 typedef enum efx_phy_cable_status_e {
1077 EFX_PHY_CABLE_STATUS_OK,
1078 EFX_PHY_CABLE_STATUS_INVALID,
1079 EFX_PHY_CABLE_STATUS_OPEN,
1080 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1081 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1082 EFX_PHY_CABLE_STATUS_BUSY,
1083 } efx_phy_cable_status_t;
1085 typedef enum efx_bist_value_e {
1086 EFX_BIST_PHY_CABLE_LENGTH_A,
1087 EFX_BIST_PHY_CABLE_LENGTH_B,
1088 EFX_BIST_PHY_CABLE_LENGTH_C,
1089 EFX_BIST_PHY_CABLE_LENGTH_D,
1090 EFX_BIST_PHY_CABLE_STATUS_A,
1091 EFX_BIST_PHY_CABLE_STATUS_B,
1092 EFX_BIST_PHY_CABLE_STATUS_C,
1093 EFX_BIST_PHY_CABLE_STATUS_D,
1094 EFX_BIST_FAULT_CODE,
1096 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1102 EFX_BIST_MEM_EXPECT,
1103 EFX_BIST_MEM_ACTUAL,
1105 EFX_BIST_MEM_ECC_PARITY,
1106 EFX_BIST_MEM_ECC_FATAL,
1110 extern __checkReturn efx_rc_t
1111 efx_bist_enable_offline(
1112 __in efx_nic_t *enp);
1114 extern __checkReturn efx_rc_t
1116 __in efx_nic_t *enp,
1117 __in efx_bist_type_t type);
1119 extern __checkReturn efx_rc_t
1121 __in efx_nic_t *enp,
1122 __in efx_bist_type_t type,
1123 __out efx_bist_result_t *resultp,
1124 __out_opt uint32_t *value_maskp,
1125 __out_ecount_opt(count) unsigned long *valuesp,
1130 __in efx_nic_t *enp,
1131 __in efx_bist_type_t type);
1133 #endif /* EFSYS_OPT_BIST */
1135 #define EFX_FEATURE_IPV6 0x00000001
1136 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1137 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1138 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1139 #define EFX_FEATURE_MCDI 0x00000020
1140 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1141 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1142 #define EFX_FEATURE_TURBO 0x00000100
1143 #define EFX_FEATURE_MCDI_DMA 0x00000200
1144 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1145 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1146 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1147 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1148 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1150 typedef enum efx_tunnel_protocol_e {
1151 EFX_TUNNEL_PROTOCOL_NONE = 0,
1152 EFX_TUNNEL_PROTOCOL_VXLAN,
1153 EFX_TUNNEL_PROTOCOL_GENEVE,
1154 EFX_TUNNEL_PROTOCOL_NVGRE,
1156 } efx_tunnel_protocol_t;
1158 typedef enum efx_vi_window_shift_e {
1159 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1160 EFX_VI_WINDOW_SHIFT_8K = 13,
1161 EFX_VI_WINDOW_SHIFT_16K = 14,
1162 EFX_VI_WINDOW_SHIFT_64K = 16,
1163 } efx_vi_window_shift_t;
1165 typedef struct efx_nic_cfg_s {
1166 uint32_t enc_board_type;
1167 uint32_t enc_phy_type;
1169 char enc_phy_name[21];
1171 char enc_phy_revision[21];
1172 efx_mon_type_t enc_mon_type;
1173 #if EFSYS_OPT_MON_STATS
1174 uint32_t enc_mon_stat_dma_buf_size;
1175 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1177 unsigned int enc_features;
1178 efx_vi_window_shift_t enc_vi_window_shift;
1179 uint8_t enc_mac_addr[6];
1180 uint8_t enc_port; /* PHY port number */
1181 uint32_t enc_intr_vec_base;
1182 uint32_t enc_intr_limit;
1183 uint32_t enc_evq_limit;
1184 uint32_t enc_txq_limit;
1185 uint32_t enc_rxq_limit;
1186 uint32_t enc_txq_max_ndescs;
1187 uint32_t enc_buftbl_limit;
1188 uint32_t enc_piobuf_limit;
1189 uint32_t enc_piobuf_size;
1190 uint32_t enc_piobuf_min_alloc_size;
1191 uint32_t enc_evq_timer_quantum_ns;
1192 uint32_t enc_evq_timer_max_us;
1193 uint32_t enc_clk_mult;
1194 uint32_t enc_rx_prefix_size;
1195 uint32_t enc_rx_buf_align_start;
1196 uint32_t enc_rx_buf_align_end;
1197 uint32_t enc_rx_scale_max_exclusive_contexts;
1199 * Mask of supported hash algorithms.
1200 * Hash algorithm types are used as the bit indices.
1202 uint32_t enc_rx_scale_hash_alg_mask;
1204 * Indicates whether port numbers can be included to the
1205 * input data for hash computation.
1207 boolean_t enc_rx_scale_l4_hash_supported;
1208 boolean_t enc_rx_scale_additional_modes_supported;
1209 #if EFSYS_OPT_LOOPBACK
1210 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1211 #endif /* EFSYS_OPT_LOOPBACK */
1212 #if EFSYS_OPT_PHY_FLAGS
1213 uint32_t enc_phy_flags_mask;
1214 #endif /* EFSYS_OPT_PHY_FLAGS */
1215 #if EFSYS_OPT_PHY_LED_CONTROL
1216 uint32_t enc_led_mask;
1217 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1218 #if EFSYS_OPT_PHY_STATS
1219 uint64_t enc_phy_stat_mask;
1220 #endif /* EFSYS_OPT_PHY_STATS */
1222 uint8_t enc_mcdi_mdio_channel;
1223 #if EFSYS_OPT_PHY_STATS
1224 uint32_t enc_mcdi_phy_stat_mask;
1225 #endif /* EFSYS_OPT_PHY_STATS */
1226 #if EFSYS_OPT_MON_STATS
1227 uint32_t *enc_mcdi_sensor_maskp;
1228 uint32_t enc_mcdi_sensor_mask_size;
1229 #endif /* EFSYS_OPT_MON_STATS */
1230 #endif /* EFSYS_OPT_MCDI */
1232 uint32_t enc_bist_mask;
1233 #endif /* EFSYS_OPT_BIST */
1234 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1237 uint32_t enc_privilege_mask;
1238 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1239 boolean_t enc_bug26807_workaround;
1240 boolean_t enc_bug35388_workaround;
1241 boolean_t enc_bug41750_workaround;
1242 boolean_t enc_bug61265_workaround;
1243 boolean_t enc_rx_batching_enabled;
1244 /* Maximum number of descriptors completed in an rx event. */
1245 uint32_t enc_rx_batch_max;
1246 /* Number of rx descriptors the hardware requires for a push. */
1247 uint32_t enc_rx_push_align;
1248 /* Maximum amount of data in DMA descriptor */
1249 uint32_t enc_tx_dma_desc_size_max;
1251 * Boundary which DMA descriptor data must not cross or 0 if no
1254 uint32_t enc_tx_dma_desc_boundary;
1256 * Maximum number of bytes into the packet the TCP header can start for
1257 * the hardware to apply TSO packet edits.
1259 uint32_t enc_tx_tso_tcp_header_offset_limit;
1260 boolean_t enc_fw_assisted_tso_enabled;
1261 boolean_t enc_fw_assisted_tso_v2_enabled;
1262 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1263 /* Number of TSO contexts on the NIC (FATSOv2) */
1264 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1265 boolean_t enc_hw_tx_insert_vlan_enabled;
1266 /* Number of PFs on the NIC */
1267 uint32_t enc_hw_pf_count;
1268 /* Datapath firmware vadapter/vport/vswitch support */
1269 boolean_t enc_datapath_cap_evb;
1270 boolean_t enc_rx_disable_scatter_supported;
1271 boolean_t enc_allow_set_mac_with_installed_filters;
1272 boolean_t enc_enhanced_set_mac_supported;
1273 boolean_t enc_init_evq_v2_supported;
1274 boolean_t enc_rx_packed_stream_supported;
1275 boolean_t enc_rx_var_packed_stream_supported;
1276 boolean_t enc_rx_es_super_buffer_supported;
1277 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1278 boolean_t enc_pm_and_rxdp_counters;
1279 boolean_t enc_mac_stats_40g_tx_size_bins;
1280 uint32_t enc_tunnel_encapsulations_supported;
1282 * NIC global maximum for unique UDP tunnel ports shared by all
1285 uint32_t enc_tunnel_config_udp_entries_max;
1286 /* External port identifier */
1287 uint8_t enc_external_port;
1288 uint32_t enc_mcdi_max_payload_length;
1289 /* VPD may be per-PF or global */
1290 boolean_t enc_vpd_is_global;
1291 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1292 uint32_t enc_required_pcie_bandwidth_mbps;
1293 uint32_t enc_max_pcie_link_gen;
1294 /* Firmware verifies integrity of NVRAM updates */
1295 uint32_t enc_nvram_update_verify_result_supported;
1296 /* Firmware support for extended MAC_STATS buffer */
1297 uint32_t enc_mac_stats_nstats;
1298 boolean_t enc_fec_counters;
1299 /* Firmware support for "FLAG" and "MARK" filter actions */
1300 boolean_t enc_filter_action_flag_supported;
1301 boolean_t enc_filter_action_mark_supported;
1302 uint32_t enc_filter_action_mark_max;
1305 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1306 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1308 #define EFX_PCI_FUNCTION(_encp) \
1309 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1311 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1313 extern const efx_nic_cfg_t *
1315 __in efx_nic_t *enp);
1317 /* RxDPCPU firmware id values by which FW variant can be identified */
1318 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1319 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1320 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1321 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1322 #define EFX_RXDP_DPDK_FW_ID 0x6
1324 typedef struct efx_nic_fw_info_s {
1325 /* Basic FW version information */
1326 uint16_t enfi_mc_fw_version[4];
1328 * If datapath capabilities can be detected,
1329 * additional FW information is to be shown
1331 boolean_t enfi_dpcpu_fw_ids_valid;
1332 /* Rx and Tx datapath CPU FW IDs */
1333 uint16_t enfi_rx_dpcpu_fw_id;
1334 uint16_t enfi_tx_dpcpu_fw_id;
1335 } efx_nic_fw_info_t;
1337 extern __checkReturn efx_rc_t
1338 efx_nic_get_fw_version(
1339 __in efx_nic_t *enp,
1340 __out efx_nic_fw_info_t *enfip);
1342 /* Driver resource limits (minimum required/maximum usable). */
1343 typedef struct efx_drv_limits_s {
1344 uint32_t edl_min_evq_count;
1345 uint32_t edl_max_evq_count;
1347 uint32_t edl_min_rxq_count;
1348 uint32_t edl_max_rxq_count;
1350 uint32_t edl_min_txq_count;
1351 uint32_t edl_max_txq_count;
1353 /* PIO blocks (sub-allocated from piobuf) */
1354 uint32_t edl_min_pio_alloc_size;
1355 uint32_t edl_max_pio_alloc_count;
1358 extern __checkReturn efx_rc_t
1359 efx_nic_set_drv_limits(
1360 __inout efx_nic_t *enp,
1361 __in efx_drv_limits_t *edlp);
1363 typedef enum efx_nic_region_e {
1364 EFX_REGION_VI, /* Memory BAR UC mapping */
1365 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1368 extern __checkReturn efx_rc_t
1369 efx_nic_get_bar_region(
1370 __in efx_nic_t *enp,
1371 __in efx_nic_region_t region,
1372 __out uint32_t *offsetp,
1373 __out size_t *sizep);
1375 extern __checkReturn efx_rc_t
1376 efx_nic_get_vi_pool(
1377 __in efx_nic_t *enp,
1378 __out uint32_t *evq_countp,
1379 __out uint32_t *rxq_countp,
1380 __out uint32_t *txq_countp);
1385 typedef enum efx_vpd_tag_e {
1392 typedef uint16_t efx_vpd_keyword_t;
1394 typedef struct efx_vpd_value_s {
1395 efx_vpd_tag_t evv_tag;
1396 efx_vpd_keyword_t evv_keyword;
1398 uint8_t evv_value[0x100];
1402 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1404 extern __checkReturn efx_rc_t
1406 __in efx_nic_t *enp);
1408 extern __checkReturn efx_rc_t
1410 __in efx_nic_t *enp,
1411 __out size_t *sizep);
1413 extern __checkReturn efx_rc_t
1415 __in efx_nic_t *enp,
1416 __out_bcount(size) caddr_t data,
1419 extern __checkReturn efx_rc_t
1421 __in efx_nic_t *enp,
1422 __in_bcount(size) caddr_t data,
1425 extern __checkReturn efx_rc_t
1427 __in efx_nic_t *enp,
1428 __in_bcount(size) caddr_t data,
1431 extern __checkReturn efx_rc_t
1433 __in efx_nic_t *enp,
1434 __in_bcount(size) caddr_t data,
1436 __inout efx_vpd_value_t *evvp);
1438 extern __checkReturn efx_rc_t
1440 __in efx_nic_t *enp,
1441 __inout_bcount(size) caddr_t data,
1443 __in efx_vpd_value_t *evvp);
1445 extern __checkReturn efx_rc_t
1447 __in efx_nic_t *enp,
1448 __inout_bcount(size) caddr_t data,
1450 __out efx_vpd_value_t *evvp,
1451 __inout unsigned int *contp);
1453 extern __checkReturn efx_rc_t
1455 __in efx_nic_t *enp,
1456 __in_bcount(size) caddr_t data,
1461 __in efx_nic_t *enp);
1463 #endif /* EFSYS_OPT_VPD */
1469 typedef enum efx_nvram_type_e {
1470 EFX_NVRAM_INVALID = 0,
1472 EFX_NVRAM_BOOTROM_CFG,
1473 EFX_NVRAM_MC_FIRMWARE,
1474 EFX_NVRAM_MC_GOLDEN,
1480 EFX_NVRAM_FPGA_BACKUP,
1481 EFX_NVRAM_DYNAMIC_CFG,
1484 EFX_NVRAM_MUM_FIRMWARE,
1488 extern __checkReturn efx_rc_t
1490 __in efx_nic_t *enp);
1494 extern __checkReturn efx_rc_t
1496 __in efx_nic_t *enp);
1498 #endif /* EFSYS_OPT_DIAG */
1500 extern __checkReturn efx_rc_t
1502 __in efx_nic_t *enp,
1503 __in efx_nvram_type_t type,
1504 __out size_t *sizep);
1506 extern __checkReturn efx_rc_t
1508 __in efx_nic_t *enp,
1509 __in efx_nvram_type_t type,
1510 __out_opt size_t *pref_chunkp);
1512 extern __checkReturn efx_rc_t
1513 efx_nvram_rw_finish(
1514 __in efx_nic_t *enp,
1515 __in efx_nvram_type_t type,
1516 __out_opt uint32_t *verify_resultp);
1518 extern __checkReturn efx_rc_t
1519 efx_nvram_get_version(
1520 __in efx_nic_t *enp,
1521 __in efx_nvram_type_t type,
1522 __out uint32_t *subtypep,
1523 __out_ecount(4) uint16_t version[4]);
1525 extern __checkReturn efx_rc_t
1526 efx_nvram_read_chunk(
1527 __in efx_nic_t *enp,
1528 __in efx_nvram_type_t type,
1529 __in unsigned int offset,
1530 __out_bcount(size) caddr_t data,
1533 extern __checkReturn efx_rc_t
1534 efx_nvram_read_backup(
1535 __in efx_nic_t *enp,
1536 __in efx_nvram_type_t type,
1537 __in unsigned int offset,
1538 __out_bcount(size) caddr_t data,
1541 extern __checkReturn efx_rc_t
1542 efx_nvram_set_version(
1543 __in efx_nic_t *enp,
1544 __in efx_nvram_type_t type,
1545 __in_ecount(4) uint16_t version[4]);
1547 extern __checkReturn efx_rc_t
1549 __in efx_nic_t *enp,
1550 __in efx_nvram_type_t type,
1551 __in_bcount(partn_size) caddr_t partn_data,
1552 __in size_t partn_size);
1554 extern __checkReturn efx_rc_t
1556 __in efx_nic_t *enp,
1557 __in efx_nvram_type_t type);
1559 extern __checkReturn efx_rc_t
1560 efx_nvram_write_chunk(
1561 __in efx_nic_t *enp,
1562 __in efx_nvram_type_t type,
1563 __in unsigned int offset,
1564 __in_bcount(size) caddr_t data,
1569 __in efx_nic_t *enp);
1571 #endif /* EFSYS_OPT_NVRAM */
1573 #if EFSYS_OPT_BOOTCFG
1575 /* Report size and offset of bootcfg sector in NVRAM partition. */
1576 extern __checkReturn efx_rc_t
1577 efx_bootcfg_sector_info(
1578 __in efx_nic_t *enp,
1580 __out_opt uint32_t *sector_countp,
1581 __out size_t *offsetp,
1582 __out size_t *max_sizep);
1585 * Copy bootcfg sector data to a target buffer which may differ in size.
1586 * Optionally corrects format errors in source buffer.
1589 efx_bootcfg_copy_sector(
1590 __in efx_nic_t *enp,
1591 __inout_bcount(sector_length)
1593 __in size_t sector_length,
1594 __out_bcount(data_size) uint8_t *data,
1595 __in size_t data_size,
1596 __in boolean_t handle_format_errors);
1600 __in efx_nic_t *enp,
1601 __out_bcount(size) uint8_t *data,
1606 __in efx_nic_t *enp,
1607 __in_bcount(size) uint8_t *data,
1610 #endif /* EFSYS_OPT_BOOTCFG */
1612 #if EFSYS_OPT_IMAGE_LAYOUT
1614 #include "ef10_signed_image_layout.h"
1617 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1620 * The image header format is extensible. However, older drivers require an
1621 * exact match of image header version and header length when validating and
1622 * writing firmware images.
1624 * To avoid breaking backward compatibility, we use the upper bits of the
1625 * controller version fields to contain an extra version number used for
1626 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1627 * version). See bug39254 and SF-102785-PS for details.
1629 typedef struct efx_image_header_s {
1631 uint32_t eih_version;
1633 uint32_t eih_subtype;
1634 uint32_t eih_code_size;
1637 uint32_t eih_controller_version_min;
1639 uint16_t eih_controller_version_min_short;
1640 uint8_t eih_extra_version_a;
1641 uint8_t eih_extra_version_b;
1645 uint32_t eih_controller_version_max;
1647 uint16_t eih_controller_version_max_short;
1648 uint8_t eih_extra_version_c;
1649 uint8_t eih_extra_version_d;
1652 uint16_t eih_code_version_a;
1653 uint16_t eih_code_version_b;
1654 uint16_t eih_code_version_c;
1655 uint16_t eih_code_version_d;
1656 } efx_image_header_t;
1658 #define EFX_IMAGE_HEADER_SIZE (40)
1659 #define EFX_IMAGE_HEADER_VERSION (4)
1660 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1663 typedef struct efx_image_trailer_s {
1665 } efx_image_trailer_t;
1667 #define EFX_IMAGE_TRAILER_SIZE (4)
1669 typedef enum efx_image_format_e {
1670 EFX_IMAGE_FORMAT_NO_IMAGE,
1671 EFX_IMAGE_FORMAT_INVALID,
1672 EFX_IMAGE_FORMAT_UNSIGNED,
1673 EFX_IMAGE_FORMAT_SIGNED,
1674 } efx_image_format_t;
1676 typedef struct efx_image_info_s {
1677 efx_image_format_t eii_format;
1678 uint8_t * eii_imagep;
1679 size_t eii_image_size;
1680 efx_image_header_t * eii_headerp;
1683 extern __checkReturn efx_rc_t
1684 efx_check_reflash_image(
1686 __in uint32_t buffer_size,
1687 __out efx_image_info_t *infop);
1689 extern __checkReturn efx_rc_t
1690 efx_build_signed_image_write_buffer(
1691 __out uint8_t *bufferp,
1692 __in uint32_t buffer_size,
1693 __in efx_image_info_t *infop,
1694 __out efx_image_header_t **headerpp);
1696 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1700 typedef enum efx_pattern_type_t {
1701 EFX_PATTERN_BYTE_INCREMENT = 0,
1702 EFX_PATTERN_ALL_THE_SAME,
1703 EFX_PATTERN_BIT_ALTERNATE,
1704 EFX_PATTERN_BYTE_ALTERNATE,
1705 EFX_PATTERN_BYTE_CHANGING,
1706 EFX_PATTERN_BIT_SWEEP,
1708 } efx_pattern_type_t;
1711 (*efx_sram_pattern_fn_t)(
1713 __in boolean_t negate,
1714 __out efx_qword_t *eqp);
1716 extern __checkReturn efx_rc_t
1718 __in efx_nic_t *enp,
1719 __in efx_pattern_type_t type);
1721 #endif /* EFSYS_OPT_DIAG */
1723 extern __checkReturn efx_rc_t
1724 efx_sram_buf_tbl_set(
1725 __in efx_nic_t *enp,
1727 __in efsys_mem_t *esmp,
1731 efx_sram_buf_tbl_clear(
1732 __in efx_nic_t *enp,
1736 #define EFX_BUF_TBL_SIZE 0x20000
1738 #define EFX_BUF_SIZE 4096
1742 typedef struct efx_evq_s efx_evq_t;
1744 #if EFSYS_OPT_QSTATS
1746 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1747 typedef enum efx_ev_qstat_e {
1753 EV_RX_PAUSE_FRM_ERR,
1754 EV_RX_BUF_OWNER_ID_ERR,
1755 EV_RX_IPV4_HDR_CHKSUM_ERR,
1756 EV_RX_TCP_UDP_CHKSUM_ERR,
1760 EV_RX_MCAST_HASH_MATCH,
1777 EV_DRIVER_SRM_UPD_DONE,
1778 EV_DRIVER_TX_DESCQ_FLS_DONE,
1779 EV_DRIVER_RX_DESCQ_FLS_DONE,
1780 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1781 EV_DRIVER_RX_DSC_ERROR,
1782 EV_DRIVER_TX_DSC_ERROR,
1788 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1790 #endif /* EFSYS_OPT_QSTATS */
1792 extern __checkReturn efx_rc_t
1794 __in efx_nic_t *enp);
1798 __in efx_nic_t *enp);
1800 #define EFX_EVQ_MAXNEVS 32768
1801 #define EFX_EVQ_MINNEVS 512
1803 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1804 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1806 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1807 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1808 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1809 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1811 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1812 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1813 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1815 extern __checkReturn efx_rc_t
1817 __in efx_nic_t *enp,
1818 __in unsigned int index,
1819 __in efsys_mem_t *esmp,
1823 __in uint32_t flags,
1824 __deref_out efx_evq_t **eepp);
1828 __in efx_evq_t *eep,
1829 __in uint16_t data);
1831 typedef __checkReturn boolean_t
1832 (*efx_initialized_ev_t)(
1833 __in_opt void *arg);
1835 #define EFX_PKT_UNICAST 0x0004
1836 #define EFX_PKT_START 0x0008
1838 #define EFX_PKT_VLAN_TAGGED 0x0010
1839 #define EFX_CKSUM_TCPUDP 0x0020
1840 #define EFX_CKSUM_IPV4 0x0040
1841 #define EFX_PKT_CONT 0x0080
1843 #define EFX_CHECK_VLAN 0x0100
1844 #define EFX_PKT_TCP 0x0200
1845 #define EFX_PKT_UDP 0x0400
1846 #define EFX_PKT_IPV4 0x0800
1848 #define EFX_PKT_IPV6 0x1000
1849 #define EFX_PKT_PREFIX_LEN 0x2000
1850 #define EFX_ADDR_MISMATCH 0x4000
1851 #define EFX_DISCARD 0x8000
1854 * The following flags are used only for packed stream
1855 * mode. The values for the flags are reused to fit into 16 bit,
1856 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1857 * packed stream mode
1859 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1860 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1863 #define EFX_EV_RX_NLABELS 32
1864 #define EFX_EV_TX_NLABELS 32
1866 typedef __checkReturn boolean_t
1869 __in uint32_t label,
1872 __in uint16_t flags);
1874 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1877 * Packed stream mode is documented in SF-112241-TC.
1878 * The general idea is that, instead of putting each incoming
1879 * packet into a separate buffer which is specified in a RX
1880 * descriptor, a large buffer is provided to the hardware and
1881 * packets are put there in a continuous stream.
1882 * The main advantage of such an approach is that RX queue refilling
1883 * happens much less frequently.
1885 * Equal stride packed stream mode is documented in SF-119419-TC.
1886 * The general idea is to utilize advantages of the packed stream,
1887 * but avoid indirection in packets representation.
1888 * The main advantage of such an approach is that RX queue refilling
1889 * happens much less frequently and packets buffers are independent
1890 * from upper layers point of view.
1893 typedef __checkReturn boolean_t
1896 __in uint32_t label,
1898 __in uint32_t pkt_count,
1899 __in uint16_t flags);
1903 typedef __checkReturn boolean_t
1906 __in uint32_t label,
1909 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1910 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1911 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1912 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1913 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1914 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1915 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1916 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1917 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1919 typedef __checkReturn boolean_t
1920 (*efx_exception_ev_t)(
1922 __in uint32_t label,
1923 __in uint32_t data);
1925 typedef __checkReturn boolean_t
1926 (*efx_rxq_flush_done_ev_t)(
1928 __in uint32_t rxq_index);
1930 typedef __checkReturn boolean_t
1931 (*efx_rxq_flush_failed_ev_t)(
1933 __in uint32_t rxq_index);
1935 typedef __checkReturn boolean_t
1936 (*efx_txq_flush_done_ev_t)(
1938 __in uint32_t txq_index);
1940 typedef __checkReturn boolean_t
1941 (*efx_software_ev_t)(
1943 __in uint16_t magic);
1945 typedef __checkReturn boolean_t
1948 __in uint32_t code);
1950 #define EFX_SRAM_CLEAR 0
1951 #define EFX_SRAM_UPDATE 1
1952 #define EFX_SRAM_ILLEGAL_CLEAR 2
1954 typedef __checkReturn boolean_t
1955 (*efx_wake_up_ev_t)(
1957 __in uint32_t label);
1959 typedef __checkReturn boolean_t
1962 __in uint32_t label);
1964 typedef __checkReturn boolean_t
1965 (*efx_link_change_ev_t)(
1967 __in efx_link_mode_t link_mode);
1969 #if EFSYS_OPT_MON_STATS
1971 typedef __checkReturn boolean_t
1972 (*efx_monitor_ev_t)(
1974 __in efx_mon_stat_t id,
1975 __in efx_mon_stat_value_t value);
1977 #endif /* EFSYS_OPT_MON_STATS */
1979 #if EFSYS_OPT_MAC_STATS
1981 typedef __checkReturn boolean_t
1982 (*efx_mac_stats_ev_t)(
1984 __in uint32_t generation);
1986 #endif /* EFSYS_OPT_MAC_STATS */
1988 typedef struct efx_ev_callbacks_s {
1989 efx_initialized_ev_t eec_initialized;
1991 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1992 efx_rx_ps_ev_t eec_rx_ps;
1995 efx_exception_ev_t eec_exception;
1996 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1997 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1998 efx_txq_flush_done_ev_t eec_txq_flush_done;
1999 efx_software_ev_t eec_software;
2000 efx_sram_ev_t eec_sram;
2001 efx_wake_up_ev_t eec_wake_up;
2002 efx_timer_ev_t eec_timer;
2003 efx_link_change_ev_t eec_link_change;
2004 #if EFSYS_OPT_MON_STATS
2005 efx_monitor_ev_t eec_monitor;
2006 #endif /* EFSYS_OPT_MON_STATS */
2007 #if EFSYS_OPT_MAC_STATS
2008 efx_mac_stats_ev_t eec_mac_stats;
2009 #endif /* EFSYS_OPT_MAC_STATS */
2010 } efx_ev_callbacks_t;
2012 extern __checkReturn boolean_t
2014 __in efx_evq_t *eep,
2015 __in unsigned int count);
2017 #if EFSYS_OPT_EV_PREFETCH
2021 __in efx_evq_t *eep,
2022 __in unsigned int count);
2024 #endif /* EFSYS_OPT_EV_PREFETCH */
2028 __in efx_evq_t *eep,
2029 __inout unsigned int *countp,
2030 __in const efx_ev_callbacks_t *eecp,
2031 __in_opt void *arg);
2033 extern __checkReturn efx_rc_t
2034 efx_ev_usecs_to_ticks(
2035 __in efx_nic_t *enp,
2036 __in unsigned int usecs,
2037 __out unsigned int *ticksp);
2039 extern __checkReturn efx_rc_t
2041 __in efx_evq_t *eep,
2042 __in unsigned int us);
2044 extern __checkReturn efx_rc_t
2046 __in efx_evq_t *eep,
2047 __in unsigned int count);
2049 #if EFSYS_OPT_QSTATS
2055 __in efx_nic_t *enp,
2056 __in unsigned int id);
2058 #endif /* EFSYS_OPT_NAMES */
2061 efx_ev_qstats_update(
2062 __in efx_evq_t *eep,
2063 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2065 #endif /* EFSYS_OPT_QSTATS */
2069 __in efx_evq_t *eep);
2073 extern __checkReturn efx_rc_t
2075 __inout efx_nic_t *enp);
2079 __in efx_nic_t *enp);
2081 #if EFSYS_OPT_RX_SCATTER
2082 __checkReturn efx_rc_t
2083 efx_rx_scatter_enable(
2084 __in efx_nic_t *enp,
2085 __in unsigned int buf_size);
2086 #endif /* EFSYS_OPT_RX_SCATTER */
2088 /* Handle to represent use of the default RSS context. */
2089 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2091 #if EFSYS_OPT_RX_SCALE
2093 typedef enum efx_rx_hash_alg_e {
2094 EFX_RX_HASHALG_LFSR = 0,
2095 EFX_RX_HASHALG_TOEPLITZ,
2096 EFX_RX_HASHALG_PACKED_STREAM,
2098 } efx_rx_hash_alg_t;
2101 * Legacy hash type flags.
2103 * They represent standard tuples for distinct traffic classes.
2105 #define EFX_RX_HASH_IPV4 (1U << 0)
2106 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2107 #define EFX_RX_HASH_IPV6 (1U << 2)
2108 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2110 #define EFX_RX_HASH_LEGACY_MASK \
2111 (EFX_RX_HASH_IPV4 | \
2112 EFX_RX_HASH_TCPIPV4 | \
2113 EFX_RX_HASH_IPV6 | \
2114 EFX_RX_HASH_TCPIPV6)
2117 * The type of the argument used by efx_rx_scale_mode_set() to
2118 * provide a means for the client drivers to configure hashing.
2120 * A properly constructed value can either be:
2121 * - a combination of legacy flags
2122 * - a combination of EFX_RX_HASH() flags
2124 typedef unsigned int efx_rx_hash_type_t;
2126 typedef enum efx_rx_hash_support_e {
2127 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2128 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2129 } efx_rx_hash_support_t;
2131 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2132 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2133 #define EFX_MAXRSS 64 /* RX indirection entry range */
2134 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2136 typedef enum efx_rx_scale_context_type_e {
2137 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2138 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2139 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2140 } efx_rx_scale_context_type_t;
2143 * Traffic classes eligible for hash computation.
2145 * Select packet headers used in computing the receive hash.
2146 * This uses the same encoding as the RSS_MODES field of
2147 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2149 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2150 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2151 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2152 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2153 #define EFX_RX_CLASS_IPV4_LBN 16
2154 #define EFX_RX_CLASS_IPV4_WIDTH 4
2155 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2156 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2157 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2158 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2159 #define EFX_RX_CLASS_IPV6_LBN 28
2160 #define EFX_RX_CLASS_IPV6_WIDTH 4
2162 #define EFX_RX_NCLASSES 6
2165 * Ancillary flags used to construct generic hash tuples.
2166 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2168 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2169 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2170 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2171 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2174 * Generic hash tuples.
2176 * They express combinations of packet fields
2177 * which can contribute to the hash value for
2178 * a particular traffic class.
2180 #define EFX_RX_CLASS_HASH_DISABLE 0
2182 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2183 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2185 #define EFX_RX_CLASS_HASH_2TUPLE \
2186 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2187 EFX_RX_CLASS_HASH_DST_ADDR)
2189 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2190 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2191 EFX_RX_CLASS_HASH_SRC_PORT)
2193 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2194 (EFX_RX_CLASS_HASH_DST_ADDR | \
2195 EFX_RX_CLASS_HASH_DST_PORT)
2197 #define EFX_RX_CLASS_HASH_4TUPLE \
2198 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2199 EFX_RX_CLASS_HASH_DST_ADDR | \
2200 EFX_RX_CLASS_HASH_SRC_PORT | \
2201 EFX_RX_CLASS_HASH_DST_PORT)
2203 #define EFX_RX_CLASS_HASH_NTUPLES 7
2206 * Hash flag constructor.
2208 * Resulting flags encode hash tuples for specific traffic classes.
2209 * The client drivers are encouraged to use these flags to form
2210 * a hash type value.
2212 #define EFX_RX_HASH(_class, _tuple) \
2213 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2214 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2217 * The maximum number of EFX_RX_HASH() flags.
2219 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2221 extern __checkReturn efx_rc_t
2222 efx_rx_scale_hash_flags_get(
2223 __in efx_nic_t *enp,
2224 __in efx_rx_hash_alg_t hash_alg,
2225 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
2226 __out unsigned int *nflagsp);
2228 extern __checkReturn efx_rc_t
2229 efx_rx_hash_default_support_get(
2230 __in efx_nic_t *enp,
2231 __out efx_rx_hash_support_t *supportp);
2234 extern __checkReturn efx_rc_t
2235 efx_rx_scale_default_support_get(
2236 __in efx_nic_t *enp,
2237 __out efx_rx_scale_context_type_t *typep);
2239 extern __checkReturn efx_rc_t
2240 efx_rx_scale_context_alloc(
2241 __in efx_nic_t *enp,
2242 __in efx_rx_scale_context_type_t type,
2243 __in uint32_t num_queues,
2244 __out uint32_t *rss_contextp);
2246 extern __checkReturn efx_rc_t
2247 efx_rx_scale_context_free(
2248 __in efx_nic_t *enp,
2249 __in uint32_t rss_context);
2251 extern __checkReturn efx_rc_t
2252 efx_rx_scale_mode_set(
2253 __in efx_nic_t *enp,
2254 __in uint32_t rss_context,
2255 __in efx_rx_hash_alg_t alg,
2256 __in efx_rx_hash_type_t type,
2257 __in boolean_t insert);
2259 extern __checkReturn efx_rc_t
2260 efx_rx_scale_tbl_set(
2261 __in efx_nic_t *enp,
2262 __in uint32_t rss_context,
2263 __in_ecount(n) unsigned int *table,
2266 extern __checkReturn efx_rc_t
2267 efx_rx_scale_key_set(
2268 __in efx_nic_t *enp,
2269 __in uint32_t rss_context,
2270 __in_ecount(n) uint8_t *key,
2273 extern __checkReturn uint32_t
2274 efx_pseudo_hdr_hash_get(
2275 __in efx_rxq_t *erp,
2276 __in efx_rx_hash_alg_t func,
2277 __in uint8_t *buffer);
2279 #endif /* EFSYS_OPT_RX_SCALE */
2281 extern __checkReturn efx_rc_t
2282 efx_pseudo_hdr_pkt_length_get(
2283 __in efx_rxq_t *erp,
2284 __in uint8_t *buffer,
2285 __out uint16_t *pkt_lengthp);
2287 #define EFX_RXQ_MAXNDESCS 4096
2288 #define EFX_RXQ_MINNDESCS 512
2290 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2291 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2292 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2293 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2295 typedef enum efx_rxq_type_e {
2296 EFX_RXQ_TYPE_DEFAULT,
2297 EFX_RXQ_TYPE_PACKED_STREAM,
2298 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2303 * Dummy flag to be used instead of 0 to make it clear that the argument
2304 * is receive queue flags.
2306 #define EFX_RXQ_FLAG_NONE 0x0
2307 #define EFX_RXQ_FLAG_SCATTER 0x1
2309 * If tunnels are supported and Rx event can provide information about
2310 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2311 * full-feature firmware variant running), outer classes are requested by
2312 * default. However, if the driver supports tunnels, the flag allows to
2313 * request inner classes which are required to be able to interpret inner
2314 * Rx checksum offload results.
2316 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2318 extern __checkReturn efx_rc_t
2320 __in efx_nic_t *enp,
2321 __in unsigned int index,
2322 __in unsigned int label,
2323 __in efx_rxq_type_t type,
2324 __in efsys_mem_t *esmp,
2327 __in unsigned int flags,
2328 __in efx_evq_t *eep,
2329 __deref_out efx_rxq_t **erpp);
2331 #if EFSYS_OPT_RX_PACKED_STREAM
2333 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2334 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2335 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2336 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2337 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2339 extern __checkReturn efx_rc_t
2340 efx_rx_qcreate_packed_stream(
2341 __in efx_nic_t *enp,
2342 __in unsigned int index,
2343 __in unsigned int label,
2344 __in uint32_t ps_buf_size,
2345 __in efsys_mem_t *esmp,
2347 __in efx_evq_t *eep,
2348 __deref_out efx_rxq_t **erpp);
2352 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2354 /* Maximum head-of-line block timeout in nanoseconds */
2355 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2357 extern __checkReturn efx_rc_t
2358 efx_rx_qcreate_es_super_buffer(
2359 __in efx_nic_t *enp,
2360 __in unsigned int index,
2361 __in unsigned int label,
2362 __in uint32_t n_bufs_per_desc,
2363 __in uint32_t max_dma_len,
2364 __in uint32_t buf_stride,
2365 __in uint32_t hol_block_timeout,
2366 __in efsys_mem_t *esmp,
2368 __in unsigned int flags,
2369 __in efx_evq_t *eep,
2370 __deref_out efx_rxq_t **erpp);
2374 typedef struct efx_buffer_s {
2375 efsys_dma_addr_t eb_addr;
2380 typedef struct efx_desc_s {
2386 __in efx_rxq_t *erp,
2387 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2389 __in unsigned int ndescs,
2390 __in unsigned int completed,
2391 __in unsigned int added);
2395 __in efx_rxq_t *erp,
2396 __in unsigned int added,
2397 __inout unsigned int *pushedp);
2399 #if EFSYS_OPT_RX_PACKED_STREAM
2402 efx_rx_qpush_ps_credits(
2403 __in efx_rxq_t *erp);
2405 extern __checkReturn uint8_t *
2406 efx_rx_qps_packet_info(
2407 __in efx_rxq_t *erp,
2408 __in uint8_t *buffer,
2409 __in uint32_t buffer_length,
2410 __in uint32_t current_offset,
2411 __out uint16_t *lengthp,
2412 __out uint32_t *next_offsetp,
2413 __out uint32_t *timestamp);
2416 extern __checkReturn efx_rc_t
2418 __in efx_rxq_t *erp);
2422 __in efx_rxq_t *erp);
2426 __in efx_rxq_t *erp);
2430 typedef struct efx_txq_s efx_txq_t;
2432 #if EFSYS_OPT_QSTATS
2434 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2435 typedef enum efx_tx_qstat_e {
2441 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2443 #endif /* EFSYS_OPT_QSTATS */
2445 extern __checkReturn efx_rc_t
2447 __in efx_nic_t *enp);
2451 __in efx_nic_t *enp);
2453 #define EFX_TXQ_MINNDESCS 512
2455 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2456 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2457 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2459 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2461 #define EFX_TXQ_CKSUM_IPV4 0x0001
2462 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2463 #define EFX_TXQ_FATSOV2 0x0004
2464 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2465 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2467 extern __checkReturn efx_rc_t
2469 __in efx_nic_t *enp,
2470 __in unsigned int index,
2471 __in unsigned int label,
2472 __in efsys_mem_t *esmp,
2475 __in uint16_t flags,
2476 __in efx_evq_t *eep,
2477 __deref_out efx_txq_t **etpp,
2478 __out unsigned int *addedp);
2480 extern __checkReturn efx_rc_t
2482 __in efx_txq_t *etp,
2483 __in_ecount(ndescs) efx_buffer_t *eb,
2484 __in unsigned int ndescs,
2485 __in unsigned int completed,
2486 __inout unsigned int *addedp);
2488 extern __checkReturn efx_rc_t
2490 __in efx_txq_t *etp,
2491 __in unsigned int ns);
2495 __in efx_txq_t *etp,
2496 __in unsigned int added,
2497 __in unsigned int pushed);
2499 extern __checkReturn efx_rc_t
2501 __in efx_txq_t *etp);
2505 __in efx_txq_t *etp);
2507 extern __checkReturn efx_rc_t
2509 __in efx_txq_t *etp);
2512 efx_tx_qpio_disable(
2513 __in efx_txq_t *etp);
2515 extern __checkReturn efx_rc_t
2517 __in efx_txq_t *etp,
2518 __in_ecount(buf_length) uint8_t *buffer,
2519 __in size_t buf_length,
2520 __in size_t pio_buf_offset);
2522 extern __checkReturn efx_rc_t
2524 __in efx_txq_t *etp,
2525 __in size_t pkt_length,
2526 __in unsigned int completed,
2527 __inout unsigned int *addedp);
2529 extern __checkReturn efx_rc_t
2531 __in efx_txq_t *etp,
2532 __in_ecount(n) efx_desc_t *ed,
2533 __in unsigned int n,
2534 __in unsigned int completed,
2535 __inout unsigned int *addedp);
2538 efx_tx_qdesc_dma_create(
2539 __in efx_txq_t *etp,
2540 __in efsys_dma_addr_t addr,
2543 __out efx_desc_t *edp);
2546 efx_tx_qdesc_tso_create(
2547 __in efx_txq_t *etp,
2548 __in uint16_t ipv4_id,
2549 __in uint32_t tcp_seq,
2550 __in uint8_t tcp_flags,
2551 __out efx_desc_t *edp);
2553 /* Number of FATSOv2 option descriptors */
2554 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2556 /* Maximum number of DMA segments per TSO packet (not superframe) */
2557 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2560 efx_tx_qdesc_tso2_create(
2561 __in efx_txq_t *etp,
2562 __in uint16_t ipv4_id,
2563 __in uint16_t outer_ipv4_id,
2564 __in uint32_t tcp_seq,
2565 __in uint16_t tcp_mss,
2566 __out_ecount(count) efx_desc_t *edp,
2570 efx_tx_qdesc_vlantci_create(
2571 __in efx_txq_t *etp,
2573 __out efx_desc_t *edp);
2576 efx_tx_qdesc_checksum_create(
2577 __in efx_txq_t *etp,
2578 __in uint16_t flags,
2579 __out efx_desc_t *edp);
2581 #if EFSYS_OPT_QSTATS
2587 __in efx_nic_t *etp,
2588 __in unsigned int id);
2590 #endif /* EFSYS_OPT_NAMES */
2593 efx_tx_qstats_update(
2594 __in efx_txq_t *etp,
2595 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2597 #endif /* EFSYS_OPT_QSTATS */
2601 __in efx_txq_t *etp);
2606 #if EFSYS_OPT_FILTER
2608 #define EFX_ETHER_TYPE_IPV4 0x0800
2609 #define EFX_ETHER_TYPE_IPV6 0x86DD
2611 #define EFX_IPPROTO_TCP 6
2612 #define EFX_IPPROTO_UDP 17
2613 #define EFX_IPPROTO_GRE 47
2615 /* Use RSS to spread across multiple queues */
2616 #define EFX_FILTER_FLAG_RX_RSS 0x01
2617 /* Enable RX scatter */
2618 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2620 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2621 * May only be set by the filter implementation for each type.
2622 * A removal request will restore the automatic filter in its place.
2624 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2625 /* Filter is for RX */
2626 #define EFX_FILTER_FLAG_RX 0x08
2627 /* Filter is for TX */
2628 #define EFX_FILTER_FLAG_TX 0x10
2629 /* Set match flag on the received packet */
2630 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2631 /* Set match mark on the received packet */
2632 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2634 typedef uint8_t efx_filter_flags_t;
2637 * Flags which specify the fields to match on. The values are the same as in the
2638 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2641 /* Match by remote IP host address */
2642 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2643 /* Match by local IP host address */
2644 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2645 /* Match by remote MAC address */
2646 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2647 /* Match by remote TCP/UDP port */
2648 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2649 /* Match by remote TCP/UDP port */
2650 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2651 /* Match by local TCP/UDP port */
2652 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2653 /* Match by Ether-type */
2654 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2655 /* Match by inner VLAN ID */
2656 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2657 /* Match by outer VLAN ID */
2658 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2659 /* Match by IP transport protocol */
2660 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2661 /* Match by VNI or VSID */
2662 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2663 /* For encapsulated packets, match by inner frame local MAC address */
2664 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2665 /* For encapsulated packets, match all multicast inner frames */
2666 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2667 /* For encapsulated packets, match all unicast inner frames */
2668 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2670 * Match by encap type, this flag does not correspond to
2671 * the MCDI match flags and any unoccupied value may be used
2673 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2674 /* Match otherwise-unmatched multicast and broadcast packets */
2675 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2676 /* Match otherwise-unmatched unicast packets */
2677 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2679 typedef uint32_t efx_filter_match_flags_t;
2681 typedef enum efx_filter_priority_s {
2682 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2683 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2684 * address list or hardware
2685 * requirements. This may only be used
2686 * by the filter implementation for
2688 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2689 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2690 * client (e.g. SR-IOV, HyperV VMQ etc.)
2692 } efx_filter_priority_t;
2695 * FIXME: All these fields are assumed to be in little-endian byte order.
2696 * It may be better for some to be big-endian. See bug42804.
2699 typedef struct efx_filter_spec_s {
2700 efx_filter_match_flags_t efs_match_flags;
2701 uint8_t efs_priority;
2702 efx_filter_flags_t efs_flags;
2703 uint16_t efs_dmaq_id;
2704 uint32_t efs_rss_context;
2705 uint16_t efs_outer_vid;
2706 uint16_t efs_inner_vid;
2707 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2708 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2709 uint16_t efs_ether_type;
2710 uint8_t efs_ip_proto;
2711 efx_tunnel_protocol_t efs_encap_type;
2712 uint16_t efs_loc_port;
2713 uint16_t efs_rem_port;
2714 efx_oword_t efs_rem_host;
2715 efx_oword_t efs_loc_host;
2716 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2717 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2719 } efx_filter_spec_t;
2722 /* Default values for use in filter specifications */
2723 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2724 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2726 extern __checkReturn efx_rc_t
2728 __in efx_nic_t *enp);
2732 __in efx_nic_t *enp);
2734 extern __checkReturn efx_rc_t
2736 __in efx_nic_t *enp,
2737 __inout efx_filter_spec_t *spec);
2739 extern __checkReturn efx_rc_t
2741 __in efx_nic_t *enp,
2742 __inout efx_filter_spec_t *spec);
2744 extern __checkReturn efx_rc_t
2746 __in efx_nic_t *enp);
2748 extern __checkReturn efx_rc_t
2749 efx_filter_supported_filters(
2750 __in efx_nic_t *enp,
2751 __out_ecount(buffer_length) uint32_t *buffer,
2752 __in size_t buffer_length,
2753 __out size_t *list_lengthp);
2756 efx_filter_spec_init_rx(
2757 __out efx_filter_spec_t *spec,
2758 __in efx_filter_priority_t priority,
2759 __in efx_filter_flags_t flags,
2760 __in efx_rxq_t *erp);
2763 efx_filter_spec_init_tx(
2764 __out efx_filter_spec_t *spec,
2765 __in efx_txq_t *etp);
2767 extern __checkReturn efx_rc_t
2768 efx_filter_spec_set_ipv4_local(
2769 __inout efx_filter_spec_t *spec,
2772 __in uint16_t port);
2774 extern __checkReturn efx_rc_t
2775 efx_filter_spec_set_ipv4_full(
2776 __inout efx_filter_spec_t *spec,
2778 __in uint32_t lhost,
2779 __in uint16_t lport,
2780 __in uint32_t rhost,
2781 __in uint16_t rport);
2783 extern __checkReturn efx_rc_t
2784 efx_filter_spec_set_eth_local(
2785 __inout efx_filter_spec_t *spec,
2787 __in const uint8_t *addr);
2790 efx_filter_spec_set_ether_type(
2791 __inout efx_filter_spec_t *spec,
2792 __in uint16_t ether_type);
2794 extern __checkReturn efx_rc_t
2795 efx_filter_spec_set_uc_def(
2796 __inout efx_filter_spec_t *spec);
2798 extern __checkReturn efx_rc_t
2799 efx_filter_spec_set_mc_def(
2800 __inout efx_filter_spec_t *spec);
2802 typedef enum efx_filter_inner_frame_match_e {
2803 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2804 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2805 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2806 } efx_filter_inner_frame_match_t;
2808 extern __checkReturn efx_rc_t
2809 efx_filter_spec_set_encap_type(
2810 __inout efx_filter_spec_t *spec,
2811 __in efx_tunnel_protocol_t encap_type,
2812 __in efx_filter_inner_frame_match_t inner_frame_match);
2814 extern __checkReturn efx_rc_t
2815 efx_filter_spec_set_vxlan_full(
2816 __inout efx_filter_spec_t *spec,
2817 __in const uint8_t *vxlan_id,
2818 __in const uint8_t *inner_addr,
2819 __in const uint8_t *outer_addr);
2821 #if EFSYS_OPT_RX_SCALE
2822 extern __checkReturn efx_rc_t
2823 efx_filter_spec_set_rss_context(
2824 __inout efx_filter_spec_t *spec,
2825 __in uint32_t rss_context);
2827 #endif /* EFSYS_OPT_FILTER */
2831 extern __checkReturn uint32_t
2833 __in_ecount(count) uint32_t const *input,
2835 __in uint32_t init);
2837 extern __checkReturn uint32_t
2839 __in_ecount(length) uint8_t const *input,
2841 __in uint32_t init);
2843 #if EFSYS_OPT_LICENSING
2847 typedef struct efx_key_stats_s {
2849 uint32_t eks_invalid;
2850 uint32_t eks_blacklisted;
2851 uint32_t eks_unverifiable;
2852 uint32_t eks_wrong_node;
2853 uint32_t eks_licensed_apps_lo;
2854 uint32_t eks_licensed_apps_hi;
2855 uint32_t eks_licensed_features_lo;
2856 uint32_t eks_licensed_features_hi;
2859 extern __checkReturn efx_rc_t
2861 __in efx_nic_t *enp);
2865 __in efx_nic_t *enp);
2867 extern __checkReturn boolean_t
2868 efx_lic_check_support(
2869 __in efx_nic_t *enp);
2871 extern __checkReturn efx_rc_t
2872 efx_lic_update_licenses(
2873 __in efx_nic_t *enp);
2875 extern __checkReturn efx_rc_t
2876 efx_lic_get_key_stats(
2877 __in efx_nic_t *enp,
2878 __out efx_key_stats_t *ksp);
2880 extern __checkReturn efx_rc_t
2882 __in efx_nic_t *enp,
2883 __in uint64_t app_id,
2884 __out boolean_t *licensedp);
2886 extern __checkReturn efx_rc_t
2888 __in efx_nic_t *enp,
2889 __in size_t buffer_size,
2890 __out uint32_t *typep,
2891 __out size_t *lengthp,
2892 __out_opt uint8_t *bufferp);
2895 extern __checkReturn efx_rc_t
2897 __in efx_nic_t *enp,
2898 __in_bcount(buffer_size)
2900 __in size_t buffer_size,
2901 __out uint32_t *startp);
2903 extern __checkReturn efx_rc_t
2905 __in efx_nic_t *enp,
2906 __in_bcount(buffer_size)
2908 __in size_t buffer_size,
2909 __in uint32_t offset,
2910 __out uint32_t *endp);
2912 extern __checkReturn __success(return != B_FALSE) boolean_t
2914 __in efx_nic_t *enp,
2915 __in_bcount(buffer_size)
2917 __in size_t buffer_size,
2918 __in uint32_t offset,
2919 __out uint32_t *startp,
2920 __out uint32_t *lengthp);
2922 extern __checkReturn __success(return != B_FALSE) boolean_t
2923 efx_lic_validate_key(
2924 __in efx_nic_t *enp,
2925 __in_bcount(length) caddr_t keyp,
2926 __in uint32_t length);
2928 extern __checkReturn efx_rc_t
2930 __in efx_nic_t *enp,
2931 __in_bcount(buffer_size)
2933 __in size_t buffer_size,
2934 __in uint32_t offset,
2935 __in uint32_t length,
2936 __out_bcount_part(key_max_size, *lengthp)
2938 __in size_t key_max_size,
2939 __out uint32_t *lengthp);
2941 extern __checkReturn efx_rc_t
2943 __in efx_nic_t *enp,
2944 __in_bcount(buffer_size)
2946 __in size_t buffer_size,
2947 __in uint32_t offset,
2948 __in_bcount(length) caddr_t keyp,
2949 __in uint32_t length,
2950 __out uint32_t *lengthp);
2952 __checkReturn efx_rc_t
2954 __in efx_nic_t *enp,
2955 __in_bcount(buffer_size)
2957 __in size_t buffer_size,
2958 __in uint32_t offset,
2959 __in uint32_t length,
2961 __out uint32_t *deltap);
2963 extern __checkReturn efx_rc_t
2964 efx_lic_create_partition(
2965 __in efx_nic_t *enp,
2966 __in_bcount(buffer_size)
2968 __in size_t buffer_size);
2970 extern __checkReturn efx_rc_t
2971 efx_lic_finish_partition(
2972 __in efx_nic_t *enp,
2973 __in_bcount(buffer_size)
2975 __in size_t buffer_size);
2977 #endif /* EFSYS_OPT_LICENSING */
2981 #if EFSYS_OPT_TUNNEL
2983 extern __checkReturn efx_rc_t
2985 __in efx_nic_t *enp);
2989 __in efx_nic_t *enp);
2992 * For overlay network encapsulation using UDP, the firmware needs to know
2993 * the configured UDP port for the overlay so it can decode encapsulated
2995 * The UDP port/protocol list is global.
2998 extern __checkReturn efx_rc_t
2999 efx_tunnel_config_udp_add(
3000 __in efx_nic_t *enp,
3001 __in uint16_t port /* host/cpu-endian */,
3002 __in efx_tunnel_protocol_t protocol);
3004 extern __checkReturn efx_rc_t
3005 efx_tunnel_config_udp_remove(
3006 __in efx_nic_t *enp,
3007 __in uint16_t port /* host/cpu-endian */,
3008 __in efx_tunnel_protocol_t protocol);
3011 efx_tunnel_config_clear(
3012 __in efx_nic_t *enp);
3015 * Apply tunnel UDP ports configuration to hardware.
3017 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3020 extern __checkReturn efx_rc_t
3021 efx_tunnel_reconfigure(
3022 __in efx_nic_t *enp);
3024 #endif /* EFSYS_OPT_TUNNEL */
3026 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3029 * Firmware subvariant choice options.
3031 * It may be switched to no Tx checksum if attached drivers are either
3032 * preboot or firmware subvariant aware and no VIS are allocated.
3033 * If may be always switched to default explicitly using set request or
3034 * implicitly if unaware driver is attaching. If switching is done when
3035 * a driver is attached, it gets MC_REBOOT event and should recreate its
3038 * See SF-119419-TC DPDK Firmware Driver Interface and
3039 * SF-109306-TC EF10 for Driver Writers for details.
3041 typedef enum efx_nic_fw_subvariant_e {
3042 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3043 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3044 EFX_NIC_FW_SUBVARIANT_NTYPES
3045 } efx_nic_fw_subvariant_t;
3047 extern __checkReturn efx_rc_t
3048 efx_nic_get_fw_subvariant(
3049 __in efx_nic_t *enp,
3050 __out efx_nic_fw_subvariant_t *subvariantp);
3052 extern __checkReturn efx_rc_t
3053 efx_nic_set_fw_subvariant(
3054 __in efx_nic_t *enp,
3055 __in efx_nic_fw_subvariant_t subvariant);
3057 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3063 #endif /* _SYS_EFX_H */