1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
34 typedef __success(return == 0) int efx_rc_t;
39 typedef enum efx_family_e {
41 EFX_FAMILY_FALCON, /* Obsolete and not supported */
43 EFX_FAMILY_HUNTINGTON,
49 extern __checkReturn efx_rc_t
53 __out efx_family_t *efp,
54 __out unsigned int *membarp);
57 #define EFX_PCI_VENID_SFC 0x1924
59 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
61 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
62 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
63 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
65 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
66 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
67 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
69 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
70 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
72 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
73 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
74 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
76 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
77 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
78 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
81 #define EFX_MEM_BAR_SIENA 2
83 #define EFX_MEM_BAR_HUNTINGTON_PF 2
84 #define EFX_MEM_BAR_HUNTINGTON_VF 0
86 #define EFX_MEM_BAR_MEDFORD_PF 2
87 #define EFX_MEM_BAR_MEDFORD_VF 0
89 #define EFX_MEM_BAR_MEDFORD2 0
110 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
111 extern __checkReturn uint32_t
113 __in uint32_t crc_init,
114 __in_ecount(length) uint8_t const *input,
118 /* Type prototypes */
120 typedef struct efx_rxq_s efx_rxq_t;
124 typedef struct efx_nic_s efx_nic_t;
126 extern __checkReturn efx_rc_t
128 __in efx_family_t family,
129 __in efsys_identifier_t *esip,
130 __in efsys_bar_t *esbp,
131 __in efsys_lock_t *eslp,
132 __deref_out efx_nic_t **enpp);
134 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
135 typedef enum efx_fw_variant_e {
136 EFX_FW_VARIANT_FULL_FEATURED,
137 EFX_FW_VARIANT_LOW_LATENCY,
138 EFX_FW_VARIANT_PACKED_STREAM,
139 EFX_FW_VARIANT_HIGH_TX_RATE,
140 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
141 EFX_FW_VARIANT_RULES_ENGINE,
143 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
146 extern __checkReturn efx_rc_t
149 __in efx_fw_variant_t efv);
151 extern __checkReturn efx_rc_t
153 __in efx_nic_t *enp);
155 extern __checkReturn efx_rc_t
157 __in efx_nic_t *enp);
159 extern __checkReturn boolean_t
160 efx_nic_hw_unavailable(
161 __in efx_nic_t *enp);
164 efx_nic_set_hw_unavailable(
165 __in efx_nic_t *enp);
169 extern __checkReturn efx_rc_t
170 efx_nic_register_test(
171 __in efx_nic_t *enp);
173 #endif /* EFSYS_OPT_DIAG */
177 __in efx_nic_t *enp);
181 __in efx_nic_t *enp);
185 __in efx_nic_t *enp);
187 #define EFX_PCIE_LINK_SPEED_GEN1 1
188 #define EFX_PCIE_LINK_SPEED_GEN2 2
189 #define EFX_PCIE_LINK_SPEED_GEN3 3
191 typedef enum efx_pcie_link_performance_e {
192 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
193 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
194 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
195 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
196 } efx_pcie_link_performance_t;
198 extern __checkReturn efx_rc_t
199 efx_nic_calculate_pcie_link_bandwidth(
200 __in uint32_t pcie_link_width,
201 __in uint32_t pcie_link_gen,
202 __out uint32_t *bandwidth_mbpsp);
204 extern __checkReturn efx_rc_t
205 efx_nic_check_pcie_link_speed(
207 __in uint32_t pcie_link_width,
208 __in uint32_t pcie_link_gen,
209 __out efx_pcie_link_performance_t *resultp);
214 /* EF10 architecture NICs require MCDIv2 commands */
215 #define WITH_MCDI_V2 1
218 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
220 typedef enum efx_mcdi_exception_e {
221 EFX_MCDI_EXCEPTION_MC_REBOOT,
222 EFX_MCDI_EXCEPTION_MC_BADASSERT,
223 } efx_mcdi_exception_t;
225 #if EFSYS_OPT_MCDI_LOGGING
226 typedef enum efx_log_msg_e {
228 EFX_LOG_MCDI_REQUEST,
229 EFX_LOG_MCDI_RESPONSE,
231 #endif /* EFSYS_OPT_MCDI_LOGGING */
233 typedef struct efx_mcdi_transport_s {
235 efsys_mem_t *emt_dma_mem;
236 void (*emt_execute)(void *, efx_mcdi_req_t *);
237 void (*emt_ev_cpl)(void *);
238 void (*emt_exception)(void *, efx_mcdi_exception_t);
239 #if EFSYS_OPT_MCDI_LOGGING
240 void (*emt_logger)(void *, efx_log_msg_t,
241 void *, size_t, void *, size_t);
242 #endif /* EFSYS_OPT_MCDI_LOGGING */
243 #if EFSYS_OPT_MCDI_PROXY_AUTH
244 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
245 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
246 } efx_mcdi_transport_t;
248 extern __checkReturn efx_rc_t
251 __in const efx_mcdi_transport_t *mtp);
253 extern __checkReturn efx_rc_t
255 __in efx_nic_t *enp);
259 __in efx_nic_t *enp);
262 efx_mcdi_get_timeout(
264 __in efx_mcdi_req_t *emrp,
265 __out uint32_t *usec_timeoutp);
268 efx_mcdi_request_start(
270 __in efx_mcdi_req_t *emrp,
271 __in boolean_t ev_cpl);
273 extern __checkReturn boolean_t
274 efx_mcdi_request_poll(
275 __in efx_nic_t *enp);
277 extern __checkReturn boolean_t
278 efx_mcdi_request_abort(
279 __in efx_nic_t *enp);
283 __in efx_nic_t *enp);
285 #endif /* EFSYS_OPT_MCDI */
289 #define EFX_NINTR_SIENA 1024
291 typedef enum efx_intr_type_e {
292 EFX_INTR_INVALID = 0,
298 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
300 extern __checkReturn efx_rc_t
303 __in efx_intr_type_t type,
304 __in_opt efsys_mem_t *esmp);
308 __in efx_nic_t *enp);
312 __in efx_nic_t *enp);
315 efx_intr_disable_unlocked(
316 __in efx_nic_t *enp);
318 #define EFX_INTR_NEVQS 32
320 extern __checkReturn efx_rc_t
323 __in unsigned int level);
326 efx_intr_status_line(
328 __out boolean_t *fatalp,
329 __out uint32_t *maskp);
332 efx_intr_status_message(
334 __in unsigned int message,
335 __out boolean_t *fatalp);
339 __in efx_nic_t *enp);
343 __in efx_nic_t *enp);
347 #if EFSYS_OPT_MAC_STATS
349 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
350 typedef enum efx_mac_stat_e {
353 EFX_MAC_RX_UNICST_PKTS,
354 EFX_MAC_RX_MULTICST_PKTS,
355 EFX_MAC_RX_BRDCST_PKTS,
356 EFX_MAC_RX_PAUSE_PKTS,
357 EFX_MAC_RX_LE_64_PKTS,
358 EFX_MAC_RX_65_TO_127_PKTS,
359 EFX_MAC_RX_128_TO_255_PKTS,
360 EFX_MAC_RX_256_TO_511_PKTS,
361 EFX_MAC_RX_512_TO_1023_PKTS,
362 EFX_MAC_RX_1024_TO_15XX_PKTS,
363 EFX_MAC_RX_GE_15XX_PKTS,
365 EFX_MAC_RX_FCS_ERRORS,
366 EFX_MAC_RX_DROP_EVENTS,
367 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
368 EFX_MAC_RX_SYMBOL_ERRORS,
369 EFX_MAC_RX_ALIGN_ERRORS,
370 EFX_MAC_RX_INTERNAL_ERRORS,
371 EFX_MAC_RX_JABBER_PKTS,
372 EFX_MAC_RX_LANE0_CHAR_ERR,
373 EFX_MAC_RX_LANE1_CHAR_ERR,
374 EFX_MAC_RX_LANE2_CHAR_ERR,
375 EFX_MAC_RX_LANE3_CHAR_ERR,
376 EFX_MAC_RX_LANE0_DISP_ERR,
377 EFX_MAC_RX_LANE1_DISP_ERR,
378 EFX_MAC_RX_LANE2_DISP_ERR,
379 EFX_MAC_RX_LANE3_DISP_ERR,
380 EFX_MAC_RX_MATCH_FAULT,
381 EFX_MAC_RX_NODESC_DROP_CNT,
384 EFX_MAC_TX_UNICST_PKTS,
385 EFX_MAC_TX_MULTICST_PKTS,
386 EFX_MAC_TX_BRDCST_PKTS,
387 EFX_MAC_TX_PAUSE_PKTS,
388 EFX_MAC_TX_LE_64_PKTS,
389 EFX_MAC_TX_65_TO_127_PKTS,
390 EFX_MAC_TX_128_TO_255_PKTS,
391 EFX_MAC_TX_256_TO_511_PKTS,
392 EFX_MAC_TX_512_TO_1023_PKTS,
393 EFX_MAC_TX_1024_TO_15XX_PKTS,
394 EFX_MAC_TX_GE_15XX_PKTS,
396 EFX_MAC_TX_SGL_COL_PKTS,
397 EFX_MAC_TX_MULT_COL_PKTS,
398 EFX_MAC_TX_EX_COL_PKTS,
399 EFX_MAC_TX_LATE_COL_PKTS,
401 EFX_MAC_TX_EX_DEF_PKTS,
402 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
403 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
404 EFX_MAC_PM_TRUNC_VFIFO_FULL,
405 EFX_MAC_PM_DISCARD_VFIFO_FULL,
406 EFX_MAC_PM_TRUNC_QBB,
407 EFX_MAC_PM_DISCARD_QBB,
408 EFX_MAC_PM_DISCARD_MAPPING,
409 EFX_MAC_RXDP_Q_DISABLED_PKTS,
410 EFX_MAC_RXDP_DI_DROPPED_PKTS,
411 EFX_MAC_RXDP_STREAMING_PKTS,
412 EFX_MAC_RXDP_HLB_FETCH,
413 EFX_MAC_RXDP_HLB_WAIT,
414 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
415 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
416 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
417 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
418 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
419 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
420 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
421 EFX_MAC_VADAPTER_RX_BAD_BYTES,
422 EFX_MAC_VADAPTER_RX_OVERFLOW,
423 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
424 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
425 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
426 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
427 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
428 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
429 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
430 EFX_MAC_VADAPTER_TX_BAD_BYTES,
431 EFX_MAC_VADAPTER_TX_OVERFLOW,
432 EFX_MAC_FEC_UNCORRECTED_ERRORS,
433 EFX_MAC_FEC_CORRECTED_ERRORS,
434 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
435 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
436 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
437 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
438 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
439 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
440 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
441 EFX_MAC_CTPIO_OVERFLOW_FAIL,
442 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
443 EFX_MAC_CTPIO_TIMEOUT_FAIL,
444 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
445 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
446 EFX_MAC_CTPIO_INVALID_WR_FAIL,
447 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
448 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
449 EFX_MAC_CTPIO_RUNT_FALLBACK,
450 EFX_MAC_CTPIO_SUCCESS,
451 EFX_MAC_CTPIO_FALLBACK,
452 EFX_MAC_CTPIO_POISON,
454 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
455 EFX_MAC_RXDP_HLB_IDLE,
456 EFX_MAC_RXDP_HLB_TIMEOUT,
460 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
462 #endif /* EFSYS_OPT_MAC_STATS */
464 typedef enum efx_link_mode_e {
465 EFX_LINK_UNKNOWN = 0,
481 #define EFX_MAC_ADDR_LEN 6
483 #define EFX_VNI_OR_VSID_LEN 3
485 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
487 #define EFX_MAC_MULTICAST_LIST_MAX 256
489 #define EFX_MAC_SDU_MAX 9202
491 #define EFX_MAC_PDU_ADJUSTMENT \
495 + /* bug16011 */ 16) \
497 #define EFX_MAC_PDU(_sdu) \
498 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
501 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
502 * the SDU rounded up slightly.
504 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
506 #define EFX_MAC_PDU_MIN 60
507 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
509 extern __checkReturn efx_rc_t
514 extern __checkReturn efx_rc_t
519 extern __checkReturn efx_rc_t
524 extern __checkReturn efx_rc_t
527 __in boolean_t all_unicst,
528 __in boolean_t mulcst,
529 __in boolean_t all_mulcst,
530 __in boolean_t brdcst);
532 extern __checkReturn efx_rc_t
533 efx_mac_multicast_list_set(
535 __in_ecount(6*count) uint8_t const *addrs,
538 extern __checkReturn efx_rc_t
539 efx_mac_filter_default_rxq_set(
542 __in boolean_t using_rss);
545 efx_mac_filter_default_rxq_clear(
546 __in efx_nic_t *enp);
548 extern __checkReturn efx_rc_t
551 __in boolean_t enabled);
553 extern __checkReturn efx_rc_t
556 __out boolean_t *mac_upp);
558 #define EFX_FCNTL_RESPOND 0x00000001
559 #define EFX_FCNTL_GENERATE 0x00000002
561 extern __checkReturn efx_rc_t
564 __in unsigned int fcntl,
565 __in boolean_t autoneg);
570 __out unsigned int *fcntl_wantedp,
571 __out unsigned int *fcntl_linkp);
574 #if EFSYS_OPT_MAC_STATS
578 extern __checkReturn const char *
581 __in unsigned int id);
583 #endif /* EFSYS_OPT_NAMES */
585 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
587 #define EFX_MAC_STATS_MASK_NPAGES \
588 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
589 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
592 * Get mask of MAC statistics supported by the hardware.
594 * If mask_size is insufficient to return the mask, EINVAL error is
595 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
596 * (which is sizeof (uint32_t)) is sufficient.
598 extern __checkReturn efx_rc_t
599 efx_mac_stats_get_mask(
601 __out_bcount(mask_size) uint32_t *maskp,
602 __in size_t mask_size);
604 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
605 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
606 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
609 extern __checkReturn efx_rc_t
611 __in efx_nic_t *enp);
614 * Upload mac statistics supported by the hardware into the given buffer.
616 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
617 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
619 * The hardware will only DMA statistics that it understands (of course).
620 * Drivers should not make any assumptions about which statistics are
621 * supported, especially when the statistics are generated by firmware.
623 * Thus, drivers should zero this buffer before use, so that not-understood
624 * statistics read back as zero.
626 extern __checkReturn efx_rc_t
627 efx_mac_stats_upload(
629 __in efsys_mem_t *esmp);
631 extern __checkReturn efx_rc_t
632 efx_mac_stats_periodic(
634 __in efsys_mem_t *esmp,
635 __in uint16_t period_ms,
636 __in boolean_t events);
638 extern __checkReturn efx_rc_t
639 efx_mac_stats_update(
641 __in efsys_mem_t *esmp,
642 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
643 __inout_opt uint32_t *generationp);
645 #endif /* EFSYS_OPT_MAC_STATS */
649 typedef enum efx_mon_type_e {
661 __in efx_nic_t *enp);
663 #endif /* EFSYS_OPT_NAMES */
665 extern __checkReturn efx_rc_t
667 __in efx_nic_t *enp);
669 #if EFSYS_OPT_MON_STATS
671 #define EFX_MON_STATS_PAGE_SIZE 0x100
672 #define EFX_MON_MASK_ELEMENT_SIZE 32
674 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
675 typedef enum efx_mon_stat_e {
676 EFX_MON_STAT_CONTROLLER_TEMP,
677 EFX_MON_STAT_PHY_COMMON_TEMP,
678 EFX_MON_STAT_CONTROLLER_COOLING,
679 EFX_MON_STAT_PHY0_TEMP,
680 EFX_MON_STAT_PHY0_COOLING,
681 EFX_MON_STAT_PHY1_TEMP,
682 EFX_MON_STAT_PHY1_COOLING,
688 EFX_MON_STAT_IN_12V0,
689 EFX_MON_STAT_IN_1V2A,
690 EFX_MON_STAT_IN_VREF,
691 EFX_MON_STAT_OUT_VAOE,
692 EFX_MON_STAT_AOE_TEMP,
693 EFX_MON_STAT_PSU_AOE_TEMP,
694 EFX_MON_STAT_PSU_TEMP,
700 EFX_MON_STAT_IN_VAOE,
701 EFX_MON_STAT_OUT_IAOE,
702 EFX_MON_STAT_IN_IAOE,
703 EFX_MON_STAT_NIC_POWER,
705 EFX_MON_STAT_IN_I0V9,
706 EFX_MON_STAT_IN_I1V2,
707 EFX_MON_STAT_IN_0V9_ADC,
708 EFX_MON_STAT_CONTROLLER_2_TEMP,
709 EFX_MON_STAT_VREG_INTERNAL_TEMP,
710 EFX_MON_STAT_VREG_0V9_TEMP,
711 EFX_MON_STAT_VREG_1V2_TEMP,
712 EFX_MON_STAT_CONTROLLER_VPTAT,
713 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
714 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
715 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
716 EFX_MON_STAT_AMBIENT_TEMP,
717 EFX_MON_STAT_AIRFLOW,
718 EFX_MON_STAT_VDD08D_VSS08D_CSR,
719 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
720 EFX_MON_STAT_HOTPOINT_TEMP,
721 EFX_MON_STAT_PHY_POWER_PORT0,
722 EFX_MON_STAT_PHY_POWER_PORT1,
723 EFX_MON_STAT_MUM_VCC,
724 EFX_MON_STAT_IN_0V9_A,
725 EFX_MON_STAT_IN_I0V9_A,
726 EFX_MON_STAT_VREG_0V9_A_TEMP,
727 EFX_MON_STAT_IN_0V9_B,
728 EFX_MON_STAT_IN_I0V9_B,
729 EFX_MON_STAT_VREG_0V9_B_TEMP,
730 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
731 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
732 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
733 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
734 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
735 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
736 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
737 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
738 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
739 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
740 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
741 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
742 EFX_MON_STAT_SODIMM_VOUT,
743 EFX_MON_STAT_SODIMM_0_TEMP,
744 EFX_MON_STAT_SODIMM_1_TEMP,
745 EFX_MON_STAT_PHY0_VCC,
746 EFX_MON_STAT_PHY1_VCC,
747 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
748 EFX_MON_STAT_BOARD_FRONT_TEMP,
749 EFX_MON_STAT_BOARD_BACK_TEMP,
750 EFX_MON_STAT_IN_I1V8,
751 EFX_MON_STAT_IN_I2V5,
752 EFX_MON_STAT_IN_I3V3,
753 EFX_MON_STAT_IN_I12V0,
755 EFX_MON_STAT_IN_I1V3,
759 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
761 typedef enum efx_mon_stat_state_e {
762 EFX_MON_STAT_STATE_OK = 0,
763 EFX_MON_STAT_STATE_WARNING = 1,
764 EFX_MON_STAT_STATE_FATAL = 2,
765 EFX_MON_STAT_STATE_BROKEN = 3,
766 EFX_MON_STAT_STATE_NO_READING = 4,
767 } efx_mon_stat_state_t;
769 typedef enum efx_mon_stat_unit_e {
770 EFX_MON_STAT_UNIT_UNKNOWN = 0,
771 EFX_MON_STAT_UNIT_BOOL,
772 EFX_MON_STAT_UNIT_TEMP_C,
773 EFX_MON_STAT_UNIT_VOLTAGE_MV,
774 EFX_MON_STAT_UNIT_CURRENT_MA,
775 EFX_MON_STAT_UNIT_POWER_W,
776 EFX_MON_STAT_UNIT_RPM,
778 } efx_mon_stat_unit_t;
780 typedef struct efx_mon_stat_value_s {
782 efx_mon_stat_state_t emsv_state;
783 efx_mon_stat_unit_t emsv_unit;
784 } efx_mon_stat_value_t;
786 typedef struct efx_mon_limit_value_s {
787 uint16_t emlv_warning_min;
788 uint16_t emlv_warning_max;
789 uint16_t emlv_fatal_min;
790 uint16_t emlv_fatal_max;
791 } efx_mon_stat_limits_t;
793 typedef enum efx_mon_stat_portmask_e {
794 EFX_MON_STAT_PORTMAP_NONE = 0,
795 EFX_MON_STAT_PORTMAP_PORT0 = 1,
796 EFX_MON_STAT_PORTMAP_PORT1 = 2,
797 EFX_MON_STAT_PORTMAP_PORT2 = 3,
798 EFX_MON_STAT_PORTMAP_PORT3 = 4,
799 EFX_MON_STAT_PORTMAP_ALL = (-1),
800 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
801 } efx_mon_stat_portmask_t;
808 __in efx_mon_stat_t id);
811 efx_mon_stat_description(
813 __in efx_mon_stat_t id);
815 #endif /* EFSYS_OPT_NAMES */
817 extern __checkReturn boolean_t
818 efx_mon_mcdi_to_efx_stat(
820 __out efx_mon_stat_t *statp);
822 extern __checkReturn boolean_t
823 efx_mon_get_stat_unit(
824 __in efx_mon_stat_t stat,
825 __out efx_mon_stat_unit_t *unitp);
827 extern __checkReturn boolean_t
828 efx_mon_get_stat_portmap(
829 __in efx_mon_stat_t stat,
830 __out efx_mon_stat_portmask_t *maskp);
832 extern __checkReturn efx_rc_t
833 efx_mon_stats_update(
835 __in efsys_mem_t *esmp,
836 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
838 extern __checkReturn efx_rc_t
839 efx_mon_limits_update(
841 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
843 #endif /* EFSYS_OPT_MON_STATS */
847 __in efx_nic_t *enp);
851 extern __checkReturn efx_rc_t
853 __in efx_nic_t *enp);
855 #if EFSYS_OPT_PHY_LED_CONTROL
857 typedef enum efx_phy_led_mode_e {
858 EFX_PHY_LED_DEFAULT = 0,
863 } efx_phy_led_mode_t;
865 extern __checkReturn efx_rc_t
868 __in efx_phy_led_mode_t mode);
870 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
872 extern __checkReturn efx_rc_t
874 __in efx_nic_t *enp);
876 #if EFSYS_OPT_LOOPBACK
878 typedef enum efx_loopback_type_e {
879 EFX_LOOPBACK_OFF = 0,
880 EFX_LOOPBACK_DATA = 1,
881 EFX_LOOPBACK_GMAC = 2,
882 EFX_LOOPBACK_XGMII = 3,
883 EFX_LOOPBACK_XGXS = 4,
884 EFX_LOOPBACK_XAUI = 5,
885 EFX_LOOPBACK_GMII = 6,
886 EFX_LOOPBACK_SGMII = 7,
887 EFX_LOOPBACK_XGBR = 8,
888 EFX_LOOPBACK_XFI = 9,
889 EFX_LOOPBACK_XAUI_FAR = 10,
890 EFX_LOOPBACK_GMII_FAR = 11,
891 EFX_LOOPBACK_SGMII_FAR = 12,
892 EFX_LOOPBACK_XFI_FAR = 13,
893 EFX_LOOPBACK_GPHY = 14,
894 EFX_LOOPBACK_PHY_XS = 15,
895 EFX_LOOPBACK_PCS = 16,
896 EFX_LOOPBACK_PMA_PMD = 17,
897 EFX_LOOPBACK_XPORT = 18,
898 EFX_LOOPBACK_XGMII_WS = 19,
899 EFX_LOOPBACK_XAUI_WS = 20,
900 EFX_LOOPBACK_XAUI_WS_FAR = 21,
901 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
902 EFX_LOOPBACK_GMII_WS = 23,
903 EFX_LOOPBACK_XFI_WS = 24,
904 EFX_LOOPBACK_XFI_WS_FAR = 25,
905 EFX_LOOPBACK_PHYXS_WS = 26,
906 EFX_LOOPBACK_PMA_INT = 27,
907 EFX_LOOPBACK_SD_NEAR = 28,
908 EFX_LOOPBACK_SD_FAR = 29,
909 EFX_LOOPBACK_PMA_INT_WS = 30,
910 EFX_LOOPBACK_SD_FEP2_WS = 31,
911 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
912 EFX_LOOPBACK_SD_FEP_WS = 33,
913 EFX_LOOPBACK_SD_FES_WS = 34,
914 EFX_LOOPBACK_AOE_INT_NEAR = 35,
915 EFX_LOOPBACK_DATA_WS = 36,
916 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
918 } efx_loopback_type_t;
920 typedef enum efx_loopback_kind_e {
921 EFX_LOOPBACK_KIND_OFF = 0,
922 EFX_LOOPBACK_KIND_ALL,
923 EFX_LOOPBACK_KIND_MAC,
924 EFX_LOOPBACK_KIND_PHY,
926 } efx_loopback_kind_t;
930 __in efx_loopback_kind_t loopback_kind,
931 __out efx_qword_t *maskp);
933 extern __checkReturn efx_rc_t
934 efx_port_loopback_set(
936 __in efx_link_mode_t link_mode,
937 __in efx_loopback_type_t type);
941 extern __checkReturn const char *
942 efx_loopback_type_name(
944 __in efx_loopback_type_t type);
946 #endif /* EFSYS_OPT_NAMES */
948 #endif /* EFSYS_OPT_LOOPBACK */
950 extern __checkReturn efx_rc_t
953 __out_opt efx_link_mode_t *link_modep);
957 __in efx_nic_t *enp);
959 typedef enum efx_phy_cap_type_e {
960 EFX_PHY_CAP_INVALID = 0,
967 EFX_PHY_CAP_10000FDX,
971 EFX_PHY_CAP_40000FDX,
973 EFX_PHY_CAP_100000FDX,
974 EFX_PHY_CAP_25000FDX,
975 EFX_PHY_CAP_50000FDX,
976 EFX_PHY_CAP_BASER_FEC,
977 EFX_PHY_CAP_BASER_FEC_REQUESTED,
979 EFX_PHY_CAP_RS_FEC_REQUESTED,
980 EFX_PHY_CAP_25G_BASER_FEC,
981 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
983 } efx_phy_cap_type_t;
986 #define EFX_PHY_CAP_CURRENT 0x00000000
987 #define EFX_PHY_CAP_DEFAULT 0x00000001
988 #define EFX_PHY_CAP_PERM 0x00000002
994 __out uint32_t *maskp);
996 extern __checkReturn efx_rc_t
1003 __in efx_nic_t *enp,
1004 __out uint32_t *maskp);
1006 extern __checkReturn efx_rc_t
1008 __in efx_nic_t *enp,
1009 __out uint32_t *ouip);
1011 typedef enum efx_phy_media_type_e {
1012 EFX_PHY_MEDIA_INVALID = 0,
1017 EFX_PHY_MEDIA_SFP_PLUS,
1018 EFX_PHY_MEDIA_BASE_T,
1019 EFX_PHY_MEDIA_QSFP_PLUS,
1020 EFX_PHY_MEDIA_NTYPES
1021 } efx_phy_media_type_t;
1024 * Get the type of medium currently used. If the board has ports for
1025 * modules, a module is present, and we recognise the media type of
1026 * the module, then this will be the media type of the module.
1027 * Otherwise it will be the media type of the port.
1030 efx_phy_media_type_get(
1031 __in efx_nic_t *enp,
1032 __out efx_phy_media_type_t *typep);
1035 * 2-wire device address of the base information in accordance with SFF-8472
1036 * Diagnostic Monitoring Interface for Optical Transceivers section
1037 * 4 Memory Organization.
1039 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1042 * 2-wire device address of the digital diagnostics monitoring interface
1043 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1044 * Transceivers section 4 Memory Organization.
1046 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1049 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1050 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1053 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1056 * Maximum accessible data offset for PHY module information.
1058 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1061 extern __checkReturn efx_rc_t
1062 efx_phy_module_get_info(
1063 __in efx_nic_t *enp,
1064 __in uint8_t dev_addr,
1067 __out_bcount(len) uint8_t *data);
1069 #if EFSYS_OPT_PHY_STATS
1071 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1072 typedef enum efx_phy_stat_e {
1074 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1075 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1076 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1077 EFX_PHY_STAT_PMA_PMD_REV_A,
1078 EFX_PHY_STAT_PMA_PMD_REV_B,
1079 EFX_PHY_STAT_PMA_PMD_REV_C,
1080 EFX_PHY_STAT_PMA_PMD_REV_D,
1081 EFX_PHY_STAT_PCS_LINK_UP,
1082 EFX_PHY_STAT_PCS_RX_FAULT,
1083 EFX_PHY_STAT_PCS_TX_FAULT,
1084 EFX_PHY_STAT_PCS_BER,
1085 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1086 EFX_PHY_STAT_PHY_XS_LINK_UP,
1087 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1088 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1089 EFX_PHY_STAT_PHY_XS_ALIGN,
1090 EFX_PHY_STAT_PHY_XS_SYNC_A,
1091 EFX_PHY_STAT_PHY_XS_SYNC_B,
1092 EFX_PHY_STAT_PHY_XS_SYNC_C,
1093 EFX_PHY_STAT_PHY_XS_SYNC_D,
1094 EFX_PHY_STAT_AN_LINK_UP,
1095 EFX_PHY_STAT_AN_MASTER,
1096 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1097 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1098 EFX_PHY_STAT_CL22EXT_LINK_UP,
1103 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1104 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1105 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1106 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1107 EFX_PHY_STAT_AN_COMPLETE,
1108 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1109 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1110 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1111 EFX_PHY_STAT_PCS_FW_VERSION_0,
1112 EFX_PHY_STAT_PCS_FW_VERSION_1,
1113 EFX_PHY_STAT_PCS_FW_VERSION_2,
1114 EFX_PHY_STAT_PCS_FW_VERSION_3,
1115 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1116 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1117 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1118 EFX_PHY_STAT_PCS_OP_MODE,
1122 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1128 __in efx_nic_t *enp,
1129 __in efx_phy_stat_t stat);
1131 #endif /* EFSYS_OPT_NAMES */
1133 #define EFX_PHY_STATS_SIZE 0x100
1135 extern __checkReturn efx_rc_t
1136 efx_phy_stats_update(
1137 __in efx_nic_t *enp,
1138 __in efsys_mem_t *esmp,
1139 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1141 #endif /* EFSYS_OPT_PHY_STATS */
1146 typedef enum efx_bist_type_e {
1147 EFX_BIST_TYPE_UNKNOWN,
1148 EFX_BIST_TYPE_PHY_NORMAL,
1149 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1150 EFX_BIST_TYPE_PHY_CABLE_LONG,
1151 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1152 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1153 EFX_BIST_TYPE_REG, /* Test the register memories */
1154 EFX_BIST_TYPE_NTYPES,
1157 typedef enum efx_bist_result_e {
1158 EFX_BIST_RESULT_UNKNOWN,
1159 EFX_BIST_RESULT_RUNNING,
1160 EFX_BIST_RESULT_PASSED,
1161 EFX_BIST_RESULT_FAILED,
1162 } efx_bist_result_t;
1164 typedef enum efx_phy_cable_status_e {
1165 EFX_PHY_CABLE_STATUS_OK,
1166 EFX_PHY_CABLE_STATUS_INVALID,
1167 EFX_PHY_CABLE_STATUS_OPEN,
1168 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1169 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1170 EFX_PHY_CABLE_STATUS_BUSY,
1171 } efx_phy_cable_status_t;
1173 typedef enum efx_bist_value_e {
1174 EFX_BIST_PHY_CABLE_LENGTH_A,
1175 EFX_BIST_PHY_CABLE_LENGTH_B,
1176 EFX_BIST_PHY_CABLE_LENGTH_C,
1177 EFX_BIST_PHY_CABLE_LENGTH_D,
1178 EFX_BIST_PHY_CABLE_STATUS_A,
1179 EFX_BIST_PHY_CABLE_STATUS_B,
1180 EFX_BIST_PHY_CABLE_STATUS_C,
1181 EFX_BIST_PHY_CABLE_STATUS_D,
1182 EFX_BIST_FAULT_CODE,
1184 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1190 EFX_BIST_MEM_EXPECT,
1191 EFX_BIST_MEM_ACTUAL,
1193 EFX_BIST_MEM_ECC_PARITY,
1194 EFX_BIST_MEM_ECC_FATAL,
1198 extern __checkReturn efx_rc_t
1199 efx_bist_enable_offline(
1200 __in efx_nic_t *enp);
1202 extern __checkReturn efx_rc_t
1204 __in efx_nic_t *enp,
1205 __in efx_bist_type_t type);
1207 extern __checkReturn efx_rc_t
1209 __in efx_nic_t *enp,
1210 __in efx_bist_type_t type,
1211 __out efx_bist_result_t *resultp,
1212 __out_opt uint32_t *value_maskp,
1213 __out_ecount_opt(count) unsigned long *valuesp,
1218 __in efx_nic_t *enp,
1219 __in efx_bist_type_t type);
1221 #endif /* EFSYS_OPT_BIST */
1223 #define EFX_FEATURE_IPV6 0x00000001
1224 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1225 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1226 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1227 #define EFX_FEATURE_MCDI 0x00000020
1228 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1229 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1230 #define EFX_FEATURE_TURBO 0x00000100
1231 #define EFX_FEATURE_MCDI_DMA 0x00000200
1232 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1233 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1234 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1235 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1236 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1237 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1239 typedef enum efx_tunnel_protocol_e {
1240 EFX_TUNNEL_PROTOCOL_NONE = 0,
1241 EFX_TUNNEL_PROTOCOL_VXLAN,
1242 EFX_TUNNEL_PROTOCOL_GENEVE,
1243 EFX_TUNNEL_PROTOCOL_NVGRE,
1245 } efx_tunnel_protocol_t;
1247 typedef enum efx_vi_window_shift_e {
1248 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1249 EFX_VI_WINDOW_SHIFT_8K = 13,
1250 EFX_VI_WINDOW_SHIFT_16K = 14,
1251 EFX_VI_WINDOW_SHIFT_64K = 16,
1252 } efx_vi_window_shift_t;
1254 typedef struct efx_nic_cfg_s {
1255 uint32_t enc_board_type;
1256 uint32_t enc_phy_type;
1258 char enc_phy_name[21];
1260 char enc_phy_revision[21];
1261 efx_mon_type_t enc_mon_type;
1262 #if EFSYS_OPT_MON_STATS
1263 uint32_t enc_mon_stat_dma_buf_size;
1264 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1266 unsigned int enc_features;
1267 efx_vi_window_shift_t enc_vi_window_shift;
1268 uint8_t enc_mac_addr[6];
1269 uint8_t enc_port; /* PHY port number */
1270 uint32_t enc_intr_vec_base;
1271 uint32_t enc_intr_limit;
1272 uint32_t enc_evq_limit;
1273 uint32_t enc_txq_limit;
1274 uint32_t enc_rxq_limit;
1275 uint32_t enc_evq_max_nevs;
1276 uint32_t enc_evq_min_nevs;
1277 uint32_t enc_rxq_max_ndescs;
1278 uint32_t enc_rxq_min_ndescs;
1279 uint32_t enc_txq_max_ndescs;
1280 uint32_t enc_txq_min_ndescs;
1281 uint32_t enc_buftbl_limit;
1282 uint32_t enc_piobuf_limit;
1283 uint32_t enc_piobuf_size;
1284 uint32_t enc_piobuf_min_alloc_size;
1285 uint32_t enc_evq_timer_quantum_ns;
1286 uint32_t enc_evq_timer_max_us;
1287 uint32_t enc_clk_mult;
1288 uint32_t enc_ev_desc_size;
1289 uint32_t enc_rx_desc_size;
1290 uint32_t enc_tx_desc_size;
1291 uint32_t enc_rx_prefix_size;
1292 uint32_t enc_rx_buf_align_start;
1293 uint32_t enc_rx_buf_align_end;
1294 #if EFSYS_OPT_RX_SCALE
1295 uint32_t enc_rx_scale_max_exclusive_contexts;
1297 * Mask of supported hash algorithms.
1298 * Hash algorithm types are used as the bit indices.
1300 uint32_t enc_rx_scale_hash_alg_mask;
1302 * Indicates whether port numbers can be included to the
1303 * input data for hash computation.
1305 boolean_t enc_rx_scale_l4_hash_supported;
1306 boolean_t enc_rx_scale_additional_modes_supported;
1307 #endif /* EFSYS_OPT_RX_SCALE */
1308 #if EFSYS_OPT_LOOPBACK
1309 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1310 #endif /* EFSYS_OPT_LOOPBACK */
1311 #if EFSYS_OPT_PHY_FLAGS
1312 uint32_t enc_phy_flags_mask;
1313 #endif /* EFSYS_OPT_PHY_FLAGS */
1314 #if EFSYS_OPT_PHY_LED_CONTROL
1315 uint32_t enc_led_mask;
1316 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1317 #if EFSYS_OPT_PHY_STATS
1318 uint64_t enc_phy_stat_mask;
1319 #endif /* EFSYS_OPT_PHY_STATS */
1321 uint8_t enc_mcdi_mdio_channel;
1322 #if EFSYS_OPT_PHY_STATS
1323 uint32_t enc_mcdi_phy_stat_mask;
1324 #endif /* EFSYS_OPT_PHY_STATS */
1325 #if EFSYS_OPT_MON_STATS
1326 uint32_t *enc_mcdi_sensor_maskp;
1327 uint32_t enc_mcdi_sensor_mask_size;
1328 #endif /* EFSYS_OPT_MON_STATS */
1329 #endif /* EFSYS_OPT_MCDI */
1331 uint32_t enc_bist_mask;
1332 #endif /* EFSYS_OPT_BIST */
1336 uint32_t enc_privilege_mask;
1337 #endif /* EFX_OPTS_EF10() */
1338 boolean_t enc_bug26807_workaround;
1339 boolean_t enc_bug35388_workaround;
1340 boolean_t enc_bug41750_workaround;
1341 boolean_t enc_bug61265_workaround;
1342 boolean_t enc_bug61297_workaround;
1343 boolean_t enc_rx_batching_enabled;
1344 /* Maximum number of descriptors completed in an rx event. */
1345 uint32_t enc_rx_batch_max;
1346 /* Number of rx descriptors the hardware requires for a push. */
1347 uint32_t enc_rx_push_align;
1348 /* Maximum amount of data in DMA descriptor */
1349 uint32_t enc_tx_dma_desc_size_max;
1351 * Boundary which DMA descriptor data must not cross or 0 if no
1354 uint32_t enc_tx_dma_desc_boundary;
1356 * Maximum number of bytes into the packet the TCP header can start for
1357 * the hardware to apply TSO packet edits.
1359 uint32_t enc_tx_tso_tcp_header_offset_limit;
1360 boolean_t enc_fw_assisted_tso_enabled;
1361 boolean_t enc_fw_assisted_tso_v2_enabled;
1362 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1363 /* Number of TSO contexts on the NIC (FATSOv2) */
1364 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1365 boolean_t enc_hw_tx_insert_vlan_enabled;
1366 /* Number of PFs on the NIC */
1367 uint32_t enc_hw_pf_count;
1368 /* Datapath firmware vadapter/vport/vswitch support */
1369 boolean_t enc_datapath_cap_evb;
1370 boolean_t enc_rx_disable_scatter_supported;
1371 boolean_t enc_allow_set_mac_with_installed_filters;
1372 boolean_t enc_enhanced_set_mac_supported;
1373 boolean_t enc_init_evq_v2_supported;
1374 boolean_t enc_no_cont_ev_mode_supported;
1375 boolean_t enc_init_rxq_with_buffer_size;
1376 boolean_t enc_rx_packed_stream_supported;
1377 boolean_t enc_rx_var_packed_stream_supported;
1378 boolean_t enc_rx_es_super_buffer_supported;
1379 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1380 boolean_t enc_pm_and_rxdp_counters;
1381 boolean_t enc_mac_stats_40g_tx_size_bins;
1382 uint32_t enc_tunnel_encapsulations_supported;
1384 * NIC global maximum for unique UDP tunnel ports shared by all
1387 uint32_t enc_tunnel_config_udp_entries_max;
1388 /* External port identifier */
1389 uint8_t enc_external_port;
1390 uint32_t enc_mcdi_max_payload_length;
1391 /* VPD may be per-PF or global */
1392 boolean_t enc_vpd_is_global;
1393 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1394 uint32_t enc_required_pcie_bandwidth_mbps;
1395 uint32_t enc_max_pcie_link_gen;
1396 /* Firmware verifies integrity of NVRAM updates */
1397 uint32_t enc_nvram_update_verify_result_supported;
1398 /* Firmware support for extended MAC_STATS buffer */
1399 uint32_t enc_mac_stats_nstats;
1400 boolean_t enc_fec_counters;
1401 boolean_t enc_hlb_counters;
1402 /* Firmware support for "FLAG" and "MARK" filter actions */
1403 boolean_t enc_filter_action_flag_supported;
1404 boolean_t enc_filter_action_mark_supported;
1405 uint32_t enc_filter_action_mark_max;
1408 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1409 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1411 #define EFX_PCI_FUNCTION(_encp) \
1412 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1414 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1416 extern const efx_nic_cfg_t *
1418 __in const efx_nic_t *enp);
1420 /* RxDPCPU firmware id values by which FW variant can be identified */
1421 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1422 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1423 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1424 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1425 #define EFX_RXDP_DPDK_FW_ID 0x6
1427 typedef struct efx_nic_fw_info_s {
1428 /* Basic FW version information */
1429 uint16_t enfi_mc_fw_version[4];
1431 * If datapath capabilities can be detected,
1432 * additional FW information is to be shown
1434 boolean_t enfi_dpcpu_fw_ids_valid;
1435 /* Rx and Tx datapath CPU FW IDs */
1436 uint16_t enfi_rx_dpcpu_fw_id;
1437 uint16_t enfi_tx_dpcpu_fw_id;
1438 } efx_nic_fw_info_t;
1440 extern __checkReturn efx_rc_t
1441 efx_nic_get_fw_version(
1442 __in efx_nic_t *enp,
1443 __out efx_nic_fw_info_t *enfip);
1445 /* Driver resource limits (minimum required/maximum usable). */
1446 typedef struct efx_drv_limits_s {
1447 uint32_t edl_min_evq_count;
1448 uint32_t edl_max_evq_count;
1450 uint32_t edl_min_rxq_count;
1451 uint32_t edl_max_rxq_count;
1453 uint32_t edl_min_txq_count;
1454 uint32_t edl_max_txq_count;
1456 /* PIO blocks (sub-allocated from piobuf) */
1457 uint32_t edl_min_pio_alloc_size;
1458 uint32_t edl_max_pio_alloc_count;
1461 extern __checkReturn efx_rc_t
1462 efx_nic_set_drv_limits(
1463 __inout efx_nic_t *enp,
1464 __in efx_drv_limits_t *edlp);
1466 typedef enum efx_nic_region_e {
1467 EFX_REGION_VI, /* Memory BAR UC mapping */
1468 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1471 extern __checkReturn efx_rc_t
1472 efx_nic_get_bar_region(
1473 __in efx_nic_t *enp,
1474 __in efx_nic_region_t region,
1475 __out uint32_t *offsetp,
1476 __out size_t *sizep);
1478 extern __checkReturn efx_rc_t
1479 efx_nic_get_vi_pool(
1480 __in efx_nic_t *enp,
1481 __out uint32_t *evq_countp,
1482 __out uint32_t *rxq_countp,
1483 __out uint32_t *txq_countp);
1488 typedef enum efx_vpd_tag_e {
1495 typedef uint16_t efx_vpd_keyword_t;
1497 typedef struct efx_vpd_value_s {
1498 efx_vpd_tag_t evv_tag;
1499 efx_vpd_keyword_t evv_keyword;
1501 uint8_t evv_value[0x100];
1505 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1507 extern __checkReturn efx_rc_t
1509 __in efx_nic_t *enp);
1511 extern __checkReturn efx_rc_t
1513 __in efx_nic_t *enp,
1514 __out size_t *sizep);
1516 extern __checkReturn efx_rc_t
1518 __in efx_nic_t *enp,
1519 __out_bcount(size) caddr_t data,
1522 extern __checkReturn efx_rc_t
1524 __in efx_nic_t *enp,
1525 __in_bcount(size) caddr_t data,
1528 extern __checkReturn efx_rc_t
1530 __in efx_nic_t *enp,
1531 __in_bcount(size) caddr_t data,
1534 extern __checkReturn efx_rc_t
1536 __in efx_nic_t *enp,
1537 __in_bcount(size) caddr_t data,
1539 __inout efx_vpd_value_t *evvp);
1541 extern __checkReturn efx_rc_t
1543 __in efx_nic_t *enp,
1544 __inout_bcount(size) caddr_t data,
1546 __in efx_vpd_value_t *evvp);
1548 extern __checkReturn efx_rc_t
1550 __in efx_nic_t *enp,
1551 __inout_bcount(size) caddr_t data,
1553 __out efx_vpd_value_t *evvp,
1554 __inout unsigned int *contp);
1556 extern __checkReturn efx_rc_t
1558 __in efx_nic_t *enp,
1559 __in_bcount(size) caddr_t data,
1564 __in efx_nic_t *enp);
1566 #endif /* EFSYS_OPT_VPD */
1572 typedef enum efx_nvram_type_e {
1573 EFX_NVRAM_INVALID = 0,
1575 EFX_NVRAM_BOOTROM_CFG,
1576 EFX_NVRAM_MC_FIRMWARE,
1577 EFX_NVRAM_MC_GOLDEN,
1583 EFX_NVRAM_FPGA_BACKUP,
1584 EFX_NVRAM_DYNAMIC_CFG,
1587 EFX_NVRAM_MUM_FIRMWARE,
1588 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1589 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1594 extern __checkReturn efx_rc_t
1596 __in efx_nic_t *enp);
1600 extern __checkReturn efx_rc_t
1602 __in efx_nic_t *enp);
1604 #endif /* EFSYS_OPT_DIAG */
1606 extern __checkReturn efx_rc_t
1608 __in efx_nic_t *enp,
1609 __in efx_nvram_type_t type,
1610 __out size_t *sizep);
1612 extern __checkReturn efx_rc_t
1614 __in efx_nic_t *enp,
1615 __in efx_nvram_type_t type,
1616 __out_opt size_t *pref_chunkp);
1618 extern __checkReturn efx_rc_t
1619 efx_nvram_rw_finish(
1620 __in efx_nic_t *enp,
1621 __in efx_nvram_type_t type,
1622 __out_opt uint32_t *verify_resultp);
1624 extern __checkReturn efx_rc_t
1625 efx_nvram_get_version(
1626 __in efx_nic_t *enp,
1627 __in efx_nvram_type_t type,
1628 __out uint32_t *subtypep,
1629 __out_ecount(4) uint16_t version[4]);
1631 extern __checkReturn efx_rc_t
1632 efx_nvram_read_chunk(
1633 __in efx_nic_t *enp,
1634 __in efx_nvram_type_t type,
1635 __in unsigned int offset,
1636 __out_bcount(size) caddr_t data,
1639 extern __checkReturn efx_rc_t
1640 efx_nvram_read_backup(
1641 __in efx_nic_t *enp,
1642 __in efx_nvram_type_t type,
1643 __in unsigned int offset,
1644 __out_bcount(size) caddr_t data,
1647 extern __checkReturn efx_rc_t
1648 efx_nvram_set_version(
1649 __in efx_nic_t *enp,
1650 __in efx_nvram_type_t type,
1651 __in_ecount(4) uint16_t version[4]);
1653 extern __checkReturn efx_rc_t
1655 __in efx_nic_t *enp,
1656 __in efx_nvram_type_t type,
1657 __in_bcount(partn_size) caddr_t partn_data,
1658 __in size_t partn_size);
1660 extern __checkReturn efx_rc_t
1662 __in efx_nic_t *enp,
1663 __in efx_nvram_type_t type);
1665 extern __checkReturn efx_rc_t
1666 efx_nvram_write_chunk(
1667 __in efx_nic_t *enp,
1668 __in efx_nvram_type_t type,
1669 __in unsigned int offset,
1670 __in_bcount(size) caddr_t data,
1675 __in efx_nic_t *enp);
1677 #endif /* EFSYS_OPT_NVRAM */
1679 #if EFSYS_OPT_BOOTCFG
1681 /* Report size and offset of bootcfg sector in NVRAM partition. */
1682 extern __checkReturn efx_rc_t
1683 efx_bootcfg_sector_info(
1684 __in efx_nic_t *enp,
1686 __out_opt uint32_t *sector_countp,
1687 __out size_t *offsetp,
1688 __out size_t *max_sizep);
1691 * Copy bootcfg sector data to a target buffer which may differ in size.
1692 * Optionally corrects format errors in source buffer.
1695 efx_bootcfg_copy_sector(
1696 __in efx_nic_t *enp,
1697 __inout_bcount(sector_length)
1699 __in size_t sector_length,
1700 __out_bcount(data_size) uint8_t *data,
1701 __in size_t data_size,
1702 __in boolean_t handle_format_errors);
1706 __in efx_nic_t *enp,
1707 __out_bcount(size) uint8_t *data,
1712 __in efx_nic_t *enp,
1713 __in_bcount(size) uint8_t *data,
1718 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1719 * (see https://tools.ietf.org/html/rfc1533)
1721 * Summarising the format: the buffer is a sequence of options. All options
1722 * begin with a tag octet, which uniquely identifies the option. Fixed-
1723 * length options without data consist of only a tag octet. Only options PAD
1724 * (0) and END (255) are fixed length. All other options are variable-length
1725 * with a length octet following the tag octet. The value of the length
1726 * octet does not include the two octets specifying the tag and length. The
1727 * length octet is followed by "length" octets of data.
1729 * Option data may be a sequence of sub-options in the same format. The data
1730 * content of the encapsulating option is one or more encapsulated sub-options,
1731 * with no terminating END tag is required.
1733 * To be valid, the top-level sequence of options should be terminated by an
1734 * END tag. The buffer should be padded with the PAD byte.
1736 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1737 * checksum octet. The full buffer (including after the END tag) contributes
1738 * to the checksum, hence the need to fill the buffer to the end with PAD.
1741 #define EFX_DHCP_END ((uint8_t)0xff)
1742 #define EFX_DHCP_PAD ((uint8_t)0)
1744 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1745 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1747 extern __checkReturn uint8_t
1749 __in_bcount(size) uint8_t const *data,
1752 extern __checkReturn efx_rc_t
1754 __in_bcount(size) uint8_t const *data,
1756 __out_opt size_t *usedp);
1758 extern __checkReturn efx_rc_t
1760 __in_bcount(buffer_length) uint8_t *bufferp,
1761 __in size_t buffer_length,
1763 __deref_out uint8_t **valuepp,
1764 __out size_t *value_lengthp);
1766 extern __checkReturn efx_rc_t
1768 __in_bcount(buffer_length) uint8_t *bufferp,
1769 __in size_t buffer_length,
1770 __deref_out uint8_t **endpp);
1773 extern __checkReturn efx_rc_t
1774 efx_dhcp_delete_tag(
1775 __inout_bcount(buffer_length) uint8_t *bufferp,
1776 __in size_t buffer_length,
1779 extern __checkReturn efx_rc_t
1781 __inout_bcount(buffer_length) uint8_t *bufferp,
1782 __in size_t buffer_length,
1784 __in_bcount_opt(value_length) uint8_t *valuep,
1785 __in size_t value_length);
1787 extern __checkReturn efx_rc_t
1788 efx_dhcp_update_tag(
1789 __inout_bcount(buffer_length) uint8_t *bufferp,
1790 __in size_t buffer_length,
1792 __in uint8_t *value_locationp,
1793 __in_bcount_opt(value_length) uint8_t *valuep,
1794 __in size_t value_length);
1797 #endif /* EFSYS_OPT_BOOTCFG */
1799 #if EFSYS_OPT_IMAGE_LAYOUT
1801 #include "ef10_signed_image_layout.h"
1804 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1807 * The image header format is extensible. However, older drivers require an
1808 * exact match of image header version and header length when validating and
1809 * writing firmware images.
1811 * To avoid breaking backward compatibility, we use the upper bits of the
1812 * controller version fields to contain an extra version number used for
1813 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1814 * version). See bug39254 and SF-102785-PS for details.
1816 typedef struct efx_image_header_s {
1818 uint32_t eih_version;
1820 uint32_t eih_subtype;
1821 uint32_t eih_code_size;
1824 uint32_t eih_controller_version_min;
1826 uint16_t eih_controller_version_min_short;
1827 uint8_t eih_extra_version_a;
1828 uint8_t eih_extra_version_b;
1832 uint32_t eih_controller_version_max;
1834 uint16_t eih_controller_version_max_short;
1835 uint8_t eih_extra_version_c;
1836 uint8_t eih_extra_version_d;
1839 uint16_t eih_code_version_a;
1840 uint16_t eih_code_version_b;
1841 uint16_t eih_code_version_c;
1842 uint16_t eih_code_version_d;
1843 } efx_image_header_t;
1845 #define EFX_IMAGE_HEADER_SIZE (40)
1846 #define EFX_IMAGE_HEADER_VERSION (4)
1847 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1850 typedef struct efx_image_trailer_s {
1852 } efx_image_trailer_t;
1854 #define EFX_IMAGE_TRAILER_SIZE (4)
1856 typedef enum efx_image_format_e {
1857 EFX_IMAGE_FORMAT_NO_IMAGE,
1858 EFX_IMAGE_FORMAT_INVALID,
1859 EFX_IMAGE_FORMAT_UNSIGNED,
1860 EFX_IMAGE_FORMAT_SIGNED,
1861 } efx_image_format_t;
1863 typedef struct efx_image_info_s {
1864 efx_image_format_t eii_format;
1865 uint8_t * eii_imagep;
1866 size_t eii_image_size;
1867 efx_image_header_t * eii_headerp;
1870 extern __checkReturn efx_rc_t
1871 efx_check_reflash_image(
1873 __in uint32_t buffer_size,
1874 __out efx_image_info_t *infop);
1876 extern __checkReturn efx_rc_t
1877 efx_build_signed_image_write_buffer(
1878 __out_bcount(buffer_size)
1880 __in uint32_t buffer_size,
1881 __in efx_image_info_t *infop,
1882 __out efx_image_header_t **headerpp);
1884 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1888 typedef enum efx_pattern_type_t {
1889 EFX_PATTERN_BYTE_INCREMENT = 0,
1890 EFX_PATTERN_ALL_THE_SAME,
1891 EFX_PATTERN_BIT_ALTERNATE,
1892 EFX_PATTERN_BYTE_ALTERNATE,
1893 EFX_PATTERN_BYTE_CHANGING,
1894 EFX_PATTERN_BIT_SWEEP,
1896 } efx_pattern_type_t;
1899 (*efx_sram_pattern_fn_t)(
1901 __in boolean_t negate,
1902 __out efx_qword_t *eqp);
1904 extern __checkReturn efx_rc_t
1906 __in efx_nic_t *enp,
1907 __in efx_pattern_type_t type);
1909 #endif /* EFSYS_OPT_DIAG */
1911 extern __checkReturn efx_rc_t
1912 efx_sram_buf_tbl_set(
1913 __in efx_nic_t *enp,
1915 __in efsys_mem_t *esmp,
1919 efx_sram_buf_tbl_clear(
1920 __in efx_nic_t *enp,
1924 #define EFX_BUF_TBL_SIZE 0x20000
1926 #define EFX_BUF_SIZE 4096
1930 typedef struct efx_evq_s efx_evq_t;
1932 #if EFSYS_OPT_QSTATS
1934 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
1935 typedef enum efx_ev_qstat_e {
1941 EV_RX_PAUSE_FRM_ERR,
1942 EV_RX_BUF_OWNER_ID_ERR,
1943 EV_RX_IPV4_HDR_CHKSUM_ERR,
1944 EV_RX_TCP_UDP_CHKSUM_ERR,
1948 EV_RX_MCAST_HASH_MATCH,
1965 EV_DRIVER_SRM_UPD_DONE,
1966 EV_DRIVER_TX_DESCQ_FLS_DONE,
1967 EV_DRIVER_RX_DESCQ_FLS_DONE,
1968 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1969 EV_DRIVER_RX_DSC_ERROR,
1970 EV_DRIVER_TX_DSC_ERROR,
1973 EV_RX_PARSE_INCOMPLETE,
1977 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1979 #endif /* EFSYS_OPT_QSTATS */
1981 extern __checkReturn efx_rc_t
1983 __in efx_nic_t *enp);
1987 __in efx_nic_t *enp);
1989 extern __checkReturn size_t
1991 __in const efx_nic_t *enp,
1992 __in unsigned int ndescs);
1994 extern __checkReturn unsigned int
1996 __in const efx_nic_t *enp,
1997 __in unsigned int ndescs);
1999 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2000 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2001 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2002 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2004 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2005 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2006 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2009 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2010 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2013 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2014 * which is the case when an event queue is set to THROUGHPUT mode.
2016 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2018 extern __checkReturn efx_rc_t
2020 __in efx_nic_t *enp,
2021 __in unsigned int index,
2022 __in efsys_mem_t *esmp,
2026 __in uint32_t flags,
2027 __deref_out efx_evq_t **eepp);
2031 __in efx_evq_t *eep,
2032 __in uint16_t data);
2034 typedef __checkReturn boolean_t
2035 (*efx_initialized_ev_t)(
2036 __in_opt void *arg);
2038 #define EFX_PKT_UNICAST 0x0004
2039 #define EFX_PKT_START 0x0008
2041 #define EFX_PKT_VLAN_TAGGED 0x0010
2042 #define EFX_CKSUM_TCPUDP 0x0020
2043 #define EFX_CKSUM_IPV4 0x0040
2044 #define EFX_PKT_CONT 0x0080
2046 #define EFX_CHECK_VLAN 0x0100
2047 #define EFX_PKT_TCP 0x0200
2048 #define EFX_PKT_UDP 0x0400
2049 #define EFX_PKT_IPV4 0x0800
2051 #define EFX_PKT_IPV6 0x1000
2052 #define EFX_PKT_PREFIX_LEN 0x2000
2053 #define EFX_ADDR_MISMATCH 0x4000
2054 #define EFX_DISCARD 0x8000
2057 * The following flags are used only for packed stream
2058 * mode. The values for the flags are reused to fit into 16 bit,
2059 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2060 * packed stream mode
2062 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2063 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2066 #define EFX_EV_RX_NLABELS 32
2067 #define EFX_EV_TX_NLABELS 32
2069 typedef __checkReturn boolean_t
2072 __in uint32_t label,
2075 __in uint16_t flags);
2077 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2080 * Packed stream mode is documented in SF-112241-TC.
2081 * The general idea is that, instead of putting each incoming
2082 * packet into a separate buffer which is specified in a RX
2083 * descriptor, a large buffer is provided to the hardware and
2084 * packets are put there in a continuous stream.
2085 * The main advantage of such an approach is that RX queue refilling
2086 * happens much less frequently.
2088 * Equal stride packed stream mode is documented in SF-119419-TC.
2089 * The general idea is to utilize advantages of the packed stream,
2090 * but avoid indirection in packets representation.
2091 * The main advantage of such an approach is that RX queue refilling
2092 * happens much less frequently and packets buffers are independent
2093 * from upper layers point of view.
2096 typedef __checkReturn boolean_t
2099 __in uint32_t label,
2101 __in uint32_t pkt_count,
2102 __in uint16_t flags);
2106 typedef __checkReturn boolean_t
2109 __in uint32_t label,
2112 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2113 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2114 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2115 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2116 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2117 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2118 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2119 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2120 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2122 typedef __checkReturn boolean_t
2123 (*efx_exception_ev_t)(
2125 __in uint32_t label,
2126 __in uint32_t data);
2128 typedef __checkReturn boolean_t
2129 (*efx_rxq_flush_done_ev_t)(
2131 __in uint32_t rxq_index);
2133 typedef __checkReturn boolean_t
2134 (*efx_rxq_flush_failed_ev_t)(
2136 __in uint32_t rxq_index);
2138 typedef __checkReturn boolean_t
2139 (*efx_txq_flush_done_ev_t)(
2141 __in uint32_t txq_index);
2143 typedef __checkReturn boolean_t
2144 (*efx_software_ev_t)(
2146 __in uint16_t magic);
2148 typedef __checkReturn boolean_t
2151 __in uint32_t code);
2153 #define EFX_SRAM_CLEAR 0
2154 #define EFX_SRAM_UPDATE 1
2155 #define EFX_SRAM_ILLEGAL_CLEAR 2
2157 typedef __checkReturn boolean_t
2158 (*efx_wake_up_ev_t)(
2160 __in uint32_t label);
2162 typedef __checkReturn boolean_t
2165 __in uint32_t label);
2167 typedef __checkReturn boolean_t
2168 (*efx_link_change_ev_t)(
2170 __in efx_link_mode_t link_mode);
2172 #if EFSYS_OPT_MON_STATS
2174 typedef __checkReturn boolean_t
2175 (*efx_monitor_ev_t)(
2177 __in efx_mon_stat_t id,
2178 __in efx_mon_stat_value_t value);
2180 #endif /* EFSYS_OPT_MON_STATS */
2182 #if EFSYS_OPT_MAC_STATS
2184 typedef __checkReturn boolean_t
2185 (*efx_mac_stats_ev_t)(
2187 __in uint32_t generation);
2189 #endif /* EFSYS_OPT_MAC_STATS */
2191 typedef struct efx_ev_callbacks_s {
2192 efx_initialized_ev_t eec_initialized;
2194 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2195 efx_rx_ps_ev_t eec_rx_ps;
2198 efx_exception_ev_t eec_exception;
2199 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2200 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2201 efx_txq_flush_done_ev_t eec_txq_flush_done;
2202 efx_software_ev_t eec_software;
2203 efx_sram_ev_t eec_sram;
2204 efx_wake_up_ev_t eec_wake_up;
2205 efx_timer_ev_t eec_timer;
2206 efx_link_change_ev_t eec_link_change;
2207 #if EFSYS_OPT_MON_STATS
2208 efx_monitor_ev_t eec_monitor;
2209 #endif /* EFSYS_OPT_MON_STATS */
2210 #if EFSYS_OPT_MAC_STATS
2211 efx_mac_stats_ev_t eec_mac_stats;
2212 #endif /* EFSYS_OPT_MAC_STATS */
2213 } efx_ev_callbacks_t;
2215 extern __checkReturn boolean_t
2217 __in efx_evq_t *eep,
2218 __in unsigned int count);
2220 #if EFSYS_OPT_EV_PREFETCH
2224 __in efx_evq_t *eep,
2225 __in unsigned int count);
2227 #endif /* EFSYS_OPT_EV_PREFETCH */
2231 __in efx_evq_t *eep,
2232 __inout unsigned int *countp,
2233 __in const efx_ev_callbacks_t *eecp,
2234 __in_opt void *arg);
2236 extern __checkReturn efx_rc_t
2237 efx_ev_usecs_to_ticks(
2238 __in efx_nic_t *enp,
2239 __in unsigned int usecs,
2240 __out unsigned int *ticksp);
2242 extern __checkReturn efx_rc_t
2244 __in efx_evq_t *eep,
2245 __in unsigned int us);
2247 extern __checkReturn efx_rc_t
2249 __in efx_evq_t *eep,
2250 __in unsigned int count);
2252 #if EFSYS_OPT_QSTATS
2258 __in efx_nic_t *enp,
2259 __in unsigned int id);
2261 #endif /* EFSYS_OPT_NAMES */
2264 efx_ev_qstats_update(
2265 __in efx_evq_t *eep,
2266 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2268 #endif /* EFSYS_OPT_QSTATS */
2272 __in efx_evq_t *eep);
2276 extern __checkReturn efx_rc_t
2278 __inout efx_nic_t *enp);
2282 __in efx_nic_t *enp);
2284 #if EFSYS_OPT_RX_SCATTER
2285 __checkReturn efx_rc_t
2286 efx_rx_scatter_enable(
2287 __in efx_nic_t *enp,
2288 __in unsigned int buf_size);
2289 #endif /* EFSYS_OPT_RX_SCATTER */
2291 /* Handle to represent use of the default RSS context. */
2292 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2294 #if EFSYS_OPT_RX_SCALE
2296 typedef enum efx_rx_hash_alg_e {
2297 EFX_RX_HASHALG_LFSR = 0,
2298 EFX_RX_HASHALG_TOEPLITZ,
2299 EFX_RX_HASHALG_PACKED_STREAM,
2301 } efx_rx_hash_alg_t;
2304 * Legacy hash type flags.
2306 * They represent standard tuples for distinct traffic classes.
2308 #define EFX_RX_HASH_IPV4 (1U << 0)
2309 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2310 #define EFX_RX_HASH_IPV6 (1U << 2)
2311 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2313 #define EFX_RX_HASH_LEGACY_MASK \
2314 (EFX_RX_HASH_IPV4 | \
2315 EFX_RX_HASH_TCPIPV4 | \
2316 EFX_RX_HASH_IPV6 | \
2317 EFX_RX_HASH_TCPIPV6)
2320 * The type of the argument used by efx_rx_scale_mode_set() to
2321 * provide a means for the client drivers to configure hashing.
2323 * A properly constructed value can either be:
2324 * - a combination of legacy flags
2325 * - a combination of EFX_RX_HASH() flags
2327 typedef uint32_t efx_rx_hash_type_t;
2329 typedef enum efx_rx_hash_support_e {
2330 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2331 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2332 } efx_rx_hash_support_t;
2334 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2335 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2336 #define EFX_MAXRSS 64 /* RX indirection entry range */
2337 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2339 typedef enum efx_rx_scale_context_type_e {
2340 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2341 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2342 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2343 } efx_rx_scale_context_type_t;
2346 * Traffic classes eligible for hash computation.
2348 * Select packet headers used in computing the receive hash.
2349 * This uses the same encoding as the RSS_MODES field of
2350 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2352 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2353 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2354 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2355 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2356 #define EFX_RX_CLASS_IPV4_LBN 16
2357 #define EFX_RX_CLASS_IPV4_WIDTH 4
2358 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2359 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2360 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2361 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2362 #define EFX_RX_CLASS_IPV6_LBN 28
2363 #define EFX_RX_CLASS_IPV6_WIDTH 4
2365 #define EFX_RX_NCLASSES 6
2368 * Ancillary flags used to construct generic hash tuples.
2369 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2371 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2372 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2373 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2374 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2377 * Generic hash tuples.
2379 * They express combinations of packet fields
2380 * which can contribute to the hash value for
2381 * a particular traffic class.
2383 #define EFX_RX_CLASS_HASH_DISABLE 0
2385 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2386 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2388 #define EFX_RX_CLASS_HASH_2TUPLE \
2389 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2390 EFX_RX_CLASS_HASH_DST_ADDR)
2392 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2393 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2394 EFX_RX_CLASS_HASH_SRC_PORT)
2396 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2397 (EFX_RX_CLASS_HASH_DST_ADDR | \
2398 EFX_RX_CLASS_HASH_DST_PORT)
2400 #define EFX_RX_CLASS_HASH_4TUPLE \
2401 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2402 EFX_RX_CLASS_HASH_DST_ADDR | \
2403 EFX_RX_CLASS_HASH_SRC_PORT | \
2404 EFX_RX_CLASS_HASH_DST_PORT)
2406 #define EFX_RX_CLASS_HASH_NTUPLES 7
2409 * Hash flag constructor.
2411 * Resulting flags encode hash tuples for specific traffic classes.
2412 * The client drivers are encouraged to use these flags to form
2413 * a hash type value.
2415 #define EFX_RX_HASH(_class, _tuple) \
2416 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2417 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2420 * The maximum number of EFX_RX_HASH() flags.
2422 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2424 extern __checkReturn efx_rc_t
2425 efx_rx_scale_hash_flags_get(
2426 __in efx_nic_t *enp,
2427 __in efx_rx_hash_alg_t hash_alg,
2428 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2429 __in unsigned int max_nflags,
2430 __out unsigned int *nflagsp);
2432 extern __checkReturn efx_rc_t
2433 efx_rx_hash_default_support_get(
2434 __in efx_nic_t *enp,
2435 __out efx_rx_hash_support_t *supportp);
2438 extern __checkReturn efx_rc_t
2439 efx_rx_scale_default_support_get(
2440 __in efx_nic_t *enp,
2441 __out efx_rx_scale_context_type_t *typep);
2443 extern __checkReturn efx_rc_t
2444 efx_rx_scale_context_alloc(
2445 __in efx_nic_t *enp,
2446 __in efx_rx_scale_context_type_t type,
2447 __in uint32_t num_queues,
2448 __out uint32_t *rss_contextp);
2450 extern __checkReturn efx_rc_t
2451 efx_rx_scale_context_free(
2452 __in efx_nic_t *enp,
2453 __in uint32_t rss_context);
2455 extern __checkReturn efx_rc_t
2456 efx_rx_scale_mode_set(
2457 __in efx_nic_t *enp,
2458 __in uint32_t rss_context,
2459 __in efx_rx_hash_alg_t alg,
2460 __in efx_rx_hash_type_t type,
2461 __in boolean_t insert);
2463 extern __checkReturn efx_rc_t
2464 efx_rx_scale_tbl_set(
2465 __in efx_nic_t *enp,
2466 __in uint32_t rss_context,
2467 __in_ecount(n) unsigned int *table,
2470 extern __checkReturn efx_rc_t
2471 efx_rx_scale_key_set(
2472 __in efx_nic_t *enp,
2473 __in uint32_t rss_context,
2474 __in_ecount(n) uint8_t *key,
2477 extern __checkReturn uint32_t
2478 efx_pseudo_hdr_hash_get(
2479 __in efx_rxq_t *erp,
2480 __in efx_rx_hash_alg_t func,
2481 __in uint8_t *buffer);
2483 #endif /* EFSYS_OPT_RX_SCALE */
2485 extern __checkReturn efx_rc_t
2486 efx_pseudo_hdr_pkt_length_get(
2487 __in efx_rxq_t *erp,
2488 __in uint8_t *buffer,
2489 __out uint16_t *pkt_lengthp);
2491 extern __checkReturn size_t
2493 __in const efx_nic_t *enp,
2494 __in unsigned int ndescs);
2496 extern __checkReturn unsigned int
2498 __in const efx_nic_t *enp,
2499 __in unsigned int ndescs);
2501 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2503 typedef enum efx_rxq_type_e {
2504 EFX_RXQ_TYPE_DEFAULT,
2505 EFX_RXQ_TYPE_PACKED_STREAM,
2506 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2511 * Dummy flag to be used instead of 0 to make it clear that the argument
2512 * is receive queue flags.
2514 #define EFX_RXQ_FLAG_NONE 0x0
2515 #define EFX_RXQ_FLAG_SCATTER 0x1
2517 * If tunnels are supported and Rx event can provide information about
2518 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2519 * full-feature firmware variant running), outer classes are requested by
2520 * default. However, if the driver supports tunnels, the flag allows to
2521 * request inner classes which are required to be able to interpret inner
2522 * Rx checksum offload results.
2524 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2526 extern __checkReturn efx_rc_t
2528 __in efx_nic_t *enp,
2529 __in unsigned int index,
2530 __in unsigned int label,
2531 __in efx_rxq_type_t type,
2532 __in size_t buf_size,
2533 __in efsys_mem_t *esmp,
2536 __in unsigned int flags,
2537 __in efx_evq_t *eep,
2538 __deref_out efx_rxq_t **erpp);
2540 #if EFSYS_OPT_RX_PACKED_STREAM
2542 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2543 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2544 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2545 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2546 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2548 extern __checkReturn efx_rc_t
2549 efx_rx_qcreate_packed_stream(
2550 __in efx_nic_t *enp,
2551 __in unsigned int index,
2552 __in unsigned int label,
2553 __in uint32_t ps_buf_size,
2554 __in efsys_mem_t *esmp,
2556 __in efx_evq_t *eep,
2557 __deref_out efx_rxq_t **erpp);
2561 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2563 /* Maximum head-of-line block timeout in nanoseconds */
2564 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2566 extern __checkReturn efx_rc_t
2567 efx_rx_qcreate_es_super_buffer(
2568 __in efx_nic_t *enp,
2569 __in unsigned int index,
2570 __in unsigned int label,
2571 __in uint32_t n_bufs_per_desc,
2572 __in uint32_t max_dma_len,
2573 __in uint32_t buf_stride,
2574 __in uint32_t hol_block_timeout,
2575 __in efsys_mem_t *esmp,
2577 __in unsigned int flags,
2578 __in efx_evq_t *eep,
2579 __deref_out efx_rxq_t **erpp);
2583 typedef struct efx_buffer_s {
2584 efsys_dma_addr_t eb_addr;
2589 typedef struct efx_desc_s {
2595 __in efx_rxq_t *erp,
2596 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2598 __in unsigned int ndescs,
2599 __in unsigned int completed,
2600 __in unsigned int added);
2604 __in efx_rxq_t *erp,
2605 __in unsigned int added,
2606 __inout unsigned int *pushedp);
2608 #if EFSYS_OPT_RX_PACKED_STREAM
2611 efx_rx_qpush_ps_credits(
2612 __in efx_rxq_t *erp);
2614 extern __checkReturn uint8_t *
2615 efx_rx_qps_packet_info(
2616 __in efx_rxq_t *erp,
2617 __in uint8_t *buffer,
2618 __in uint32_t buffer_length,
2619 __in uint32_t current_offset,
2620 __out uint16_t *lengthp,
2621 __out uint32_t *next_offsetp,
2622 __out uint32_t *timestamp);
2625 extern __checkReturn efx_rc_t
2627 __in efx_rxq_t *erp);
2631 __in efx_rxq_t *erp);
2635 __in efx_rxq_t *erp);
2639 typedef struct efx_txq_s efx_txq_t;
2641 #if EFSYS_OPT_QSTATS
2643 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2644 typedef enum efx_tx_qstat_e {
2650 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2652 #endif /* EFSYS_OPT_QSTATS */
2654 extern __checkReturn efx_rc_t
2656 __in efx_nic_t *enp);
2660 __in efx_nic_t *enp);
2662 extern __checkReturn size_t
2664 __in const efx_nic_t *enp,
2665 __in unsigned int ndescs);
2667 extern __checkReturn unsigned int
2669 __in const efx_nic_t *enp,
2670 __in unsigned int ndescs);
2672 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2674 #define EFX_TXQ_CKSUM_IPV4 0x0001
2675 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2676 #define EFX_TXQ_FATSOV2 0x0004
2677 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2678 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2680 extern __checkReturn efx_rc_t
2682 __in efx_nic_t *enp,
2683 __in unsigned int index,
2684 __in unsigned int label,
2685 __in efsys_mem_t *esmp,
2688 __in uint16_t flags,
2689 __in efx_evq_t *eep,
2690 __deref_out efx_txq_t **etpp,
2691 __out unsigned int *addedp);
2693 extern __checkReturn efx_rc_t
2695 __in efx_txq_t *etp,
2696 __in_ecount(ndescs) efx_buffer_t *eb,
2697 __in unsigned int ndescs,
2698 __in unsigned int completed,
2699 __inout unsigned int *addedp);
2701 extern __checkReturn efx_rc_t
2703 __in efx_txq_t *etp,
2704 __in unsigned int ns);
2708 __in efx_txq_t *etp,
2709 __in unsigned int added,
2710 __in unsigned int pushed);
2712 extern __checkReturn efx_rc_t
2714 __in efx_txq_t *etp);
2718 __in efx_txq_t *etp);
2720 extern __checkReturn efx_rc_t
2722 __in efx_txq_t *etp);
2725 efx_tx_qpio_disable(
2726 __in efx_txq_t *etp);
2728 extern __checkReturn efx_rc_t
2730 __in efx_txq_t *etp,
2731 __in_ecount(buf_length) uint8_t *buffer,
2732 __in size_t buf_length,
2733 __in size_t pio_buf_offset);
2735 extern __checkReturn efx_rc_t
2737 __in efx_txq_t *etp,
2738 __in size_t pkt_length,
2739 __in unsigned int completed,
2740 __inout unsigned int *addedp);
2742 extern __checkReturn efx_rc_t
2744 __in efx_txq_t *etp,
2745 __in_ecount(n) efx_desc_t *ed,
2746 __in unsigned int n,
2747 __in unsigned int completed,
2748 __inout unsigned int *addedp);
2751 efx_tx_qdesc_dma_create(
2752 __in efx_txq_t *etp,
2753 __in efsys_dma_addr_t addr,
2756 __out efx_desc_t *edp);
2759 efx_tx_qdesc_tso_create(
2760 __in efx_txq_t *etp,
2761 __in uint16_t ipv4_id,
2762 __in uint32_t tcp_seq,
2763 __in uint8_t tcp_flags,
2764 __out efx_desc_t *edp);
2766 /* Number of FATSOv2 option descriptors */
2767 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2769 /* Maximum number of DMA segments per TSO packet (not superframe) */
2770 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2773 efx_tx_qdesc_tso2_create(
2774 __in efx_txq_t *etp,
2775 __in uint16_t ipv4_id,
2776 __in uint16_t outer_ipv4_id,
2777 __in uint32_t tcp_seq,
2778 __in uint16_t tcp_mss,
2779 __out_ecount(count) efx_desc_t *edp,
2783 efx_tx_qdesc_vlantci_create(
2784 __in efx_txq_t *etp,
2786 __out efx_desc_t *edp);
2789 efx_tx_qdesc_checksum_create(
2790 __in efx_txq_t *etp,
2791 __in uint16_t flags,
2792 __out efx_desc_t *edp);
2794 #if EFSYS_OPT_QSTATS
2800 __in efx_nic_t *etp,
2801 __in unsigned int id);
2803 #endif /* EFSYS_OPT_NAMES */
2806 efx_tx_qstats_update(
2807 __in efx_txq_t *etp,
2808 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2810 #endif /* EFSYS_OPT_QSTATS */
2814 __in efx_txq_t *etp);
2819 #if EFSYS_OPT_FILTER
2821 #define EFX_ETHER_TYPE_IPV4 0x0800
2822 #define EFX_ETHER_TYPE_IPV6 0x86DD
2824 #define EFX_IPPROTO_TCP 6
2825 #define EFX_IPPROTO_UDP 17
2826 #define EFX_IPPROTO_GRE 47
2828 /* Use RSS to spread across multiple queues */
2829 #define EFX_FILTER_FLAG_RX_RSS 0x01
2830 /* Enable RX scatter */
2831 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2833 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2834 * May only be set by the filter implementation for each type.
2835 * A removal request will restore the automatic filter in its place.
2837 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2838 /* Filter is for RX */
2839 #define EFX_FILTER_FLAG_RX 0x08
2840 /* Filter is for TX */
2841 #define EFX_FILTER_FLAG_TX 0x10
2842 /* Set match flag on the received packet */
2843 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2844 /* Set match mark on the received packet */
2845 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2847 typedef uint8_t efx_filter_flags_t;
2850 * Flags which specify the fields to match on. The values are the same as in the
2851 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2854 /* Match by remote IP host address */
2855 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2856 /* Match by local IP host address */
2857 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2858 /* Match by remote MAC address */
2859 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2860 /* Match by remote TCP/UDP port */
2861 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2862 /* Match by remote TCP/UDP port */
2863 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2864 /* Match by local TCP/UDP port */
2865 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2866 /* Match by Ether-type */
2867 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2868 /* Match by inner VLAN ID */
2869 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2870 /* Match by outer VLAN ID */
2871 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2872 /* Match by IP transport protocol */
2873 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2874 /* Match by VNI or VSID */
2875 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2876 /* For encapsulated packets, match by inner frame local MAC address */
2877 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2878 /* For encapsulated packets, match all multicast inner frames */
2879 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2880 /* For encapsulated packets, match all unicast inner frames */
2881 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2883 * Match by encap type, this flag does not correspond to
2884 * the MCDI match flags and any unoccupied value may be used
2886 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2887 /* Match otherwise-unmatched multicast and broadcast packets */
2888 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2889 /* Match otherwise-unmatched unicast packets */
2890 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2892 typedef uint32_t efx_filter_match_flags_t;
2894 typedef enum efx_filter_priority_s {
2895 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2896 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2897 * address list or hardware
2898 * requirements. This may only be used
2899 * by the filter implementation for
2901 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2902 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2903 * client (e.g. SR-IOV, HyperV VMQ etc.)
2905 } efx_filter_priority_t;
2908 * FIXME: All these fields are assumed to be in little-endian byte order.
2909 * It may be better for some to be big-endian. See bug42804.
2912 typedef struct efx_filter_spec_s {
2913 efx_filter_match_flags_t efs_match_flags;
2914 uint8_t efs_priority;
2915 efx_filter_flags_t efs_flags;
2916 uint16_t efs_dmaq_id;
2917 uint32_t efs_rss_context;
2919 /* Fields below here are hashed for software filter lookup */
2920 uint16_t efs_outer_vid;
2921 uint16_t efs_inner_vid;
2922 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2923 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2924 uint16_t efs_ether_type;
2925 uint8_t efs_ip_proto;
2926 efx_tunnel_protocol_t efs_encap_type;
2927 uint16_t efs_loc_port;
2928 uint16_t efs_rem_port;
2929 efx_oword_t efs_rem_host;
2930 efx_oword_t efs_loc_host;
2931 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2932 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2933 } efx_filter_spec_t;
2936 /* Default values for use in filter specifications */
2937 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2938 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2940 extern __checkReturn efx_rc_t
2942 __in efx_nic_t *enp);
2946 __in efx_nic_t *enp);
2948 extern __checkReturn efx_rc_t
2950 __in efx_nic_t *enp,
2951 __inout efx_filter_spec_t *spec);
2953 extern __checkReturn efx_rc_t
2955 __in efx_nic_t *enp,
2956 __inout efx_filter_spec_t *spec);
2958 extern __checkReturn efx_rc_t
2960 __in efx_nic_t *enp);
2962 extern __checkReturn efx_rc_t
2963 efx_filter_supported_filters(
2964 __in efx_nic_t *enp,
2965 __out_ecount(buffer_length) uint32_t *buffer,
2966 __in size_t buffer_length,
2967 __out size_t *list_lengthp);
2970 efx_filter_spec_init_rx(
2971 __out efx_filter_spec_t *spec,
2972 __in efx_filter_priority_t priority,
2973 __in efx_filter_flags_t flags,
2974 __in efx_rxq_t *erp);
2977 efx_filter_spec_init_tx(
2978 __out efx_filter_spec_t *spec,
2979 __in efx_txq_t *etp);
2981 extern __checkReturn efx_rc_t
2982 efx_filter_spec_set_ipv4_local(
2983 __inout efx_filter_spec_t *spec,
2986 __in uint16_t port);
2988 extern __checkReturn efx_rc_t
2989 efx_filter_spec_set_ipv4_full(
2990 __inout efx_filter_spec_t *spec,
2992 __in uint32_t lhost,
2993 __in uint16_t lport,
2994 __in uint32_t rhost,
2995 __in uint16_t rport);
2997 extern __checkReturn efx_rc_t
2998 efx_filter_spec_set_eth_local(
2999 __inout efx_filter_spec_t *spec,
3001 __in const uint8_t *addr);
3004 efx_filter_spec_set_ether_type(
3005 __inout efx_filter_spec_t *spec,
3006 __in uint16_t ether_type);
3008 extern __checkReturn efx_rc_t
3009 efx_filter_spec_set_uc_def(
3010 __inout efx_filter_spec_t *spec);
3012 extern __checkReturn efx_rc_t
3013 efx_filter_spec_set_mc_def(
3014 __inout efx_filter_spec_t *spec);
3016 typedef enum efx_filter_inner_frame_match_e {
3017 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3018 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3019 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3020 } efx_filter_inner_frame_match_t;
3022 extern __checkReturn efx_rc_t
3023 efx_filter_spec_set_encap_type(
3024 __inout efx_filter_spec_t *spec,
3025 __in efx_tunnel_protocol_t encap_type,
3026 __in efx_filter_inner_frame_match_t inner_frame_match);
3028 extern __checkReturn efx_rc_t
3029 efx_filter_spec_set_vxlan(
3030 __inout efx_filter_spec_t *spec,
3031 __in const uint8_t *vni,
3032 __in const uint8_t *inner_addr,
3033 __in const uint8_t *outer_addr);
3035 extern __checkReturn efx_rc_t
3036 efx_filter_spec_set_geneve(
3037 __inout efx_filter_spec_t *spec,
3038 __in const uint8_t *vni,
3039 __in const uint8_t *inner_addr,
3040 __in const uint8_t *outer_addr);
3042 extern __checkReturn efx_rc_t
3043 efx_filter_spec_set_nvgre(
3044 __inout efx_filter_spec_t *spec,
3045 __in const uint8_t *vsid,
3046 __in const uint8_t *inner_addr,
3047 __in const uint8_t *outer_addr);
3049 #if EFSYS_OPT_RX_SCALE
3050 extern __checkReturn efx_rc_t
3051 efx_filter_spec_set_rss_context(
3052 __inout efx_filter_spec_t *spec,
3053 __in uint32_t rss_context);
3055 #endif /* EFSYS_OPT_FILTER */
3059 extern __checkReturn uint32_t
3061 __in_ecount(count) uint32_t const *input,
3063 __in uint32_t init);
3065 extern __checkReturn uint32_t
3067 __in_ecount(length) uint8_t const *input,
3069 __in uint32_t init);
3071 #if EFSYS_OPT_LICENSING
3075 typedef struct efx_key_stats_s {
3077 uint32_t eks_invalid;
3078 uint32_t eks_blacklisted;
3079 uint32_t eks_unverifiable;
3080 uint32_t eks_wrong_node;
3081 uint32_t eks_licensed_apps_lo;
3082 uint32_t eks_licensed_apps_hi;
3083 uint32_t eks_licensed_features_lo;
3084 uint32_t eks_licensed_features_hi;
3087 extern __checkReturn efx_rc_t
3089 __in efx_nic_t *enp);
3093 __in efx_nic_t *enp);
3095 extern __checkReturn boolean_t
3096 efx_lic_check_support(
3097 __in efx_nic_t *enp);
3099 extern __checkReturn efx_rc_t
3100 efx_lic_update_licenses(
3101 __in efx_nic_t *enp);
3103 extern __checkReturn efx_rc_t
3104 efx_lic_get_key_stats(
3105 __in efx_nic_t *enp,
3106 __out efx_key_stats_t *ksp);
3108 extern __checkReturn efx_rc_t
3110 __in efx_nic_t *enp,
3111 __in uint64_t app_id,
3112 __out boolean_t *licensedp);
3114 extern __checkReturn efx_rc_t
3116 __in efx_nic_t *enp,
3117 __in size_t buffer_size,
3118 __out uint32_t *typep,
3119 __out size_t *lengthp,
3120 __out_opt uint8_t *bufferp);
3123 extern __checkReturn efx_rc_t
3125 __in efx_nic_t *enp,
3126 __in_bcount(buffer_size)
3128 __in size_t buffer_size,
3129 __out uint32_t *startp);
3131 extern __checkReturn efx_rc_t
3133 __in efx_nic_t *enp,
3134 __in_bcount(buffer_size)
3136 __in size_t buffer_size,
3137 __in uint32_t offset,
3138 __out uint32_t *endp);
3140 extern __checkReturn __success(return != B_FALSE) boolean_t
3142 __in efx_nic_t *enp,
3143 __in_bcount(buffer_size)
3145 __in size_t buffer_size,
3146 __in uint32_t offset,
3147 __out uint32_t *startp,
3148 __out uint32_t *lengthp);
3150 extern __checkReturn __success(return != B_FALSE) boolean_t
3151 efx_lic_validate_key(
3152 __in efx_nic_t *enp,
3153 __in_bcount(length) caddr_t keyp,
3154 __in uint32_t length);
3156 extern __checkReturn efx_rc_t
3158 __in efx_nic_t *enp,
3159 __in_bcount(buffer_size)
3161 __in size_t buffer_size,
3162 __in uint32_t offset,
3163 __in uint32_t length,
3164 __out_bcount_part(key_max_size, *lengthp)
3166 __in size_t key_max_size,
3167 __out uint32_t *lengthp);
3169 extern __checkReturn efx_rc_t
3171 __in efx_nic_t *enp,
3172 __in_bcount(buffer_size)
3174 __in size_t buffer_size,
3175 __in uint32_t offset,
3176 __in_bcount(length) caddr_t keyp,
3177 __in uint32_t length,
3178 __out uint32_t *lengthp);
3180 __checkReturn efx_rc_t
3182 __in efx_nic_t *enp,
3183 __in_bcount(buffer_size)
3185 __in size_t buffer_size,
3186 __in uint32_t offset,
3187 __in uint32_t length,
3189 __out uint32_t *deltap);
3191 extern __checkReturn efx_rc_t
3192 efx_lic_create_partition(
3193 __in efx_nic_t *enp,
3194 __in_bcount(buffer_size)
3196 __in size_t buffer_size);
3198 extern __checkReturn efx_rc_t
3199 efx_lic_finish_partition(
3200 __in efx_nic_t *enp,
3201 __in_bcount(buffer_size)
3203 __in size_t buffer_size);
3205 #endif /* EFSYS_OPT_LICENSING */
3209 #if EFSYS_OPT_TUNNEL
3211 extern __checkReturn efx_rc_t
3213 __in efx_nic_t *enp);
3217 __in efx_nic_t *enp);
3220 * For overlay network encapsulation using UDP, the firmware needs to know
3221 * the configured UDP port for the overlay so it can decode encapsulated
3223 * The UDP port/protocol list is global.
3226 extern __checkReturn efx_rc_t
3227 efx_tunnel_config_udp_add(
3228 __in efx_nic_t *enp,
3229 __in uint16_t port /* host/cpu-endian */,
3230 __in efx_tunnel_protocol_t protocol);
3232 extern __checkReturn efx_rc_t
3233 efx_tunnel_config_udp_remove(
3234 __in efx_nic_t *enp,
3235 __in uint16_t port /* host/cpu-endian */,
3236 __in efx_tunnel_protocol_t protocol);
3239 efx_tunnel_config_clear(
3240 __in efx_nic_t *enp);
3243 * Apply tunnel UDP ports configuration to hardware.
3245 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3248 extern __checkReturn efx_rc_t
3249 efx_tunnel_reconfigure(
3250 __in efx_nic_t *enp);
3252 #endif /* EFSYS_OPT_TUNNEL */
3254 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3257 * Firmware subvariant choice options.
3259 * It may be switched to no Tx checksum if attached drivers are either
3260 * preboot or firmware subvariant aware and no VIS are allocated.
3261 * If may be always switched to default explicitly using set request or
3262 * implicitly if unaware driver is attaching. If switching is done when
3263 * a driver is attached, it gets MC_REBOOT event and should recreate its
3266 * See SF-119419-TC DPDK Firmware Driver Interface and
3267 * SF-109306-TC EF10 for Driver Writers for details.
3269 typedef enum efx_nic_fw_subvariant_e {
3270 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3271 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3272 EFX_NIC_FW_SUBVARIANT_NTYPES
3273 } efx_nic_fw_subvariant_t;
3275 extern __checkReturn efx_rc_t
3276 efx_nic_get_fw_subvariant(
3277 __in efx_nic_t *enp,
3278 __out efx_nic_fw_subvariant_t *subvariantp);
3280 extern __checkReturn efx_rc_t
3281 efx_nic_set_fw_subvariant(
3282 __in efx_nic_t *enp,
3283 __in efx_nic_fw_subvariant_t subvariant);
3285 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3287 typedef enum efx_phy_fec_type_e {
3288 EFX_PHY_FEC_NONE = 0,
3291 } efx_phy_fec_type_t;
3293 extern __checkReturn efx_rc_t
3294 efx_phy_fec_type_get(
3295 __in efx_nic_t *enp,
3296 __out efx_phy_fec_type_t *typep);
3298 typedef struct efx_phy_link_state_s {
3299 uint32_t epls_adv_cap_mask;
3300 uint32_t epls_lp_cap_mask;
3301 uint32_t epls_ld_cap_mask;
3302 unsigned int epls_fcntl;
3303 efx_phy_fec_type_t epls_fec;
3304 efx_link_mode_t epls_link_mode;
3305 } efx_phy_link_state_t;
3307 extern __checkReturn efx_rc_t
3308 efx_phy_link_state_get(
3309 __in efx_nic_t *enp,
3310 __out efx_phy_link_state_t *eplsp);
3317 #endif /* _SYS_EFX_H */