1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 extern __checkReturn efx_rc_t
134 __in efx_nic_t *enp);
136 extern __checkReturn efx_rc_t
138 __in efx_nic_t *enp);
140 extern __checkReturn efx_rc_t
142 __in efx_nic_t *enp);
146 extern __checkReturn efx_rc_t
147 efx_nic_register_test(
148 __in efx_nic_t *enp);
150 #endif /* EFSYS_OPT_DIAG */
154 __in efx_nic_t *enp);
158 __in efx_nic_t *enp);
162 __in efx_nic_t *enp);
164 #define EFX_PCIE_LINK_SPEED_GEN1 1
165 #define EFX_PCIE_LINK_SPEED_GEN2 2
166 #define EFX_PCIE_LINK_SPEED_GEN3 3
168 typedef enum efx_pcie_link_performance_e {
169 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
170 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
171 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
172 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
173 } efx_pcie_link_performance_t;
175 extern __checkReturn efx_rc_t
176 efx_nic_calculate_pcie_link_bandwidth(
177 __in uint32_t pcie_link_width,
178 __in uint32_t pcie_link_gen,
179 __out uint32_t *bandwidth_mbpsp);
181 extern __checkReturn efx_rc_t
182 efx_nic_check_pcie_link_speed(
184 __in uint32_t pcie_link_width,
185 __in uint32_t pcie_link_gen,
186 __out efx_pcie_link_performance_t *resultp);
190 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
191 /* Huntington and Medford require MCDIv2 commands */
192 #define WITH_MCDI_V2 1
195 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
197 typedef enum efx_mcdi_exception_e {
198 EFX_MCDI_EXCEPTION_MC_REBOOT,
199 EFX_MCDI_EXCEPTION_MC_BADASSERT,
200 } efx_mcdi_exception_t;
202 #if EFSYS_OPT_MCDI_LOGGING
203 typedef enum efx_log_msg_e {
205 EFX_LOG_MCDI_REQUEST,
206 EFX_LOG_MCDI_RESPONSE,
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
210 typedef struct efx_mcdi_transport_s {
212 efsys_mem_t *emt_dma_mem;
213 void (*emt_execute)(void *, efx_mcdi_req_t *);
214 void (*emt_ev_cpl)(void *);
215 void (*emt_exception)(void *, efx_mcdi_exception_t);
216 #if EFSYS_OPT_MCDI_LOGGING
217 void (*emt_logger)(void *, efx_log_msg_t,
218 void *, size_t, void *, size_t);
219 #endif /* EFSYS_OPT_MCDI_LOGGING */
220 #if EFSYS_OPT_MCDI_PROXY_AUTH
221 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
222 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
223 } efx_mcdi_transport_t;
225 extern __checkReturn efx_rc_t
228 __in const efx_mcdi_transport_t *mtp);
230 extern __checkReturn efx_rc_t
232 __in efx_nic_t *enp);
236 __in efx_nic_t *enp);
239 efx_mcdi_get_timeout(
241 __in efx_mcdi_req_t *emrp,
242 __out uint32_t *usec_timeoutp);
245 efx_mcdi_request_start(
247 __in efx_mcdi_req_t *emrp,
248 __in boolean_t ev_cpl);
250 extern __checkReturn boolean_t
251 efx_mcdi_request_poll(
252 __in efx_nic_t *enp);
254 extern __checkReturn boolean_t
255 efx_mcdi_request_abort(
256 __in efx_nic_t *enp);
260 __in efx_nic_t *enp);
262 #endif /* EFSYS_OPT_MCDI */
266 #define EFX_NINTR_SIENA 1024
268 typedef enum efx_intr_type_e {
269 EFX_INTR_INVALID = 0,
275 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
277 extern __checkReturn efx_rc_t
280 __in efx_intr_type_t type,
281 __in efsys_mem_t *esmp);
285 __in efx_nic_t *enp);
289 __in efx_nic_t *enp);
292 efx_intr_disable_unlocked(
293 __in efx_nic_t *enp);
295 #define EFX_INTR_NEVQS 32
297 extern __checkReturn efx_rc_t
300 __in unsigned int level);
303 efx_intr_status_line(
305 __out boolean_t *fatalp,
306 __out uint32_t *maskp);
309 efx_intr_status_message(
311 __in unsigned int message,
312 __out boolean_t *fatalp);
316 __in efx_nic_t *enp);
320 __in efx_nic_t *enp);
324 #if EFSYS_OPT_MAC_STATS
326 /* START MKCONFIG GENERATED EfxHeaderMacBlock 7d59c0d68431a5d1 */
327 typedef enum efx_mac_stat_e {
330 EFX_MAC_RX_UNICST_PKTS,
331 EFX_MAC_RX_MULTICST_PKTS,
332 EFX_MAC_RX_BRDCST_PKTS,
333 EFX_MAC_RX_PAUSE_PKTS,
334 EFX_MAC_RX_LE_64_PKTS,
335 EFX_MAC_RX_65_TO_127_PKTS,
336 EFX_MAC_RX_128_TO_255_PKTS,
337 EFX_MAC_RX_256_TO_511_PKTS,
338 EFX_MAC_RX_512_TO_1023_PKTS,
339 EFX_MAC_RX_1024_TO_15XX_PKTS,
340 EFX_MAC_RX_GE_15XX_PKTS,
342 EFX_MAC_RX_FCS_ERRORS,
343 EFX_MAC_RX_DROP_EVENTS,
344 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345 EFX_MAC_RX_SYMBOL_ERRORS,
346 EFX_MAC_RX_ALIGN_ERRORS,
347 EFX_MAC_RX_INTERNAL_ERRORS,
348 EFX_MAC_RX_JABBER_PKTS,
349 EFX_MAC_RX_LANE0_CHAR_ERR,
350 EFX_MAC_RX_LANE1_CHAR_ERR,
351 EFX_MAC_RX_LANE2_CHAR_ERR,
352 EFX_MAC_RX_LANE3_CHAR_ERR,
353 EFX_MAC_RX_LANE0_DISP_ERR,
354 EFX_MAC_RX_LANE1_DISP_ERR,
355 EFX_MAC_RX_LANE2_DISP_ERR,
356 EFX_MAC_RX_LANE3_DISP_ERR,
357 EFX_MAC_RX_MATCH_FAULT,
358 EFX_MAC_RX_NODESC_DROP_CNT,
361 EFX_MAC_TX_UNICST_PKTS,
362 EFX_MAC_TX_MULTICST_PKTS,
363 EFX_MAC_TX_BRDCST_PKTS,
364 EFX_MAC_TX_PAUSE_PKTS,
365 EFX_MAC_TX_LE_64_PKTS,
366 EFX_MAC_TX_65_TO_127_PKTS,
367 EFX_MAC_TX_128_TO_255_PKTS,
368 EFX_MAC_TX_256_TO_511_PKTS,
369 EFX_MAC_TX_512_TO_1023_PKTS,
370 EFX_MAC_TX_1024_TO_15XX_PKTS,
371 EFX_MAC_TX_GE_15XX_PKTS,
373 EFX_MAC_TX_SGL_COL_PKTS,
374 EFX_MAC_TX_MULT_COL_PKTS,
375 EFX_MAC_TX_EX_COL_PKTS,
376 EFX_MAC_TX_LATE_COL_PKTS,
378 EFX_MAC_TX_EX_DEF_PKTS,
379 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381 EFX_MAC_PM_TRUNC_VFIFO_FULL,
382 EFX_MAC_PM_DISCARD_VFIFO_FULL,
383 EFX_MAC_PM_TRUNC_QBB,
384 EFX_MAC_PM_DISCARD_QBB,
385 EFX_MAC_PM_DISCARD_MAPPING,
386 EFX_MAC_RXDP_Q_DISABLED_PKTS,
387 EFX_MAC_RXDP_DI_DROPPED_PKTS,
388 EFX_MAC_RXDP_STREAMING_PKTS,
389 EFX_MAC_RXDP_HLB_FETCH,
390 EFX_MAC_RXDP_HLB_WAIT,
391 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398 EFX_MAC_VADAPTER_RX_BAD_BYTES,
399 EFX_MAC_VADAPTER_RX_OVERFLOW,
400 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407 EFX_MAC_VADAPTER_TX_BAD_BYTES,
408 EFX_MAC_VADAPTER_TX_OVERFLOW,
409 EFX_MAC_FEC_UNCORRECTED_ERRORS,
410 EFX_MAC_FEC_CORRECTED_ERRORS,
411 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
412 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
413 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
414 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
415 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
416 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
417 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
418 EFX_MAC_CTPIO_OVERFLOW_FAIL,
419 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
420 EFX_MAC_CTPIO_TIMEOUT_FAIL,
421 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
422 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
423 EFX_MAC_CTPIO_INVALID_WR_FAIL,
424 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
425 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
426 EFX_MAC_CTPIO_RUNT_FALLBACK,
427 EFX_MAC_CTPIO_SUCCESS,
428 EFX_MAC_CTPIO_FALLBACK,
429 EFX_MAC_CTPIO_POISON,
434 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
436 #endif /* EFSYS_OPT_MAC_STATS */
438 typedef enum efx_link_mode_e {
439 EFX_LINK_UNKNOWN = 0,
455 #define EFX_MAC_ADDR_LEN 6
457 #define EFX_VNI_OR_VSID_LEN 3
459 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
461 #define EFX_MAC_MULTICAST_LIST_MAX 256
463 #define EFX_MAC_SDU_MAX 9202
465 #define EFX_MAC_PDU_ADJUSTMENT \
469 + /* bug16011 */ 16) \
471 #define EFX_MAC_PDU(_sdu) \
472 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
475 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
476 * the SDU rounded up slightly.
478 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
480 #define EFX_MAC_PDU_MIN 60
481 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
483 extern __checkReturn efx_rc_t
488 extern __checkReturn efx_rc_t
493 extern __checkReturn efx_rc_t
498 extern __checkReturn efx_rc_t
501 __in boolean_t all_unicst,
502 __in boolean_t mulcst,
503 __in boolean_t all_mulcst,
504 __in boolean_t brdcst);
506 extern __checkReturn efx_rc_t
507 efx_mac_multicast_list_set(
509 __in_ecount(6*count) uint8_t const *addrs,
512 extern __checkReturn efx_rc_t
513 efx_mac_filter_default_rxq_set(
516 __in boolean_t using_rss);
519 efx_mac_filter_default_rxq_clear(
520 __in efx_nic_t *enp);
522 extern __checkReturn efx_rc_t
525 __in boolean_t enabled);
527 extern __checkReturn efx_rc_t
530 __out boolean_t *mac_upp);
532 #define EFX_FCNTL_RESPOND 0x00000001
533 #define EFX_FCNTL_GENERATE 0x00000002
535 extern __checkReturn efx_rc_t
538 __in unsigned int fcntl,
539 __in boolean_t autoneg);
544 __out unsigned int *fcntl_wantedp,
545 __out unsigned int *fcntl_linkp);
548 #if EFSYS_OPT_MAC_STATS
552 extern __checkReturn const char *
555 __in unsigned int id);
557 #endif /* EFSYS_OPT_NAMES */
559 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
561 #define EFX_MAC_STATS_MASK_NPAGES \
562 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
563 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
566 * Get mask of MAC statistics supported by the hardware.
568 * If mask_size is insufficient to return the mask, EINVAL error is
569 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
570 * (which is sizeof (uint32_t)) is sufficient.
572 extern __checkReturn efx_rc_t
573 efx_mac_stats_get_mask(
575 __out_bcount(mask_size) uint32_t *maskp,
576 __in size_t mask_size);
578 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
579 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
580 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
583 extern __checkReturn efx_rc_t
585 __in efx_nic_t *enp);
588 * Upload mac statistics supported by the hardware into the given buffer.
590 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
591 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
593 * The hardware will only DMA statistics that it understands (of course).
594 * Drivers should not make any assumptions about which statistics are
595 * supported, especially when the statistics are generated by firmware.
597 * Thus, drivers should zero this buffer before use, so that not-understood
598 * statistics read back as zero.
600 extern __checkReturn efx_rc_t
601 efx_mac_stats_upload(
603 __in efsys_mem_t *esmp);
605 extern __checkReturn efx_rc_t
606 efx_mac_stats_periodic(
608 __in efsys_mem_t *esmp,
609 __in uint16_t period_ms,
610 __in boolean_t events);
612 extern __checkReturn efx_rc_t
613 efx_mac_stats_update(
615 __in efsys_mem_t *esmp,
616 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
617 __inout_opt uint32_t *generationp);
619 #endif /* EFSYS_OPT_MAC_STATS */
623 typedef enum efx_mon_type_e {
635 __in efx_nic_t *enp);
637 #endif /* EFSYS_OPT_NAMES */
639 extern __checkReturn efx_rc_t
641 __in efx_nic_t *enp);
643 #if EFSYS_OPT_MON_STATS
645 #define EFX_MON_STATS_PAGE_SIZE 0x100
646 #define EFX_MON_MASK_ELEMENT_SIZE 32
648 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
649 typedef enum efx_mon_stat_e {
656 EFX_MON_STAT_EXT_TEMP,
657 EFX_MON_STAT_INT_TEMP,
660 EFX_MON_STAT_INT_COOLING,
661 EFX_MON_STAT_EXT_COOLING,
669 EFX_MON_STAT_AOE_TEMP,
670 EFX_MON_STAT_PSU_AOE_TEMP,
671 EFX_MON_STAT_PSU_TEMP,
677 EFX_MON_STAT_VAOE_IN,
679 EFX_MON_STAT_IAOE_IN,
680 EFX_MON_STAT_NIC_POWER,
684 EFX_MON_STAT_0_9V_ADC,
685 EFX_MON_STAT_INT_TEMP2,
686 EFX_MON_STAT_VREG_TEMP,
687 EFX_MON_STAT_VREG_0_9V_TEMP,
688 EFX_MON_STAT_VREG_1_2V_TEMP,
689 EFX_MON_STAT_INT_VPTAT,
690 EFX_MON_STAT_INT_ADC_TEMP,
691 EFX_MON_STAT_EXT_VPTAT,
692 EFX_MON_STAT_EXT_ADC_TEMP,
693 EFX_MON_STAT_AMBIENT_TEMP,
694 EFX_MON_STAT_AIRFLOW,
695 EFX_MON_STAT_VDD08D_VSS08D_CSR,
696 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
697 EFX_MON_STAT_HOTPOINT_TEMP,
698 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
699 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
700 EFX_MON_STAT_MUM_VCC,
703 EFX_MON_STAT_0V9_A_TEMP,
706 EFX_MON_STAT_0V9_B_TEMP,
707 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
708 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
709 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
710 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
711 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
712 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
713 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
714 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
715 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
716 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
717 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
718 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
719 EFX_MON_STAT_SODIMM_VOUT,
720 EFX_MON_STAT_SODIMM_0_TEMP,
721 EFX_MON_STAT_SODIMM_1_TEMP,
722 EFX_MON_STAT_PHY0_VCC,
723 EFX_MON_STAT_PHY1_VCC,
724 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
725 EFX_MON_STAT_BOARD_FRONT_TEMP,
726 EFX_MON_STAT_BOARD_BACK_TEMP,
736 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
738 typedef enum efx_mon_stat_state_e {
739 EFX_MON_STAT_STATE_OK = 0,
740 EFX_MON_STAT_STATE_WARNING = 1,
741 EFX_MON_STAT_STATE_FATAL = 2,
742 EFX_MON_STAT_STATE_BROKEN = 3,
743 EFX_MON_STAT_STATE_NO_READING = 4,
744 } efx_mon_stat_state_t;
746 typedef struct efx_mon_stat_value_s {
749 } efx_mon_stat_value_t;
756 __in efx_mon_stat_t id);
758 #endif /* EFSYS_OPT_NAMES */
760 extern __checkReturn efx_rc_t
761 efx_mon_stats_update(
763 __in efsys_mem_t *esmp,
764 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
766 #endif /* EFSYS_OPT_MON_STATS */
770 __in efx_nic_t *enp);
774 extern __checkReturn efx_rc_t
776 __in efx_nic_t *enp);
778 #if EFSYS_OPT_PHY_LED_CONTROL
780 typedef enum efx_phy_led_mode_e {
781 EFX_PHY_LED_DEFAULT = 0,
786 } efx_phy_led_mode_t;
788 extern __checkReturn efx_rc_t
791 __in efx_phy_led_mode_t mode);
793 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
795 extern __checkReturn efx_rc_t
797 __in efx_nic_t *enp);
799 #if EFSYS_OPT_LOOPBACK
801 typedef enum efx_loopback_type_e {
802 EFX_LOOPBACK_OFF = 0,
803 EFX_LOOPBACK_DATA = 1,
804 EFX_LOOPBACK_GMAC = 2,
805 EFX_LOOPBACK_XGMII = 3,
806 EFX_LOOPBACK_XGXS = 4,
807 EFX_LOOPBACK_XAUI = 5,
808 EFX_LOOPBACK_GMII = 6,
809 EFX_LOOPBACK_SGMII = 7,
810 EFX_LOOPBACK_XGBR = 8,
811 EFX_LOOPBACK_XFI = 9,
812 EFX_LOOPBACK_XAUI_FAR = 10,
813 EFX_LOOPBACK_GMII_FAR = 11,
814 EFX_LOOPBACK_SGMII_FAR = 12,
815 EFX_LOOPBACK_XFI_FAR = 13,
816 EFX_LOOPBACK_GPHY = 14,
817 EFX_LOOPBACK_PHY_XS = 15,
818 EFX_LOOPBACK_PCS = 16,
819 EFX_LOOPBACK_PMA_PMD = 17,
820 EFX_LOOPBACK_XPORT = 18,
821 EFX_LOOPBACK_XGMII_WS = 19,
822 EFX_LOOPBACK_XAUI_WS = 20,
823 EFX_LOOPBACK_XAUI_WS_FAR = 21,
824 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
825 EFX_LOOPBACK_GMII_WS = 23,
826 EFX_LOOPBACK_XFI_WS = 24,
827 EFX_LOOPBACK_XFI_WS_FAR = 25,
828 EFX_LOOPBACK_PHYXS_WS = 26,
829 EFX_LOOPBACK_PMA_INT = 27,
830 EFX_LOOPBACK_SD_NEAR = 28,
831 EFX_LOOPBACK_SD_FAR = 29,
832 EFX_LOOPBACK_PMA_INT_WS = 30,
833 EFX_LOOPBACK_SD_FEP2_WS = 31,
834 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
835 EFX_LOOPBACK_SD_FEP_WS = 33,
836 EFX_LOOPBACK_SD_FES_WS = 34,
837 EFX_LOOPBACK_AOE_INT_NEAR = 35,
838 EFX_LOOPBACK_DATA_WS = 36,
839 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
841 } efx_loopback_type_t;
843 typedef enum efx_loopback_kind_e {
844 EFX_LOOPBACK_KIND_OFF = 0,
845 EFX_LOOPBACK_KIND_ALL,
846 EFX_LOOPBACK_KIND_MAC,
847 EFX_LOOPBACK_KIND_PHY,
849 } efx_loopback_kind_t;
853 __in efx_loopback_kind_t loopback_kind,
854 __out efx_qword_t *maskp);
856 extern __checkReturn efx_rc_t
857 efx_port_loopback_set(
859 __in efx_link_mode_t link_mode,
860 __in efx_loopback_type_t type);
864 extern __checkReturn const char *
865 efx_loopback_type_name(
867 __in efx_loopback_type_t type);
869 #endif /* EFSYS_OPT_NAMES */
871 #endif /* EFSYS_OPT_LOOPBACK */
873 extern __checkReturn efx_rc_t
876 __out_opt efx_link_mode_t *link_modep);
880 __in efx_nic_t *enp);
882 typedef enum efx_phy_cap_type_e {
883 EFX_PHY_CAP_INVALID = 0,
890 EFX_PHY_CAP_10000FDX,
894 EFX_PHY_CAP_40000FDX,
896 EFX_PHY_CAP_100000FDX,
897 EFX_PHY_CAP_25000FDX,
898 EFX_PHY_CAP_50000FDX,
899 EFX_PHY_CAP_BASER_FEC,
900 EFX_PHY_CAP_BASER_FEC_REQUESTED,
902 EFX_PHY_CAP_RS_FEC_REQUESTED,
903 EFX_PHY_CAP_25G_BASER_FEC,
904 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
906 } efx_phy_cap_type_t;
909 #define EFX_PHY_CAP_CURRENT 0x00000000
910 #define EFX_PHY_CAP_DEFAULT 0x00000001
911 #define EFX_PHY_CAP_PERM 0x00000002
917 __out uint32_t *maskp);
919 extern __checkReturn efx_rc_t
927 __out uint32_t *maskp);
929 extern __checkReturn efx_rc_t
932 __out uint32_t *ouip);
934 typedef enum efx_phy_media_type_e {
935 EFX_PHY_MEDIA_INVALID = 0,
940 EFX_PHY_MEDIA_SFP_PLUS,
941 EFX_PHY_MEDIA_BASE_T,
942 EFX_PHY_MEDIA_QSFP_PLUS,
944 } efx_phy_media_type_t;
947 * Get the type of medium currently used. If the board has ports for
948 * modules, a module is present, and we recognise the media type of
949 * the module, then this will be the media type of the module.
950 * Otherwise it will be the media type of the port.
953 efx_phy_media_type_get(
955 __out efx_phy_media_type_t *typep);
957 extern __checkReturn efx_rc_t
958 efx_phy_module_get_info(
960 __in uint8_t dev_addr,
963 __out_bcount(len) uint8_t *data);
965 #if EFSYS_OPT_PHY_STATS
967 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
968 typedef enum efx_phy_stat_e {
970 EFX_PHY_STAT_PMA_PMD_LINK_UP,
971 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
972 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
973 EFX_PHY_STAT_PMA_PMD_REV_A,
974 EFX_PHY_STAT_PMA_PMD_REV_B,
975 EFX_PHY_STAT_PMA_PMD_REV_C,
976 EFX_PHY_STAT_PMA_PMD_REV_D,
977 EFX_PHY_STAT_PCS_LINK_UP,
978 EFX_PHY_STAT_PCS_RX_FAULT,
979 EFX_PHY_STAT_PCS_TX_FAULT,
980 EFX_PHY_STAT_PCS_BER,
981 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
982 EFX_PHY_STAT_PHY_XS_LINK_UP,
983 EFX_PHY_STAT_PHY_XS_RX_FAULT,
984 EFX_PHY_STAT_PHY_XS_TX_FAULT,
985 EFX_PHY_STAT_PHY_XS_ALIGN,
986 EFX_PHY_STAT_PHY_XS_SYNC_A,
987 EFX_PHY_STAT_PHY_XS_SYNC_B,
988 EFX_PHY_STAT_PHY_XS_SYNC_C,
989 EFX_PHY_STAT_PHY_XS_SYNC_D,
990 EFX_PHY_STAT_AN_LINK_UP,
991 EFX_PHY_STAT_AN_MASTER,
992 EFX_PHY_STAT_AN_LOCAL_RX_OK,
993 EFX_PHY_STAT_AN_REMOTE_RX_OK,
994 EFX_PHY_STAT_CL22EXT_LINK_UP,
999 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1000 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1001 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1002 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1003 EFX_PHY_STAT_AN_COMPLETE,
1004 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1005 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1006 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1007 EFX_PHY_STAT_PCS_FW_VERSION_0,
1008 EFX_PHY_STAT_PCS_FW_VERSION_1,
1009 EFX_PHY_STAT_PCS_FW_VERSION_2,
1010 EFX_PHY_STAT_PCS_FW_VERSION_3,
1011 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1012 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1013 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1014 EFX_PHY_STAT_PCS_OP_MODE,
1018 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1024 __in efx_nic_t *enp,
1025 __in efx_phy_stat_t stat);
1027 #endif /* EFSYS_OPT_NAMES */
1029 #define EFX_PHY_STATS_SIZE 0x100
1031 extern __checkReturn efx_rc_t
1032 efx_phy_stats_update(
1033 __in efx_nic_t *enp,
1034 __in efsys_mem_t *esmp,
1035 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1037 #endif /* EFSYS_OPT_PHY_STATS */
1042 typedef enum efx_bist_type_e {
1043 EFX_BIST_TYPE_UNKNOWN,
1044 EFX_BIST_TYPE_PHY_NORMAL,
1045 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1046 EFX_BIST_TYPE_PHY_CABLE_LONG,
1047 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1048 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1049 EFX_BIST_TYPE_REG, /* Test the register memories */
1050 EFX_BIST_TYPE_NTYPES,
1053 typedef enum efx_bist_result_e {
1054 EFX_BIST_RESULT_UNKNOWN,
1055 EFX_BIST_RESULT_RUNNING,
1056 EFX_BIST_RESULT_PASSED,
1057 EFX_BIST_RESULT_FAILED,
1058 } efx_bist_result_t;
1060 typedef enum efx_phy_cable_status_e {
1061 EFX_PHY_CABLE_STATUS_OK,
1062 EFX_PHY_CABLE_STATUS_INVALID,
1063 EFX_PHY_CABLE_STATUS_OPEN,
1064 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1065 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1066 EFX_PHY_CABLE_STATUS_BUSY,
1067 } efx_phy_cable_status_t;
1069 typedef enum efx_bist_value_e {
1070 EFX_BIST_PHY_CABLE_LENGTH_A,
1071 EFX_BIST_PHY_CABLE_LENGTH_B,
1072 EFX_BIST_PHY_CABLE_LENGTH_C,
1073 EFX_BIST_PHY_CABLE_LENGTH_D,
1074 EFX_BIST_PHY_CABLE_STATUS_A,
1075 EFX_BIST_PHY_CABLE_STATUS_B,
1076 EFX_BIST_PHY_CABLE_STATUS_C,
1077 EFX_BIST_PHY_CABLE_STATUS_D,
1078 EFX_BIST_FAULT_CODE,
1080 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1086 EFX_BIST_MEM_EXPECT,
1087 EFX_BIST_MEM_ACTUAL,
1089 EFX_BIST_MEM_ECC_PARITY,
1090 EFX_BIST_MEM_ECC_FATAL,
1094 extern __checkReturn efx_rc_t
1095 efx_bist_enable_offline(
1096 __in efx_nic_t *enp);
1098 extern __checkReturn efx_rc_t
1100 __in efx_nic_t *enp,
1101 __in efx_bist_type_t type);
1103 extern __checkReturn efx_rc_t
1105 __in efx_nic_t *enp,
1106 __in efx_bist_type_t type,
1107 __out efx_bist_result_t *resultp,
1108 __out_opt uint32_t *value_maskp,
1109 __out_ecount_opt(count) unsigned long *valuesp,
1114 __in efx_nic_t *enp,
1115 __in efx_bist_type_t type);
1117 #endif /* EFSYS_OPT_BIST */
1119 #define EFX_FEATURE_IPV6 0x00000001
1120 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1121 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1122 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1123 #define EFX_FEATURE_MCDI 0x00000020
1124 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1125 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1126 #define EFX_FEATURE_TURBO 0x00000100
1127 #define EFX_FEATURE_MCDI_DMA 0x00000200
1128 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1129 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1130 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1131 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1132 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1134 typedef enum efx_tunnel_protocol_e {
1135 EFX_TUNNEL_PROTOCOL_NONE = 0,
1136 EFX_TUNNEL_PROTOCOL_VXLAN,
1137 EFX_TUNNEL_PROTOCOL_GENEVE,
1138 EFX_TUNNEL_PROTOCOL_NVGRE,
1140 } efx_tunnel_protocol_t;
1142 typedef enum efx_vi_window_shift_e {
1143 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1144 EFX_VI_WINDOW_SHIFT_8K = 13,
1145 EFX_VI_WINDOW_SHIFT_16K = 14,
1146 EFX_VI_WINDOW_SHIFT_64K = 16,
1147 } efx_vi_window_shift_t;
1149 typedef struct efx_nic_cfg_s {
1150 uint32_t enc_board_type;
1151 uint32_t enc_phy_type;
1153 char enc_phy_name[21];
1155 char enc_phy_revision[21];
1156 efx_mon_type_t enc_mon_type;
1157 #if EFSYS_OPT_MON_STATS
1158 uint32_t enc_mon_stat_dma_buf_size;
1159 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1161 unsigned int enc_features;
1162 efx_vi_window_shift_t enc_vi_window_shift;
1163 uint8_t enc_mac_addr[6];
1164 uint8_t enc_port; /* PHY port number */
1165 uint32_t enc_intr_vec_base;
1166 uint32_t enc_intr_limit;
1167 uint32_t enc_evq_limit;
1168 uint32_t enc_txq_limit;
1169 uint32_t enc_rxq_limit;
1170 uint32_t enc_txq_max_ndescs;
1171 uint32_t enc_buftbl_limit;
1172 uint32_t enc_piobuf_limit;
1173 uint32_t enc_piobuf_size;
1174 uint32_t enc_piobuf_min_alloc_size;
1175 uint32_t enc_evq_timer_quantum_ns;
1176 uint32_t enc_evq_timer_max_us;
1177 uint32_t enc_clk_mult;
1178 uint32_t enc_rx_prefix_size;
1179 uint32_t enc_rx_buf_align_start;
1180 uint32_t enc_rx_buf_align_end;
1181 uint32_t enc_rx_scale_max_exclusive_contexts;
1182 #if EFSYS_OPT_LOOPBACK
1183 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1184 #endif /* EFSYS_OPT_LOOPBACK */
1185 #if EFSYS_OPT_PHY_FLAGS
1186 uint32_t enc_phy_flags_mask;
1187 #endif /* EFSYS_OPT_PHY_FLAGS */
1188 #if EFSYS_OPT_PHY_LED_CONTROL
1189 uint32_t enc_led_mask;
1190 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1191 #if EFSYS_OPT_PHY_STATS
1192 uint64_t enc_phy_stat_mask;
1193 #endif /* EFSYS_OPT_PHY_STATS */
1195 uint8_t enc_mcdi_mdio_channel;
1196 #if EFSYS_OPT_PHY_STATS
1197 uint32_t enc_mcdi_phy_stat_mask;
1198 #endif /* EFSYS_OPT_PHY_STATS */
1199 #if EFSYS_OPT_MON_STATS
1200 uint32_t *enc_mcdi_sensor_maskp;
1201 uint32_t enc_mcdi_sensor_mask_size;
1202 #endif /* EFSYS_OPT_MON_STATS */
1203 #endif /* EFSYS_OPT_MCDI */
1205 uint32_t enc_bist_mask;
1206 #endif /* EFSYS_OPT_BIST */
1207 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1210 uint32_t enc_privilege_mask;
1211 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1212 boolean_t enc_bug26807_workaround;
1213 boolean_t enc_bug35388_workaround;
1214 boolean_t enc_bug41750_workaround;
1215 boolean_t enc_bug61265_workaround;
1216 boolean_t enc_rx_batching_enabled;
1217 /* Maximum number of descriptors completed in an rx event. */
1218 uint32_t enc_rx_batch_max;
1219 /* Number of rx descriptors the hardware requires for a push. */
1220 uint32_t enc_rx_push_align;
1221 /* Maximum amount of data in DMA descriptor */
1222 uint32_t enc_tx_dma_desc_size_max;
1224 * Boundary which DMA descriptor data must not cross or 0 if no
1227 uint32_t enc_tx_dma_desc_boundary;
1229 * Maximum number of bytes into the packet the TCP header can start for
1230 * the hardware to apply TSO packet edits.
1232 uint32_t enc_tx_tso_tcp_header_offset_limit;
1233 boolean_t enc_fw_assisted_tso_enabled;
1234 boolean_t enc_fw_assisted_tso_v2_enabled;
1235 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1236 /* Number of TSO contexts on the NIC (FATSOv2) */
1237 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1238 boolean_t enc_hw_tx_insert_vlan_enabled;
1239 /* Number of PFs on the NIC */
1240 uint32_t enc_hw_pf_count;
1241 /* Datapath firmware vadapter/vport/vswitch support */
1242 boolean_t enc_datapath_cap_evb;
1243 boolean_t enc_rx_disable_scatter_supported;
1244 boolean_t enc_allow_set_mac_with_installed_filters;
1245 boolean_t enc_enhanced_set_mac_supported;
1246 boolean_t enc_init_evq_v2_supported;
1247 boolean_t enc_rx_packed_stream_supported;
1248 boolean_t enc_rx_var_packed_stream_supported;
1249 boolean_t enc_pm_and_rxdp_counters;
1250 boolean_t enc_mac_stats_40g_tx_size_bins;
1251 uint32_t enc_tunnel_encapsulations_supported;
1253 * NIC global maximum for unique UDP tunnel ports shared by all
1256 uint32_t enc_tunnel_config_udp_entries_max;
1257 /* External port identifier */
1258 uint8_t enc_external_port;
1259 uint32_t enc_mcdi_max_payload_length;
1260 /* VPD may be per-PF or global */
1261 boolean_t enc_vpd_is_global;
1262 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1263 uint32_t enc_required_pcie_bandwidth_mbps;
1264 uint32_t enc_max_pcie_link_gen;
1265 /* Firmware verifies integrity of NVRAM updates */
1266 uint32_t enc_nvram_update_verify_result_supported;
1267 /* Firmware support for extended MAC_STATS buffer */
1268 uint32_t enc_mac_stats_nstats;
1269 boolean_t enc_fec_counters;
1272 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1273 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1275 #define EFX_PCI_FUNCTION(_encp) \
1276 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1278 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1280 extern const efx_nic_cfg_t *
1282 __in efx_nic_t *enp);
1284 typedef struct efx_nic_fw_info_s {
1285 /* Basic FW version information */
1286 uint16_t enfi_mc_fw_version[4];
1288 * If datapath capabilities can be detected,
1289 * additional FW information is to be shown
1291 boolean_t enfi_dpcpu_fw_ids_valid;
1292 /* Rx and Tx datapath CPU FW IDs */
1293 uint16_t enfi_rx_dpcpu_fw_id;
1294 uint16_t enfi_tx_dpcpu_fw_id;
1295 } efx_nic_fw_info_t;
1297 extern __checkReturn efx_rc_t
1298 efx_nic_get_fw_version(
1299 __in efx_nic_t *enp,
1300 __out efx_nic_fw_info_t *enfip);
1302 /* Driver resource limits (minimum required/maximum usable). */
1303 typedef struct efx_drv_limits_s {
1304 uint32_t edl_min_evq_count;
1305 uint32_t edl_max_evq_count;
1307 uint32_t edl_min_rxq_count;
1308 uint32_t edl_max_rxq_count;
1310 uint32_t edl_min_txq_count;
1311 uint32_t edl_max_txq_count;
1313 /* PIO blocks (sub-allocated from piobuf) */
1314 uint32_t edl_min_pio_alloc_size;
1315 uint32_t edl_max_pio_alloc_count;
1318 extern __checkReturn efx_rc_t
1319 efx_nic_set_drv_limits(
1320 __inout efx_nic_t *enp,
1321 __in efx_drv_limits_t *edlp);
1323 typedef enum efx_nic_region_e {
1324 EFX_REGION_VI, /* Memory BAR UC mapping */
1325 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1328 extern __checkReturn efx_rc_t
1329 efx_nic_get_bar_region(
1330 __in efx_nic_t *enp,
1331 __in efx_nic_region_t region,
1332 __out uint32_t *offsetp,
1333 __out size_t *sizep);
1335 extern __checkReturn efx_rc_t
1336 efx_nic_get_vi_pool(
1337 __in efx_nic_t *enp,
1338 __out uint32_t *evq_countp,
1339 __out uint32_t *rxq_countp,
1340 __out uint32_t *txq_countp);
1345 typedef enum efx_vpd_tag_e {
1352 typedef uint16_t efx_vpd_keyword_t;
1354 typedef struct efx_vpd_value_s {
1355 efx_vpd_tag_t evv_tag;
1356 efx_vpd_keyword_t evv_keyword;
1358 uint8_t evv_value[0x100];
1362 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1364 extern __checkReturn efx_rc_t
1366 __in efx_nic_t *enp);
1368 extern __checkReturn efx_rc_t
1370 __in efx_nic_t *enp,
1371 __out size_t *sizep);
1373 extern __checkReturn efx_rc_t
1375 __in efx_nic_t *enp,
1376 __out_bcount(size) caddr_t data,
1379 extern __checkReturn efx_rc_t
1381 __in efx_nic_t *enp,
1382 __in_bcount(size) caddr_t data,
1385 extern __checkReturn efx_rc_t
1387 __in efx_nic_t *enp,
1388 __in_bcount(size) caddr_t data,
1391 extern __checkReturn efx_rc_t
1393 __in efx_nic_t *enp,
1394 __in_bcount(size) caddr_t data,
1396 __inout efx_vpd_value_t *evvp);
1398 extern __checkReturn efx_rc_t
1400 __in efx_nic_t *enp,
1401 __inout_bcount(size) caddr_t data,
1403 __in efx_vpd_value_t *evvp);
1405 extern __checkReturn efx_rc_t
1407 __in efx_nic_t *enp,
1408 __inout_bcount(size) caddr_t data,
1410 __out efx_vpd_value_t *evvp,
1411 __inout unsigned int *contp);
1413 extern __checkReturn efx_rc_t
1415 __in efx_nic_t *enp,
1416 __in_bcount(size) caddr_t data,
1421 __in efx_nic_t *enp);
1423 #endif /* EFSYS_OPT_VPD */
1429 typedef enum efx_nvram_type_e {
1430 EFX_NVRAM_INVALID = 0,
1432 EFX_NVRAM_BOOTROM_CFG,
1433 EFX_NVRAM_MC_FIRMWARE,
1434 EFX_NVRAM_MC_GOLDEN,
1440 EFX_NVRAM_FPGA_BACKUP,
1441 EFX_NVRAM_DYNAMIC_CFG,
1444 EFX_NVRAM_MUM_FIRMWARE,
1448 extern __checkReturn efx_rc_t
1450 __in efx_nic_t *enp);
1454 extern __checkReturn efx_rc_t
1456 __in efx_nic_t *enp);
1458 #endif /* EFSYS_OPT_DIAG */
1460 extern __checkReturn efx_rc_t
1462 __in efx_nic_t *enp,
1463 __in efx_nvram_type_t type,
1464 __out size_t *sizep);
1466 extern __checkReturn efx_rc_t
1468 __in efx_nic_t *enp,
1469 __in efx_nvram_type_t type,
1470 __out_opt size_t *pref_chunkp);
1472 extern __checkReturn efx_rc_t
1473 efx_nvram_rw_finish(
1474 __in efx_nic_t *enp,
1475 __in efx_nvram_type_t type,
1476 __out_opt uint32_t *verify_resultp);
1478 extern __checkReturn efx_rc_t
1479 efx_nvram_get_version(
1480 __in efx_nic_t *enp,
1481 __in efx_nvram_type_t type,
1482 __out uint32_t *subtypep,
1483 __out_ecount(4) uint16_t version[4]);
1485 extern __checkReturn efx_rc_t
1486 efx_nvram_read_chunk(
1487 __in efx_nic_t *enp,
1488 __in efx_nvram_type_t type,
1489 __in unsigned int offset,
1490 __out_bcount(size) caddr_t data,
1493 extern __checkReturn efx_rc_t
1494 efx_nvram_read_backup(
1495 __in efx_nic_t *enp,
1496 __in efx_nvram_type_t type,
1497 __in unsigned int offset,
1498 __out_bcount(size) caddr_t data,
1501 extern __checkReturn efx_rc_t
1502 efx_nvram_set_version(
1503 __in efx_nic_t *enp,
1504 __in efx_nvram_type_t type,
1505 __in_ecount(4) uint16_t version[4]);
1507 extern __checkReturn efx_rc_t
1509 __in efx_nic_t *enp,
1510 __in efx_nvram_type_t type,
1511 __in_bcount(partn_size) caddr_t partn_data,
1512 __in size_t partn_size);
1514 extern __checkReturn efx_rc_t
1516 __in efx_nic_t *enp,
1517 __in efx_nvram_type_t type);
1519 extern __checkReturn efx_rc_t
1520 efx_nvram_write_chunk(
1521 __in efx_nic_t *enp,
1522 __in efx_nvram_type_t type,
1523 __in unsigned int offset,
1524 __in_bcount(size) caddr_t data,
1529 __in efx_nic_t *enp);
1531 #endif /* EFSYS_OPT_NVRAM */
1533 #if EFSYS_OPT_BOOTCFG
1535 /* Report size and offset of bootcfg sector in NVRAM partition. */
1536 extern __checkReturn efx_rc_t
1537 efx_bootcfg_sector_info(
1538 __in efx_nic_t *enp,
1540 __out_opt uint32_t *sector_countp,
1541 __out size_t *offsetp,
1542 __out size_t *max_sizep);
1545 * Copy bootcfg sector data to a target buffer which may differ in size.
1546 * Optionally corrects format errors in source buffer.
1549 efx_bootcfg_copy_sector(
1550 __in efx_nic_t *enp,
1551 __inout_bcount(sector_length)
1553 __in size_t sector_length,
1554 __out_bcount(data_size) uint8_t *data,
1555 __in size_t data_size,
1556 __in boolean_t handle_format_errors);
1560 __in efx_nic_t *enp,
1561 __out_bcount(size) uint8_t *data,
1566 __in efx_nic_t *enp,
1567 __in_bcount(size) uint8_t *data,
1570 #endif /* EFSYS_OPT_BOOTCFG */
1572 #if EFSYS_OPT_IMAGE_LAYOUT
1574 #include "ef10_signed_image_layout.h"
1577 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1580 * The image header format is extensible. However, older drivers require an
1581 * exact match of image header version and header length when validating and
1582 * writing firmware images.
1584 * To avoid breaking backward compatibility, we use the upper bits of the
1585 * controller version fields to contain an extra version number used for
1586 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1587 * version). See bug39254 and SF-102785-PS for details.
1589 typedef struct efx_image_header_s {
1591 uint32_t eih_version;
1593 uint32_t eih_subtype;
1594 uint32_t eih_code_size;
1597 uint32_t eih_controller_version_min;
1599 uint16_t eih_controller_version_min_short;
1600 uint8_t eih_extra_version_a;
1601 uint8_t eih_extra_version_b;
1605 uint32_t eih_controller_version_max;
1607 uint16_t eih_controller_version_max_short;
1608 uint8_t eih_extra_version_c;
1609 uint8_t eih_extra_version_d;
1612 uint16_t eih_code_version_a;
1613 uint16_t eih_code_version_b;
1614 uint16_t eih_code_version_c;
1615 uint16_t eih_code_version_d;
1616 } efx_image_header_t;
1618 #define EFX_IMAGE_HEADER_SIZE (40)
1619 #define EFX_IMAGE_HEADER_VERSION (4)
1620 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1623 typedef struct efx_image_trailer_s {
1625 } efx_image_trailer_t;
1627 #define EFX_IMAGE_TRAILER_SIZE (4)
1629 typedef enum efx_image_format_e {
1630 EFX_IMAGE_FORMAT_NO_IMAGE,
1631 EFX_IMAGE_FORMAT_INVALID,
1632 EFX_IMAGE_FORMAT_UNSIGNED,
1633 EFX_IMAGE_FORMAT_SIGNED,
1634 } efx_image_format_t;
1636 typedef struct efx_image_info_s {
1637 efx_image_format_t eii_format;
1638 uint8_t * eii_imagep;
1639 size_t eii_image_size;
1640 efx_image_header_t * eii_headerp;
1643 extern __checkReturn efx_rc_t
1644 efx_check_reflash_image(
1646 __in uint32_t buffer_size,
1647 __out efx_image_info_t *infop);
1649 extern __checkReturn efx_rc_t
1650 efx_build_signed_image_write_buffer(
1651 __out uint8_t *bufferp,
1652 __in uint32_t buffer_size,
1653 __in efx_image_info_t *infop,
1654 __out efx_image_header_t **headerpp);
1656 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1660 typedef enum efx_pattern_type_t {
1661 EFX_PATTERN_BYTE_INCREMENT = 0,
1662 EFX_PATTERN_ALL_THE_SAME,
1663 EFX_PATTERN_BIT_ALTERNATE,
1664 EFX_PATTERN_BYTE_ALTERNATE,
1665 EFX_PATTERN_BYTE_CHANGING,
1666 EFX_PATTERN_BIT_SWEEP,
1668 } efx_pattern_type_t;
1671 (*efx_sram_pattern_fn_t)(
1673 __in boolean_t negate,
1674 __out efx_qword_t *eqp);
1676 extern __checkReturn efx_rc_t
1678 __in efx_nic_t *enp,
1679 __in efx_pattern_type_t type);
1681 #endif /* EFSYS_OPT_DIAG */
1683 extern __checkReturn efx_rc_t
1684 efx_sram_buf_tbl_set(
1685 __in efx_nic_t *enp,
1687 __in efsys_mem_t *esmp,
1691 efx_sram_buf_tbl_clear(
1692 __in efx_nic_t *enp,
1696 #define EFX_BUF_TBL_SIZE 0x20000
1698 #define EFX_BUF_SIZE 4096
1702 typedef struct efx_evq_s efx_evq_t;
1704 #if EFSYS_OPT_QSTATS
1706 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1707 typedef enum efx_ev_qstat_e {
1713 EV_RX_PAUSE_FRM_ERR,
1714 EV_RX_BUF_OWNER_ID_ERR,
1715 EV_RX_IPV4_HDR_CHKSUM_ERR,
1716 EV_RX_TCP_UDP_CHKSUM_ERR,
1720 EV_RX_MCAST_HASH_MATCH,
1737 EV_DRIVER_SRM_UPD_DONE,
1738 EV_DRIVER_TX_DESCQ_FLS_DONE,
1739 EV_DRIVER_RX_DESCQ_FLS_DONE,
1740 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1741 EV_DRIVER_RX_DSC_ERROR,
1742 EV_DRIVER_TX_DSC_ERROR,
1748 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1750 #endif /* EFSYS_OPT_QSTATS */
1752 extern __checkReturn efx_rc_t
1754 __in efx_nic_t *enp);
1758 __in efx_nic_t *enp);
1760 #define EFX_EVQ_MAXNEVS 32768
1761 #define EFX_EVQ_MINNEVS 512
1763 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1764 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1766 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1767 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1768 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1769 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1771 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1772 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1773 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1775 extern __checkReturn efx_rc_t
1777 __in efx_nic_t *enp,
1778 __in unsigned int index,
1779 __in efsys_mem_t *esmp,
1783 __in uint32_t flags,
1784 __deref_out efx_evq_t **eepp);
1788 __in efx_evq_t *eep,
1789 __in uint16_t data);
1791 typedef __checkReturn boolean_t
1792 (*efx_initialized_ev_t)(
1793 __in_opt void *arg);
1795 #define EFX_PKT_UNICAST 0x0004
1796 #define EFX_PKT_START 0x0008
1798 #define EFX_PKT_VLAN_TAGGED 0x0010
1799 #define EFX_CKSUM_TCPUDP 0x0020
1800 #define EFX_CKSUM_IPV4 0x0040
1801 #define EFX_PKT_CONT 0x0080
1803 #define EFX_CHECK_VLAN 0x0100
1804 #define EFX_PKT_TCP 0x0200
1805 #define EFX_PKT_UDP 0x0400
1806 #define EFX_PKT_IPV4 0x0800
1808 #define EFX_PKT_IPV6 0x1000
1809 #define EFX_PKT_PREFIX_LEN 0x2000
1810 #define EFX_ADDR_MISMATCH 0x4000
1811 #define EFX_DISCARD 0x8000
1814 * The following flags are used only for packed stream
1815 * mode. The values for the flags are reused to fit into 16 bit,
1816 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1817 * packed stream mode
1819 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1820 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1823 #define EFX_EV_RX_NLABELS 32
1824 #define EFX_EV_TX_NLABELS 32
1826 typedef __checkReturn boolean_t
1829 __in uint32_t label,
1832 __in uint16_t flags);
1834 #if EFSYS_OPT_RX_PACKED_STREAM
1837 * Packed stream mode is documented in SF-112241-TC.
1838 * The general idea is that, instead of putting each incoming
1839 * packet into a separate buffer which is specified in a RX
1840 * descriptor, a large buffer is provided to the hardware and
1841 * packets are put there in a continuous stream.
1842 * The main advantage of such an approach is that RX queue refilling
1843 * happens much less frequently.
1846 typedef __checkReturn boolean_t
1849 __in uint32_t label,
1851 __in uint32_t pkt_count,
1852 __in uint16_t flags);
1856 typedef __checkReturn boolean_t
1859 __in uint32_t label,
1862 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1863 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1864 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1865 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1866 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1867 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1868 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1869 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1870 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1872 typedef __checkReturn boolean_t
1873 (*efx_exception_ev_t)(
1875 __in uint32_t label,
1876 __in uint32_t data);
1878 typedef __checkReturn boolean_t
1879 (*efx_rxq_flush_done_ev_t)(
1881 __in uint32_t rxq_index);
1883 typedef __checkReturn boolean_t
1884 (*efx_rxq_flush_failed_ev_t)(
1886 __in uint32_t rxq_index);
1888 typedef __checkReturn boolean_t
1889 (*efx_txq_flush_done_ev_t)(
1891 __in uint32_t txq_index);
1893 typedef __checkReturn boolean_t
1894 (*efx_software_ev_t)(
1896 __in uint16_t magic);
1898 typedef __checkReturn boolean_t
1901 __in uint32_t code);
1903 #define EFX_SRAM_CLEAR 0
1904 #define EFX_SRAM_UPDATE 1
1905 #define EFX_SRAM_ILLEGAL_CLEAR 2
1907 typedef __checkReturn boolean_t
1908 (*efx_wake_up_ev_t)(
1910 __in uint32_t label);
1912 typedef __checkReturn boolean_t
1915 __in uint32_t label);
1917 typedef __checkReturn boolean_t
1918 (*efx_link_change_ev_t)(
1920 __in efx_link_mode_t link_mode);
1922 #if EFSYS_OPT_MON_STATS
1924 typedef __checkReturn boolean_t
1925 (*efx_monitor_ev_t)(
1927 __in efx_mon_stat_t id,
1928 __in efx_mon_stat_value_t value);
1930 #endif /* EFSYS_OPT_MON_STATS */
1932 #if EFSYS_OPT_MAC_STATS
1934 typedef __checkReturn boolean_t
1935 (*efx_mac_stats_ev_t)(
1937 __in uint32_t generation);
1939 #endif /* EFSYS_OPT_MAC_STATS */
1941 typedef struct efx_ev_callbacks_s {
1942 efx_initialized_ev_t eec_initialized;
1944 #if EFSYS_OPT_RX_PACKED_STREAM
1945 efx_rx_ps_ev_t eec_rx_ps;
1948 efx_exception_ev_t eec_exception;
1949 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1950 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1951 efx_txq_flush_done_ev_t eec_txq_flush_done;
1952 efx_software_ev_t eec_software;
1953 efx_sram_ev_t eec_sram;
1954 efx_wake_up_ev_t eec_wake_up;
1955 efx_timer_ev_t eec_timer;
1956 efx_link_change_ev_t eec_link_change;
1957 #if EFSYS_OPT_MON_STATS
1958 efx_monitor_ev_t eec_monitor;
1959 #endif /* EFSYS_OPT_MON_STATS */
1960 #if EFSYS_OPT_MAC_STATS
1961 efx_mac_stats_ev_t eec_mac_stats;
1962 #endif /* EFSYS_OPT_MAC_STATS */
1963 } efx_ev_callbacks_t;
1965 extern __checkReturn boolean_t
1967 __in efx_evq_t *eep,
1968 __in unsigned int count);
1970 #if EFSYS_OPT_EV_PREFETCH
1974 __in efx_evq_t *eep,
1975 __in unsigned int count);
1977 #endif /* EFSYS_OPT_EV_PREFETCH */
1981 __in efx_evq_t *eep,
1982 __inout unsigned int *countp,
1983 __in const efx_ev_callbacks_t *eecp,
1984 __in_opt void *arg);
1986 extern __checkReturn efx_rc_t
1987 efx_ev_usecs_to_ticks(
1988 __in efx_nic_t *enp,
1989 __in unsigned int usecs,
1990 __out unsigned int *ticksp);
1992 extern __checkReturn efx_rc_t
1994 __in efx_evq_t *eep,
1995 __in unsigned int us);
1997 extern __checkReturn efx_rc_t
1999 __in efx_evq_t *eep,
2000 __in unsigned int count);
2002 #if EFSYS_OPT_QSTATS
2008 __in efx_nic_t *enp,
2009 __in unsigned int id);
2011 #endif /* EFSYS_OPT_NAMES */
2014 efx_ev_qstats_update(
2015 __in efx_evq_t *eep,
2016 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2018 #endif /* EFSYS_OPT_QSTATS */
2022 __in efx_evq_t *eep);
2026 extern __checkReturn efx_rc_t
2028 __inout efx_nic_t *enp);
2032 __in efx_nic_t *enp);
2034 #if EFSYS_OPT_RX_SCATTER
2035 __checkReturn efx_rc_t
2036 efx_rx_scatter_enable(
2037 __in efx_nic_t *enp,
2038 __in unsigned int buf_size);
2039 #endif /* EFSYS_OPT_RX_SCATTER */
2041 /* Handle to represent use of the default RSS context. */
2042 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2044 #if EFSYS_OPT_RX_SCALE
2046 typedef enum efx_rx_hash_alg_e {
2047 EFX_RX_HASHALG_LFSR = 0,
2048 EFX_RX_HASHALG_TOEPLITZ
2049 } efx_rx_hash_alg_t;
2051 #define EFX_RX_HASH_IPV4 (1U << 0)
2052 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2053 #define EFX_RX_HASH_IPV6 (1U << 2)
2054 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2056 typedef unsigned int efx_rx_hash_type_t;
2058 typedef enum efx_rx_hash_support_e {
2059 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2060 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2061 } efx_rx_hash_support_t;
2063 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2064 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2065 #define EFX_MAXRSS 64 /* RX indirection entry range */
2066 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2068 typedef enum efx_rx_scale_context_type_e {
2069 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2070 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2071 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2072 } efx_rx_scale_context_type_t;
2074 extern __checkReturn efx_rc_t
2075 efx_rx_hash_default_support_get(
2076 __in efx_nic_t *enp,
2077 __out efx_rx_hash_support_t *supportp);
2080 extern __checkReturn efx_rc_t
2081 efx_rx_scale_default_support_get(
2082 __in efx_nic_t *enp,
2083 __out efx_rx_scale_context_type_t *typep);
2085 extern __checkReturn efx_rc_t
2086 efx_rx_scale_context_alloc(
2087 __in efx_nic_t *enp,
2088 __in efx_rx_scale_context_type_t type,
2089 __in uint32_t num_queues,
2090 __out uint32_t *rss_contextp);
2092 extern __checkReturn efx_rc_t
2093 efx_rx_scale_context_free(
2094 __in efx_nic_t *enp,
2095 __in uint32_t rss_context);
2097 extern __checkReturn efx_rc_t
2098 efx_rx_scale_mode_set(
2099 __in efx_nic_t *enp,
2100 __in uint32_t rss_context,
2101 __in efx_rx_hash_alg_t alg,
2102 __in efx_rx_hash_type_t type,
2103 __in boolean_t insert);
2105 extern __checkReturn efx_rc_t
2106 efx_rx_scale_tbl_set(
2107 __in efx_nic_t *enp,
2108 __in uint32_t rss_context,
2109 __in_ecount(n) unsigned int *table,
2112 extern __checkReturn efx_rc_t
2113 efx_rx_scale_key_set(
2114 __in efx_nic_t *enp,
2115 __in uint32_t rss_context,
2116 __in_ecount(n) uint8_t *key,
2119 extern __checkReturn uint32_t
2120 efx_pseudo_hdr_hash_get(
2121 __in efx_rxq_t *erp,
2122 __in efx_rx_hash_alg_t func,
2123 __in uint8_t *buffer);
2125 #endif /* EFSYS_OPT_RX_SCALE */
2127 extern __checkReturn efx_rc_t
2128 efx_pseudo_hdr_pkt_length_get(
2129 __in efx_rxq_t *erp,
2130 __in uint8_t *buffer,
2131 __out uint16_t *pkt_lengthp);
2133 #define EFX_RXQ_MAXNDESCS 4096
2134 #define EFX_RXQ_MINNDESCS 512
2136 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2137 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2138 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2139 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2141 typedef enum efx_rxq_type_e {
2142 EFX_RXQ_TYPE_DEFAULT,
2143 EFX_RXQ_TYPE_PACKED_STREAM,
2148 * Dummy flag to be used instead of 0 to make it clear that the argument
2149 * is receive queue flags.
2151 #define EFX_RXQ_FLAG_NONE 0x0
2152 #define EFX_RXQ_FLAG_SCATTER 0x1
2154 * If tunnels are supported and Rx event can provide information about
2155 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2156 * full-feature firmware variant running), outer classes are requested by
2157 * default. However, if the driver supports tunnels, the flag allows to
2158 * request inner classes which are required to be able to interpret inner
2159 * Rx checksum offload results.
2161 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2163 extern __checkReturn efx_rc_t
2165 __in efx_nic_t *enp,
2166 __in unsigned int index,
2167 __in unsigned int label,
2168 __in efx_rxq_type_t type,
2169 __in efsys_mem_t *esmp,
2172 __in unsigned int flags,
2173 __in efx_evq_t *eep,
2174 __deref_out efx_rxq_t **erpp);
2176 #if EFSYS_OPT_RX_PACKED_STREAM
2178 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2179 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2180 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2181 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2182 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2184 extern __checkReturn efx_rc_t
2185 efx_rx_qcreate_packed_stream(
2186 __in efx_nic_t *enp,
2187 __in unsigned int index,
2188 __in unsigned int label,
2189 __in uint32_t ps_buf_size,
2190 __in efsys_mem_t *esmp,
2192 __in efx_evq_t *eep,
2193 __deref_out efx_rxq_t **erpp);
2197 typedef struct efx_buffer_s {
2198 efsys_dma_addr_t eb_addr;
2203 typedef struct efx_desc_s {
2209 __in efx_rxq_t *erp,
2210 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2212 __in unsigned int ndescs,
2213 __in unsigned int completed,
2214 __in unsigned int added);
2218 __in efx_rxq_t *erp,
2219 __in unsigned int added,
2220 __inout unsigned int *pushedp);
2222 #if EFSYS_OPT_RX_PACKED_STREAM
2225 efx_rx_qpush_ps_credits(
2226 __in efx_rxq_t *erp);
2228 extern __checkReturn uint8_t *
2229 efx_rx_qps_packet_info(
2230 __in efx_rxq_t *erp,
2231 __in uint8_t *buffer,
2232 __in uint32_t buffer_length,
2233 __in uint32_t current_offset,
2234 __out uint16_t *lengthp,
2235 __out uint32_t *next_offsetp,
2236 __out uint32_t *timestamp);
2239 extern __checkReturn efx_rc_t
2241 __in efx_rxq_t *erp);
2245 __in efx_rxq_t *erp);
2249 __in efx_rxq_t *erp);
2253 typedef struct efx_txq_s efx_txq_t;
2255 #if EFSYS_OPT_QSTATS
2257 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2258 typedef enum efx_tx_qstat_e {
2264 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2266 #endif /* EFSYS_OPT_QSTATS */
2268 extern __checkReturn efx_rc_t
2270 __in efx_nic_t *enp);
2274 __in efx_nic_t *enp);
2276 #define EFX_TXQ_MINNDESCS 512
2278 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2279 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2280 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2282 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2284 #define EFX_TXQ_CKSUM_IPV4 0x0001
2285 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2286 #define EFX_TXQ_FATSOV2 0x0004
2287 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2288 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2290 extern __checkReturn efx_rc_t
2292 __in efx_nic_t *enp,
2293 __in unsigned int index,
2294 __in unsigned int label,
2295 __in efsys_mem_t *esmp,
2298 __in uint16_t flags,
2299 __in efx_evq_t *eep,
2300 __deref_out efx_txq_t **etpp,
2301 __out unsigned int *addedp);
2303 extern __checkReturn efx_rc_t
2305 __in efx_txq_t *etp,
2306 __in_ecount(ndescs) efx_buffer_t *eb,
2307 __in unsigned int ndescs,
2308 __in unsigned int completed,
2309 __inout unsigned int *addedp);
2311 extern __checkReturn efx_rc_t
2313 __in efx_txq_t *etp,
2314 __in unsigned int ns);
2318 __in efx_txq_t *etp,
2319 __in unsigned int added,
2320 __in unsigned int pushed);
2322 extern __checkReturn efx_rc_t
2324 __in efx_txq_t *etp);
2328 __in efx_txq_t *etp);
2330 extern __checkReturn efx_rc_t
2332 __in efx_txq_t *etp);
2335 efx_tx_qpio_disable(
2336 __in efx_txq_t *etp);
2338 extern __checkReturn efx_rc_t
2340 __in efx_txq_t *etp,
2341 __in_ecount(buf_length) uint8_t *buffer,
2342 __in size_t buf_length,
2343 __in size_t pio_buf_offset);
2345 extern __checkReturn efx_rc_t
2347 __in efx_txq_t *etp,
2348 __in size_t pkt_length,
2349 __in unsigned int completed,
2350 __inout unsigned int *addedp);
2352 extern __checkReturn efx_rc_t
2354 __in efx_txq_t *etp,
2355 __in_ecount(n) efx_desc_t *ed,
2356 __in unsigned int n,
2357 __in unsigned int completed,
2358 __inout unsigned int *addedp);
2361 efx_tx_qdesc_dma_create(
2362 __in efx_txq_t *etp,
2363 __in efsys_dma_addr_t addr,
2366 __out efx_desc_t *edp);
2369 efx_tx_qdesc_tso_create(
2370 __in efx_txq_t *etp,
2371 __in uint16_t ipv4_id,
2372 __in uint32_t tcp_seq,
2373 __in uint8_t tcp_flags,
2374 __out efx_desc_t *edp);
2376 /* Number of FATSOv2 option descriptors */
2377 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2379 /* Maximum number of DMA segments per TSO packet (not superframe) */
2380 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2383 efx_tx_qdesc_tso2_create(
2384 __in efx_txq_t *etp,
2385 __in uint16_t ipv4_id,
2386 __in uint16_t outer_ipv4_id,
2387 __in uint32_t tcp_seq,
2388 __in uint16_t tcp_mss,
2389 __out_ecount(count) efx_desc_t *edp,
2393 efx_tx_qdesc_vlantci_create(
2394 __in efx_txq_t *etp,
2396 __out efx_desc_t *edp);
2399 efx_tx_qdesc_checksum_create(
2400 __in efx_txq_t *etp,
2401 __in uint16_t flags,
2402 __out efx_desc_t *edp);
2404 #if EFSYS_OPT_QSTATS
2410 __in efx_nic_t *etp,
2411 __in unsigned int id);
2413 #endif /* EFSYS_OPT_NAMES */
2416 efx_tx_qstats_update(
2417 __in efx_txq_t *etp,
2418 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2420 #endif /* EFSYS_OPT_QSTATS */
2424 __in efx_txq_t *etp);
2429 #if EFSYS_OPT_FILTER
2431 #define EFX_ETHER_TYPE_IPV4 0x0800
2432 #define EFX_ETHER_TYPE_IPV6 0x86DD
2434 #define EFX_IPPROTO_TCP 6
2435 #define EFX_IPPROTO_UDP 17
2436 #define EFX_IPPROTO_GRE 47
2438 /* Use RSS to spread across multiple queues */
2439 #define EFX_FILTER_FLAG_RX_RSS 0x01
2440 /* Enable RX scatter */
2441 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2443 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2444 * May only be set by the filter implementation for each type.
2445 * A removal request will restore the automatic filter in its place.
2447 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2448 /* Filter is for RX */
2449 #define EFX_FILTER_FLAG_RX 0x08
2450 /* Filter is for TX */
2451 #define EFX_FILTER_FLAG_TX 0x10
2453 typedef uint8_t efx_filter_flags_t;
2456 * Flags which specify the fields to match on. The values are the same as in the
2457 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2460 /* Match by remote IP host address */
2461 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2462 /* Match by local IP host address */
2463 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2464 /* Match by remote MAC address */
2465 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2466 /* Match by remote TCP/UDP port */
2467 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2468 /* Match by remote TCP/UDP port */
2469 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2470 /* Match by local TCP/UDP port */
2471 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2472 /* Match by Ether-type */
2473 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2474 /* Match by inner VLAN ID */
2475 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2476 /* Match by outer VLAN ID */
2477 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2478 /* Match by IP transport protocol */
2479 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2480 /* Match by VNI or VSID */
2481 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2482 /* For encapsulated packets, match by inner frame local MAC address */
2483 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2484 /* For encapsulated packets, match all multicast inner frames */
2485 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2486 /* For encapsulated packets, match all unicast inner frames */
2487 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2489 * Match by encap type, this flag does not correspond to
2490 * the MCDI match flags and any unoccupied value may be used
2492 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2493 /* Match otherwise-unmatched multicast and broadcast packets */
2494 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2495 /* Match otherwise-unmatched unicast packets */
2496 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2498 typedef uint32_t efx_filter_match_flags_t;
2500 typedef enum efx_filter_priority_s {
2501 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2502 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2503 * address list or hardware
2504 * requirements. This may only be used
2505 * by the filter implementation for
2507 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2508 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2509 * client (e.g. SR-IOV, HyperV VMQ etc.)
2511 } efx_filter_priority_t;
2514 * FIXME: All these fields are assumed to be in little-endian byte order.
2515 * It may be better for some to be big-endian. See bug42804.
2518 typedef struct efx_filter_spec_s {
2519 efx_filter_match_flags_t efs_match_flags;
2520 uint8_t efs_priority;
2521 efx_filter_flags_t efs_flags;
2522 uint16_t efs_dmaq_id;
2523 uint32_t efs_rss_context;
2524 uint16_t efs_outer_vid;
2525 uint16_t efs_inner_vid;
2526 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2527 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2528 uint16_t efs_ether_type;
2529 uint8_t efs_ip_proto;
2530 efx_tunnel_protocol_t efs_encap_type;
2531 uint16_t efs_loc_port;
2532 uint16_t efs_rem_port;
2533 efx_oword_t efs_rem_host;
2534 efx_oword_t efs_loc_host;
2535 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2536 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2537 } efx_filter_spec_t;
2540 /* Default values for use in filter specifications */
2541 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2542 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2544 extern __checkReturn efx_rc_t
2546 __in efx_nic_t *enp);
2550 __in efx_nic_t *enp);
2552 extern __checkReturn efx_rc_t
2554 __in efx_nic_t *enp,
2555 __inout efx_filter_spec_t *spec);
2557 extern __checkReturn efx_rc_t
2559 __in efx_nic_t *enp,
2560 __inout efx_filter_spec_t *spec);
2562 extern __checkReturn efx_rc_t
2564 __in efx_nic_t *enp);
2566 extern __checkReturn efx_rc_t
2567 efx_filter_supported_filters(
2568 __in efx_nic_t *enp,
2569 __out_ecount(buffer_length) uint32_t *buffer,
2570 __in size_t buffer_length,
2571 __out size_t *list_lengthp);
2574 efx_filter_spec_init_rx(
2575 __out efx_filter_spec_t *spec,
2576 __in efx_filter_priority_t priority,
2577 __in efx_filter_flags_t flags,
2578 __in efx_rxq_t *erp);
2581 efx_filter_spec_init_tx(
2582 __out efx_filter_spec_t *spec,
2583 __in efx_txq_t *etp);
2585 extern __checkReturn efx_rc_t
2586 efx_filter_spec_set_ipv4_local(
2587 __inout efx_filter_spec_t *spec,
2590 __in uint16_t port);
2592 extern __checkReturn efx_rc_t
2593 efx_filter_spec_set_ipv4_full(
2594 __inout efx_filter_spec_t *spec,
2596 __in uint32_t lhost,
2597 __in uint16_t lport,
2598 __in uint32_t rhost,
2599 __in uint16_t rport);
2601 extern __checkReturn efx_rc_t
2602 efx_filter_spec_set_eth_local(
2603 __inout efx_filter_spec_t *spec,
2605 __in const uint8_t *addr);
2608 efx_filter_spec_set_ether_type(
2609 __inout efx_filter_spec_t *spec,
2610 __in uint16_t ether_type);
2612 extern __checkReturn efx_rc_t
2613 efx_filter_spec_set_uc_def(
2614 __inout efx_filter_spec_t *spec);
2616 extern __checkReturn efx_rc_t
2617 efx_filter_spec_set_mc_def(
2618 __inout efx_filter_spec_t *spec);
2620 typedef enum efx_filter_inner_frame_match_e {
2621 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2622 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2623 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2624 } efx_filter_inner_frame_match_t;
2626 extern __checkReturn efx_rc_t
2627 efx_filter_spec_set_encap_type(
2628 __inout efx_filter_spec_t *spec,
2629 __in efx_tunnel_protocol_t encap_type,
2630 __in efx_filter_inner_frame_match_t inner_frame_match);
2632 extern __checkReturn efx_rc_t
2633 efx_filter_spec_set_vxlan_full(
2634 __inout efx_filter_spec_t *spec,
2635 __in const uint8_t *vxlan_id,
2636 __in const uint8_t *inner_addr,
2637 __in const uint8_t *outer_addr);
2639 #if EFSYS_OPT_RX_SCALE
2640 extern __checkReturn efx_rc_t
2641 efx_filter_spec_set_rss_context(
2642 __inout efx_filter_spec_t *spec,
2643 __in uint32_t rss_context);
2645 #endif /* EFSYS_OPT_FILTER */
2649 extern __checkReturn uint32_t
2651 __in_ecount(count) uint32_t const *input,
2653 __in uint32_t init);
2655 extern __checkReturn uint32_t
2657 __in_ecount(length) uint8_t const *input,
2659 __in uint32_t init);
2661 #if EFSYS_OPT_LICENSING
2665 typedef struct efx_key_stats_s {
2667 uint32_t eks_invalid;
2668 uint32_t eks_blacklisted;
2669 uint32_t eks_unverifiable;
2670 uint32_t eks_wrong_node;
2671 uint32_t eks_licensed_apps_lo;
2672 uint32_t eks_licensed_apps_hi;
2673 uint32_t eks_licensed_features_lo;
2674 uint32_t eks_licensed_features_hi;
2677 extern __checkReturn efx_rc_t
2679 __in efx_nic_t *enp);
2683 __in efx_nic_t *enp);
2685 extern __checkReturn boolean_t
2686 efx_lic_check_support(
2687 __in efx_nic_t *enp);
2689 extern __checkReturn efx_rc_t
2690 efx_lic_update_licenses(
2691 __in efx_nic_t *enp);
2693 extern __checkReturn efx_rc_t
2694 efx_lic_get_key_stats(
2695 __in efx_nic_t *enp,
2696 __out efx_key_stats_t *ksp);
2698 extern __checkReturn efx_rc_t
2700 __in efx_nic_t *enp,
2701 __in uint64_t app_id,
2702 __out boolean_t *licensedp);
2704 extern __checkReturn efx_rc_t
2706 __in efx_nic_t *enp,
2707 __in size_t buffer_size,
2708 __out uint32_t *typep,
2709 __out size_t *lengthp,
2710 __out_opt uint8_t *bufferp);
2713 extern __checkReturn efx_rc_t
2715 __in efx_nic_t *enp,
2716 __in_bcount(buffer_size)
2718 __in size_t buffer_size,
2719 __out uint32_t *startp);
2721 extern __checkReturn efx_rc_t
2723 __in efx_nic_t *enp,
2724 __in_bcount(buffer_size)
2726 __in size_t buffer_size,
2727 __in uint32_t offset,
2728 __out uint32_t *endp);
2730 extern __checkReturn __success(return != B_FALSE) boolean_t
2732 __in efx_nic_t *enp,
2733 __in_bcount(buffer_size)
2735 __in size_t buffer_size,
2736 __in uint32_t offset,
2737 __out uint32_t *startp,
2738 __out uint32_t *lengthp);
2740 extern __checkReturn __success(return != B_FALSE) boolean_t
2741 efx_lic_validate_key(
2742 __in efx_nic_t *enp,
2743 __in_bcount(length) caddr_t keyp,
2744 __in uint32_t length);
2746 extern __checkReturn efx_rc_t
2748 __in efx_nic_t *enp,
2749 __in_bcount(buffer_size)
2751 __in size_t buffer_size,
2752 __in uint32_t offset,
2753 __in uint32_t length,
2754 __out_bcount_part(key_max_size, *lengthp)
2756 __in size_t key_max_size,
2757 __out uint32_t *lengthp);
2759 extern __checkReturn efx_rc_t
2761 __in efx_nic_t *enp,
2762 __in_bcount(buffer_size)
2764 __in size_t buffer_size,
2765 __in uint32_t offset,
2766 __in_bcount(length) caddr_t keyp,
2767 __in uint32_t length,
2768 __out uint32_t *lengthp);
2770 __checkReturn efx_rc_t
2772 __in efx_nic_t *enp,
2773 __in_bcount(buffer_size)
2775 __in size_t buffer_size,
2776 __in uint32_t offset,
2777 __in uint32_t length,
2779 __out uint32_t *deltap);
2781 extern __checkReturn efx_rc_t
2782 efx_lic_create_partition(
2783 __in efx_nic_t *enp,
2784 __in_bcount(buffer_size)
2786 __in size_t buffer_size);
2788 extern __checkReturn efx_rc_t
2789 efx_lic_finish_partition(
2790 __in efx_nic_t *enp,
2791 __in_bcount(buffer_size)
2793 __in size_t buffer_size);
2795 #endif /* EFSYS_OPT_LICENSING */
2799 #if EFSYS_OPT_TUNNEL
2801 extern __checkReturn efx_rc_t
2803 __in efx_nic_t *enp);
2807 __in efx_nic_t *enp);
2810 * For overlay network encapsulation using UDP, the firmware needs to know
2811 * the configured UDP port for the overlay so it can decode encapsulated
2813 * The UDP port/protocol list is global.
2816 extern __checkReturn efx_rc_t
2817 efx_tunnel_config_udp_add(
2818 __in efx_nic_t *enp,
2819 __in uint16_t port /* host/cpu-endian */,
2820 __in efx_tunnel_protocol_t protocol);
2822 extern __checkReturn efx_rc_t
2823 efx_tunnel_config_udp_remove(
2824 __in efx_nic_t *enp,
2825 __in uint16_t port /* host/cpu-endian */,
2826 __in efx_tunnel_protocol_t protocol);
2829 efx_tunnel_config_clear(
2830 __in efx_nic_t *enp);
2833 * Apply tunnel UDP ports configuration to hardware.
2835 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2838 extern __checkReturn efx_rc_t
2839 efx_tunnel_reconfigure(
2840 __in efx_nic_t *enp);
2842 #endif /* EFSYS_OPT_TUNNEL */
2849 #endif /* _SYS_EFX_H */