1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp);
54 #define EFX_PCI_VENID_SFC 0x1924
56 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
58 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
59 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
60 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
62 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
63 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
64 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
66 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
67 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
69 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
70 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
71 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
73 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
74 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
75 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
97 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
98 extern __checkReturn uint32_t
100 __in uint32_t crc_init,
101 __in_ecount(length) uint8_t const *input,
105 /* Type prototypes */
107 typedef struct efx_rxq_s efx_rxq_t;
111 typedef struct efx_nic_s efx_nic_t;
113 extern __checkReturn efx_rc_t
115 __in efx_family_t family,
116 __in efsys_identifier_t *esip,
117 __in efsys_bar_t *esbp,
118 __in efsys_lock_t *eslp,
119 __deref_out efx_nic_t **enpp);
121 extern __checkReturn efx_rc_t
123 __in efx_nic_t *enp);
125 extern __checkReturn efx_rc_t
127 __in efx_nic_t *enp);
129 extern __checkReturn efx_rc_t
131 __in efx_nic_t *enp);
135 extern __checkReturn efx_rc_t
136 efx_nic_register_test(
137 __in efx_nic_t *enp);
139 #endif /* EFSYS_OPT_DIAG */
143 __in efx_nic_t *enp);
147 __in efx_nic_t *enp);
151 __in efx_nic_t *enp);
153 #define EFX_PCIE_LINK_SPEED_GEN1 1
154 #define EFX_PCIE_LINK_SPEED_GEN2 2
155 #define EFX_PCIE_LINK_SPEED_GEN3 3
157 typedef enum efx_pcie_link_performance_e {
158 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
159 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
160 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
161 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
162 } efx_pcie_link_performance_t;
164 extern __checkReturn efx_rc_t
165 efx_nic_calculate_pcie_link_bandwidth(
166 __in uint32_t pcie_link_width,
167 __in uint32_t pcie_link_gen,
168 __out uint32_t *bandwidth_mbpsp);
170 extern __checkReturn efx_rc_t
171 efx_nic_check_pcie_link_speed(
173 __in uint32_t pcie_link_width,
174 __in uint32_t pcie_link_gen,
175 __out efx_pcie_link_performance_t *resultp);
179 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
180 /* Huntington and Medford require MCDIv2 commands */
181 #define WITH_MCDI_V2 1
184 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
186 typedef enum efx_mcdi_exception_e {
187 EFX_MCDI_EXCEPTION_MC_REBOOT,
188 EFX_MCDI_EXCEPTION_MC_BADASSERT,
189 } efx_mcdi_exception_t;
191 #if EFSYS_OPT_MCDI_LOGGING
192 typedef enum efx_log_msg_e {
194 EFX_LOG_MCDI_REQUEST,
195 EFX_LOG_MCDI_RESPONSE,
197 #endif /* EFSYS_OPT_MCDI_LOGGING */
199 typedef struct efx_mcdi_transport_s {
201 efsys_mem_t *emt_dma_mem;
202 void (*emt_execute)(void *, efx_mcdi_req_t *);
203 void (*emt_ev_cpl)(void *);
204 void (*emt_exception)(void *, efx_mcdi_exception_t);
205 #if EFSYS_OPT_MCDI_LOGGING
206 void (*emt_logger)(void *, efx_log_msg_t,
207 void *, size_t, void *, size_t);
208 #endif /* EFSYS_OPT_MCDI_LOGGING */
209 #if EFSYS_OPT_MCDI_PROXY_AUTH
210 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
211 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
212 } efx_mcdi_transport_t;
214 extern __checkReturn efx_rc_t
217 __in const efx_mcdi_transport_t *mtp);
219 extern __checkReturn efx_rc_t
221 __in efx_nic_t *enp);
225 __in efx_nic_t *enp);
228 efx_mcdi_get_timeout(
230 __in efx_mcdi_req_t *emrp,
231 __out uint32_t *usec_timeoutp);
234 efx_mcdi_request_start(
236 __in efx_mcdi_req_t *emrp,
237 __in boolean_t ev_cpl);
239 extern __checkReturn boolean_t
240 efx_mcdi_request_poll(
241 __in efx_nic_t *enp);
243 extern __checkReturn boolean_t
244 efx_mcdi_request_abort(
245 __in efx_nic_t *enp);
249 __in efx_nic_t *enp);
251 #endif /* EFSYS_OPT_MCDI */
255 #define EFX_NINTR_SIENA 1024
257 typedef enum efx_intr_type_e {
258 EFX_INTR_INVALID = 0,
264 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
266 extern __checkReturn efx_rc_t
269 __in efx_intr_type_t type,
270 __in efsys_mem_t *esmp);
274 __in efx_nic_t *enp);
278 __in efx_nic_t *enp);
281 efx_intr_disable_unlocked(
282 __in efx_nic_t *enp);
284 #define EFX_INTR_NEVQS 32
286 extern __checkReturn efx_rc_t
289 __in unsigned int level);
292 efx_intr_status_line(
294 __out boolean_t *fatalp,
295 __out uint32_t *maskp);
298 efx_intr_status_message(
300 __in unsigned int message,
301 __out boolean_t *fatalp);
305 __in efx_nic_t *enp);
309 __in efx_nic_t *enp);
313 #if EFSYS_OPT_MAC_STATS
315 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
316 typedef enum efx_mac_stat_e {
319 EFX_MAC_RX_UNICST_PKTS,
320 EFX_MAC_RX_MULTICST_PKTS,
321 EFX_MAC_RX_BRDCST_PKTS,
322 EFX_MAC_RX_PAUSE_PKTS,
323 EFX_MAC_RX_LE_64_PKTS,
324 EFX_MAC_RX_65_TO_127_PKTS,
325 EFX_MAC_RX_128_TO_255_PKTS,
326 EFX_MAC_RX_256_TO_511_PKTS,
327 EFX_MAC_RX_512_TO_1023_PKTS,
328 EFX_MAC_RX_1024_TO_15XX_PKTS,
329 EFX_MAC_RX_GE_15XX_PKTS,
331 EFX_MAC_RX_FCS_ERRORS,
332 EFX_MAC_RX_DROP_EVENTS,
333 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
334 EFX_MAC_RX_SYMBOL_ERRORS,
335 EFX_MAC_RX_ALIGN_ERRORS,
336 EFX_MAC_RX_INTERNAL_ERRORS,
337 EFX_MAC_RX_JABBER_PKTS,
338 EFX_MAC_RX_LANE0_CHAR_ERR,
339 EFX_MAC_RX_LANE1_CHAR_ERR,
340 EFX_MAC_RX_LANE2_CHAR_ERR,
341 EFX_MAC_RX_LANE3_CHAR_ERR,
342 EFX_MAC_RX_LANE0_DISP_ERR,
343 EFX_MAC_RX_LANE1_DISP_ERR,
344 EFX_MAC_RX_LANE2_DISP_ERR,
345 EFX_MAC_RX_LANE3_DISP_ERR,
346 EFX_MAC_RX_MATCH_FAULT,
347 EFX_MAC_RX_NODESC_DROP_CNT,
350 EFX_MAC_TX_UNICST_PKTS,
351 EFX_MAC_TX_MULTICST_PKTS,
352 EFX_MAC_TX_BRDCST_PKTS,
353 EFX_MAC_TX_PAUSE_PKTS,
354 EFX_MAC_TX_LE_64_PKTS,
355 EFX_MAC_TX_65_TO_127_PKTS,
356 EFX_MAC_TX_128_TO_255_PKTS,
357 EFX_MAC_TX_256_TO_511_PKTS,
358 EFX_MAC_TX_512_TO_1023_PKTS,
359 EFX_MAC_TX_1024_TO_15XX_PKTS,
360 EFX_MAC_TX_GE_15XX_PKTS,
362 EFX_MAC_TX_SGL_COL_PKTS,
363 EFX_MAC_TX_MULT_COL_PKTS,
364 EFX_MAC_TX_EX_COL_PKTS,
365 EFX_MAC_TX_LATE_COL_PKTS,
367 EFX_MAC_TX_EX_DEF_PKTS,
368 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
369 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
370 EFX_MAC_PM_TRUNC_VFIFO_FULL,
371 EFX_MAC_PM_DISCARD_VFIFO_FULL,
372 EFX_MAC_PM_TRUNC_QBB,
373 EFX_MAC_PM_DISCARD_QBB,
374 EFX_MAC_PM_DISCARD_MAPPING,
375 EFX_MAC_RXDP_Q_DISABLED_PKTS,
376 EFX_MAC_RXDP_DI_DROPPED_PKTS,
377 EFX_MAC_RXDP_STREAMING_PKTS,
378 EFX_MAC_RXDP_HLB_FETCH,
379 EFX_MAC_RXDP_HLB_WAIT,
380 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
381 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
382 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
383 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
384 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
385 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
386 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
387 EFX_MAC_VADAPTER_RX_BAD_BYTES,
388 EFX_MAC_VADAPTER_RX_OVERFLOW,
389 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
390 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
391 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
392 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
393 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
394 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
395 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
396 EFX_MAC_VADAPTER_TX_BAD_BYTES,
397 EFX_MAC_VADAPTER_TX_OVERFLOW,
401 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
403 #endif /* EFSYS_OPT_MAC_STATS */
405 typedef enum efx_link_mode_e {
406 EFX_LINK_UNKNOWN = 0,
419 #define EFX_MAC_ADDR_LEN 6
421 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
423 #define EFX_MAC_MULTICAST_LIST_MAX 256
425 #define EFX_MAC_SDU_MAX 9202
427 #define EFX_MAC_PDU_ADJUSTMENT \
431 + /* bug16011 */ 16) \
433 #define EFX_MAC_PDU(_sdu) \
434 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
437 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
438 * the SDU rounded up slightly.
440 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
442 #define EFX_MAC_PDU_MIN 60
443 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
445 extern __checkReturn efx_rc_t
450 extern __checkReturn efx_rc_t
455 extern __checkReturn efx_rc_t
460 extern __checkReturn efx_rc_t
463 __in boolean_t all_unicst,
464 __in boolean_t mulcst,
465 __in boolean_t all_mulcst,
466 __in boolean_t brdcst);
468 extern __checkReturn efx_rc_t
469 efx_mac_multicast_list_set(
471 __in_ecount(6*count) uint8_t const *addrs,
474 extern __checkReturn efx_rc_t
475 efx_mac_filter_default_rxq_set(
478 __in boolean_t using_rss);
481 efx_mac_filter_default_rxq_clear(
482 __in efx_nic_t *enp);
484 extern __checkReturn efx_rc_t
487 __in boolean_t enabled);
489 extern __checkReturn efx_rc_t
492 __out boolean_t *mac_upp);
494 #define EFX_FCNTL_RESPOND 0x00000001
495 #define EFX_FCNTL_GENERATE 0x00000002
497 extern __checkReturn efx_rc_t
500 __in unsigned int fcntl,
501 __in boolean_t autoneg);
506 __out unsigned int *fcntl_wantedp,
507 __out unsigned int *fcntl_linkp);
510 #if EFSYS_OPT_MAC_STATS
514 extern __checkReturn const char *
517 __in unsigned int id);
519 #endif /* EFSYS_OPT_NAMES */
521 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
523 #define EFX_MAC_STATS_MASK_NPAGES \
524 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
525 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
528 * Get mask of MAC statistics supported by the hardware.
530 * If mask_size is insufficient to return the mask, EINVAL error is
531 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
532 * (which is sizeof (uint32_t)) is sufficient.
534 extern __checkReturn efx_rc_t
535 efx_mac_stats_get_mask(
537 __out_bcount(mask_size) uint32_t *maskp,
538 __in size_t mask_size);
540 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
541 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
542 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
544 #define EFX_MAC_STATS_SIZE 0x400
546 extern __checkReturn efx_rc_t
548 __in efx_nic_t *enp);
551 * Upload mac statistics supported by the hardware into the given buffer.
553 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
556 * The hardware will only DMA statistics that it understands (of course).
557 * Drivers should not make any assumptions about which statistics are
558 * supported, especially when the statistics are generated by firmware.
560 * Thus, drivers should zero this buffer before use, so that not-understood
561 * statistics read back as zero.
563 extern __checkReturn efx_rc_t
564 efx_mac_stats_upload(
566 __in efsys_mem_t *esmp);
568 extern __checkReturn efx_rc_t
569 efx_mac_stats_periodic(
571 __in efsys_mem_t *esmp,
572 __in uint16_t period_ms,
573 __in boolean_t events);
575 extern __checkReturn efx_rc_t
576 efx_mac_stats_update(
578 __in efsys_mem_t *esmp,
579 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
580 __inout_opt uint32_t *generationp);
582 #endif /* EFSYS_OPT_MAC_STATS */
586 typedef enum efx_mon_type_e {
598 __in efx_nic_t *enp);
600 #endif /* EFSYS_OPT_NAMES */
602 extern __checkReturn efx_rc_t
604 __in efx_nic_t *enp);
606 #if EFSYS_OPT_MON_STATS
608 #define EFX_MON_STATS_PAGE_SIZE 0x100
609 #define EFX_MON_MASK_ELEMENT_SIZE 32
611 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock fcc1b6748432e1ac */
612 typedef enum efx_mon_stat_e {
619 EFX_MON_STAT_EXT_TEMP,
620 EFX_MON_STAT_INT_TEMP,
623 EFX_MON_STAT_INT_COOLING,
624 EFX_MON_STAT_EXT_COOLING,
632 EFX_MON_STAT_AOE_TEMP,
633 EFX_MON_STAT_PSU_AOE_TEMP,
634 EFX_MON_STAT_PSU_TEMP,
640 EFX_MON_STAT_VAOE_IN,
642 EFX_MON_STAT_IAOE_IN,
643 EFX_MON_STAT_NIC_POWER,
647 EFX_MON_STAT_0_9V_ADC,
648 EFX_MON_STAT_INT_TEMP2,
649 EFX_MON_STAT_VREG_TEMP,
650 EFX_MON_STAT_VREG_0_9V_TEMP,
651 EFX_MON_STAT_VREG_1_2V_TEMP,
652 EFX_MON_STAT_INT_VPTAT,
653 EFX_MON_STAT_INT_ADC_TEMP,
654 EFX_MON_STAT_EXT_VPTAT,
655 EFX_MON_STAT_EXT_ADC_TEMP,
656 EFX_MON_STAT_AMBIENT_TEMP,
657 EFX_MON_STAT_AIRFLOW,
658 EFX_MON_STAT_VDD08D_VSS08D_CSR,
659 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
660 EFX_MON_STAT_HOTPOINT_TEMP,
661 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
662 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
663 EFX_MON_STAT_MUM_VCC,
666 EFX_MON_STAT_0V9_A_TEMP,
669 EFX_MON_STAT_0V9_B_TEMP,
670 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
671 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
672 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
673 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
674 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
675 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
676 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
677 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
678 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
679 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
680 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
681 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
682 EFX_MON_STAT_SODIMM_VOUT,
683 EFX_MON_STAT_SODIMM_0_TEMP,
684 EFX_MON_STAT_SODIMM_1_TEMP,
685 EFX_MON_STAT_PHY0_VCC,
686 EFX_MON_STAT_PHY1_VCC,
687 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
688 EFX_MON_STAT_BOARD_FRONT_TEMP,
689 EFX_MON_STAT_BOARD_BACK_TEMP,
697 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
699 typedef enum efx_mon_stat_state_e {
700 EFX_MON_STAT_STATE_OK = 0,
701 EFX_MON_STAT_STATE_WARNING = 1,
702 EFX_MON_STAT_STATE_FATAL = 2,
703 EFX_MON_STAT_STATE_BROKEN = 3,
704 EFX_MON_STAT_STATE_NO_READING = 4,
705 } efx_mon_stat_state_t;
707 typedef struct efx_mon_stat_value_s {
710 } efx_mon_stat_value_t;
717 __in efx_mon_stat_t id);
719 #endif /* EFSYS_OPT_NAMES */
721 extern __checkReturn efx_rc_t
722 efx_mon_stats_update(
724 __in efsys_mem_t *esmp,
725 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
727 #endif /* EFSYS_OPT_MON_STATS */
731 __in efx_nic_t *enp);
735 extern __checkReturn efx_rc_t
737 __in efx_nic_t *enp);
739 #if EFSYS_OPT_PHY_LED_CONTROL
741 typedef enum efx_phy_led_mode_e {
742 EFX_PHY_LED_DEFAULT = 0,
747 } efx_phy_led_mode_t;
749 extern __checkReturn efx_rc_t
752 __in efx_phy_led_mode_t mode);
754 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
756 extern __checkReturn efx_rc_t
758 __in efx_nic_t *enp);
760 #if EFSYS_OPT_LOOPBACK
762 typedef enum efx_loopback_type_e {
763 EFX_LOOPBACK_OFF = 0,
764 EFX_LOOPBACK_DATA = 1,
765 EFX_LOOPBACK_GMAC = 2,
766 EFX_LOOPBACK_XGMII = 3,
767 EFX_LOOPBACK_XGXS = 4,
768 EFX_LOOPBACK_XAUI = 5,
769 EFX_LOOPBACK_GMII = 6,
770 EFX_LOOPBACK_SGMII = 7,
771 EFX_LOOPBACK_XGBR = 8,
772 EFX_LOOPBACK_XFI = 9,
773 EFX_LOOPBACK_XAUI_FAR = 10,
774 EFX_LOOPBACK_GMII_FAR = 11,
775 EFX_LOOPBACK_SGMII_FAR = 12,
776 EFX_LOOPBACK_XFI_FAR = 13,
777 EFX_LOOPBACK_GPHY = 14,
778 EFX_LOOPBACK_PHY_XS = 15,
779 EFX_LOOPBACK_PCS = 16,
780 EFX_LOOPBACK_PMA_PMD = 17,
781 EFX_LOOPBACK_XPORT = 18,
782 EFX_LOOPBACK_XGMII_WS = 19,
783 EFX_LOOPBACK_XAUI_WS = 20,
784 EFX_LOOPBACK_XAUI_WS_FAR = 21,
785 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
786 EFX_LOOPBACK_GMII_WS = 23,
787 EFX_LOOPBACK_XFI_WS = 24,
788 EFX_LOOPBACK_XFI_WS_FAR = 25,
789 EFX_LOOPBACK_PHYXS_WS = 26,
790 EFX_LOOPBACK_PMA_INT = 27,
791 EFX_LOOPBACK_SD_NEAR = 28,
792 EFX_LOOPBACK_SD_FAR = 29,
793 EFX_LOOPBACK_PMA_INT_WS = 30,
794 EFX_LOOPBACK_SD_FEP2_WS = 31,
795 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
796 EFX_LOOPBACK_SD_FEP_WS = 33,
797 EFX_LOOPBACK_SD_FES_WS = 34,
799 } efx_loopback_type_t;
801 typedef enum efx_loopback_kind_e {
802 EFX_LOOPBACK_KIND_OFF = 0,
803 EFX_LOOPBACK_KIND_ALL,
804 EFX_LOOPBACK_KIND_MAC,
805 EFX_LOOPBACK_KIND_PHY,
807 } efx_loopback_kind_t;
811 __in efx_loopback_kind_t loopback_kind,
812 __out efx_qword_t *maskp);
814 extern __checkReturn efx_rc_t
815 efx_port_loopback_set(
817 __in efx_link_mode_t link_mode,
818 __in efx_loopback_type_t type);
822 extern __checkReturn const char *
823 efx_loopback_type_name(
825 __in efx_loopback_type_t type);
827 #endif /* EFSYS_OPT_NAMES */
829 #endif /* EFSYS_OPT_LOOPBACK */
831 extern __checkReturn efx_rc_t
834 __out_opt efx_link_mode_t *link_modep);
838 __in efx_nic_t *enp);
840 typedef enum efx_phy_cap_type_e {
841 EFX_PHY_CAP_INVALID = 0,
848 EFX_PHY_CAP_10000FDX,
852 EFX_PHY_CAP_40000FDX,
854 } efx_phy_cap_type_t;
857 #define EFX_PHY_CAP_CURRENT 0x00000000
858 #define EFX_PHY_CAP_DEFAULT 0x00000001
859 #define EFX_PHY_CAP_PERM 0x00000002
865 __out uint32_t *maskp);
867 extern __checkReturn efx_rc_t
875 __out uint32_t *maskp);
877 extern __checkReturn efx_rc_t
880 __out uint32_t *ouip);
882 typedef enum efx_phy_media_type_e {
883 EFX_PHY_MEDIA_INVALID = 0,
888 EFX_PHY_MEDIA_SFP_PLUS,
889 EFX_PHY_MEDIA_BASE_T,
890 EFX_PHY_MEDIA_QSFP_PLUS,
892 } efx_phy_media_type_t;
895 * Get the type of medium currently used. If the board has ports for
896 * modules, a module is present, and we recognise the media type of
897 * the module, then this will be the media type of the module.
898 * Otherwise it will be the media type of the port.
901 efx_phy_media_type_get(
903 __out efx_phy_media_type_t *typep);
905 extern __checkReturn efx_rc_t
906 efx_phy_module_get_info(
908 __in uint8_t dev_addr,
911 __out_bcount(len) uint8_t *data);
913 #if EFSYS_OPT_PHY_STATS
915 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
916 typedef enum efx_phy_stat_e {
918 EFX_PHY_STAT_PMA_PMD_LINK_UP,
919 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
920 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
921 EFX_PHY_STAT_PMA_PMD_REV_A,
922 EFX_PHY_STAT_PMA_PMD_REV_B,
923 EFX_PHY_STAT_PMA_PMD_REV_C,
924 EFX_PHY_STAT_PMA_PMD_REV_D,
925 EFX_PHY_STAT_PCS_LINK_UP,
926 EFX_PHY_STAT_PCS_RX_FAULT,
927 EFX_PHY_STAT_PCS_TX_FAULT,
928 EFX_PHY_STAT_PCS_BER,
929 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
930 EFX_PHY_STAT_PHY_XS_LINK_UP,
931 EFX_PHY_STAT_PHY_XS_RX_FAULT,
932 EFX_PHY_STAT_PHY_XS_TX_FAULT,
933 EFX_PHY_STAT_PHY_XS_ALIGN,
934 EFX_PHY_STAT_PHY_XS_SYNC_A,
935 EFX_PHY_STAT_PHY_XS_SYNC_B,
936 EFX_PHY_STAT_PHY_XS_SYNC_C,
937 EFX_PHY_STAT_PHY_XS_SYNC_D,
938 EFX_PHY_STAT_AN_LINK_UP,
939 EFX_PHY_STAT_AN_MASTER,
940 EFX_PHY_STAT_AN_LOCAL_RX_OK,
941 EFX_PHY_STAT_AN_REMOTE_RX_OK,
942 EFX_PHY_STAT_CL22EXT_LINK_UP,
947 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
948 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
949 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
950 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
951 EFX_PHY_STAT_AN_COMPLETE,
952 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
953 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
954 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
955 EFX_PHY_STAT_PCS_FW_VERSION_0,
956 EFX_PHY_STAT_PCS_FW_VERSION_1,
957 EFX_PHY_STAT_PCS_FW_VERSION_2,
958 EFX_PHY_STAT_PCS_FW_VERSION_3,
959 EFX_PHY_STAT_PCS_FW_BUILD_YY,
960 EFX_PHY_STAT_PCS_FW_BUILD_MM,
961 EFX_PHY_STAT_PCS_FW_BUILD_DD,
962 EFX_PHY_STAT_PCS_OP_MODE,
966 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
973 __in efx_phy_stat_t stat);
975 #endif /* EFSYS_OPT_NAMES */
977 #define EFX_PHY_STATS_SIZE 0x100
979 extern __checkReturn efx_rc_t
980 efx_phy_stats_update(
982 __in efsys_mem_t *esmp,
983 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
985 #endif /* EFSYS_OPT_PHY_STATS */
990 typedef enum efx_bist_type_e {
991 EFX_BIST_TYPE_UNKNOWN,
992 EFX_BIST_TYPE_PHY_NORMAL,
993 EFX_BIST_TYPE_PHY_CABLE_SHORT,
994 EFX_BIST_TYPE_PHY_CABLE_LONG,
995 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
996 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
997 EFX_BIST_TYPE_REG, /* Test the register memories */
998 EFX_BIST_TYPE_NTYPES,
1001 typedef enum efx_bist_result_e {
1002 EFX_BIST_RESULT_UNKNOWN,
1003 EFX_BIST_RESULT_RUNNING,
1004 EFX_BIST_RESULT_PASSED,
1005 EFX_BIST_RESULT_FAILED,
1006 } efx_bist_result_t;
1008 typedef enum efx_phy_cable_status_e {
1009 EFX_PHY_CABLE_STATUS_OK,
1010 EFX_PHY_CABLE_STATUS_INVALID,
1011 EFX_PHY_CABLE_STATUS_OPEN,
1012 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1013 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1014 EFX_PHY_CABLE_STATUS_BUSY,
1015 } efx_phy_cable_status_t;
1017 typedef enum efx_bist_value_e {
1018 EFX_BIST_PHY_CABLE_LENGTH_A,
1019 EFX_BIST_PHY_CABLE_LENGTH_B,
1020 EFX_BIST_PHY_CABLE_LENGTH_C,
1021 EFX_BIST_PHY_CABLE_LENGTH_D,
1022 EFX_BIST_PHY_CABLE_STATUS_A,
1023 EFX_BIST_PHY_CABLE_STATUS_B,
1024 EFX_BIST_PHY_CABLE_STATUS_C,
1025 EFX_BIST_PHY_CABLE_STATUS_D,
1026 EFX_BIST_FAULT_CODE,
1028 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1034 EFX_BIST_MEM_EXPECT,
1035 EFX_BIST_MEM_ACTUAL,
1037 EFX_BIST_MEM_ECC_PARITY,
1038 EFX_BIST_MEM_ECC_FATAL,
1042 extern __checkReturn efx_rc_t
1043 efx_bist_enable_offline(
1044 __in efx_nic_t *enp);
1046 extern __checkReturn efx_rc_t
1048 __in efx_nic_t *enp,
1049 __in efx_bist_type_t type);
1051 extern __checkReturn efx_rc_t
1053 __in efx_nic_t *enp,
1054 __in efx_bist_type_t type,
1055 __out efx_bist_result_t *resultp,
1056 __out_opt uint32_t *value_maskp,
1057 __out_ecount_opt(count) unsigned long *valuesp,
1062 __in efx_nic_t *enp,
1063 __in efx_bist_type_t type);
1065 #endif /* EFSYS_OPT_BIST */
1067 #define EFX_FEATURE_IPV6 0x00000001
1068 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1069 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1070 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1071 #define EFX_FEATURE_MCDI 0x00000020
1072 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1073 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1074 #define EFX_FEATURE_TURBO 0x00000100
1075 #define EFX_FEATURE_MCDI_DMA 0x00000200
1076 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1077 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1078 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1079 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1080 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1082 typedef enum efx_tunnel_protocol_e {
1083 EFX_TUNNEL_PROTOCOL_NONE = 0,
1084 EFX_TUNNEL_PROTOCOL_VXLAN,
1085 EFX_TUNNEL_PROTOCOL_GENEVE,
1086 EFX_TUNNEL_PROTOCOL_NVGRE,
1088 } efx_tunnel_protocol_t;
1090 typedef enum efx_vi_window_shift_e {
1091 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1092 EFX_VI_WINDOW_SHIFT_8K = 13,
1093 EFX_VI_WINDOW_SHIFT_16K = 14,
1094 EFX_VI_WINDOW_SHIFT_64K = 16,
1095 } efx_vi_window_shift_t;
1097 typedef struct efx_nic_cfg_s {
1098 uint32_t enc_board_type;
1099 uint32_t enc_phy_type;
1101 char enc_phy_name[21];
1103 char enc_phy_revision[21];
1104 efx_mon_type_t enc_mon_type;
1105 #if EFSYS_OPT_MON_STATS
1106 uint32_t enc_mon_stat_dma_buf_size;
1107 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1109 unsigned int enc_features;
1110 efx_vi_window_shift_t enc_vi_window_shift;
1111 uint8_t enc_mac_addr[6];
1112 uint8_t enc_port; /* PHY port number */
1113 uint32_t enc_intr_vec_base;
1114 uint32_t enc_intr_limit;
1115 uint32_t enc_evq_limit;
1116 uint32_t enc_txq_limit;
1117 uint32_t enc_rxq_limit;
1118 uint32_t enc_txq_max_ndescs;
1119 uint32_t enc_buftbl_limit;
1120 uint32_t enc_piobuf_limit;
1121 uint32_t enc_piobuf_size;
1122 uint32_t enc_piobuf_min_alloc_size;
1123 uint32_t enc_evq_timer_quantum_ns;
1124 uint32_t enc_evq_timer_max_us;
1125 uint32_t enc_clk_mult;
1126 uint32_t enc_rx_prefix_size;
1127 uint32_t enc_rx_buf_align_start;
1128 uint32_t enc_rx_buf_align_end;
1129 uint32_t enc_rx_scale_max_exclusive_contexts;
1130 #if EFSYS_OPT_LOOPBACK
1131 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1132 #endif /* EFSYS_OPT_LOOPBACK */
1133 #if EFSYS_OPT_PHY_FLAGS
1134 uint32_t enc_phy_flags_mask;
1135 #endif /* EFSYS_OPT_PHY_FLAGS */
1136 #if EFSYS_OPT_PHY_LED_CONTROL
1137 uint32_t enc_led_mask;
1138 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1139 #if EFSYS_OPT_PHY_STATS
1140 uint64_t enc_phy_stat_mask;
1141 #endif /* EFSYS_OPT_PHY_STATS */
1143 uint8_t enc_mcdi_mdio_channel;
1144 #if EFSYS_OPT_PHY_STATS
1145 uint32_t enc_mcdi_phy_stat_mask;
1146 #endif /* EFSYS_OPT_PHY_STATS */
1147 #if EFSYS_OPT_MON_STATS
1148 uint32_t *enc_mcdi_sensor_maskp;
1149 uint32_t enc_mcdi_sensor_mask_size;
1150 #endif /* EFSYS_OPT_MON_STATS */
1151 #endif /* EFSYS_OPT_MCDI */
1153 uint32_t enc_bist_mask;
1154 #endif /* EFSYS_OPT_BIST */
1155 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1158 uint32_t enc_privilege_mask;
1159 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1160 boolean_t enc_bug26807_workaround;
1161 boolean_t enc_bug35388_workaround;
1162 boolean_t enc_bug41750_workaround;
1163 boolean_t enc_bug61265_workaround;
1164 boolean_t enc_rx_batching_enabled;
1165 /* Maximum number of descriptors completed in an rx event. */
1166 uint32_t enc_rx_batch_max;
1167 /* Number of rx descriptors the hardware requires for a push. */
1168 uint32_t enc_rx_push_align;
1169 /* Maximum amount of data in DMA descriptor */
1170 uint32_t enc_tx_dma_desc_size_max;
1172 * Boundary which DMA descriptor data must not cross or 0 if no
1175 uint32_t enc_tx_dma_desc_boundary;
1177 * Maximum number of bytes into the packet the TCP header can start for
1178 * the hardware to apply TSO packet edits.
1180 uint32_t enc_tx_tso_tcp_header_offset_limit;
1181 boolean_t enc_fw_assisted_tso_enabled;
1182 boolean_t enc_fw_assisted_tso_v2_enabled;
1183 /* Number of TSO contexts on the NIC (FATSOv2) */
1184 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1185 boolean_t enc_hw_tx_insert_vlan_enabled;
1186 /* Number of PFs on the NIC */
1187 uint32_t enc_hw_pf_count;
1188 /* Datapath firmware vadapter/vport/vswitch support */
1189 boolean_t enc_datapath_cap_evb;
1190 boolean_t enc_rx_disable_scatter_supported;
1191 boolean_t enc_allow_set_mac_with_installed_filters;
1192 boolean_t enc_enhanced_set_mac_supported;
1193 boolean_t enc_init_evq_v2_supported;
1194 boolean_t enc_rx_packed_stream_supported;
1195 boolean_t enc_rx_var_packed_stream_supported;
1196 boolean_t enc_pm_and_rxdp_counters;
1197 boolean_t enc_mac_stats_40g_tx_size_bins;
1198 uint32_t enc_tunnel_encapsulations_supported;
1200 * NIC global maximum for unique UDP tunnel ports shared by all
1203 uint32_t enc_tunnel_config_udp_entries_max;
1204 /* External port identifier */
1205 uint8_t enc_external_port;
1206 uint32_t enc_mcdi_max_payload_length;
1207 /* VPD may be per-PF or global */
1208 boolean_t enc_vpd_is_global;
1209 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1210 uint32_t enc_required_pcie_bandwidth_mbps;
1211 uint32_t enc_max_pcie_link_gen;
1212 /* Firmware verifies integrity of NVRAM updates */
1213 uint32_t enc_nvram_update_verify_result_supported;
1216 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1217 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1219 #define EFX_PCI_FUNCTION(_encp) \
1220 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1222 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1224 extern const efx_nic_cfg_t *
1226 __in efx_nic_t *enp);
1228 typedef struct efx_nic_fw_info_s {
1229 /* Basic FW version information */
1230 uint16_t enfi_mc_fw_version[4];
1232 * If datapath capabilities can be detected,
1233 * additional FW information is to be shown
1235 boolean_t enfi_dpcpu_fw_ids_valid;
1236 /* Rx and Tx datapath CPU FW IDs */
1237 uint16_t enfi_rx_dpcpu_fw_id;
1238 uint16_t enfi_tx_dpcpu_fw_id;
1239 } efx_nic_fw_info_t;
1241 extern __checkReturn efx_rc_t
1242 efx_nic_get_fw_version(
1243 __in efx_nic_t *enp,
1244 __out efx_nic_fw_info_t *enfip);
1246 /* Driver resource limits (minimum required/maximum usable). */
1247 typedef struct efx_drv_limits_s {
1248 uint32_t edl_min_evq_count;
1249 uint32_t edl_max_evq_count;
1251 uint32_t edl_min_rxq_count;
1252 uint32_t edl_max_rxq_count;
1254 uint32_t edl_min_txq_count;
1255 uint32_t edl_max_txq_count;
1257 /* PIO blocks (sub-allocated from piobuf) */
1258 uint32_t edl_min_pio_alloc_size;
1259 uint32_t edl_max_pio_alloc_count;
1262 extern __checkReturn efx_rc_t
1263 efx_nic_set_drv_limits(
1264 __inout efx_nic_t *enp,
1265 __in efx_drv_limits_t *edlp);
1267 typedef enum efx_nic_region_e {
1268 EFX_REGION_VI, /* Memory BAR UC mapping */
1269 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1272 extern __checkReturn efx_rc_t
1273 efx_nic_get_bar_region(
1274 __in efx_nic_t *enp,
1275 __in efx_nic_region_t region,
1276 __out uint32_t *offsetp,
1277 __out size_t *sizep);
1279 extern __checkReturn efx_rc_t
1280 efx_nic_get_vi_pool(
1281 __in efx_nic_t *enp,
1282 __out uint32_t *evq_countp,
1283 __out uint32_t *rxq_countp,
1284 __out uint32_t *txq_countp);
1289 typedef enum efx_vpd_tag_e {
1296 typedef uint16_t efx_vpd_keyword_t;
1298 typedef struct efx_vpd_value_s {
1299 efx_vpd_tag_t evv_tag;
1300 efx_vpd_keyword_t evv_keyword;
1302 uint8_t evv_value[0x100];
1306 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1308 extern __checkReturn efx_rc_t
1310 __in efx_nic_t *enp);
1312 extern __checkReturn efx_rc_t
1314 __in efx_nic_t *enp,
1315 __out size_t *sizep);
1317 extern __checkReturn efx_rc_t
1319 __in efx_nic_t *enp,
1320 __out_bcount(size) caddr_t data,
1323 extern __checkReturn efx_rc_t
1325 __in efx_nic_t *enp,
1326 __in_bcount(size) caddr_t data,
1329 extern __checkReturn efx_rc_t
1331 __in efx_nic_t *enp,
1332 __in_bcount(size) caddr_t data,
1335 extern __checkReturn efx_rc_t
1337 __in efx_nic_t *enp,
1338 __in_bcount(size) caddr_t data,
1340 __inout efx_vpd_value_t *evvp);
1342 extern __checkReturn efx_rc_t
1344 __in efx_nic_t *enp,
1345 __inout_bcount(size) caddr_t data,
1347 __in efx_vpd_value_t *evvp);
1349 extern __checkReturn efx_rc_t
1351 __in efx_nic_t *enp,
1352 __inout_bcount(size) caddr_t data,
1354 __out efx_vpd_value_t *evvp,
1355 __inout unsigned int *contp);
1357 extern __checkReturn efx_rc_t
1359 __in efx_nic_t *enp,
1360 __in_bcount(size) caddr_t data,
1365 __in efx_nic_t *enp);
1367 #endif /* EFSYS_OPT_VPD */
1373 typedef enum efx_nvram_type_e {
1374 EFX_NVRAM_INVALID = 0,
1376 EFX_NVRAM_BOOTROM_CFG,
1377 EFX_NVRAM_MC_FIRMWARE,
1378 EFX_NVRAM_MC_GOLDEN,
1384 EFX_NVRAM_FPGA_BACKUP,
1385 EFX_NVRAM_DYNAMIC_CFG,
1388 EFX_NVRAM_MUM_FIRMWARE,
1392 extern __checkReturn efx_rc_t
1394 __in efx_nic_t *enp);
1398 extern __checkReturn efx_rc_t
1400 __in efx_nic_t *enp);
1402 #endif /* EFSYS_OPT_DIAG */
1404 extern __checkReturn efx_rc_t
1406 __in efx_nic_t *enp,
1407 __in efx_nvram_type_t type,
1408 __out size_t *sizep);
1410 extern __checkReturn efx_rc_t
1412 __in efx_nic_t *enp,
1413 __in efx_nvram_type_t type,
1414 __out_opt size_t *pref_chunkp);
1416 extern __checkReturn efx_rc_t
1417 efx_nvram_rw_finish(
1418 __in efx_nic_t *enp,
1419 __in efx_nvram_type_t type,
1420 __out_opt uint32_t *verify_resultp);
1422 extern __checkReturn efx_rc_t
1423 efx_nvram_get_version(
1424 __in efx_nic_t *enp,
1425 __in efx_nvram_type_t type,
1426 __out uint32_t *subtypep,
1427 __out_ecount(4) uint16_t version[4]);
1429 extern __checkReturn efx_rc_t
1430 efx_nvram_read_chunk(
1431 __in efx_nic_t *enp,
1432 __in efx_nvram_type_t type,
1433 __in unsigned int offset,
1434 __out_bcount(size) caddr_t data,
1437 extern __checkReturn efx_rc_t
1438 efx_nvram_read_backup(
1439 __in efx_nic_t *enp,
1440 __in efx_nvram_type_t type,
1441 __in unsigned int offset,
1442 __out_bcount(size) caddr_t data,
1445 extern __checkReturn efx_rc_t
1446 efx_nvram_set_version(
1447 __in efx_nic_t *enp,
1448 __in efx_nvram_type_t type,
1449 __in_ecount(4) uint16_t version[4]);
1451 extern __checkReturn efx_rc_t
1453 __in efx_nic_t *enp,
1454 __in efx_nvram_type_t type,
1455 __in_bcount(partn_size) caddr_t partn_data,
1456 __in size_t partn_size);
1458 extern __checkReturn efx_rc_t
1460 __in efx_nic_t *enp,
1461 __in efx_nvram_type_t type);
1463 extern __checkReturn efx_rc_t
1464 efx_nvram_write_chunk(
1465 __in efx_nic_t *enp,
1466 __in efx_nvram_type_t type,
1467 __in unsigned int offset,
1468 __in_bcount(size) caddr_t data,
1473 __in efx_nic_t *enp);
1475 #endif /* EFSYS_OPT_NVRAM */
1477 #if EFSYS_OPT_BOOTCFG
1479 /* Report size and offset of bootcfg sector in NVRAM partition. */
1480 extern __checkReturn efx_rc_t
1481 efx_bootcfg_sector_info(
1482 __in efx_nic_t *enp,
1484 __out_opt uint32_t *sector_countp,
1485 __out size_t *offsetp,
1486 __out size_t *max_sizep);
1489 * Copy bootcfg sector data to a target buffer which may differ in size.
1490 * Optionally corrects format errors in source buffer.
1493 efx_bootcfg_copy_sector(
1494 __in efx_nic_t *enp,
1495 __inout_bcount(sector_length)
1497 __in size_t sector_length,
1498 __out_bcount(data_size) uint8_t *data,
1499 __in size_t data_size,
1500 __in boolean_t handle_format_errors);
1504 __in efx_nic_t *enp,
1505 __out_bcount(size) uint8_t *data,
1510 __in efx_nic_t *enp,
1511 __in_bcount(size) uint8_t *data,
1514 #endif /* EFSYS_OPT_BOOTCFG */
1518 typedef enum efx_pattern_type_t {
1519 EFX_PATTERN_BYTE_INCREMENT = 0,
1520 EFX_PATTERN_ALL_THE_SAME,
1521 EFX_PATTERN_BIT_ALTERNATE,
1522 EFX_PATTERN_BYTE_ALTERNATE,
1523 EFX_PATTERN_BYTE_CHANGING,
1524 EFX_PATTERN_BIT_SWEEP,
1526 } efx_pattern_type_t;
1529 (*efx_sram_pattern_fn_t)(
1531 __in boolean_t negate,
1532 __out efx_qword_t *eqp);
1534 extern __checkReturn efx_rc_t
1536 __in efx_nic_t *enp,
1537 __in efx_pattern_type_t type);
1539 #endif /* EFSYS_OPT_DIAG */
1541 extern __checkReturn efx_rc_t
1542 efx_sram_buf_tbl_set(
1543 __in efx_nic_t *enp,
1545 __in efsys_mem_t *esmp,
1549 efx_sram_buf_tbl_clear(
1550 __in efx_nic_t *enp,
1554 #define EFX_BUF_TBL_SIZE 0x20000
1556 #define EFX_BUF_SIZE 4096
1560 typedef struct efx_evq_s efx_evq_t;
1562 #if EFSYS_OPT_QSTATS
1564 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1565 typedef enum efx_ev_qstat_e {
1571 EV_RX_PAUSE_FRM_ERR,
1572 EV_RX_BUF_OWNER_ID_ERR,
1573 EV_RX_IPV4_HDR_CHKSUM_ERR,
1574 EV_RX_TCP_UDP_CHKSUM_ERR,
1578 EV_RX_MCAST_HASH_MATCH,
1595 EV_DRIVER_SRM_UPD_DONE,
1596 EV_DRIVER_TX_DESCQ_FLS_DONE,
1597 EV_DRIVER_RX_DESCQ_FLS_DONE,
1598 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1599 EV_DRIVER_RX_DSC_ERROR,
1600 EV_DRIVER_TX_DSC_ERROR,
1606 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1608 #endif /* EFSYS_OPT_QSTATS */
1610 extern __checkReturn efx_rc_t
1612 __in efx_nic_t *enp);
1616 __in efx_nic_t *enp);
1618 #define EFX_EVQ_MAXNEVS 32768
1619 #define EFX_EVQ_MINNEVS 512
1621 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1622 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1624 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1625 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1626 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1627 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1629 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1630 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1631 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1633 extern __checkReturn efx_rc_t
1635 __in efx_nic_t *enp,
1636 __in unsigned int index,
1637 __in efsys_mem_t *esmp,
1641 __in uint32_t flags,
1642 __deref_out efx_evq_t **eepp);
1646 __in efx_evq_t *eep,
1647 __in uint16_t data);
1649 typedef __checkReturn boolean_t
1650 (*efx_initialized_ev_t)(
1651 __in_opt void *arg);
1653 #define EFX_PKT_UNICAST 0x0004
1654 #define EFX_PKT_START 0x0008
1656 #define EFX_PKT_VLAN_TAGGED 0x0010
1657 #define EFX_CKSUM_TCPUDP 0x0020
1658 #define EFX_CKSUM_IPV4 0x0040
1659 #define EFX_PKT_CONT 0x0080
1661 #define EFX_CHECK_VLAN 0x0100
1662 #define EFX_PKT_TCP 0x0200
1663 #define EFX_PKT_UDP 0x0400
1664 #define EFX_PKT_IPV4 0x0800
1666 #define EFX_PKT_IPV6 0x1000
1667 #define EFX_PKT_PREFIX_LEN 0x2000
1668 #define EFX_ADDR_MISMATCH 0x4000
1669 #define EFX_DISCARD 0x8000
1672 * The following flags are used only for packed stream
1673 * mode. The values for the flags are reused to fit into 16 bit,
1674 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1675 * packed stream mode
1677 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1678 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1681 #define EFX_EV_RX_NLABELS 32
1682 #define EFX_EV_TX_NLABELS 32
1684 typedef __checkReturn boolean_t
1687 __in uint32_t label,
1690 __in uint16_t flags);
1692 #if EFSYS_OPT_RX_PACKED_STREAM
1695 * Packed stream mode is documented in SF-112241-TC.
1696 * The general idea is that, instead of putting each incoming
1697 * packet into a separate buffer which is specified in a RX
1698 * descriptor, a large buffer is provided to the hardware and
1699 * packets are put there in a continuous stream.
1700 * The main advantage of such an approach is that RX queue refilling
1701 * happens much less frequently.
1704 typedef __checkReturn boolean_t
1707 __in uint32_t label,
1709 __in uint32_t pkt_count,
1710 __in uint16_t flags);
1714 typedef __checkReturn boolean_t
1717 __in uint32_t label,
1720 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1721 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1722 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1723 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1724 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1725 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1726 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1727 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1728 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1730 typedef __checkReturn boolean_t
1731 (*efx_exception_ev_t)(
1733 __in uint32_t label,
1734 __in uint32_t data);
1736 typedef __checkReturn boolean_t
1737 (*efx_rxq_flush_done_ev_t)(
1739 __in uint32_t rxq_index);
1741 typedef __checkReturn boolean_t
1742 (*efx_rxq_flush_failed_ev_t)(
1744 __in uint32_t rxq_index);
1746 typedef __checkReturn boolean_t
1747 (*efx_txq_flush_done_ev_t)(
1749 __in uint32_t txq_index);
1751 typedef __checkReturn boolean_t
1752 (*efx_software_ev_t)(
1754 __in uint16_t magic);
1756 typedef __checkReturn boolean_t
1759 __in uint32_t code);
1761 #define EFX_SRAM_CLEAR 0
1762 #define EFX_SRAM_UPDATE 1
1763 #define EFX_SRAM_ILLEGAL_CLEAR 2
1765 typedef __checkReturn boolean_t
1766 (*efx_wake_up_ev_t)(
1768 __in uint32_t label);
1770 typedef __checkReturn boolean_t
1773 __in uint32_t label);
1775 typedef __checkReturn boolean_t
1776 (*efx_link_change_ev_t)(
1778 __in efx_link_mode_t link_mode);
1780 #if EFSYS_OPT_MON_STATS
1782 typedef __checkReturn boolean_t
1783 (*efx_monitor_ev_t)(
1785 __in efx_mon_stat_t id,
1786 __in efx_mon_stat_value_t value);
1788 #endif /* EFSYS_OPT_MON_STATS */
1790 #if EFSYS_OPT_MAC_STATS
1792 typedef __checkReturn boolean_t
1793 (*efx_mac_stats_ev_t)(
1795 __in uint32_t generation);
1797 #endif /* EFSYS_OPT_MAC_STATS */
1799 typedef struct efx_ev_callbacks_s {
1800 efx_initialized_ev_t eec_initialized;
1802 #if EFSYS_OPT_RX_PACKED_STREAM
1803 efx_rx_ps_ev_t eec_rx_ps;
1806 efx_exception_ev_t eec_exception;
1807 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1808 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1809 efx_txq_flush_done_ev_t eec_txq_flush_done;
1810 efx_software_ev_t eec_software;
1811 efx_sram_ev_t eec_sram;
1812 efx_wake_up_ev_t eec_wake_up;
1813 efx_timer_ev_t eec_timer;
1814 efx_link_change_ev_t eec_link_change;
1815 #if EFSYS_OPT_MON_STATS
1816 efx_monitor_ev_t eec_monitor;
1817 #endif /* EFSYS_OPT_MON_STATS */
1818 #if EFSYS_OPT_MAC_STATS
1819 efx_mac_stats_ev_t eec_mac_stats;
1820 #endif /* EFSYS_OPT_MAC_STATS */
1821 } efx_ev_callbacks_t;
1823 extern __checkReturn boolean_t
1825 __in efx_evq_t *eep,
1826 __in unsigned int count);
1828 #if EFSYS_OPT_EV_PREFETCH
1832 __in efx_evq_t *eep,
1833 __in unsigned int count);
1835 #endif /* EFSYS_OPT_EV_PREFETCH */
1839 __in efx_evq_t *eep,
1840 __inout unsigned int *countp,
1841 __in const efx_ev_callbacks_t *eecp,
1842 __in_opt void *arg);
1844 extern __checkReturn efx_rc_t
1845 efx_ev_usecs_to_ticks(
1846 __in efx_nic_t *enp,
1847 __in unsigned int usecs,
1848 __out unsigned int *ticksp);
1850 extern __checkReturn efx_rc_t
1852 __in efx_evq_t *eep,
1853 __in unsigned int us);
1855 extern __checkReturn efx_rc_t
1857 __in efx_evq_t *eep,
1858 __in unsigned int count);
1860 #if EFSYS_OPT_QSTATS
1866 __in efx_nic_t *enp,
1867 __in unsigned int id);
1869 #endif /* EFSYS_OPT_NAMES */
1872 efx_ev_qstats_update(
1873 __in efx_evq_t *eep,
1874 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1876 #endif /* EFSYS_OPT_QSTATS */
1880 __in efx_evq_t *eep);
1884 extern __checkReturn efx_rc_t
1886 __inout efx_nic_t *enp);
1890 __in efx_nic_t *enp);
1892 #if EFSYS_OPT_RX_SCATTER
1893 __checkReturn efx_rc_t
1894 efx_rx_scatter_enable(
1895 __in efx_nic_t *enp,
1896 __in unsigned int buf_size);
1897 #endif /* EFSYS_OPT_RX_SCATTER */
1899 /* Handle to represent use of the default RSS context. */
1900 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1902 #if EFSYS_OPT_RX_SCALE
1904 typedef enum efx_rx_hash_alg_e {
1905 EFX_RX_HASHALG_LFSR = 0,
1906 EFX_RX_HASHALG_TOEPLITZ
1907 } efx_rx_hash_alg_t;
1909 #define EFX_RX_HASH_IPV4 (1U << 0)
1910 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1911 #define EFX_RX_HASH_IPV6 (1U << 2)
1912 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1914 typedef unsigned int efx_rx_hash_type_t;
1916 typedef enum efx_rx_hash_support_e {
1917 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1918 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1919 } efx_rx_hash_support_t;
1921 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1922 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1923 #define EFX_MAXRSS 64 /* RX indirection entry range */
1924 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1926 typedef enum efx_rx_scale_context_type_e {
1927 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1928 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1929 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1930 } efx_rx_scale_context_type_t;
1932 extern __checkReturn efx_rc_t
1933 efx_rx_hash_default_support_get(
1934 __in efx_nic_t *enp,
1935 __out efx_rx_hash_support_t *supportp);
1938 extern __checkReturn efx_rc_t
1939 efx_rx_scale_default_support_get(
1940 __in efx_nic_t *enp,
1941 __out efx_rx_scale_context_type_t *typep);
1943 extern __checkReturn efx_rc_t
1944 efx_rx_scale_context_alloc(
1945 __in efx_nic_t *enp,
1946 __in efx_rx_scale_context_type_t type,
1947 __in uint32_t num_queues,
1948 __out uint32_t *rss_contextp);
1950 extern __checkReturn efx_rc_t
1951 efx_rx_scale_context_free(
1952 __in efx_nic_t *enp,
1953 __in uint32_t rss_context);
1955 extern __checkReturn efx_rc_t
1956 efx_rx_scale_mode_set(
1957 __in efx_nic_t *enp,
1958 __in uint32_t rss_context,
1959 __in efx_rx_hash_alg_t alg,
1960 __in efx_rx_hash_type_t type,
1961 __in boolean_t insert);
1963 extern __checkReturn efx_rc_t
1964 efx_rx_scale_tbl_set(
1965 __in efx_nic_t *enp,
1966 __in uint32_t rss_context,
1967 __in_ecount(n) unsigned int *table,
1970 extern __checkReturn efx_rc_t
1971 efx_rx_scale_key_set(
1972 __in efx_nic_t *enp,
1973 __in uint32_t rss_context,
1974 __in_ecount(n) uint8_t *key,
1977 extern __checkReturn uint32_t
1978 efx_pseudo_hdr_hash_get(
1979 __in efx_rxq_t *erp,
1980 __in efx_rx_hash_alg_t func,
1981 __in uint8_t *buffer);
1983 #endif /* EFSYS_OPT_RX_SCALE */
1985 extern __checkReturn efx_rc_t
1986 efx_pseudo_hdr_pkt_length_get(
1987 __in efx_rxq_t *erp,
1988 __in uint8_t *buffer,
1989 __out uint16_t *pkt_lengthp);
1991 #define EFX_RXQ_MAXNDESCS 4096
1992 #define EFX_RXQ_MINNDESCS 512
1994 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1995 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1996 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1997 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1999 typedef enum efx_rxq_type_e {
2000 EFX_RXQ_TYPE_DEFAULT,
2001 EFX_RXQ_TYPE_PACKED_STREAM,
2006 * Dummy flag to be used instead of 0 to make it clear that the argument
2007 * is receive queue flags.
2009 #define EFX_RXQ_FLAG_NONE 0x0
2010 #define EFX_RXQ_FLAG_SCATTER 0x1
2012 * If tunnels are supported and Rx event can provide information about
2013 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2014 * full-feature firmware variant running), outer classes are requested by
2015 * default. However, if the driver supports tunnels, the flag allows to
2016 * request inner classes which are required to be able to interpret inner
2017 * Rx checksum offload results.
2019 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2021 extern __checkReturn efx_rc_t
2023 __in efx_nic_t *enp,
2024 __in unsigned int index,
2025 __in unsigned int label,
2026 __in efx_rxq_type_t type,
2027 __in efsys_mem_t *esmp,
2030 __in unsigned int flags,
2031 __in efx_evq_t *eep,
2032 __deref_out efx_rxq_t **erpp);
2034 #if EFSYS_OPT_RX_PACKED_STREAM
2036 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2037 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2038 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2039 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2040 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2042 extern __checkReturn efx_rc_t
2043 efx_rx_qcreate_packed_stream(
2044 __in efx_nic_t *enp,
2045 __in unsigned int index,
2046 __in unsigned int label,
2047 __in uint32_t ps_buf_size,
2048 __in efsys_mem_t *esmp,
2050 __in efx_evq_t *eep,
2051 __deref_out efx_rxq_t **erpp);
2055 typedef struct efx_buffer_s {
2056 efsys_dma_addr_t eb_addr;
2061 typedef struct efx_desc_s {
2067 __in efx_rxq_t *erp,
2068 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2070 __in unsigned int ndescs,
2071 __in unsigned int completed,
2072 __in unsigned int added);
2076 __in efx_rxq_t *erp,
2077 __in unsigned int added,
2078 __inout unsigned int *pushedp);
2080 #if EFSYS_OPT_RX_PACKED_STREAM
2083 efx_rx_qpush_ps_credits(
2084 __in efx_rxq_t *erp);
2086 extern __checkReturn uint8_t *
2087 efx_rx_qps_packet_info(
2088 __in efx_rxq_t *erp,
2089 __in uint8_t *buffer,
2090 __in uint32_t buffer_length,
2091 __in uint32_t current_offset,
2092 __out uint16_t *lengthp,
2093 __out uint32_t *next_offsetp,
2094 __out uint32_t *timestamp);
2097 extern __checkReturn efx_rc_t
2099 __in efx_rxq_t *erp);
2103 __in efx_rxq_t *erp);
2107 __in efx_rxq_t *erp);
2111 typedef struct efx_txq_s efx_txq_t;
2113 #if EFSYS_OPT_QSTATS
2115 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2116 typedef enum efx_tx_qstat_e {
2122 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2124 #endif /* EFSYS_OPT_QSTATS */
2126 extern __checkReturn efx_rc_t
2128 __in efx_nic_t *enp);
2132 __in efx_nic_t *enp);
2134 #define EFX_TXQ_MINNDESCS 512
2136 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2137 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2138 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2140 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2142 #define EFX_TXQ_CKSUM_IPV4 0x0001
2143 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2144 #define EFX_TXQ_FATSOV2 0x0004
2145 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2146 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2148 extern __checkReturn efx_rc_t
2150 __in efx_nic_t *enp,
2151 __in unsigned int index,
2152 __in unsigned int label,
2153 __in efsys_mem_t *esmp,
2156 __in uint16_t flags,
2157 __in efx_evq_t *eep,
2158 __deref_out efx_txq_t **etpp,
2159 __out unsigned int *addedp);
2161 extern __checkReturn efx_rc_t
2163 __in efx_txq_t *etp,
2164 __in_ecount(ndescs) efx_buffer_t *eb,
2165 __in unsigned int ndescs,
2166 __in unsigned int completed,
2167 __inout unsigned int *addedp);
2169 extern __checkReturn efx_rc_t
2171 __in efx_txq_t *etp,
2172 __in unsigned int ns);
2176 __in efx_txq_t *etp,
2177 __in unsigned int added,
2178 __in unsigned int pushed);
2180 extern __checkReturn efx_rc_t
2182 __in efx_txq_t *etp);
2186 __in efx_txq_t *etp);
2188 extern __checkReturn efx_rc_t
2190 __in efx_txq_t *etp);
2193 efx_tx_qpio_disable(
2194 __in efx_txq_t *etp);
2196 extern __checkReturn efx_rc_t
2198 __in efx_txq_t *etp,
2199 __in_ecount(buf_length) uint8_t *buffer,
2200 __in size_t buf_length,
2201 __in size_t pio_buf_offset);
2203 extern __checkReturn efx_rc_t
2205 __in efx_txq_t *etp,
2206 __in size_t pkt_length,
2207 __in unsigned int completed,
2208 __inout unsigned int *addedp);
2210 extern __checkReturn efx_rc_t
2212 __in efx_txq_t *etp,
2213 __in_ecount(n) efx_desc_t *ed,
2214 __in unsigned int n,
2215 __in unsigned int completed,
2216 __inout unsigned int *addedp);
2219 efx_tx_qdesc_dma_create(
2220 __in efx_txq_t *etp,
2221 __in efsys_dma_addr_t addr,
2224 __out efx_desc_t *edp);
2227 efx_tx_qdesc_tso_create(
2228 __in efx_txq_t *etp,
2229 __in uint16_t ipv4_id,
2230 __in uint32_t tcp_seq,
2231 __in uint8_t tcp_flags,
2232 __out efx_desc_t *edp);
2234 /* Number of FATSOv2 option descriptors */
2235 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2237 /* Maximum number of DMA segments per TSO packet (not superframe) */
2238 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2241 efx_tx_qdesc_tso2_create(
2242 __in efx_txq_t *etp,
2243 __in uint16_t ipv4_id,
2244 __in uint32_t tcp_seq,
2245 __in uint16_t tcp_mss,
2246 __out_ecount(count) efx_desc_t *edp,
2250 efx_tx_qdesc_vlantci_create(
2251 __in efx_txq_t *etp,
2253 __out efx_desc_t *edp);
2255 #if EFSYS_OPT_QSTATS
2261 __in efx_nic_t *etp,
2262 __in unsigned int id);
2264 #endif /* EFSYS_OPT_NAMES */
2267 efx_tx_qstats_update(
2268 __in efx_txq_t *etp,
2269 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2271 #endif /* EFSYS_OPT_QSTATS */
2275 __in efx_txq_t *etp);
2280 #if EFSYS_OPT_FILTER
2282 #define EFX_ETHER_TYPE_IPV4 0x0800
2283 #define EFX_ETHER_TYPE_IPV6 0x86DD
2285 #define EFX_IPPROTO_TCP 6
2286 #define EFX_IPPROTO_UDP 17
2287 #define EFX_IPPROTO_GRE 47
2289 /* Use RSS to spread across multiple queues */
2290 #define EFX_FILTER_FLAG_RX_RSS 0x01
2291 /* Enable RX scatter */
2292 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2294 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2295 * May only be set by the filter implementation for each type.
2296 * A removal request will restore the automatic filter in its place.
2298 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2299 /* Filter is for RX */
2300 #define EFX_FILTER_FLAG_RX 0x08
2301 /* Filter is for TX */
2302 #define EFX_FILTER_FLAG_TX 0x10
2304 typedef uint8_t efx_filter_flags_t;
2307 * Flags which specify the fields to match on. The values are the same as in the
2308 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2311 /* Match by remote IP host address */
2312 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2313 /* Match by local IP host address */
2314 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2315 /* Match by remote MAC address */
2316 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2317 /* Match by remote TCP/UDP port */
2318 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2319 /* Match by remote TCP/UDP port */
2320 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2321 /* Match by local TCP/UDP port */
2322 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2323 /* Match by Ether-type */
2324 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2325 /* Match by inner VLAN ID */
2326 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2327 /* Match by outer VLAN ID */
2328 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2329 /* Match by IP transport protocol */
2330 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2331 /* For encapsulated packets, match all multicast inner frames */
2332 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2333 /* For encapsulated packets, match all unicast inner frames */
2334 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2335 /* Match otherwise-unmatched multicast and broadcast packets */
2336 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2337 /* Match otherwise-unmatched unicast packets */
2338 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2340 typedef uint32_t efx_filter_match_flags_t;
2342 typedef enum efx_filter_priority_s {
2343 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2344 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2345 * address list or hardware
2346 * requirements. This may only be used
2347 * by the filter implementation for
2349 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2350 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2351 * client (e.g. SR-IOV, HyperV VMQ etc.)
2353 } efx_filter_priority_t;
2356 * FIXME: All these fields are assumed to be in little-endian byte order.
2357 * It may be better for some to be big-endian. See bug42804.
2360 typedef struct efx_filter_spec_s {
2361 efx_filter_match_flags_t efs_match_flags;
2362 uint8_t efs_priority;
2363 efx_filter_flags_t efs_flags;
2364 uint16_t efs_dmaq_id;
2365 uint32_t efs_rss_context;
2366 uint16_t efs_outer_vid;
2367 uint16_t efs_inner_vid;
2368 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2369 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2370 uint16_t efs_ether_type;
2371 uint8_t efs_ip_proto;
2372 efx_tunnel_protocol_t efs_encap_type;
2373 uint16_t efs_loc_port;
2374 uint16_t efs_rem_port;
2375 efx_oword_t efs_rem_host;
2376 efx_oword_t efs_loc_host;
2377 } efx_filter_spec_t;
2380 /* Default values for use in filter specifications */
2381 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2382 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2384 extern __checkReturn efx_rc_t
2386 __in efx_nic_t *enp);
2390 __in efx_nic_t *enp);
2392 extern __checkReturn efx_rc_t
2394 __in efx_nic_t *enp,
2395 __inout efx_filter_spec_t *spec);
2397 extern __checkReturn efx_rc_t
2399 __in efx_nic_t *enp,
2400 __inout efx_filter_spec_t *spec);
2402 extern __checkReturn efx_rc_t
2404 __in efx_nic_t *enp);
2406 extern __checkReturn efx_rc_t
2407 efx_filter_supported_filters(
2408 __in efx_nic_t *enp,
2409 __out_ecount(buffer_length) uint32_t *buffer,
2410 __in size_t buffer_length,
2411 __out size_t *list_lengthp);
2414 efx_filter_spec_init_rx(
2415 __out efx_filter_spec_t *spec,
2416 __in efx_filter_priority_t priority,
2417 __in efx_filter_flags_t flags,
2418 __in efx_rxq_t *erp);
2421 efx_filter_spec_init_tx(
2422 __out efx_filter_spec_t *spec,
2423 __in efx_txq_t *etp);
2425 extern __checkReturn efx_rc_t
2426 efx_filter_spec_set_ipv4_local(
2427 __inout efx_filter_spec_t *spec,
2430 __in uint16_t port);
2432 extern __checkReturn efx_rc_t
2433 efx_filter_spec_set_ipv4_full(
2434 __inout efx_filter_spec_t *spec,
2436 __in uint32_t lhost,
2437 __in uint16_t lport,
2438 __in uint32_t rhost,
2439 __in uint16_t rport);
2441 extern __checkReturn efx_rc_t
2442 efx_filter_spec_set_eth_local(
2443 __inout efx_filter_spec_t *spec,
2445 __in const uint8_t *addr);
2448 efx_filter_spec_set_ether_type(
2449 __inout efx_filter_spec_t *spec,
2450 __in uint16_t ether_type);
2452 extern __checkReturn efx_rc_t
2453 efx_filter_spec_set_uc_def(
2454 __inout efx_filter_spec_t *spec);
2456 extern __checkReturn efx_rc_t
2457 efx_filter_spec_set_mc_def(
2458 __inout efx_filter_spec_t *spec);
2460 typedef enum efx_filter_inner_frame_match_e {
2461 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2462 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2463 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2464 } efx_filter_inner_frame_match_t;
2466 extern __checkReturn efx_rc_t
2467 efx_filter_spec_set_encap_type(
2468 __inout efx_filter_spec_t *spec,
2469 __in efx_tunnel_protocol_t encap_type,
2470 __in efx_filter_inner_frame_match_t inner_frame_match);
2472 #if EFSYS_OPT_RX_SCALE
2473 extern __checkReturn efx_rc_t
2474 efx_filter_spec_set_rss_context(
2475 __inout efx_filter_spec_t *spec,
2476 __in uint32_t rss_context);
2478 #endif /* EFSYS_OPT_FILTER */
2482 extern __checkReturn uint32_t
2484 __in_ecount(count) uint32_t const *input,
2486 __in uint32_t init);
2488 extern __checkReturn uint32_t
2490 __in_ecount(length) uint8_t const *input,
2492 __in uint32_t init);
2494 #if EFSYS_OPT_LICENSING
2498 typedef struct efx_key_stats_s {
2500 uint32_t eks_invalid;
2501 uint32_t eks_blacklisted;
2502 uint32_t eks_unverifiable;
2503 uint32_t eks_wrong_node;
2504 uint32_t eks_licensed_apps_lo;
2505 uint32_t eks_licensed_apps_hi;
2506 uint32_t eks_licensed_features_lo;
2507 uint32_t eks_licensed_features_hi;
2510 extern __checkReturn efx_rc_t
2512 __in efx_nic_t *enp);
2516 __in efx_nic_t *enp);
2518 extern __checkReturn boolean_t
2519 efx_lic_check_support(
2520 __in efx_nic_t *enp);
2522 extern __checkReturn efx_rc_t
2523 efx_lic_update_licenses(
2524 __in efx_nic_t *enp);
2526 extern __checkReturn efx_rc_t
2527 efx_lic_get_key_stats(
2528 __in efx_nic_t *enp,
2529 __out efx_key_stats_t *ksp);
2531 extern __checkReturn efx_rc_t
2533 __in efx_nic_t *enp,
2534 __in uint64_t app_id,
2535 __out boolean_t *licensedp);
2537 extern __checkReturn efx_rc_t
2539 __in efx_nic_t *enp,
2540 __in size_t buffer_size,
2541 __out uint32_t *typep,
2542 __out size_t *lengthp,
2543 __out_opt uint8_t *bufferp);
2546 extern __checkReturn efx_rc_t
2548 __in efx_nic_t *enp,
2549 __in_bcount(buffer_size)
2551 __in size_t buffer_size,
2552 __out uint32_t *startp);
2554 extern __checkReturn efx_rc_t
2556 __in efx_nic_t *enp,
2557 __in_bcount(buffer_size)
2559 __in size_t buffer_size,
2560 __in uint32_t offset,
2561 __out uint32_t *endp);
2563 extern __checkReturn __success(return != B_FALSE) boolean_t
2565 __in efx_nic_t *enp,
2566 __in_bcount(buffer_size)
2568 __in size_t buffer_size,
2569 __in uint32_t offset,
2570 __out uint32_t *startp,
2571 __out uint32_t *lengthp);
2573 extern __checkReturn __success(return != B_FALSE) boolean_t
2574 efx_lic_validate_key(
2575 __in efx_nic_t *enp,
2576 __in_bcount(length) caddr_t keyp,
2577 __in uint32_t length);
2579 extern __checkReturn efx_rc_t
2581 __in efx_nic_t *enp,
2582 __in_bcount(buffer_size)
2584 __in size_t buffer_size,
2585 __in uint32_t offset,
2586 __in uint32_t length,
2587 __out_bcount_part(key_max_size, *lengthp)
2589 __in size_t key_max_size,
2590 __out uint32_t *lengthp);
2592 extern __checkReturn efx_rc_t
2594 __in efx_nic_t *enp,
2595 __in_bcount(buffer_size)
2597 __in size_t buffer_size,
2598 __in uint32_t offset,
2599 __in_bcount(length) caddr_t keyp,
2600 __in uint32_t length,
2601 __out uint32_t *lengthp);
2603 __checkReturn efx_rc_t
2605 __in efx_nic_t *enp,
2606 __in_bcount(buffer_size)
2608 __in size_t buffer_size,
2609 __in uint32_t offset,
2610 __in uint32_t length,
2612 __out uint32_t *deltap);
2614 extern __checkReturn efx_rc_t
2615 efx_lic_create_partition(
2616 __in efx_nic_t *enp,
2617 __in_bcount(buffer_size)
2619 __in size_t buffer_size);
2621 extern __checkReturn efx_rc_t
2622 efx_lic_finish_partition(
2623 __in efx_nic_t *enp,
2624 __in_bcount(buffer_size)
2626 __in size_t buffer_size);
2628 #endif /* EFSYS_OPT_LICENSING */
2632 #if EFSYS_OPT_TUNNEL
2634 extern __checkReturn efx_rc_t
2636 __in efx_nic_t *enp);
2640 __in efx_nic_t *enp);
2643 * For overlay network encapsulation using UDP, the firmware needs to know
2644 * the configured UDP port for the overlay so it can decode encapsulated
2646 * The UDP port/protocol list is global.
2649 extern __checkReturn efx_rc_t
2650 efx_tunnel_config_udp_add(
2651 __in efx_nic_t *enp,
2652 __in uint16_t port /* host/cpu-endian */,
2653 __in efx_tunnel_protocol_t protocol);
2655 extern __checkReturn efx_rc_t
2656 efx_tunnel_config_udp_remove(
2657 __in efx_nic_t *enp,
2658 __in uint16_t port /* host/cpu-endian */,
2659 __in efx_tunnel_protocol_t protocol);
2662 efx_tunnel_config_clear(
2663 __in efx_nic_t *enp);
2666 * Apply tunnel UDP ports configuration to hardware.
2668 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2671 extern __checkReturn efx_rc_t
2672 efx_tunnel_reconfigure(
2673 __in efx_nic_t *enp);
2675 #endif /* EFSYS_OPT_TUNNEL */
2682 #endif /* _SYS_EFX_H */