2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 extern __checkReturn efx_rc_t
152 efx_nic_register_test(
153 __in efx_nic_t *enp);
155 #endif /* EFSYS_OPT_DIAG */
159 __in efx_nic_t *enp);
163 __in efx_nic_t *enp);
167 __in efx_nic_t *enp);
169 #define EFX_PCIE_LINK_SPEED_GEN1 1
170 #define EFX_PCIE_LINK_SPEED_GEN2 2
171 #define EFX_PCIE_LINK_SPEED_GEN3 3
173 typedef enum efx_pcie_link_performance_e {
174 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
175 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
176 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
177 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
178 } efx_pcie_link_performance_t;
180 extern __checkReturn efx_rc_t
181 efx_nic_calculate_pcie_link_bandwidth(
182 __in uint32_t pcie_link_width,
183 __in uint32_t pcie_link_gen,
184 __out uint32_t *bandwidth_mbpsp);
186 extern __checkReturn efx_rc_t
187 efx_nic_check_pcie_link_speed(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out efx_pcie_link_performance_t *resultp);
195 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
196 /* Huntington and Medford require MCDIv2 commands */
197 #define WITH_MCDI_V2 1
200 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
202 typedef enum efx_mcdi_exception_e {
203 EFX_MCDI_EXCEPTION_MC_REBOOT,
204 EFX_MCDI_EXCEPTION_MC_BADASSERT,
205 } efx_mcdi_exception_t;
207 #if EFSYS_OPT_MCDI_LOGGING
208 typedef enum efx_log_msg_e {
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_get_timeout(
246 __in efx_mcdi_req_t *emrp,
247 __out uint32_t *usec_timeoutp);
250 efx_mcdi_request_start(
252 __in efx_mcdi_req_t *emrp,
253 __in boolean_t ev_cpl);
255 extern __checkReturn boolean_t
256 efx_mcdi_request_poll(
257 __in efx_nic_t *enp);
259 extern __checkReturn boolean_t
260 efx_mcdi_request_abort(
261 __in efx_nic_t *enp);
265 __in efx_nic_t *enp);
267 #endif /* EFSYS_OPT_MCDI */
271 #define EFX_NINTR_SIENA 1024
273 typedef enum efx_intr_type_e {
274 EFX_INTR_INVALID = 0,
280 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
282 extern __checkReturn efx_rc_t
285 __in efx_intr_type_t type,
286 __in efsys_mem_t *esmp);
290 __in efx_nic_t *enp);
294 __in efx_nic_t *enp);
297 efx_intr_disable_unlocked(
298 __in efx_nic_t *enp);
300 #define EFX_INTR_NEVQS 32
302 extern __checkReturn efx_rc_t
305 __in unsigned int level);
308 efx_intr_status_line(
310 __out boolean_t *fatalp,
311 __out uint32_t *maskp);
314 efx_intr_status_message(
316 __in unsigned int message,
317 __out boolean_t *fatalp);
321 __in efx_nic_t *enp);
325 __in efx_nic_t *enp);
329 typedef enum efx_link_mode_e {
330 EFX_LINK_UNKNOWN = 0,
343 #define EFX_MAC_ADDR_LEN 6
345 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
347 #define EFX_MAC_MULTICAST_LIST_MAX 256
349 #define EFX_MAC_SDU_MAX 9202
351 #define EFX_MAC_PDU_ADJUSTMENT \
355 + /* bug16011 */ 16) \
357 #define EFX_MAC_PDU(_sdu) \
358 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
361 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
362 * the SDU rounded up slightly.
364 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
366 #define EFX_MAC_PDU_MIN 60
367 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
369 extern __checkReturn efx_rc_t
374 extern __checkReturn efx_rc_t
379 extern __checkReturn efx_rc_t
384 extern __checkReturn efx_rc_t
387 __in boolean_t all_unicst,
388 __in boolean_t mulcst,
389 __in boolean_t all_mulcst,
390 __in boolean_t brdcst);
392 extern __checkReturn efx_rc_t
393 efx_mac_multicast_list_set(
395 __in_ecount(6*count) uint8_t const *addrs,
398 extern __checkReturn efx_rc_t
399 efx_mac_filter_default_rxq_set(
402 __in boolean_t using_rss);
405 efx_mac_filter_default_rxq_clear(
406 __in efx_nic_t *enp);
408 extern __checkReturn efx_rc_t
411 __in boolean_t enabled);
413 extern __checkReturn efx_rc_t
416 __out boolean_t *mac_upp);
418 #define EFX_FCNTL_RESPOND 0x00000001
419 #define EFX_FCNTL_GENERATE 0x00000002
421 extern __checkReturn efx_rc_t
424 __in unsigned int fcntl,
425 __in boolean_t autoneg);
430 __out unsigned int *fcntl_wantedp,
431 __out unsigned int *fcntl_linkp);
436 typedef enum efx_mon_type_e {
448 __in efx_nic_t *enp);
450 #endif /* EFSYS_OPT_NAMES */
452 extern __checkReturn efx_rc_t
454 __in efx_nic_t *enp);
458 __in efx_nic_t *enp);
462 extern __checkReturn efx_rc_t
464 __in efx_nic_t *enp);
466 extern __checkReturn efx_rc_t
468 __in efx_nic_t *enp);
470 extern __checkReturn efx_rc_t
473 __out_opt efx_link_mode_t *link_modep);
477 __in efx_nic_t *enp);
479 typedef enum efx_phy_cap_type_e {
480 EFX_PHY_CAP_INVALID = 0,
487 EFX_PHY_CAP_10000FDX,
491 EFX_PHY_CAP_40000FDX,
493 } efx_phy_cap_type_t;
496 #define EFX_PHY_CAP_CURRENT 0x00000000
497 #define EFX_PHY_CAP_DEFAULT 0x00000001
498 #define EFX_PHY_CAP_PERM 0x00000002
504 __out uint32_t *maskp);
506 extern __checkReturn efx_rc_t
514 __out uint32_t *maskp);
516 extern __checkReturn efx_rc_t
519 __out uint32_t *ouip);
521 typedef enum efx_phy_media_type_e {
522 EFX_PHY_MEDIA_INVALID = 0,
527 EFX_PHY_MEDIA_SFP_PLUS,
528 EFX_PHY_MEDIA_BASE_T,
529 EFX_PHY_MEDIA_QSFP_PLUS,
531 } efx_phy_media_type_t;
533 /* Get the type of medium currently used. If the board has ports for
534 * modules, a module is present, and we recognise the media type of
535 * the module, then this will be the media type of the module.
536 * Otherwise it will be the media type of the port.
539 efx_phy_media_type_get(
541 __out efx_phy_media_type_t *typep);
544 efx_phy_module_get_info(
546 __in uint8_t dev_addr,
549 __out_bcount(len) uint8_t *data);
551 #if EFSYS_OPT_PHY_STATS
553 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
554 typedef enum efx_phy_stat_e {
556 EFX_PHY_STAT_PMA_PMD_LINK_UP,
557 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
558 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
559 EFX_PHY_STAT_PMA_PMD_REV_A,
560 EFX_PHY_STAT_PMA_PMD_REV_B,
561 EFX_PHY_STAT_PMA_PMD_REV_C,
562 EFX_PHY_STAT_PMA_PMD_REV_D,
563 EFX_PHY_STAT_PCS_LINK_UP,
564 EFX_PHY_STAT_PCS_RX_FAULT,
565 EFX_PHY_STAT_PCS_TX_FAULT,
566 EFX_PHY_STAT_PCS_BER,
567 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
568 EFX_PHY_STAT_PHY_XS_LINK_UP,
569 EFX_PHY_STAT_PHY_XS_RX_FAULT,
570 EFX_PHY_STAT_PHY_XS_TX_FAULT,
571 EFX_PHY_STAT_PHY_XS_ALIGN,
572 EFX_PHY_STAT_PHY_XS_SYNC_A,
573 EFX_PHY_STAT_PHY_XS_SYNC_B,
574 EFX_PHY_STAT_PHY_XS_SYNC_C,
575 EFX_PHY_STAT_PHY_XS_SYNC_D,
576 EFX_PHY_STAT_AN_LINK_UP,
577 EFX_PHY_STAT_AN_MASTER,
578 EFX_PHY_STAT_AN_LOCAL_RX_OK,
579 EFX_PHY_STAT_AN_REMOTE_RX_OK,
580 EFX_PHY_STAT_CL22EXT_LINK_UP,
585 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
586 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
587 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
588 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
589 EFX_PHY_STAT_AN_COMPLETE,
590 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
591 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
592 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
593 EFX_PHY_STAT_PCS_FW_VERSION_0,
594 EFX_PHY_STAT_PCS_FW_VERSION_1,
595 EFX_PHY_STAT_PCS_FW_VERSION_2,
596 EFX_PHY_STAT_PCS_FW_VERSION_3,
597 EFX_PHY_STAT_PCS_FW_BUILD_YY,
598 EFX_PHY_STAT_PCS_FW_BUILD_MM,
599 EFX_PHY_STAT_PCS_FW_BUILD_DD,
600 EFX_PHY_STAT_PCS_OP_MODE,
604 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
611 __in efx_phy_stat_t stat);
613 #endif /* EFSYS_OPT_NAMES */
615 #define EFX_PHY_STATS_SIZE 0x100
617 extern __checkReturn efx_rc_t
618 efx_phy_stats_update(
620 __in efsys_mem_t *esmp,
621 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
623 #endif /* EFSYS_OPT_PHY_STATS */
628 typedef enum efx_bist_type_e {
629 EFX_BIST_TYPE_UNKNOWN,
630 EFX_BIST_TYPE_PHY_NORMAL,
631 EFX_BIST_TYPE_PHY_CABLE_SHORT,
632 EFX_BIST_TYPE_PHY_CABLE_LONG,
633 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
634 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
635 EFX_BIST_TYPE_REG, /* Test the register memories */
636 EFX_BIST_TYPE_NTYPES,
639 typedef enum efx_bist_result_e {
640 EFX_BIST_RESULT_UNKNOWN,
641 EFX_BIST_RESULT_RUNNING,
642 EFX_BIST_RESULT_PASSED,
643 EFX_BIST_RESULT_FAILED,
646 typedef enum efx_phy_cable_status_e {
647 EFX_PHY_CABLE_STATUS_OK,
648 EFX_PHY_CABLE_STATUS_INVALID,
649 EFX_PHY_CABLE_STATUS_OPEN,
650 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
651 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
652 EFX_PHY_CABLE_STATUS_BUSY,
653 } efx_phy_cable_status_t;
655 typedef enum efx_bist_value_e {
656 EFX_BIST_PHY_CABLE_LENGTH_A,
657 EFX_BIST_PHY_CABLE_LENGTH_B,
658 EFX_BIST_PHY_CABLE_LENGTH_C,
659 EFX_BIST_PHY_CABLE_LENGTH_D,
660 EFX_BIST_PHY_CABLE_STATUS_A,
661 EFX_BIST_PHY_CABLE_STATUS_B,
662 EFX_BIST_PHY_CABLE_STATUS_C,
663 EFX_BIST_PHY_CABLE_STATUS_D,
665 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
673 EFX_BIST_MEM_ECC_PARITY,
674 EFX_BIST_MEM_ECC_FATAL,
678 extern __checkReturn efx_rc_t
679 efx_bist_enable_offline(
680 __in efx_nic_t *enp);
682 extern __checkReturn efx_rc_t
685 __in efx_bist_type_t type);
687 extern __checkReturn efx_rc_t
690 __in efx_bist_type_t type,
691 __out efx_bist_result_t *resultp,
692 __out_opt uint32_t *value_maskp,
693 __out_ecount_opt(count) unsigned long *valuesp,
699 __in efx_bist_type_t type);
701 #endif /* EFSYS_OPT_BIST */
703 #define EFX_FEATURE_IPV6 0x00000001
704 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
705 #define EFX_FEATURE_LINK_EVENTS 0x00000004
706 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
707 #define EFX_FEATURE_MCDI 0x00000020
708 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
709 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
710 #define EFX_FEATURE_TURBO 0x00000100
711 #define EFX_FEATURE_MCDI_DMA 0x00000200
712 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
713 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
714 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
715 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
716 #define EFX_FEATURE_PACKED_STREAM 0x00004000
718 typedef struct efx_nic_cfg_s {
719 uint32_t enc_board_type;
720 uint32_t enc_phy_type;
722 char enc_phy_name[21];
724 char enc_phy_revision[21];
725 efx_mon_type_t enc_mon_type;
726 unsigned int enc_features;
727 uint8_t enc_mac_addr[6];
728 uint8_t enc_port; /* PHY port number */
729 uint32_t enc_intr_vec_base;
730 uint32_t enc_intr_limit;
731 uint32_t enc_evq_limit;
732 uint32_t enc_txq_limit;
733 uint32_t enc_rxq_limit;
734 uint32_t enc_txq_max_ndescs;
735 uint32_t enc_buftbl_limit;
736 uint32_t enc_piobuf_limit;
737 uint32_t enc_piobuf_size;
738 uint32_t enc_piobuf_min_alloc_size;
739 uint32_t enc_evq_timer_quantum_ns;
740 uint32_t enc_evq_timer_max_us;
741 uint32_t enc_clk_mult;
742 uint32_t enc_rx_prefix_size;
743 uint32_t enc_rx_buf_align_start;
744 uint32_t enc_rx_buf_align_end;
745 #if EFSYS_OPT_PHY_FLAGS
746 uint32_t enc_phy_flags_mask;
747 #endif /* EFSYS_OPT_PHY_FLAGS */
748 #if EFSYS_OPT_PHY_STATS
749 uint64_t enc_phy_stat_mask;
750 #endif /* EFSYS_OPT_PHY_STATS */
752 uint8_t enc_mcdi_mdio_channel;
753 #if EFSYS_OPT_PHY_STATS
754 uint32_t enc_mcdi_phy_stat_mask;
755 #endif /* EFSYS_OPT_PHY_STATS */
756 #endif /* EFSYS_OPT_MCDI */
758 uint32_t enc_bist_mask;
759 #endif /* EFSYS_OPT_BIST */
760 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
763 uint32_t enc_privilege_mask;
764 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
765 boolean_t enc_bug26807_workaround;
766 boolean_t enc_bug35388_workaround;
767 boolean_t enc_bug41750_workaround;
768 boolean_t enc_bug61265_workaround;
769 boolean_t enc_rx_batching_enabled;
770 /* Maximum number of descriptors completed in an rx event. */
771 uint32_t enc_rx_batch_max;
772 /* Number of rx descriptors the hardware requires for a push. */
773 uint32_t enc_rx_push_align;
775 * Maximum number of bytes into the packet the TCP header can start for
776 * the hardware to apply TSO packet edits.
778 uint32_t enc_tx_tso_tcp_header_offset_limit;
779 boolean_t enc_fw_assisted_tso_enabled;
780 boolean_t enc_fw_assisted_tso_v2_enabled;
781 /* Number of TSO contexts on the NIC (FATSOv2) */
782 uint32_t enc_fw_assisted_tso_v2_n_contexts;
783 boolean_t enc_hw_tx_insert_vlan_enabled;
784 /* Number of PFs on the NIC */
785 uint32_t enc_hw_pf_count;
786 /* Datapath firmware vadapter/vport/vswitch support */
787 boolean_t enc_datapath_cap_evb;
788 boolean_t enc_rx_disable_scatter_supported;
789 boolean_t enc_allow_set_mac_with_installed_filters;
790 boolean_t enc_enhanced_set_mac_supported;
791 boolean_t enc_init_evq_v2_supported;
792 boolean_t enc_rx_packed_stream_supported;
793 boolean_t enc_rx_var_packed_stream_supported;
794 boolean_t enc_pm_and_rxdp_counters;
795 boolean_t enc_mac_stats_40g_tx_size_bins;
796 /* External port identifier */
797 uint8_t enc_external_port;
798 uint32_t enc_mcdi_max_payload_length;
799 /* VPD may be per-PF or global */
800 boolean_t enc_vpd_is_global;
801 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
802 uint32_t enc_required_pcie_bandwidth_mbps;
803 uint32_t enc_max_pcie_link_gen;
804 /* Firmware verifies integrity of NVRAM updates */
805 uint32_t enc_fw_verified_nvram_update_required;
808 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
809 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
811 #define EFX_PCI_FUNCTION(_encp) \
812 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
814 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
816 extern const efx_nic_cfg_t *
818 __in efx_nic_t *enp);
820 /* Driver resource limits (minimum required/maximum usable). */
821 typedef struct efx_drv_limits_s {
822 uint32_t edl_min_evq_count;
823 uint32_t edl_max_evq_count;
825 uint32_t edl_min_rxq_count;
826 uint32_t edl_max_rxq_count;
828 uint32_t edl_min_txq_count;
829 uint32_t edl_max_txq_count;
831 /* PIO blocks (sub-allocated from piobuf) */
832 uint32_t edl_min_pio_alloc_size;
833 uint32_t edl_max_pio_alloc_count;
836 extern __checkReturn efx_rc_t
837 efx_nic_set_drv_limits(
838 __inout efx_nic_t *enp,
839 __in efx_drv_limits_t *edlp);
841 typedef enum efx_nic_region_e {
842 EFX_REGION_VI, /* Memory BAR UC mapping */
843 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
846 extern __checkReturn efx_rc_t
847 efx_nic_get_bar_region(
849 __in efx_nic_region_t region,
850 __out uint32_t *offsetp,
851 __out size_t *sizep);
853 extern __checkReturn efx_rc_t
856 __out uint32_t *evq_countp,
857 __out uint32_t *rxq_countp,
858 __out uint32_t *txq_countp);
865 typedef enum efx_pattern_type_t {
866 EFX_PATTERN_BYTE_INCREMENT = 0,
867 EFX_PATTERN_ALL_THE_SAME,
868 EFX_PATTERN_BIT_ALTERNATE,
869 EFX_PATTERN_BYTE_ALTERNATE,
870 EFX_PATTERN_BYTE_CHANGING,
871 EFX_PATTERN_BIT_SWEEP,
873 } efx_pattern_type_t;
876 (*efx_sram_pattern_fn_t)(
878 __in boolean_t negate,
879 __out efx_qword_t *eqp);
881 extern __checkReturn efx_rc_t
884 __in efx_pattern_type_t type);
886 #endif /* EFSYS_OPT_DIAG */
888 extern __checkReturn efx_rc_t
889 efx_sram_buf_tbl_set(
892 __in efsys_mem_t *esmp,
896 efx_sram_buf_tbl_clear(
901 #define EFX_BUF_TBL_SIZE 0x20000
903 #define EFX_BUF_SIZE 4096
907 typedef struct efx_evq_s efx_evq_t;
911 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
912 typedef enum efx_ev_qstat_e {
919 EV_RX_BUF_OWNER_ID_ERR,
920 EV_RX_IPV4_HDR_CHKSUM_ERR,
921 EV_RX_TCP_UDP_CHKSUM_ERR,
925 EV_RX_MCAST_HASH_MATCH,
942 EV_DRIVER_SRM_UPD_DONE,
943 EV_DRIVER_TX_DESCQ_FLS_DONE,
944 EV_DRIVER_RX_DESCQ_FLS_DONE,
945 EV_DRIVER_RX_DESCQ_FLS_FAILED,
946 EV_DRIVER_RX_DSC_ERROR,
947 EV_DRIVER_TX_DSC_ERROR,
953 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
955 #endif /* EFSYS_OPT_QSTATS */
957 extern __checkReturn efx_rc_t
959 __in efx_nic_t *enp);
963 __in efx_nic_t *enp);
965 #define EFX_EVQ_MAXNEVS 32768
966 #define EFX_EVQ_MINNEVS 512
968 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
969 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
971 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
972 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
973 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
974 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
976 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
977 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
978 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
980 extern __checkReturn efx_rc_t
983 __in unsigned int index,
984 __in efsys_mem_t *esmp,
989 __deref_out efx_evq_t **eepp);
996 typedef __checkReturn boolean_t
997 (*efx_initialized_ev_t)(
1000 #define EFX_PKT_UNICAST 0x0004
1001 #define EFX_PKT_START 0x0008
1003 #define EFX_PKT_VLAN_TAGGED 0x0010
1004 #define EFX_CKSUM_TCPUDP 0x0020
1005 #define EFX_CKSUM_IPV4 0x0040
1006 #define EFX_PKT_CONT 0x0080
1008 #define EFX_CHECK_VLAN 0x0100
1009 #define EFX_PKT_TCP 0x0200
1010 #define EFX_PKT_UDP 0x0400
1011 #define EFX_PKT_IPV4 0x0800
1013 #define EFX_PKT_IPV6 0x1000
1014 #define EFX_PKT_PREFIX_LEN 0x2000
1015 #define EFX_ADDR_MISMATCH 0x4000
1016 #define EFX_DISCARD 0x8000
1019 * The following flags are used only for packed stream
1020 * mode. The values for the flags are reused to fit into 16 bit,
1021 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1022 * packed stream mode
1024 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1025 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1028 #define EFX_EV_RX_NLABELS 32
1029 #define EFX_EV_TX_NLABELS 32
1031 typedef __checkReturn boolean_t
1034 __in uint32_t label,
1037 __in uint16_t flags);
1039 typedef __checkReturn boolean_t
1042 __in uint32_t label,
1045 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1046 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1047 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1048 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1049 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1050 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1051 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1052 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1053 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1055 typedef __checkReturn boolean_t
1056 (*efx_exception_ev_t)(
1058 __in uint32_t label,
1059 __in uint32_t data);
1061 typedef __checkReturn boolean_t
1062 (*efx_rxq_flush_done_ev_t)(
1064 __in uint32_t rxq_index);
1066 typedef __checkReturn boolean_t
1067 (*efx_rxq_flush_failed_ev_t)(
1069 __in uint32_t rxq_index);
1071 typedef __checkReturn boolean_t
1072 (*efx_txq_flush_done_ev_t)(
1074 __in uint32_t txq_index);
1076 typedef __checkReturn boolean_t
1077 (*efx_software_ev_t)(
1079 __in uint16_t magic);
1081 typedef __checkReturn boolean_t
1084 __in uint32_t code);
1086 #define EFX_SRAM_CLEAR 0
1087 #define EFX_SRAM_UPDATE 1
1088 #define EFX_SRAM_ILLEGAL_CLEAR 2
1090 typedef __checkReturn boolean_t
1091 (*efx_wake_up_ev_t)(
1093 __in uint32_t label);
1095 typedef __checkReturn boolean_t
1098 __in uint32_t label);
1100 typedef __checkReturn boolean_t
1101 (*efx_link_change_ev_t)(
1103 __in efx_link_mode_t link_mode);
1105 typedef struct efx_ev_callbacks_s {
1106 efx_initialized_ev_t eec_initialized;
1109 efx_exception_ev_t eec_exception;
1110 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1111 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1112 efx_txq_flush_done_ev_t eec_txq_flush_done;
1113 efx_software_ev_t eec_software;
1114 efx_sram_ev_t eec_sram;
1115 efx_wake_up_ev_t eec_wake_up;
1116 efx_timer_ev_t eec_timer;
1117 efx_link_change_ev_t eec_link_change;
1118 } efx_ev_callbacks_t;
1120 extern __checkReturn boolean_t
1122 __in efx_evq_t *eep,
1123 __in unsigned int count);
1127 __in efx_evq_t *eep,
1128 __inout unsigned int *countp,
1129 __in const efx_ev_callbacks_t *eecp,
1130 __in_opt void *arg);
1132 extern __checkReturn efx_rc_t
1133 efx_ev_usecs_to_ticks(
1134 __in efx_nic_t *enp,
1135 __in unsigned int usecs,
1136 __out unsigned int *ticksp);
1138 extern __checkReturn efx_rc_t
1140 __in efx_evq_t *eep,
1141 __in unsigned int us);
1143 extern __checkReturn efx_rc_t
1145 __in efx_evq_t *eep,
1146 __in unsigned int count);
1148 #if EFSYS_OPT_QSTATS
1154 __in efx_nic_t *enp,
1155 __in unsigned int id);
1157 #endif /* EFSYS_OPT_NAMES */
1160 efx_ev_qstats_update(
1161 __in efx_evq_t *eep,
1162 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1164 #endif /* EFSYS_OPT_QSTATS */
1168 __in efx_evq_t *eep);
1172 extern __checkReturn efx_rc_t
1174 __inout efx_nic_t *enp);
1178 __in efx_nic_t *enp);
1180 extern __checkReturn efx_rc_t
1181 efx_pseudo_hdr_pkt_length_get(
1182 __in efx_rxq_t *erp,
1183 __in uint8_t *buffer,
1184 __out uint16_t *pkt_lengthp);
1186 #define EFX_RXQ_MAXNDESCS 4096
1187 #define EFX_RXQ_MINNDESCS 512
1189 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1190 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1191 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1192 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1194 typedef enum efx_rxq_type_e {
1195 EFX_RXQ_TYPE_DEFAULT,
1196 EFX_RXQ_TYPE_SCATTER,
1197 EFX_RXQ_TYPE_PACKED_STREAM_1M,
1198 EFX_RXQ_TYPE_PACKED_STREAM_512K,
1199 EFX_RXQ_TYPE_PACKED_STREAM_256K,
1200 EFX_RXQ_TYPE_PACKED_STREAM_128K,
1201 EFX_RXQ_TYPE_PACKED_STREAM_64K,
1205 extern __checkReturn efx_rc_t
1207 __in efx_nic_t *enp,
1208 __in unsigned int index,
1209 __in unsigned int label,
1210 __in efx_rxq_type_t type,
1211 __in efsys_mem_t *esmp,
1214 __in efx_evq_t *eep,
1215 __deref_out efx_rxq_t **erpp);
1217 typedef struct efx_buffer_s {
1218 efsys_dma_addr_t eb_addr;
1223 typedef struct efx_desc_s {
1229 __in efx_rxq_t *erp,
1230 __in_ecount(n) efsys_dma_addr_t *addrp,
1232 __in unsigned int n,
1233 __in unsigned int completed,
1234 __in unsigned int added);
1238 __in efx_rxq_t *erp,
1239 __in unsigned int added,
1240 __inout unsigned int *pushedp);
1242 extern __checkReturn efx_rc_t
1244 __in efx_rxq_t *erp);
1248 __in efx_rxq_t *erp);
1252 __in efx_rxq_t *erp);
1256 typedef struct efx_txq_s efx_txq_t;
1258 #if EFSYS_OPT_QSTATS
1260 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1261 typedef enum efx_tx_qstat_e {
1267 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1269 #endif /* EFSYS_OPT_QSTATS */
1271 extern __checkReturn efx_rc_t
1273 __in efx_nic_t *enp);
1277 __in efx_nic_t *enp);
1279 #define EFX_TXQ_MINNDESCS 512
1281 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1282 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1283 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1284 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1286 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1288 #define EFX_TXQ_CKSUM_IPV4 0x0001
1289 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1290 #define EFX_TXQ_FATSOV2 0x0004
1292 extern __checkReturn efx_rc_t
1294 __in efx_nic_t *enp,
1295 __in unsigned int index,
1296 __in unsigned int label,
1297 __in efsys_mem_t *esmp,
1300 __in uint16_t flags,
1301 __in efx_evq_t *eep,
1302 __deref_out efx_txq_t **etpp,
1303 __out unsigned int *addedp);
1305 extern __checkReturn efx_rc_t
1307 __in efx_txq_t *etp,
1308 __in_ecount(n) efx_buffer_t *eb,
1309 __in unsigned int n,
1310 __in unsigned int completed,
1311 __inout unsigned int *addedp);
1313 extern __checkReturn efx_rc_t
1315 __in efx_txq_t *etp,
1316 __in unsigned int ns);
1320 __in efx_txq_t *etp,
1321 __in unsigned int added,
1322 __in unsigned int pushed);
1324 extern __checkReturn efx_rc_t
1326 __in efx_txq_t *etp);
1330 __in efx_txq_t *etp);
1332 extern __checkReturn efx_rc_t
1334 __in efx_txq_t *etp);
1337 efx_tx_qpio_disable(
1338 __in efx_txq_t *etp);
1340 extern __checkReturn efx_rc_t
1342 __in efx_txq_t *etp,
1343 __in_ecount(buf_length) uint8_t *buffer,
1344 __in size_t buf_length,
1345 __in size_t pio_buf_offset);
1347 extern __checkReturn efx_rc_t
1349 __in efx_txq_t *etp,
1350 __in size_t pkt_length,
1351 __in unsigned int completed,
1352 __inout unsigned int *addedp);
1354 extern __checkReturn efx_rc_t
1356 __in efx_txq_t *etp,
1357 __in_ecount(n) efx_desc_t *ed,
1358 __in unsigned int n,
1359 __in unsigned int completed,
1360 __inout unsigned int *addedp);
1363 efx_tx_qdesc_dma_create(
1364 __in efx_txq_t *etp,
1365 __in efsys_dma_addr_t addr,
1368 __out efx_desc_t *edp);
1371 efx_tx_qdesc_tso_create(
1372 __in efx_txq_t *etp,
1373 __in uint16_t ipv4_id,
1374 __in uint32_t tcp_seq,
1375 __in uint8_t tcp_flags,
1376 __out efx_desc_t *edp);
1378 /* Number of FATSOv2 option descriptors */
1379 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1381 /* Maximum number of DMA segments per TSO packet (not superframe) */
1382 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1385 efx_tx_qdesc_tso2_create(
1386 __in efx_txq_t *etp,
1387 __in uint16_t ipv4_id,
1388 __in uint32_t tcp_seq,
1389 __in uint16_t tcp_mss,
1390 __out_ecount(count) efx_desc_t *edp,
1394 efx_tx_qdesc_vlantci_create(
1395 __in efx_txq_t *etp,
1397 __out efx_desc_t *edp);
1399 #if EFSYS_OPT_QSTATS
1405 __in efx_nic_t *etp,
1406 __in unsigned int id);
1408 #endif /* EFSYS_OPT_NAMES */
1411 efx_tx_qstats_update(
1412 __in efx_txq_t *etp,
1413 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1415 #endif /* EFSYS_OPT_QSTATS */
1419 __in efx_txq_t *etp);
1424 #if EFSYS_OPT_FILTER
1426 #define EFX_ETHER_TYPE_IPV4 0x0800
1427 #define EFX_ETHER_TYPE_IPV6 0x86DD
1429 #define EFX_IPPROTO_TCP 6
1430 #define EFX_IPPROTO_UDP 17
1432 /* Use RSS to spread across multiple queues */
1433 #define EFX_FILTER_FLAG_RX_RSS 0x01
1434 /* Enable RX scatter */
1435 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1437 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1438 * May only be set by the filter implementation for each type.
1439 * A removal request will restore the automatic filter in its place.
1441 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1442 /* Filter is for RX */
1443 #define EFX_FILTER_FLAG_RX 0x08
1444 /* Filter is for TX */
1445 #define EFX_FILTER_FLAG_TX 0x10
1447 typedef unsigned int efx_filter_flags_t;
1449 typedef enum efx_filter_match_flags_e {
1450 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1452 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1454 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1455 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1456 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1457 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1458 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1459 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1460 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1461 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1463 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1464 * I/G bit. Used for RX default
1465 * unicast and multicast/
1466 * broadcast filters. */
1467 } efx_filter_match_flags_t;
1469 typedef enum efx_filter_priority_s {
1470 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1471 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1472 * address list or hardware
1473 * requirements. This may only be used
1474 * by the filter implementation for
1476 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1477 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1478 * client (e.g. SR-IOV, HyperV VMQ etc.)
1480 } efx_filter_priority_t;
1483 * FIXME: All these fields are assumed to be in little-endian byte order.
1484 * It may be better for some to be big-endian. See bug42804.
1487 typedef struct efx_filter_spec_s {
1488 uint32_t efs_match_flags:12;
1489 uint32_t efs_priority:2;
1490 uint32_t efs_flags:6;
1491 uint32_t efs_dmaq_id:12;
1492 uint32_t efs_rss_context;
1493 uint16_t efs_outer_vid;
1494 uint16_t efs_inner_vid;
1495 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1496 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1497 uint16_t efs_ether_type;
1498 uint8_t efs_ip_proto;
1499 uint16_t efs_loc_port;
1500 uint16_t efs_rem_port;
1501 efx_oword_t efs_rem_host;
1502 efx_oword_t efs_loc_host;
1503 } efx_filter_spec_t;
1506 /* Default values for use in filter specifications */
1507 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1508 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1509 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1511 extern __checkReturn efx_rc_t
1513 __in efx_nic_t *enp);
1517 __in efx_nic_t *enp);
1519 extern __checkReturn efx_rc_t
1521 __in efx_nic_t *enp,
1522 __inout efx_filter_spec_t *spec);
1524 extern __checkReturn efx_rc_t
1526 __in efx_nic_t *enp,
1527 __inout efx_filter_spec_t *spec);
1529 extern __checkReturn efx_rc_t
1531 __in efx_nic_t *enp);
1533 extern __checkReturn efx_rc_t
1534 efx_filter_supported_filters(
1535 __in efx_nic_t *enp,
1536 __out uint32_t *list,
1537 __out size_t *length);
1540 efx_filter_spec_init_rx(
1541 __out efx_filter_spec_t *spec,
1542 __in efx_filter_priority_t priority,
1543 __in efx_filter_flags_t flags,
1544 __in efx_rxq_t *erp);
1547 efx_filter_spec_init_tx(
1548 __out efx_filter_spec_t *spec,
1549 __in efx_txq_t *etp);
1551 extern __checkReturn efx_rc_t
1552 efx_filter_spec_set_ipv4_local(
1553 __inout efx_filter_spec_t *spec,
1556 __in uint16_t port);
1558 extern __checkReturn efx_rc_t
1559 efx_filter_spec_set_ipv4_full(
1560 __inout efx_filter_spec_t *spec,
1562 __in uint32_t lhost,
1563 __in uint16_t lport,
1564 __in uint32_t rhost,
1565 __in uint16_t rport);
1567 extern __checkReturn efx_rc_t
1568 efx_filter_spec_set_eth_local(
1569 __inout efx_filter_spec_t *spec,
1571 __in const uint8_t *addr);
1573 extern __checkReturn efx_rc_t
1574 efx_filter_spec_set_uc_def(
1575 __inout efx_filter_spec_t *spec);
1577 extern __checkReturn efx_rc_t
1578 efx_filter_spec_set_mc_def(
1579 __inout efx_filter_spec_t *spec);
1581 #endif /* EFSYS_OPT_FILTER */
1585 extern __checkReturn uint32_t
1587 __in_ecount(count) uint32_t const *input,
1589 __in uint32_t init);
1591 extern __checkReturn uint32_t
1593 __in_ecount(length) uint8_t const *input,
1595 __in uint32_t init);
1603 #endif /* _SYS_EFX_H */