2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof (char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof (_array) / sizeof ((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t)&(((_type *)0)->_field))
51 /* The macro expands divider twice */
52 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
56 typedef __success(return == 0) int efx_rc_t;
61 typedef enum efx_family_e {
63 EFX_FAMILY_FALCON, /* Obsolete and not supported */
65 EFX_FAMILY_HUNTINGTON,
70 extern __checkReturn efx_rc_t
74 __out efx_family_t *efp);
77 #define EFX_PCI_VENID_SFC 0x1924
79 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
81 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
82 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
83 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
85 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
86 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
87 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
89 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
90 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
92 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
93 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
94 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
103 EFX_ERR_BUFID_DC_OOB,
116 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
117 extern __checkReturn uint32_t
119 __in uint32_t crc_init,
120 __in_ecount(length) uint8_t const *input,
124 /* Type prototypes */
126 typedef struct efx_rxq_s efx_rxq_t;
130 typedef struct efx_nic_s efx_nic_t;
132 extern __checkReturn efx_rc_t
134 __in efx_family_t family,
135 __in efsys_identifier_t *esip,
136 __in efsys_bar_t *esbp,
137 __in efsys_lock_t *eslp,
138 __deref_out efx_nic_t **enpp);
140 extern __checkReturn efx_rc_t
142 __in efx_nic_t *enp);
144 extern __checkReturn efx_rc_t
146 __in efx_nic_t *enp);
148 extern __checkReturn efx_rc_t
150 __in efx_nic_t *enp);
154 extern __checkReturn efx_rc_t
155 efx_nic_register_test(
156 __in efx_nic_t *enp);
158 #endif /* EFSYS_OPT_DIAG */
162 __in efx_nic_t *enp);
166 __in efx_nic_t *enp);
170 __in efx_nic_t *enp);
172 #define EFX_PCIE_LINK_SPEED_GEN1 1
173 #define EFX_PCIE_LINK_SPEED_GEN2 2
174 #define EFX_PCIE_LINK_SPEED_GEN3 3
176 typedef enum efx_pcie_link_performance_e {
177 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
178 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
179 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
180 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
181 } efx_pcie_link_performance_t;
183 extern __checkReturn efx_rc_t
184 efx_nic_calculate_pcie_link_bandwidth(
185 __in uint32_t pcie_link_width,
186 __in uint32_t pcie_link_gen,
187 __out uint32_t *bandwidth_mbpsp);
189 extern __checkReturn efx_rc_t
190 efx_nic_check_pcie_link_speed(
192 __in uint32_t pcie_link_width,
193 __in uint32_t pcie_link_gen,
194 __out efx_pcie_link_performance_t *resultp);
198 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
199 /* Huntington and Medford require MCDIv2 commands */
200 #define WITH_MCDI_V2 1
203 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
205 typedef enum efx_mcdi_exception_e {
206 EFX_MCDI_EXCEPTION_MC_REBOOT,
207 EFX_MCDI_EXCEPTION_MC_BADASSERT,
208 } efx_mcdi_exception_t;
210 #if EFSYS_OPT_MCDI_LOGGING
211 typedef enum efx_log_msg_e {
213 EFX_LOG_MCDI_REQUEST,
214 EFX_LOG_MCDI_RESPONSE,
216 #endif /* EFSYS_OPT_MCDI_LOGGING */
218 typedef struct efx_mcdi_transport_s {
220 efsys_mem_t *emt_dma_mem;
221 void (*emt_execute)(void *, efx_mcdi_req_t *);
222 void (*emt_ev_cpl)(void *);
223 void (*emt_exception)(void *, efx_mcdi_exception_t);
224 #if EFSYS_OPT_MCDI_LOGGING
225 void (*emt_logger)(void *, efx_log_msg_t,
226 void *, size_t, void *, size_t);
227 #endif /* EFSYS_OPT_MCDI_LOGGING */
228 #if EFSYS_OPT_MCDI_PROXY_AUTH
229 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
230 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
231 } efx_mcdi_transport_t;
233 extern __checkReturn efx_rc_t
236 __in const efx_mcdi_transport_t *mtp);
238 extern __checkReturn efx_rc_t
240 __in efx_nic_t *enp);
244 __in efx_nic_t *enp);
247 efx_mcdi_get_timeout(
249 __in efx_mcdi_req_t *emrp,
250 __out uint32_t *usec_timeoutp);
253 efx_mcdi_request_start(
255 __in efx_mcdi_req_t *emrp,
256 __in boolean_t ev_cpl);
258 extern __checkReturn boolean_t
259 efx_mcdi_request_poll(
260 __in efx_nic_t *enp);
262 extern __checkReturn boolean_t
263 efx_mcdi_request_abort(
264 __in efx_nic_t *enp);
268 __in efx_nic_t *enp);
270 #endif /* EFSYS_OPT_MCDI */
274 #define EFX_NINTR_SIENA 1024
276 typedef enum efx_intr_type_e {
277 EFX_INTR_INVALID = 0,
283 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
285 extern __checkReturn efx_rc_t
288 __in efx_intr_type_t type,
289 __in efsys_mem_t *esmp);
293 __in efx_nic_t *enp);
297 __in efx_nic_t *enp);
300 efx_intr_disable_unlocked(
301 __in efx_nic_t *enp);
303 #define EFX_INTR_NEVQS 32
305 extern __checkReturn efx_rc_t
308 __in unsigned int level);
311 efx_intr_status_line(
313 __out boolean_t *fatalp,
314 __out uint32_t *maskp);
317 efx_intr_status_message(
319 __in unsigned int message,
320 __out boolean_t *fatalp);
324 __in efx_nic_t *enp);
328 __in efx_nic_t *enp);
332 #if EFSYS_OPT_MAC_STATS
334 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
335 typedef enum efx_mac_stat_e {
338 EFX_MAC_RX_UNICST_PKTS,
339 EFX_MAC_RX_MULTICST_PKTS,
340 EFX_MAC_RX_BRDCST_PKTS,
341 EFX_MAC_RX_PAUSE_PKTS,
342 EFX_MAC_RX_LE_64_PKTS,
343 EFX_MAC_RX_65_TO_127_PKTS,
344 EFX_MAC_RX_128_TO_255_PKTS,
345 EFX_MAC_RX_256_TO_511_PKTS,
346 EFX_MAC_RX_512_TO_1023_PKTS,
347 EFX_MAC_RX_1024_TO_15XX_PKTS,
348 EFX_MAC_RX_GE_15XX_PKTS,
350 EFX_MAC_RX_FCS_ERRORS,
351 EFX_MAC_RX_DROP_EVENTS,
352 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
353 EFX_MAC_RX_SYMBOL_ERRORS,
354 EFX_MAC_RX_ALIGN_ERRORS,
355 EFX_MAC_RX_INTERNAL_ERRORS,
356 EFX_MAC_RX_JABBER_PKTS,
357 EFX_MAC_RX_LANE0_CHAR_ERR,
358 EFX_MAC_RX_LANE1_CHAR_ERR,
359 EFX_MAC_RX_LANE2_CHAR_ERR,
360 EFX_MAC_RX_LANE3_CHAR_ERR,
361 EFX_MAC_RX_LANE0_DISP_ERR,
362 EFX_MAC_RX_LANE1_DISP_ERR,
363 EFX_MAC_RX_LANE2_DISP_ERR,
364 EFX_MAC_RX_LANE3_DISP_ERR,
365 EFX_MAC_RX_MATCH_FAULT,
366 EFX_MAC_RX_NODESC_DROP_CNT,
369 EFX_MAC_TX_UNICST_PKTS,
370 EFX_MAC_TX_MULTICST_PKTS,
371 EFX_MAC_TX_BRDCST_PKTS,
372 EFX_MAC_TX_PAUSE_PKTS,
373 EFX_MAC_TX_LE_64_PKTS,
374 EFX_MAC_TX_65_TO_127_PKTS,
375 EFX_MAC_TX_128_TO_255_PKTS,
376 EFX_MAC_TX_256_TO_511_PKTS,
377 EFX_MAC_TX_512_TO_1023_PKTS,
378 EFX_MAC_TX_1024_TO_15XX_PKTS,
379 EFX_MAC_TX_GE_15XX_PKTS,
381 EFX_MAC_TX_SGL_COL_PKTS,
382 EFX_MAC_TX_MULT_COL_PKTS,
383 EFX_MAC_TX_EX_COL_PKTS,
384 EFX_MAC_TX_LATE_COL_PKTS,
386 EFX_MAC_TX_EX_DEF_PKTS,
387 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
388 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
389 EFX_MAC_PM_TRUNC_VFIFO_FULL,
390 EFX_MAC_PM_DISCARD_VFIFO_FULL,
391 EFX_MAC_PM_TRUNC_QBB,
392 EFX_MAC_PM_DISCARD_QBB,
393 EFX_MAC_PM_DISCARD_MAPPING,
394 EFX_MAC_RXDP_Q_DISABLED_PKTS,
395 EFX_MAC_RXDP_DI_DROPPED_PKTS,
396 EFX_MAC_RXDP_STREAMING_PKTS,
397 EFX_MAC_RXDP_HLB_FETCH,
398 EFX_MAC_RXDP_HLB_WAIT,
399 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
400 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
401 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
402 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
403 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
404 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
405 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
406 EFX_MAC_VADAPTER_RX_BAD_BYTES,
407 EFX_MAC_VADAPTER_RX_OVERFLOW,
408 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
409 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
410 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
411 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
412 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
413 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
414 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
415 EFX_MAC_VADAPTER_TX_BAD_BYTES,
416 EFX_MAC_VADAPTER_TX_OVERFLOW,
420 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
422 #endif /* EFSYS_OPT_MAC_STATS */
424 typedef enum efx_link_mode_e {
425 EFX_LINK_UNKNOWN = 0,
438 #define EFX_MAC_ADDR_LEN 6
440 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
442 #define EFX_MAC_MULTICAST_LIST_MAX 256
444 #define EFX_MAC_SDU_MAX 9202
446 #define EFX_MAC_PDU_ADJUSTMENT \
450 + /* bug16011 */ 16) \
452 #define EFX_MAC_PDU(_sdu) \
453 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
456 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
457 * the SDU rounded up slightly.
459 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
461 #define EFX_MAC_PDU_MIN 60
462 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
464 extern __checkReturn efx_rc_t
469 extern __checkReturn efx_rc_t
474 extern __checkReturn efx_rc_t
479 extern __checkReturn efx_rc_t
482 __in boolean_t all_unicst,
483 __in boolean_t mulcst,
484 __in boolean_t all_mulcst,
485 __in boolean_t brdcst);
487 extern __checkReturn efx_rc_t
488 efx_mac_multicast_list_set(
490 __in_ecount(6*count) uint8_t const *addrs,
493 extern __checkReturn efx_rc_t
494 efx_mac_filter_default_rxq_set(
497 __in boolean_t using_rss);
500 efx_mac_filter_default_rxq_clear(
501 __in efx_nic_t *enp);
503 extern __checkReturn efx_rc_t
506 __in boolean_t enabled);
508 extern __checkReturn efx_rc_t
511 __out boolean_t *mac_upp);
513 #define EFX_FCNTL_RESPOND 0x00000001
514 #define EFX_FCNTL_GENERATE 0x00000002
516 extern __checkReturn efx_rc_t
519 __in unsigned int fcntl,
520 __in boolean_t autoneg);
525 __out unsigned int *fcntl_wantedp,
526 __out unsigned int *fcntl_linkp);
529 #if EFSYS_OPT_MAC_STATS
533 extern __checkReturn const char *
536 __in unsigned int id);
538 #endif /* EFSYS_OPT_NAMES */
540 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
542 #define EFX_MAC_STATS_MASK_NPAGES \
543 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
544 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
547 * Get mask of MAC statistics supported by the hardware.
549 * If mask_size is insufficient to return the mask, EINVAL error is
550 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
551 * (which is sizeof (uint32_t)) is sufficient.
553 extern __checkReturn efx_rc_t
554 efx_mac_stats_get_mask(
556 __out_bcount(mask_size) uint32_t *maskp,
557 __in size_t mask_size);
559 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
560 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
561 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
563 #define EFX_MAC_STATS_SIZE 0x400
565 extern __checkReturn efx_rc_t
567 __in efx_nic_t *enp);
570 * Upload mac statistics supported by the hardware into the given buffer.
572 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
575 * The hardware will only DMA statistics that it understands (of course).
576 * Drivers should not make any assumptions about which statistics are
577 * supported, especially when the statistics are generated by firmware.
579 * Thus, drivers should zero this buffer before use, so that not-understood
580 * statistics read back as zero.
582 extern __checkReturn efx_rc_t
583 efx_mac_stats_upload(
585 __in efsys_mem_t *esmp);
587 extern __checkReturn efx_rc_t
588 efx_mac_stats_periodic(
590 __in efsys_mem_t *esmp,
591 __in uint16_t period_ms,
592 __in boolean_t events);
594 extern __checkReturn efx_rc_t
595 efx_mac_stats_update(
597 __in efsys_mem_t *esmp,
598 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
599 __inout_opt uint32_t *generationp);
601 #endif /* EFSYS_OPT_MAC_STATS */
605 typedef enum efx_mon_type_e {
617 __in efx_nic_t *enp);
619 #endif /* EFSYS_OPT_NAMES */
621 extern __checkReturn efx_rc_t
623 __in efx_nic_t *enp);
625 #if EFSYS_OPT_MON_STATS
627 #define EFX_MON_STATS_PAGE_SIZE 0x100
628 #define EFX_MON_MASK_ELEMENT_SIZE 32
630 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock aa0233c80156308e */
631 typedef enum efx_mon_stat_e {
638 EFX_MON_STAT_EXT_TEMP,
639 EFX_MON_STAT_INT_TEMP,
642 EFX_MON_STAT_INT_COOLING,
643 EFX_MON_STAT_EXT_COOLING,
651 EFX_MON_STAT_AOE_TEMP,
652 EFX_MON_STAT_PSU_AOE_TEMP,
653 EFX_MON_STAT_PSU_TEMP,
659 EFX_MON_STAT_VAOE_IN,
661 EFX_MON_STAT_IAOE_IN,
662 EFX_MON_STAT_NIC_POWER,
666 EFX_MON_STAT_0_9V_ADC,
667 EFX_MON_STAT_INT_TEMP2,
668 EFX_MON_STAT_VREG_TEMP,
669 EFX_MON_STAT_VREG_0_9V_TEMP,
670 EFX_MON_STAT_VREG_1_2V_TEMP,
671 EFX_MON_STAT_INT_VPTAT,
672 EFX_MON_STAT_INT_ADC_TEMP,
673 EFX_MON_STAT_EXT_VPTAT,
674 EFX_MON_STAT_EXT_ADC_TEMP,
675 EFX_MON_STAT_AMBIENT_TEMP,
676 EFX_MON_STAT_AIRFLOW,
677 EFX_MON_STAT_VDD08D_VSS08D_CSR,
678 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
679 EFX_MON_STAT_HOTPOINT_TEMP,
680 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
681 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
682 EFX_MON_STAT_MUM_VCC,
685 EFX_MON_STAT_0V9_A_TEMP,
688 EFX_MON_STAT_0V9_B_TEMP,
689 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
690 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
691 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
692 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
693 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
694 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
695 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
696 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
697 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
698 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
699 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
700 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
701 EFX_MON_STAT_SODIMM_VOUT,
702 EFX_MON_STAT_SODIMM_0_TEMP,
703 EFX_MON_STAT_SODIMM_1_TEMP,
704 EFX_MON_STAT_PHY0_VCC,
705 EFX_MON_STAT_PHY1_VCC,
706 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
707 EFX_MON_STAT_BOARD_FRONT_TEMP,
708 EFX_MON_STAT_BOARD_BACK_TEMP,
714 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
716 typedef enum efx_mon_stat_state_e {
717 EFX_MON_STAT_STATE_OK = 0,
718 EFX_MON_STAT_STATE_WARNING = 1,
719 EFX_MON_STAT_STATE_FATAL = 2,
720 EFX_MON_STAT_STATE_BROKEN = 3,
721 EFX_MON_STAT_STATE_NO_READING = 4,
722 } efx_mon_stat_state_t;
724 typedef struct efx_mon_stat_value_s {
727 } efx_mon_stat_value_t;
734 __in efx_mon_stat_t id);
736 #endif /* EFSYS_OPT_NAMES */
738 extern __checkReturn efx_rc_t
739 efx_mon_stats_update(
741 __in efsys_mem_t *esmp,
742 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
744 #endif /* EFSYS_OPT_MON_STATS */
748 __in efx_nic_t *enp);
752 extern __checkReturn efx_rc_t
754 __in efx_nic_t *enp);
756 #if EFSYS_OPT_PHY_LED_CONTROL
758 typedef enum efx_phy_led_mode_e {
759 EFX_PHY_LED_DEFAULT = 0,
764 } efx_phy_led_mode_t;
766 extern __checkReturn efx_rc_t
769 __in efx_phy_led_mode_t mode);
771 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
773 extern __checkReturn efx_rc_t
775 __in efx_nic_t *enp);
777 #if EFSYS_OPT_LOOPBACK
779 typedef enum efx_loopback_type_e {
780 EFX_LOOPBACK_OFF = 0,
781 EFX_LOOPBACK_DATA = 1,
782 EFX_LOOPBACK_GMAC = 2,
783 EFX_LOOPBACK_XGMII = 3,
784 EFX_LOOPBACK_XGXS = 4,
785 EFX_LOOPBACK_XAUI = 5,
786 EFX_LOOPBACK_GMII = 6,
787 EFX_LOOPBACK_SGMII = 7,
788 EFX_LOOPBACK_XGBR = 8,
789 EFX_LOOPBACK_XFI = 9,
790 EFX_LOOPBACK_XAUI_FAR = 10,
791 EFX_LOOPBACK_GMII_FAR = 11,
792 EFX_LOOPBACK_SGMII_FAR = 12,
793 EFX_LOOPBACK_XFI_FAR = 13,
794 EFX_LOOPBACK_GPHY = 14,
795 EFX_LOOPBACK_PHY_XS = 15,
796 EFX_LOOPBACK_PCS = 16,
797 EFX_LOOPBACK_PMA_PMD = 17,
798 EFX_LOOPBACK_XPORT = 18,
799 EFX_LOOPBACK_XGMII_WS = 19,
800 EFX_LOOPBACK_XAUI_WS = 20,
801 EFX_LOOPBACK_XAUI_WS_FAR = 21,
802 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
803 EFX_LOOPBACK_GMII_WS = 23,
804 EFX_LOOPBACK_XFI_WS = 24,
805 EFX_LOOPBACK_XFI_WS_FAR = 25,
806 EFX_LOOPBACK_PHYXS_WS = 26,
807 EFX_LOOPBACK_PMA_INT = 27,
808 EFX_LOOPBACK_SD_NEAR = 28,
809 EFX_LOOPBACK_SD_FAR = 29,
810 EFX_LOOPBACK_PMA_INT_WS = 30,
811 EFX_LOOPBACK_SD_FEP2_WS = 31,
812 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
813 EFX_LOOPBACK_SD_FEP_WS = 33,
814 EFX_LOOPBACK_SD_FES_WS = 34,
816 } efx_loopback_type_t;
818 typedef enum efx_loopback_kind_e {
819 EFX_LOOPBACK_KIND_OFF = 0,
820 EFX_LOOPBACK_KIND_ALL,
821 EFX_LOOPBACK_KIND_MAC,
822 EFX_LOOPBACK_KIND_PHY,
824 } efx_loopback_kind_t;
828 __in efx_loopback_kind_t loopback_kind,
829 __out efx_qword_t *maskp);
831 extern __checkReturn efx_rc_t
832 efx_port_loopback_set(
834 __in efx_link_mode_t link_mode,
835 __in efx_loopback_type_t type);
839 extern __checkReturn const char *
840 efx_loopback_type_name(
842 __in efx_loopback_type_t type);
844 #endif /* EFSYS_OPT_NAMES */
846 #endif /* EFSYS_OPT_LOOPBACK */
848 extern __checkReturn efx_rc_t
851 __out_opt efx_link_mode_t *link_modep);
855 __in efx_nic_t *enp);
857 typedef enum efx_phy_cap_type_e {
858 EFX_PHY_CAP_INVALID = 0,
865 EFX_PHY_CAP_10000FDX,
869 EFX_PHY_CAP_40000FDX,
871 } efx_phy_cap_type_t;
874 #define EFX_PHY_CAP_CURRENT 0x00000000
875 #define EFX_PHY_CAP_DEFAULT 0x00000001
876 #define EFX_PHY_CAP_PERM 0x00000002
882 __out uint32_t *maskp);
884 extern __checkReturn efx_rc_t
892 __out uint32_t *maskp);
894 extern __checkReturn efx_rc_t
897 __out uint32_t *ouip);
899 typedef enum efx_phy_media_type_e {
900 EFX_PHY_MEDIA_INVALID = 0,
905 EFX_PHY_MEDIA_SFP_PLUS,
906 EFX_PHY_MEDIA_BASE_T,
907 EFX_PHY_MEDIA_QSFP_PLUS,
909 } efx_phy_media_type_t;
912 * Get the type of medium currently used. If the board has ports for
913 * modules, a module is present, and we recognise the media type of
914 * the module, then this will be the media type of the module.
915 * Otherwise it will be the media type of the port.
918 efx_phy_media_type_get(
920 __out efx_phy_media_type_t *typep);
922 extern __checkReturn efx_rc_t
923 efx_phy_module_get_info(
925 __in uint8_t dev_addr,
928 __out_bcount(len) uint8_t *data);
930 #if EFSYS_OPT_PHY_STATS
932 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
933 typedef enum efx_phy_stat_e {
935 EFX_PHY_STAT_PMA_PMD_LINK_UP,
936 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
937 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
938 EFX_PHY_STAT_PMA_PMD_REV_A,
939 EFX_PHY_STAT_PMA_PMD_REV_B,
940 EFX_PHY_STAT_PMA_PMD_REV_C,
941 EFX_PHY_STAT_PMA_PMD_REV_D,
942 EFX_PHY_STAT_PCS_LINK_UP,
943 EFX_PHY_STAT_PCS_RX_FAULT,
944 EFX_PHY_STAT_PCS_TX_FAULT,
945 EFX_PHY_STAT_PCS_BER,
946 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
947 EFX_PHY_STAT_PHY_XS_LINK_UP,
948 EFX_PHY_STAT_PHY_XS_RX_FAULT,
949 EFX_PHY_STAT_PHY_XS_TX_FAULT,
950 EFX_PHY_STAT_PHY_XS_ALIGN,
951 EFX_PHY_STAT_PHY_XS_SYNC_A,
952 EFX_PHY_STAT_PHY_XS_SYNC_B,
953 EFX_PHY_STAT_PHY_XS_SYNC_C,
954 EFX_PHY_STAT_PHY_XS_SYNC_D,
955 EFX_PHY_STAT_AN_LINK_UP,
956 EFX_PHY_STAT_AN_MASTER,
957 EFX_PHY_STAT_AN_LOCAL_RX_OK,
958 EFX_PHY_STAT_AN_REMOTE_RX_OK,
959 EFX_PHY_STAT_CL22EXT_LINK_UP,
964 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
965 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
966 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
967 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
968 EFX_PHY_STAT_AN_COMPLETE,
969 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
970 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
971 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
972 EFX_PHY_STAT_PCS_FW_VERSION_0,
973 EFX_PHY_STAT_PCS_FW_VERSION_1,
974 EFX_PHY_STAT_PCS_FW_VERSION_2,
975 EFX_PHY_STAT_PCS_FW_VERSION_3,
976 EFX_PHY_STAT_PCS_FW_BUILD_YY,
977 EFX_PHY_STAT_PCS_FW_BUILD_MM,
978 EFX_PHY_STAT_PCS_FW_BUILD_DD,
979 EFX_PHY_STAT_PCS_OP_MODE,
983 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
990 __in efx_phy_stat_t stat);
992 #endif /* EFSYS_OPT_NAMES */
994 #define EFX_PHY_STATS_SIZE 0x100
996 extern __checkReturn efx_rc_t
997 efx_phy_stats_update(
999 __in efsys_mem_t *esmp,
1000 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1002 #endif /* EFSYS_OPT_PHY_STATS */
1007 typedef enum efx_bist_type_e {
1008 EFX_BIST_TYPE_UNKNOWN,
1009 EFX_BIST_TYPE_PHY_NORMAL,
1010 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1011 EFX_BIST_TYPE_PHY_CABLE_LONG,
1012 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1013 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1014 EFX_BIST_TYPE_REG, /* Test the register memories */
1015 EFX_BIST_TYPE_NTYPES,
1018 typedef enum efx_bist_result_e {
1019 EFX_BIST_RESULT_UNKNOWN,
1020 EFX_BIST_RESULT_RUNNING,
1021 EFX_BIST_RESULT_PASSED,
1022 EFX_BIST_RESULT_FAILED,
1023 } efx_bist_result_t;
1025 typedef enum efx_phy_cable_status_e {
1026 EFX_PHY_CABLE_STATUS_OK,
1027 EFX_PHY_CABLE_STATUS_INVALID,
1028 EFX_PHY_CABLE_STATUS_OPEN,
1029 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1030 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1031 EFX_PHY_CABLE_STATUS_BUSY,
1032 } efx_phy_cable_status_t;
1034 typedef enum efx_bist_value_e {
1035 EFX_BIST_PHY_CABLE_LENGTH_A,
1036 EFX_BIST_PHY_CABLE_LENGTH_B,
1037 EFX_BIST_PHY_CABLE_LENGTH_C,
1038 EFX_BIST_PHY_CABLE_LENGTH_D,
1039 EFX_BIST_PHY_CABLE_STATUS_A,
1040 EFX_BIST_PHY_CABLE_STATUS_B,
1041 EFX_BIST_PHY_CABLE_STATUS_C,
1042 EFX_BIST_PHY_CABLE_STATUS_D,
1043 EFX_BIST_FAULT_CODE,
1045 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1051 EFX_BIST_MEM_EXPECT,
1052 EFX_BIST_MEM_ACTUAL,
1054 EFX_BIST_MEM_ECC_PARITY,
1055 EFX_BIST_MEM_ECC_FATAL,
1059 extern __checkReturn efx_rc_t
1060 efx_bist_enable_offline(
1061 __in efx_nic_t *enp);
1063 extern __checkReturn efx_rc_t
1065 __in efx_nic_t *enp,
1066 __in efx_bist_type_t type);
1068 extern __checkReturn efx_rc_t
1070 __in efx_nic_t *enp,
1071 __in efx_bist_type_t type,
1072 __out efx_bist_result_t *resultp,
1073 __out_opt uint32_t *value_maskp,
1074 __out_ecount_opt(count) unsigned long *valuesp,
1079 __in efx_nic_t *enp,
1080 __in efx_bist_type_t type);
1082 #endif /* EFSYS_OPT_BIST */
1084 #define EFX_FEATURE_IPV6 0x00000001
1085 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1086 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1087 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1088 #define EFX_FEATURE_MCDI 0x00000020
1089 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1090 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1091 #define EFX_FEATURE_TURBO 0x00000100
1092 #define EFX_FEATURE_MCDI_DMA 0x00000200
1093 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1094 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1095 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1096 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1097 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1099 typedef enum efx_tunnel_protocol_e {
1100 EFX_TUNNEL_PROTOCOL_NONE = 0,
1101 EFX_TUNNEL_PROTOCOL_VXLAN,
1102 EFX_TUNNEL_PROTOCOL_GENEVE,
1103 EFX_TUNNEL_PROTOCOL_NVGRE,
1105 } efx_tunnel_protocol_t;
1107 typedef struct efx_nic_cfg_s {
1108 uint32_t enc_board_type;
1109 uint32_t enc_phy_type;
1111 char enc_phy_name[21];
1113 char enc_phy_revision[21];
1114 efx_mon_type_t enc_mon_type;
1115 #if EFSYS_OPT_MON_STATS
1116 uint32_t enc_mon_stat_dma_buf_size;
1117 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1119 unsigned int enc_features;
1120 uint8_t enc_mac_addr[6];
1121 uint8_t enc_port; /* PHY port number */
1122 uint32_t enc_intr_vec_base;
1123 uint32_t enc_intr_limit;
1124 uint32_t enc_evq_limit;
1125 uint32_t enc_txq_limit;
1126 uint32_t enc_rxq_limit;
1127 uint32_t enc_txq_max_ndescs;
1128 uint32_t enc_buftbl_limit;
1129 uint32_t enc_piobuf_limit;
1130 uint32_t enc_piobuf_size;
1131 uint32_t enc_piobuf_min_alloc_size;
1132 uint32_t enc_evq_timer_quantum_ns;
1133 uint32_t enc_evq_timer_max_us;
1134 uint32_t enc_clk_mult;
1135 uint32_t enc_rx_prefix_size;
1136 uint32_t enc_rx_buf_align_start;
1137 uint32_t enc_rx_buf_align_end;
1138 uint32_t enc_rx_scale_max_exclusive_contexts;
1139 #if EFSYS_OPT_LOOPBACK
1140 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1141 #endif /* EFSYS_OPT_LOOPBACK */
1142 #if EFSYS_OPT_PHY_FLAGS
1143 uint32_t enc_phy_flags_mask;
1144 #endif /* EFSYS_OPT_PHY_FLAGS */
1145 #if EFSYS_OPT_PHY_LED_CONTROL
1146 uint32_t enc_led_mask;
1147 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1148 #if EFSYS_OPT_PHY_STATS
1149 uint64_t enc_phy_stat_mask;
1150 #endif /* EFSYS_OPT_PHY_STATS */
1152 uint8_t enc_mcdi_mdio_channel;
1153 #if EFSYS_OPT_PHY_STATS
1154 uint32_t enc_mcdi_phy_stat_mask;
1155 #endif /* EFSYS_OPT_PHY_STATS */
1156 #if EFSYS_OPT_MON_STATS
1157 uint32_t *enc_mcdi_sensor_maskp;
1158 uint32_t enc_mcdi_sensor_mask_size;
1159 #endif /* EFSYS_OPT_MON_STATS */
1160 #endif /* EFSYS_OPT_MCDI */
1162 uint32_t enc_bist_mask;
1163 #endif /* EFSYS_OPT_BIST */
1164 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1167 uint32_t enc_privilege_mask;
1168 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1169 boolean_t enc_bug26807_workaround;
1170 boolean_t enc_bug35388_workaround;
1171 boolean_t enc_bug41750_workaround;
1172 boolean_t enc_bug61265_workaround;
1173 boolean_t enc_rx_batching_enabled;
1174 /* Maximum number of descriptors completed in an rx event. */
1175 uint32_t enc_rx_batch_max;
1176 /* Number of rx descriptors the hardware requires for a push. */
1177 uint32_t enc_rx_push_align;
1178 /* Maximum amount of data in DMA descriptor */
1179 uint32_t enc_tx_dma_desc_size_max;
1181 * Boundary which DMA descriptor data must not cross or 0 if no
1184 uint32_t enc_tx_dma_desc_boundary;
1186 * Maximum number of bytes into the packet the TCP header can start for
1187 * the hardware to apply TSO packet edits.
1189 uint32_t enc_tx_tso_tcp_header_offset_limit;
1190 boolean_t enc_fw_assisted_tso_enabled;
1191 boolean_t enc_fw_assisted_tso_v2_enabled;
1192 /* Number of TSO contexts on the NIC (FATSOv2) */
1193 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1194 boolean_t enc_hw_tx_insert_vlan_enabled;
1195 /* Number of PFs on the NIC */
1196 uint32_t enc_hw_pf_count;
1197 /* Datapath firmware vadapter/vport/vswitch support */
1198 boolean_t enc_datapath_cap_evb;
1199 boolean_t enc_rx_disable_scatter_supported;
1200 boolean_t enc_allow_set_mac_with_installed_filters;
1201 boolean_t enc_enhanced_set_mac_supported;
1202 boolean_t enc_init_evq_v2_supported;
1203 boolean_t enc_rx_packed_stream_supported;
1204 boolean_t enc_rx_var_packed_stream_supported;
1205 boolean_t enc_pm_and_rxdp_counters;
1206 boolean_t enc_mac_stats_40g_tx_size_bins;
1207 uint32_t enc_tunnel_encapsulations_supported;
1208 /* External port identifier */
1209 uint8_t enc_external_port;
1210 uint32_t enc_mcdi_max_payload_length;
1211 /* VPD may be per-PF or global */
1212 boolean_t enc_vpd_is_global;
1213 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1214 uint32_t enc_required_pcie_bandwidth_mbps;
1215 uint32_t enc_max_pcie_link_gen;
1216 /* Firmware verifies integrity of NVRAM updates */
1217 uint32_t enc_nvram_update_verify_result_supported;
1220 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1221 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1223 #define EFX_PCI_FUNCTION(_encp) \
1224 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1226 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1228 extern const efx_nic_cfg_t *
1230 __in efx_nic_t *enp);
1232 typedef struct efx_nic_fw_info_s {
1233 /* Basic FW version information */
1234 uint16_t enfi_mc_fw_version[4];
1236 * If datapath capabilities can be detected,
1237 * additional FW information is to be shown
1239 boolean_t enfi_dpcpu_fw_ids_valid;
1240 /* Rx and Tx datapath CPU FW IDs */
1241 uint16_t enfi_rx_dpcpu_fw_id;
1242 uint16_t enfi_tx_dpcpu_fw_id;
1243 } efx_nic_fw_info_t;
1245 extern __checkReturn efx_rc_t
1246 efx_nic_get_fw_version(
1247 __in efx_nic_t *enp,
1248 __out efx_nic_fw_info_t *enfip);
1250 /* Driver resource limits (minimum required/maximum usable). */
1251 typedef struct efx_drv_limits_s {
1252 uint32_t edl_min_evq_count;
1253 uint32_t edl_max_evq_count;
1255 uint32_t edl_min_rxq_count;
1256 uint32_t edl_max_rxq_count;
1258 uint32_t edl_min_txq_count;
1259 uint32_t edl_max_txq_count;
1261 /* PIO blocks (sub-allocated from piobuf) */
1262 uint32_t edl_min_pio_alloc_size;
1263 uint32_t edl_max_pio_alloc_count;
1266 extern __checkReturn efx_rc_t
1267 efx_nic_set_drv_limits(
1268 __inout efx_nic_t *enp,
1269 __in efx_drv_limits_t *edlp);
1271 typedef enum efx_nic_region_e {
1272 EFX_REGION_VI, /* Memory BAR UC mapping */
1273 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1276 extern __checkReturn efx_rc_t
1277 efx_nic_get_bar_region(
1278 __in efx_nic_t *enp,
1279 __in efx_nic_region_t region,
1280 __out uint32_t *offsetp,
1281 __out size_t *sizep);
1283 extern __checkReturn efx_rc_t
1284 efx_nic_get_vi_pool(
1285 __in efx_nic_t *enp,
1286 __out uint32_t *evq_countp,
1287 __out uint32_t *rxq_countp,
1288 __out uint32_t *txq_countp);
1293 typedef enum efx_vpd_tag_e {
1300 typedef uint16_t efx_vpd_keyword_t;
1302 typedef struct efx_vpd_value_s {
1303 efx_vpd_tag_t evv_tag;
1304 efx_vpd_keyword_t evv_keyword;
1306 uint8_t evv_value[0x100];
1310 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1312 extern __checkReturn efx_rc_t
1314 __in efx_nic_t *enp);
1316 extern __checkReturn efx_rc_t
1318 __in efx_nic_t *enp,
1319 __out size_t *sizep);
1321 extern __checkReturn efx_rc_t
1323 __in efx_nic_t *enp,
1324 __out_bcount(size) caddr_t data,
1327 extern __checkReturn efx_rc_t
1329 __in efx_nic_t *enp,
1330 __in_bcount(size) caddr_t data,
1333 extern __checkReturn efx_rc_t
1335 __in efx_nic_t *enp,
1336 __in_bcount(size) caddr_t data,
1339 extern __checkReturn efx_rc_t
1341 __in efx_nic_t *enp,
1342 __in_bcount(size) caddr_t data,
1344 __inout efx_vpd_value_t *evvp);
1346 extern __checkReturn efx_rc_t
1348 __in efx_nic_t *enp,
1349 __inout_bcount(size) caddr_t data,
1351 __in efx_vpd_value_t *evvp);
1353 extern __checkReturn efx_rc_t
1355 __in efx_nic_t *enp,
1356 __inout_bcount(size) caddr_t data,
1358 __out efx_vpd_value_t *evvp,
1359 __inout unsigned int *contp);
1361 extern __checkReturn efx_rc_t
1363 __in efx_nic_t *enp,
1364 __in_bcount(size) caddr_t data,
1369 __in efx_nic_t *enp);
1371 #endif /* EFSYS_OPT_VPD */
1377 typedef enum efx_nvram_type_e {
1378 EFX_NVRAM_INVALID = 0,
1380 EFX_NVRAM_BOOTROM_CFG,
1381 EFX_NVRAM_MC_FIRMWARE,
1382 EFX_NVRAM_MC_GOLDEN,
1388 EFX_NVRAM_FPGA_BACKUP,
1389 EFX_NVRAM_DYNAMIC_CFG,
1392 EFX_NVRAM_MUM_FIRMWARE,
1396 extern __checkReturn efx_rc_t
1398 __in efx_nic_t *enp);
1402 extern __checkReturn efx_rc_t
1404 __in efx_nic_t *enp);
1406 #endif /* EFSYS_OPT_DIAG */
1408 extern __checkReturn efx_rc_t
1410 __in efx_nic_t *enp,
1411 __in efx_nvram_type_t type,
1412 __out size_t *sizep);
1414 extern __checkReturn efx_rc_t
1416 __in efx_nic_t *enp,
1417 __in efx_nvram_type_t type,
1418 __out_opt size_t *pref_chunkp);
1420 extern __checkReturn efx_rc_t
1421 efx_nvram_rw_finish(
1422 __in efx_nic_t *enp,
1423 __in efx_nvram_type_t type,
1424 __out_opt uint32_t *verify_resultp);
1426 extern __checkReturn efx_rc_t
1427 efx_nvram_get_version(
1428 __in efx_nic_t *enp,
1429 __in efx_nvram_type_t type,
1430 __out uint32_t *subtypep,
1431 __out_ecount(4) uint16_t version[4]);
1433 extern __checkReturn efx_rc_t
1434 efx_nvram_read_chunk(
1435 __in efx_nic_t *enp,
1436 __in efx_nvram_type_t type,
1437 __in unsigned int offset,
1438 __out_bcount(size) caddr_t data,
1441 extern __checkReturn efx_rc_t
1442 efx_nvram_read_backup(
1443 __in efx_nic_t *enp,
1444 __in efx_nvram_type_t type,
1445 __in unsigned int offset,
1446 __out_bcount(size) caddr_t data,
1449 extern __checkReturn efx_rc_t
1450 efx_nvram_set_version(
1451 __in efx_nic_t *enp,
1452 __in efx_nvram_type_t type,
1453 __in_ecount(4) uint16_t version[4]);
1455 extern __checkReturn efx_rc_t
1457 __in efx_nic_t *enp,
1458 __in efx_nvram_type_t type,
1459 __in_bcount(partn_size) caddr_t partn_data,
1460 __in size_t partn_size);
1462 extern __checkReturn efx_rc_t
1464 __in efx_nic_t *enp,
1465 __in efx_nvram_type_t type);
1467 extern __checkReturn efx_rc_t
1468 efx_nvram_write_chunk(
1469 __in efx_nic_t *enp,
1470 __in efx_nvram_type_t type,
1471 __in unsigned int offset,
1472 __in_bcount(size) caddr_t data,
1477 __in efx_nic_t *enp);
1479 #endif /* EFSYS_OPT_NVRAM */
1481 #if EFSYS_OPT_BOOTCFG
1483 /* Report size and offset of bootcfg sector in NVRAM partition. */
1484 extern __checkReturn efx_rc_t
1485 efx_bootcfg_sector_info(
1486 __in efx_nic_t *enp,
1488 __out_opt uint32_t *sector_countp,
1489 __out size_t *offsetp,
1490 __out size_t *max_sizep);
1493 * Copy bootcfg sector data to a target buffer which may differ in size.
1494 * Optionally corrects format errors in source buffer.
1497 efx_bootcfg_copy_sector(
1498 __in efx_nic_t *enp,
1499 __inout_bcount(sector_length)
1501 __in size_t sector_length,
1502 __out_bcount(data_size) uint8_t *data,
1503 __in size_t data_size,
1504 __in boolean_t handle_format_errors);
1508 __in efx_nic_t *enp,
1509 __out_bcount(size) uint8_t *data,
1514 __in efx_nic_t *enp,
1515 __in_bcount(size) uint8_t *data,
1518 #endif /* EFSYS_OPT_BOOTCFG */
1522 typedef enum efx_pattern_type_t {
1523 EFX_PATTERN_BYTE_INCREMENT = 0,
1524 EFX_PATTERN_ALL_THE_SAME,
1525 EFX_PATTERN_BIT_ALTERNATE,
1526 EFX_PATTERN_BYTE_ALTERNATE,
1527 EFX_PATTERN_BYTE_CHANGING,
1528 EFX_PATTERN_BIT_SWEEP,
1530 } efx_pattern_type_t;
1533 (*efx_sram_pattern_fn_t)(
1535 __in boolean_t negate,
1536 __out efx_qword_t *eqp);
1538 extern __checkReturn efx_rc_t
1540 __in efx_nic_t *enp,
1541 __in efx_pattern_type_t type);
1543 #endif /* EFSYS_OPT_DIAG */
1545 extern __checkReturn efx_rc_t
1546 efx_sram_buf_tbl_set(
1547 __in efx_nic_t *enp,
1549 __in efsys_mem_t *esmp,
1553 efx_sram_buf_tbl_clear(
1554 __in efx_nic_t *enp,
1558 #define EFX_BUF_TBL_SIZE 0x20000
1560 #define EFX_BUF_SIZE 4096
1564 typedef struct efx_evq_s efx_evq_t;
1566 #if EFSYS_OPT_QSTATS
1568 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1569 typedef enum efx_ev_qstat_e {
1575 EV_RX_PAUSE_FRM_ERR,
1576 EV_RX_BUF_OWNER_ID_ERR,
1577 EV_RX_IPV4_HDR_CHKSUM_ERR,
1578 EV_RX_TCP_UDP_CHKSUM_ERR,
1582 EV_RX_MCAST_HASH_MATCH,
1599 EV_DRIVER_SRM_UPD_DONE,
1600 EV_DRIVER_TX_DESCQ_FLS_DONE,
1601 EV_DRIVER_RX_DESCQ_FLS_DONE,
1602 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1603 EV_DRIVER_RX_DSC_ERROR,
1604 EV_DRIVER_TX_DSC_ERROR,
1610 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1612 #endif /* EFSYS_OPT_QSTATS */
1614 extern __checkReturn efx_rc_t
1616 __in efx_nic_t *enp);
1620 __in efx_nic_t *enp);
1622 #define EFX_EVQ_MAXNEVS 32768
1623 #define EFX_EVQ_MINNEVS 512
1625 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1626 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1628 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1629 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1630 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1631 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1633 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1634 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1635 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1637 extern __checkReturn efx_rc_t
1639 __in efx_nic_t *enp,
1640 __in unsigned int index,
1641 __in efsys_mem_t *esmp,
1645 __in uint32_t flags,
1646 __deref_out efx_evq_t **eepp);
1650 __in efx_evq_t *eep,
1651 __in uint16_t data);
1653 typedef __checkReturn boolean_t
1654 (*efx_initialized_ev_t)(
1655 __in_opt void *arg);
1657 #define EFX_PKT_UNICAST 0x0004
1658 #define EFX_PKT_START 0x0008
1660 #define EFX_PKT_VLAN_TAGGED 0x0010
1661 #define EFX_CKSUM_TCPUDP 0x0020
1662 #define EFX_CKSUM_IPV4 0x0040
1663 #define EFX_PKT_CONT 0x0080
1665 #define EFX_CHECK_VLAN 0x0100
1666 #define EFX_PKT_TCP 0x0200
1667 #define EFX_PKT_UDP 0x0400
1668 #define EFX_PKT_IPV4 0x0800
1670 #define EFX_PKT_IPV6 0x1000
1671 #define EFX_PKT_PREFIX_LEN 0x2000
1672 #define EFX_ADDR_MISMATCH 0x4000
1673 #define EFX_DISCARD 0x8000
1676 * The following flags are used only for packed stream
1677 * mode. The values for the flags are reused to fit into 16 bit,
1678 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1679 * packed stream mode
1681 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1682 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1685 #define EFX_EV_RX_NLABELS 32
1686 #define EFX_EV_TX_NLABELS 32
1688 typedef __checkReturn boolean_t
1691 __in uint32_t label,
1694 __in uint16_t flags);
1696 #if EFSYS_OPT_RX_PACKED_STREAM
1699 * Packed stream mode is documented in SF-112241-TC.
1700 * The general idea is that, instead of putting each incoming
1701 * packet into a separate buffer which is specified in a RX
1702 * descriptor, a large buffer is provided to the hardware and
1703 * packets are put there in a continuous stream.
1704 * The main advantage of such an approach is that RX queue refilling
1705 * happens much less frequently.
1708 typedef __checkReturn boolean_t
1711 __in uint32_t label,
1713 __in uint32_t pkt_count,
1714 __in uint16_t flags);
1718 typedef __checkReturn boolean_t
1721 __in uint32_t label,
1724 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1725 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1726 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1727 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1728 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1729 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1730 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1731 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1732 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1734 typedef __checkReturn boolean_t
1735 (*efx_exception_ev_t)(
1737 __in uint32_t label,
1738 __in uint32_t data);
1740 typedef __checkReturn boolean_t
1741 (*efx_rxq_flush_done_ev_t)(
1743 __in uint32_t rxq_index);
1745 typedef __checkReturn boolean_t
1746 (*efx_rxq_flush_failed_ev_t)(
1748 __in uint32_t rxq_index);
1750 typedef __checkReturn boolean_t
1751 (*efx_txq_flush_done_ev_t)(
1753 __in uint32_t txq_index);
1755 typedef __checkReturn boolean_t
1756 (*efx_software_ev_t)(
1758 __in uint16_t magic);
1760 typedef __checkReturn boolean_t
1763 __in uint32_t code);
1765 #define EFX_SRAM_CLEAR 0
1766 #define EFX_SRAM_UPDATE 1
1767 #define EFX_SRAM_ILLEGAL_CLEAR 2
1769 typedef __checkReturn boolean_t
1770 (*efx_wake_up_ev_t)(
1772 __in uint32_t label);
1774 typedef __checkReturn boolean_t
1777 __in uint32_t label);
1779 typedef __checkReturn boolean_t
1780 (*efx_link_change_ev_t)(
1782 __in efx_link_mode_t link_mode);
1784 #if EFSYS_OPT_MON_STATS
1786 typedef __checkReturn boolean_t
1787 (*efx_monitor_ev_t)(
1789 __in efx_mon_stat_t id,
1790 __in efx_mon_stat_value_t value);
1792 #endif /* EFSYS_OPT_MON_STATS */
1794 #if EFSYS_OPT_MAC_STATS
1796 typedef __checkReturn boolean_t
1797 (*efx_mac_stats_ev_t)(
1799 __in uint32_t generation);
1801 #endif /* EFSYS_OPT_MAC_STATS */
1803 typedef struct efx_ev_callbacks_s {
1804 efx_initialized_ev_t eec_initialized;
1806 #if EFSYS_OPT_RX_PACKED_STREAM
1807 efx_rx_ps_ev_t eec_rx_ps;
1810 efx_exception_ev_t eec_exception;
1811 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1812 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1813 efx_txq_flush_done_ev_t eec_txq_flush_done;
1814 efx_software_ev_t eec_software;
1815 efx_sram_ev_t eec_sram;
1816 efx_wake_up_ev_t eec_wake_up;
1817 efx_timer_ev_t eec_timer;
1818 efx_link_change_ev_t eec_link_change;
1819 #if EFSYS_OPT_MON_STATS
1820 efx_monitor_ev_t eec_monitor;
1821 #endif /* EFSYS_OPT_MON_STATS */
1822 #if EFSYS_OPT_MAC_STATS
1823 efx_mac_stats_ev_t eec_mac_stats;
1824 #endif /* EFSYS_OPT_MAC_STATS */
1825 } efx_ev_callbacks_t;
1827 extern __checkReturn boolean_t
1829 __in efx_evq_t *eep,
1830 __in unsigned int count);
1832 #if EFSYS_OPT_EV_PREFETCH
1836 __in efx_evq_t *eep,
1837 __in unsigned int count);
1839 #endif /* EFSYS_OPT_EV_PREFETCH */
1843 __in efx_evq_t *eep,
1844 __inout unsigned int *countp,
1845 __in const efx_ev_callbacks_t *eecp,
1846 __in_opt void *arg);
1848 extern __checkReturn efx_rc_t
1849 efx_ev_usecs_to_ticks(
1850 __in efx_nic_t *enp,
1851 __in unsigned int usecs,
1852 __out unsigned int *ticksp);
1854 extern __checkReturn efx_rc_t
1856 __in efx_evq_t *eep,
1857 __in unsigned int us);
1859 extern __checkReturn efx_rc_t
1861 __in efx_evq_t *eep,
1862 __in unsigned int count);
1864 #if EFSYS_OPT_QSTATS
1870 __in efx_nic_t *enp,
1871 __in unsigned int id);
1873 #endif /* EFSYS_OPT_NAMES */
1876 efx_ev_qstats_update(
1877 __in efx_evq_t *eep,
1878 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1880 #endif /* EFSYS_OPT_QSTATS */
1884 __in efx_evq_t *eep);
1888 extern __checkReturn efx_rc_t
1890 __inout efx_nic_t *enp);
1894 __in efx_nic_t *enp);
1896 #if EFSYS_OPT_RX_SCATTER
1897 __checkReturn efx_rc_t
1898 efx_rx_scatter_enable(
1899 __in efx_nic_t *enp,
1900 __in unsigned int buf_size);
1901 #endif /* EFSYS_OPT_RX_SCATTER */
1903 /* Handle to represent use of the default RSS context. */
1904 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1906 #if EFSYS_OPT_RX_SCALE
1908 typedef enum efx_rx_hash_alg_e {
1909 EFX_RX_HASHALG_LFSR = 0,
1910 EFX_RX_HASHALG_TOEPLITZ
1911 } efx_rx_hash_alg_t;
1913 #define EFX_RX_HASH_IPV4 (1U << 0)
1914 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1915 #define EFX_RX_HASH_IPV6 (1U << 2)
1916 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1918 typedef unsigned int efx_rx_hash_type_t;
1920 typedef enum efx_rx_hash_support_e {
1921 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1922 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1923 } efx_rx_hash_support_t;
1925 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1926 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1927 #define EFX_MAXRSS 64 /* RX indirection entry range */
1928 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1930 typedef enum efx_rx_scale_context_type_e {
1931 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1932 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1933 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1934 } efx_rx_scale_context_type_t;
1936 extern __checkReturn efx_rc_t
1937 efx_rx_hash_default_support_get(
1938 __in efx_nic_t *enp,
1939 __out efx_rx_hash_support_t *supportp);
1942 extern __checkReturn efx_rc_t
1943 efx_rx_scale_default_support_get(
1944 __in efx_nic_t *enp,
1945 __out efx_rx_scale_context_type_t *typep);
1947 extern __checkReturn efx_rc_t
1948 efx_rx_scale_context_alloc(
1949 __in efx_nic_t *enp,
1950 __in efx_rx_scale_context_type_t type,
1951 __in uint32_t num_queues,
1952 __out uint32_t *rss_contextp);
1954 extern __checkReturn efx_rc_t
1955 efx_rx_scale_context_free(
1956 __in efx_nic_t *enp,
1957 __in uint32_t rss_context);
1959 extern __checkReturn efx_rc_t
1960 efx_rx_scale_mode_set(
1961 __in efx_nic_t *enp,
1962 __in uint32_t rss_context,
1963 __in efx_rx_hash_alg_t alg,
1964 __in efx_rx_hash_type_t type,
1965 __in boolean_t insert);
1967 extern __checkReturn efx_rc_t
1968 efx_rx_scale_tbl_set(
1969 __in efx_nic_t *enp,
1970 __in uint32_t rss_context,
1971 __in_ecount(n) unsigned int *table,
1974 extern __checkReturn efx_rc_t
1975 efx_rx_scale_key_set(
1976 __in efx_nic_t *enp,
1977 __in uint32_t rss_context,
1978 __in_ecount(n) uint8_t *key,
1981 extern __checkReturn uint32_t
1982 efx_pseudo_hdr_hash_get(
1983 __in efx_rxq_t *erp,
1984 __in efx_rx_hash_alg_t func,
1985 __in uint8_t *buffer);
1987 #endif /* EFSYS_OPT_RX_SCALE */
1989 extern __checkReturn efx_rc_t
1990 efx_pseudo_hdr_pkt_length_get(
1991 __in efx_rxq_t *erp,
1992 __in uint8_t *buffer,
1993 __out uint16_t *pkt_lengthp);
1995 #define EFX_RXQ_MAXNDESCS 4096
1996 #define EFX_RXQ_MINNDESCS 512
1998 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1999 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2000 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2001 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2003 typedef enum efx_rxq_type_e {
2004 EFX_RXQ_TYPE_DEFAULT,
2005 EFX_RXQ_TYPE_PACKED_STREAM,
2010 * Dummy flag to be used instead of 0 to make it clear that the argument
2011 * is receive queue flags.
2013 #define EFX_RXQ_FLAG_NONE 0x0
2014 #define EFX_RXQ_FLAG_SCATTER 0x1
2016 * If tunnels are supported and Rx event can provide information about
2017 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2018 * full-feature firmware variant running), outer classes are requested by
2019 * default. However, if the driver supports tunnels, the flag allows to
2020 * request inner classes which are required to be able to interpret inner
2021 * Rx checksum offload results.
2023 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2025 extern __checkReturn efx_rc_t
2027 __in efx_nic_t *enp,
2028 __in unsigned int index,
2029 __in unsigned int label,
2030 __in efx_rxq_type_t type,
2031 __in efsys_mem_t *esmp,
2034 __in unsigned int flags,
2035 __in efx_evq_t *eep,
2036 __deref_out efx_rxq_t **erpp);
2038 #if EFSYS_OPT_RX_PACKED_STREAM
2040 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2041 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2042 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2043 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2044 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2046 extern __checkReturn efx_rc_t
2047 efx_rx_qcreate_packed_stream(
2048 __in efx_nic_t *enp,
2049 __in unsigned int index,
2050 __in unsigned int label,
2051 __in uint32_t ps_buf_size,
2052 __in efsys_mem_t *esmp,
2054 __in efx_evq_t *eep,
2055 __deref_out efx_rxq_t **erpp);
2059 typedef struct efx_buffer_s {
2060 efsys_dma_addr_t eb_addr;
2065 typedef struct efx_desc_s {
2071 __in efx_rxq_t *erp,
2072 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2074 __in unsigned int ndescs,
2075 __in unsigned int completed,
2076 __in unsigned int added);
2080 __in efx_rxq_t *erp,
2081 __in unsigned int added,
2082 __inout unsigned int *pushedp);
2084 #if EFSYS_OPT_RX_PACKED_STREAM
2087 efx_rx_qpush_ps_credits(
2088 __in efx_rxq_t *erp);
2090 extern __checkReturn uint8_t *
2091 efx_rx_qps_packet_info(
2092 __in efx_rxq_t *erp,
2093 __in uint8_t *buffer,
2094 __in uint32_t buffer_length,
2095 __in uint32_t current_offset,
2096 __out uint16_t *lengthp,
2097 __out uint32_t *next_offsetp,
2098 __out uint32_t *timestamp);
2101 extern __checkReturn efx_rc_t
2103 __in efx_rxq_t *erp);
2107 __in efx_rxq_t *erp);
2111 __in efx_rxq_t *erp);
2115 typedef struct efx_txq_s efx_txq_t;
2117 #if EFSYS_OPT_QSTATS
2119 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2120 typedef enum efx_tx_qstat_e {
2126 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2128 #endif /* EFSYS_OPT_QSTATS */
2130 extern __checkReturn efx_rc_t
2132 __in efx_nic_t *enp);
2136 __in efx_nic_t *enp);
2138 #define EFX_TXQ_MINNDESCS 512
2140 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2141 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2142 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2144 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2146 #define EFX_TXQ_CKSUM_IPV4 0x0001
2147 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2148 #define EFX_TXQ_FATSOV2 0x0004
2149 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2150 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2152 extern __checkReturn efx_rc_t
2154 __in efx_nic_t *enp,
2155 __in unsigned int index,
2156 __in unsigned int label,
2157 __in efsys_mem_t *esmp,
2160 __in uint16_t flags,
2161 __in efx_evq_t *eep,
2162 __deref_out efx_txq_t **etpp,
2163 __out unsigned int *addedp);
2165 extern __checkReturn efx_rc_t
2167 __in efx_txq_t *etp,
2168 __in_ecount(ndescs) efx_buffer_t *eb,
2169 __in unsigned int ndescs,
2170 __in unsigned int completed,
2171 __inout unsigned int *addedp);
2173 extern __checkReturn efx_rc_t
2175 __in efx_txq_t *etp,
2176 __in unsigned int ns);
2180 __in efx_txq_t *etp,
2181 __in unsigned int added,
2182 __in unsigned int pushed);
2184 extern __checkReturn efx_rc_t
2186 __in efx_txq_t *etp);
2190 __in efx_txq_t *etp);
2192 extern __checkReturn efx_rc_t
2194 __in efx_txq_t *etp);
2197 efx_tx_qpio_disable(
2198 __in efx_txq_t *etp);
2200 extern __checkReturn efx_rc_t
2202 __in efx_txq_t *etp,
2203 __in_ecount(buf_length) uint8_t *buffer,
2204 __in size_t buf_length,
2205 __in size_t pio_buf_offset);
2207 extern __checkReturn efx_rc_t
2209 __in efx_txq_t *etp,
2210 __in size_t pkt_length,
2211 __in unsigned int completed,
2212 __inout unsigned int *addedp);
2214 extern __checkReturn efx_rc_t
2216 __in efx_txq_t *etp,
2217 __in_ecount(n) efx_desc_t *ed,
2218 __in unsigned int n,
2219 __in unsigned int completed,
2220 __inout unsigned int *addedp);
2223 efx_tx_qdesc_dma_create(
2224 __in efx_txq_t *etp,
2225 __in efsys_dma_addr_t addr,
2228 __out efx_desc_t *edp);
2231 efx_tx_qdesc_tso_create(
2232 __in efx_txq_t *etp,
2233 __in uint16_t ipv4_id,
2234 __in uint32_t tcp_seq,
2235 __in uint8_t tcp_flags,
2236 __out efx_desc_t *edp);
2238 /* Number of FATSOv2 option descriptors */
2239 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2241 /* Maximum number of DMA segments per TSO packet (not superframe) */
2242 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2245 efx_tx_qdesc_tso2_create(
2246 __in efx_txq_t *etp,
2247 __in uint16_t ipv4_id,
2248 __in uint32_t tcp_seq,
2249 __in uint16_t tcp_mss,
2250 __out_ecount(count) efx_desc_t *edp,
2254 efx_tx_qdesc_vlantci_create(
2255 __in efx_txq_t *etp,
2257 __out efx_desc_t *edp);
2259 #if EFSYS_OPT_QSTATS
2265 __in efx_nic_t *etp,
2266 __in unsigned int id);
2268 #endif /* EFSYS_OPT_NAMES */
2271 efx_tx_qstats_update(
2272 __in efx_txq_t *etp,
2273 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2275 #endif /* EFSYS_OPT_QSTATS */
2279 __in efx_txq_t *etp);
2284 #if EFSYS_OPT_FILTER
2286 #define EFX_ETHER_TYPE_IPV4 0x0800
2287 #define EFX_ETHER_TYPE_IPV6 0x86DD
2289 #define EFX_IPPROTO_TCP 6
2290 #define EFX_IPPROTO_UDP 17
2291 #define EFX_IPPROTO_GRE 47
2293 /* Use RSS to spread across multiple queues */
2294 #define EFX_FILTER_FLAG_RX_RSS 0x01
2295 /* Enable RX scatter */
2296 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2298 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2299 * May only be set by the filter implementation for each type.
2300 * A removal request will restore the automatic filter in its place.
2302 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2303 /* Filter is for RX */
2304 #define EFX_FILTER_FLAG_RX 0x08
2305 /* Filter is for TX */
2306 #define EFX_FILTER_FLAG_TX 0x10
2308 typedef uint8_t efx_filter_flags_t;
2311 * Flags which specify the fields to match on. The values are the same as in the
2312 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2315 /* Match by remote IP host address */
2316 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2317 /* Match by local IP host address */
2318 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2319 /* Match by remote MAC address */
2320 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2321 /* Match by remote TCP/UDP port */
2322 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2323 /* Match by remote TCP/UDP port */
2324 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2325 /* Match by local TCP/UDP port */
2326 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2327 /* Match by Ether-type */
2328 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2329 /* Match by inner VLAN ID */
2330 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2331 /* Match by outer VLAN ID */
2332 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2333 /* Match by IP transport protocol */
2334 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2335 /* For encapsulated packets, match all multicast inner frames */
2336 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2337 /* For encapsulated packets, match all unicast inner frames */
2338 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2339 /* Match otherwise-unmatched multicast and broadcast packets */
2340 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2341 /* Match otherwise-unmatched unicast packets */
2342 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2344 typedef uint32_t efx_filter_match_flags_t;
2346 typedef enum efx_filter_priority_s {
2347 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2348 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2349 * address list or hardware
2350 * requirements. This may only be used
2351 * by the filter implementation for
2353 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2354 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2355 * client (e.g. SR-IOV, HyperV VMQ etc.)
2357 } efx_filter_priority_t;
2360 * FIXME: All these fields are assumed to be in little-endian byte order.
2361 * It may be better for some to be big-endian. See bug42804.
2364 typedef struct efx_filter_spec_s {
2365 efx_filter_match_flags_t efs_match_flags;
2366 uint8_t efs_priority;
2367 efx_filter_flags_t efs_flags;
2368 uint16_t efs_dmaq_id;
2369 uint32_t efs_rss_context;
2370 uint16_t efs_outer_vid;
2371 uint16_t efs_inner_vid;
2372 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2373 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2374 uint16_t efs_ether_type;
2375 uint8_t efs_ip_proto;
2376 efx_tunnel_protocol_t efs_encap_type;
2377 uint16_t efs_loc_port;
2378 uint16_t efs_rem_port;
2379 efx_oword_t efs_rem_host;
2380 efx_oword_t efs_loc_host;
2381 } efx_filter_spec_t;
2384 /* Default values for use in filter specifications */
2385 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2386 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2388 extern __checkReturn efx_rc_t
2390 __in efx_nic_t *enp);
2394 __in efx_nic_t *enp);
2396 extern __checkReturn efx_rc_t
2398 __in efx_nic_t *enp,
2399 __inout efx_filter_spec_t *spec);
2401 extern __checkReturn efx_rc_t
2403 __in efx_nic_t *enp,
2404 __inout efx_filter_spec_t *spec);
2406 extern __checkReturn efx_rc_t
2408 __in efx_nic_t *enp);
2410 extern __checkReturn efx_rc_t
2411 efx_filter_supported_filters(
2412 __in efx_nic_t *enp,
2413 __out_ecount(buffer_length) uint32_t *buffer,
2414 __in size_t buffer_length,
2415 __out size_t *list_lengthp);
2418 efx_filter_spec_init_rx(
2419 __out efx_filter_spec_t *spec,
2420 __in efx_filter_priority_t priority,
2421 __in efx_filter_flags_t flags,
2422 __in efx_rxq_t *erp);
2425 efx_filter_spec_init_tx(
2426 __out efx_filter_spec_t *spec,
2427 __in efx_txq_t *etp);
2429 extern __checkReturn efx_rc_t
2430 efx_filter_spec_set_ipv4_local(
2431 __inout efx_filter_spec_t *spec,
2434 __in uint16_t port);
2436 extern __checkReturn efx_rc_t
2437 efx_filter_spec_set_ipv4_full(
2438 __inout efx_filter_spec_t *spec,
2440 __in uint32_t lhost,
2441 __in uint16_t lport,
2442 __in uint32_t rhost,
2443 __in uint16_t rport);
2445 extern __checkReturn efx_rc_t
2446 efx_filter_spec_set_eth_local(
2447 __inout efx_filter_spec_t *spec,
2449 __in const uint8_t *addr);
2452 efx_filter_spec_set_ether_type(
2453 __inout efx_filter_spec_t *spec,
2454 __in uint16_t ether_type);
2456 extern __checkReturn efx_rc_t
2457 efx_filter_spec_set_uc_def(
2458 __inout efx_filter_spec_t *spec);
2460 extern __checkReturn efx_rc_t
2461 efx_filter_spec_set_mc_def(
2462 __inout efx_filter_spec_t *spec);
2464 typedef enum efx_filter_inner_frame_match_e {
2465 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2466 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2467 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2468 } efx_filter_inner_frame_match_t;
2470 extern __checkReturn efx_rc_t
2471 efx_filter_spec_set_encap_type(
2472 __inout efx_filter_spec_t *spec,
2473 __in efx_tunnel_protocol_t encap_type,
2474 __in efx_filter_inner_frame_match_t inner_frame_match);
2476 #if EFSYS_OPT_RX_SCALE
2477 extern __checkReturn efx_rc_t
2478 efx_filter_spec_set_rss_context(
2479 __inout efx_filter_spec_t *spec,
2480 __in uint32_t rss_context);
2482 #endif /* EFSYS_OPT_FILTER */
2486 extern __checkReturn uint32_t
2488 __in_ecount(count) uint32_t const *input,
2490 __in uint32_t init);
2492 extern __checkReturn uint32_t
2494 __in_ecount(length) uint8_t const *input,
2496 __in uint32_t init);
2498 #if EFSYS_OPT_LICENSING
2502 typedef struct efx_key_stats_s {
2504 uint32_t eks_invalid;
2505 uint32_t eks_blacklisted;
2506 uint32_t eks_unverifiable;
2507 uint32_t eks_wrong_node;
2508 uint32_t eks_licensed_apps_lo;
2509 uint32_t eks_licensed_apps_hi;
2510 uint32_t eks_licensed_features_lo;
2511 uint32_t eks_licensed_features_hi;
2514 extern __checkReturn efx_rc_t
2516 __in efx_nic_t *enp);
2520 __in efx_nic_t *enp);
2522 extern __checkReturn boolean_t
2523 efx_lic_check_support(
2524 __in efx_nic_t *enp);
2526 extern __checkReturn efx_rc_t
2527 efx_lic_update_licenses(
2528 __in efx_nic_t *enp);
2530 extern __checkReturn efx_rc_t
2531 efx_lic_get_key_stats(
2532 __in efx_nic_t *enp,
2533 __out efx_key_stats_t *ksp);
2535 extern __checkReturn efx_rc_t
2537 __in efx_nic_t *enp,
2538 __in uint64_t app_id,
2539 __out boolean_t *licensedp);
2541 extern __checkReturn efx_rc_t
2543 __in efx_nic_t *enp,
2544 __in size_t buffer_size,
2545 __out uint32_t *typep,
2546 __out size_t *lengthp,
2547 __out_opt uint8_t *bufferp);
2550 extern __checkReturn efx_rc_t
2552 __in efx_nic_t *enp,
2553 __in_bcount(buffer_size)
2555 __in size_t buffer_size,
2556 __out uint32_t *startp);
2558 extern __checkReturn efx_rc_t
2560 __in efx_nic_t *enp,
2561 __in_bcount(buffer_size)
2563 __in size_t buffer_size,
2564 __in uint32_t offset,
2565 __out uint32_t *endp);
2567 extern __checkReturn __success(return != B_FALSE) boolean_t
2569 __in efx_nic_t *enp,
2570 __in_bcount(buffer_size)
2572 __in size_t buffer_size,
2573 __in uint32_t offset,
2574 __out uint32_t *startp,
2575 __out uint32_t *lengthp);
2577 extern __checkReturn __success(return != B_FALSE) boolean_t
2578 efx_lic_validate_key(
2579 __in efx_nic_t *enp,
2580 __in_bcount(length) caddr_t keyp,
2581 __in uint32_t length);
2583 extern __checkReturn efx_rc_t
2585 __in efx_nic_t *enp,
2586 __in_bcount(buffer_size)
2588 __in size_t buffer_size,
2589 __in uint32_t offset,
2590 __in uint32_t length,
2591 __out_bcount_part(key_max_size, *lengthp)
2593 __in size_t key_max_size,
2594 __out uint32_t *lengthp);
2596 extern __checkReturn efx_rc_t
2598 __in efx_nic_t *enp,
2599 __in_bcount(buffer_size)
2601 __in size_t buffer_size,
2602 __in uint32_t offset,
2603 __in_bcount(length) caddr_t keyp,
2604 __in uint32_t length,
2605 __out uint32_t *lengthp);
2607 __checkReturn efx_rc_t
2609 __in efx_nic_t *enp,
2610 __in_bcount(buffer_size)
2612 __in size_t buffer_size,
2613 __in uint32_t offset,
2614 __in uint32_t length,
2616 __out uint32_t *deltap);
2618 extern __checkReturn efx_rc_t
2619 efx_lic_create_partition(
2620 __in efx_nic_t *enp,
2621 __in_bcount(buffer_size)
2623 __in size_t buffer_size);
2625 extern __checkReturn efx_rc_t
2626 efx_lic_finish_partition(
2627 __in efx_nic_t *enp,
2628 __in_bcount(buffer_size)
2630 __in size_t buffer_size);
2632 #endif /* EFSYS_OPT_LICENSING */
2640 #endif /* _SYS_EFX_H */