1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
46 extern __checkReturn efx_rc_t
50 __out efx_family_t *efp);
53 #define EFX_PCI_VENID_SFC 0x1924
55 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
57 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
58 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
59 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
61 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
62 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
63 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
65 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
66 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
68 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
69 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
70 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
92 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
93 extern __checkReturn uint32_t
95 __in uint32_t crc_init,
96 __in_ecount(length) uint8_t const *input,
100 /* Type prototypes */
102 typedef struct efx_rxq_s efx_rxq_t;
106 typedef struct efx_nic_s efx_nic_t;
108 extern __checkReturn efx_rc_t
110 __in efx_family_t family,
111 __in efsys_identifier_t *esip,
112 __in efsys_bar_t *esbp,
113 __in efsys_lock_t *eslp,
114 __deref_out efx_nic_t **enpp);
116 extern __checkReturn efx_rc_t
118 __in efx_nic_t *enp);
120 extern __checkReturn efx_rc_t
122 __in efx_nic_t *enp);
124 extern __checkReturn efx_rc_t
126 __in efx_nic_t *enp);
130 extern __checkReturn efx_rc_t
131 efx_nic_register_test(
132 __in efx_nic_t *enp);
134 #endif /* EFSYS_OPT_DIAG */
138 __in efx_nic_t *enp);
142 __in efx_nic_t *enp);
146 __in efx_nic_t *enp);
148 #define EFX_PCIE_LINK_SPEED_GEN1 1
149 #define EFX_PCIE_LINK_SPEED_GEN2 2
150 #define EFX_PCIE_LINK_SPEED_GEN3 3
152 typedef enum efx_pcie_link_performance_e {
153 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
154 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
155 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
156 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
157 } efx_pcie_link_performance_t;
159 extern __checkReturn efx_rc_t
160 efx_nic_calculate_pcie_link_bandwidth(
161 __in uint32_t pcie_link_width,
162 __in uint32_t pcie_link_gen,
163 __out uint32_t *bandwidth_mbpsp);
165 extern __checkReturn efx_rc_t
166 efx_nic_check_pcie_link_speed(
168 __in uint32_t pcie_link_width,
169 __in uint32_t pcie_link_gen,
170 __out efx_pcie_link_performance_t *resultp);
174 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
175 /* Huntington and Medford require MCDIv2 commands */
176 #define WITH_MCDI_V2 1
179 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
181 typedef enum efx_mcdi_exception_e {
182 EFX_MCDI_EXCEPTION_MC_REBOOT,
183 EFX_MCDI_EXCEPTION_MC_BADASSERT,
184 } efx_mcdi_exception_t;
186 #if EFSYS_OPT_MCDI_LOGGING
187 typedef enum efx_log_msg_e {
189 EFX_LOG_MCDI_REQUEST,
190 EFX_LOG_MCDI_RESPONSE,
192 #endif /* EFSYS_OPT_MCDI_LOGGING */
194 typedef struct efx_mcdi_transport_s {
196 efsys_mem_t *emt_dma_mem;
197 void (*emt_execute)(void *, efx_mcdi_req_t *);
198 void (*emt_ev_cpl)(void *);
199 void (*emt_exception)(void *, efx_mcdi_exception_t);
200 #if EFSYS_OPT_MCDI_LOGGING
201 void (*emt_logger)(void *, efx_log_msg_t,
202 void *, size_t, void *, size_t);
203 #endif /* EFSYS_OPT_MCDI_LOGGING */
204 #if EFSYS_OPT_MCDI_PROXY_AUTH
205 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
206 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
207 } efx_mcdi_transport_t;
209 extern __checkReturn efx_rc_t
212 __in const efx_mcdi_transport_t *mtp);
214 extern __checkReturn efx_rc_t
216 __in efx_nic_t *enp);
220 __in efx_nic_t *enp);
223 efx_mcdi_get_timeout(
225 __in efx_mcdi_req_t *emrp,
226 __out uint32_t *usec_timeoutp);
229 efx_mcdi_request_start(
231 __in efx_mcdi_req_t *emrp,
232 __in boolean_t ev_cpl);
234 extern __checkReturn boolean_t
235 efx_mcdi_request_poll(
236 __in efx_nic_t *enp);
238 extern __checkReturn boolean_t
239 efx_mcdi_request_abort(
240 __in efx_nic_t *enp);
244 __in efx_nic_t *enp);
246 #endif /* EFSYS_OPT_MCDI */
250 #define EFX_NINTR_SIENA 1024
252 typedef enum efx_intr_type_e {
253 EFX_INTR_INVALID = 0,
259 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
261 extern __checkReturn efx_rc_t
264 __in efx_intr_type_t type,
265 __in efsys_mem_t *esmp);
269 __in efx_nic_t *enp);
273 __in efx_nic_t *enp);
276 efx_intr_disable_unlocked(
277 __in efx_nic_t *enp);
279 #define EFX_INTR_NEVQS 32
281 extern __checkReturn efx_rc_t
284 __in unsigned int level);
287 efx_intr_status_line(
289 __out boolean_t *fatalp,
290 __out uint32_t *maskp);
293 efx_intr_status_message(
295 __in unsigned int message,
296 __out boolean_t *fatalp);
300 __in efx_nic_t *enp);
304 __in efx_nic_t *enp);
308 #if EFSYS_OPT_MAC_STATS
310 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
311 typedef enum efx_mac_stat_e {
314 EFX_MAC_RX_UNICST_PKTS,
315 EFX_MAC_RX_MULTICST_PKTS,
316 EFX_MAC_RX_BRDCST_PKTS,
317 EFX_MAC_RX_PAUSE_PKTS,
318 EFX_MAC_RX_LE_64_PKTS,
319 EFX_MAC_RX_65_TO_127_PKTS,
320 EFX_MAC_RX_128_TO_255_PKTS,
321 EFX_MAC_RX_256_TO_511_PKTS,
322 EFX_MAC_RX_512_TO_1023_PKTS,
323 EFX_MAC_RX_1024_TO_15XX_PKTS,
324 EFX_MAC_RX_GE_15XX_PKTS,
326 EFX_MAC_RX_FCS_ERRORS,
327 EFX_MAC_RX_DROP_EVENTS,
328 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
329 EFX_MAC_RX_SYMBOL_ERRORS,
330 EFX_MAC_RX_ALIGN_ERRORS,
331 EFX_MAC_RX_INTERNAL_ERRORS,
332 EFX_MAC_RX_JABBER_PKTS,
333 EFX_MAC_RX_LANE0_CHAR_ERR,
334 EFX_MAC_RX_LANE1_CHAR_ERR,
335 EFX_MAC_RX_LANE2_CHAR_ERR,
336 EFX_MAC_RX_LANE3_CHAR_ERR,
337 EFX_MAC_RX_LANE0_DISP_ERR,
338 EFX_MAC_RX_LANE1_DISP_ERR,
339 EFX_MAC_RX_LANE2_DISP_ERR,
340 EFX_MAC_RX_LANE3_DISP_ERR,
341 EFX_MAC_RX_MATCH_FAULT,
342 EFX_MAC_RX_NODESC_DROP_CNT,
345 EFX_MAC_TX_UNICST_PKTS,
346 EFX_MAC_TX_MULTICST_PKTS,
347 EFX_MAC_TX_BRDCST_PKTS,
348 EFX_MAC_TX_PAUSE_PKTS,
349 EFX_MAC_TX_LE_64_PKTS,
350 EFX_MAC_TX_65_TO_127_PKTS,
351 EFX_MAC_TX_128_TO_255_PKTS,
352 EFX_MAC_TX_256_TO_511_PKTS,
353 EFX_MAC_TX_512_TO_1023_PKTS,
354 EFX_MAC_TX_1024_TO_15XX_PKTS,
355 EFX_MAC_TX_GE_15XX_PKTS,
357 EFX_MAC_TX_SGL_COL_PKTS,
358 EFX_MAC_TX_MULT_COL_PKTS,
359 EFX_MAC_TX_EX_COL_PKTS,
360 EFX_MAC_TX_LATE_COL_PKTS,
362 EFX_MAC_TX_EX_DEF_PKTS,
363 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
364 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
365 EFX_MAC_PM_TRUNC_VFIFO_FULL,
366 EFX_MAC_PM_DISCARD_VFIFO_FULL,
367 EFX_MAC_PM_TRUNC_QBB,
368 EFX_MAC_PM_DISCARD_QBB,
369 EFX_MAC_PM_DISCARD_MAPPING,
370 EFX_MAC_RXDP_Q_DISABLED_PKTS,
371 EFX_MAC_RXDP_DI_DROPPED_PKTS,
372 EFX_MAC_RXDP_STREAMING_PKTS,
373 EFX_MAC_RXDP_HLB_FETCH,
374 EFX_MAC_RXDP_HLB_WAIT,
375 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
376 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
377 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
378 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
379 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
380 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
381 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
382 EFX_MAC_VADAPTER_RX_BAD_BYTES,
383 EFX_MAC_VADAPTER_RX_OVERFLOW,
384 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
385 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
386 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
387 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
388 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
389 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
390 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
391 EFX_MAC_VADAPTER_TX_BAD_BYTES,
392 EFX_MAC_VADAPTER_TX_OVERFLOW,
396 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
398 #endif /* EFSYS_OPT_MAC_STATS */
400 typedef enum efx_link_mode_e {
401 EFX_LINK_UNKNOWN = 0,
414 #define EFX_MAC_ADDR_LEN 6
416 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
418 #define EFX_MAC_MULTICAST_LIST_MAX 256
420 #define EFX_MAC_SDU_MAX 9202
422 #define EFX_MAC_PDU_ADJUSTMENT \
426 + /* bug16011 */ 16) \
428 #define EFX_MAC_PDU(_sdu) \
429 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
432 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
433 * the SDU rounded up slightly.
435 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
437 #define EFX_MAC_PDU_MIN 60
438 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
440 extern __checkReturn efx_rc_t
445 extern __checkReturn efx_rc_t
450 extern __checkReturn efx_rc_t
455 extern __checkReturn efx_rc_t
458 __in boolean_t all_unicst,
459 __in boolean_t mulcst,
460 __in boolean_t all_mulcst,
461 __in boolean_t brdcst);
463 extern __checkReturn efx_rc_t
464 efx_mac_multicast_list_set(
466 __in_ecount(6*count) uint8_t const *addrs,
469 extern __checkReturn efx_rc_t
470 efx_mac_filter_default_rxq_set(
473 __in boolean_t using_rss);
476 efx_mac_filter_default_rxq_clear(
477 __in efx_nic_t *enp);
479 extern __checkReturn efx_rc_t
482 __in boolean_t enabled);
484 extern __checkReturn efx_rc_t
487 __out boolean_t *mac_upp);
489 #define EFX_FCNTL_RESPOND 0x00000001
490 #define EFX_FCNTL_GENERATE 0x00000002
492 extern __checkReturn efx_rc_t
495 __in unsigned int fcntl,
496 __in boolean_t autoneg);
501 __out unsigned int *fcntl_wantedp,
502 __out unsigned int *fcntl_linkp);
505 #if EFSYS_OPT_MAC_STATS
509 extern __checkReturn const char *
512 __in unsigned int id);
514 #endif /* EFSYS_OPT_NAMES */
516 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
518 #define EFX_MAC_STATS_MASK_NPAGES \
519 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
520 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
523 * Get mask of MAC statistics supported by the hardware.
525 * If mask_size is insufficient to return the mask, EINVAL error is
526 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
527 * (which is sizeof (uint32_t)) is sufficient.
529 extern __checkReturn efx_rc_t
530 efx_mac_stats_get_mask(
532 __out_bcount(mask_size) uint32_t *maskp,
533 __in size_t mask_size);
535 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
536 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
537 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
539 #define EFX_MAC_STATS_SIZE 0x400
541 extern __checkReturn efx_rc_t
543 __in efx_nic_t *enp);
546 * Upload mac statistics supported by the hardware into the given buffer.
548 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
551 * The hardware will only DMA statistics that it understands (of course).
552 * Drivers should not make any assumptions about which statistics are
553 * supported, especially when the statistics are generated by firmware.
555 * Thus, drivers should zero this buffer before use, so that not-understood
556 * statistics read back as zero.
558 extern __checkReturn efx_rc_t
559 efx_mac_stats_upload(
561 __in efsys_mem_t *esmp);
563 extern __checkReturn efx_rc_t
564 efx_mac_stats_periodic(
566 __in efsys_mem_t *esmp,
567 __in uint16_t period_ms,
568 __in boolean_t events);
570 extern __checkReturn efx_rc_t
571 efx_mac_stats_update(
573 __in efsys_mem_t *esmp,
574 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
575 __inout_opt uint32_t *generationp);
577 #endif /* EFSYS_OPT_MAC_STATS */
581 typedef enum efx_mon_type_e {
593 __in efx_nic_t *enp);
595 #endif /* EFSYS_OPT_NAMES */
597 extern __checkReturn efx_rc_t
599 __in efx_nic_t *enp);
601 #if EFSYS_OPT_MON_STATS
603 #define EFX_MON_STATS_PAGE_SIZE 0x100
604 #define EFX_MON_MASK_ELEMENT_SIZE 32
606 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock aa0233c80156308e */
607 typedef enum efx_mon_stat_e {
614 EFX_MON_STAT_EXT_TEMP,
615 EFX_MON_STAT_INT_TEMP,
618 EFX_MON_STAT_INT_COOLING,
619 EFX_MON_STAT_EXT_COOLING,
627 EFX_MON_STAT_AOE_TEMP,
628 EFX_MON_STAT_PSU_AOE_TEMP,
629 EFX_MON_STAT_PSU_TEMP,
635 EFX_MON_STAT_VAOE_IN,
637 EFX_MON_STAT_IAOE_IN,
638 EFX_MON_STAT_NIC_POWER,
642 EFX_MON_STAT_0_9V_ADC,
643 EFX_MON_STAT_INT_TEMP2,
644 EFX_MON_STAT_VREG_TEMP,
645 EFX_MON_STAT_VREG_0_9V_TEMP,
646 EFX_MON_STAT_VREG_1_2V_TEMP,
647 EFX_MON_STAT_INT_VPTAT,
648 EFX_MON_STAT_INT_ADC_TEMP,
649 EFX_MON_STAT_EXT_VPTAT,
650 EFX_MON_STAT_EXT_ADC_TEMP,
651 EFX_MON_STAT_AMBIENT_TEMP,
652 EFX_MON_STAT_AIRFLOW,
653 EFX_MON_STAT_VDD08D_VSS08D_CSR,
654 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
655 EFX_MON_STAT_HOTPOINT_TEMP,
656 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
657 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
658 EFX_MON_STAT_MUM_VCC,
661 EFX_MON_STAT_0V9_A_TEMP,
664 EFX_MON_STAT_0V9_B_TEMP,
665 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
666 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
667 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
668 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
669 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
670 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
671 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
672 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
673 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
674 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
675 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
676 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
677 EFX_MON_STAT_SODIMM_VOUT,
678 EFX_MON_STAT_SODIMM_0_TEMP,
679 EFX_MON_STAT_SODIMM_1_TEMP,
680 EFX_MON_STAT_PHY0_VCC,
681 EFX_MON_STAT_PHY1_VCC,
682 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
683 EFX_MON_STAT_BOARD_FRONT_TEMP,
684 EFX_MON_STAT_BOARD_BACK_TEMP,
690 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
692 typedef enum efx_mon_stat_state_e {
693 EFX_MON_STAT_STATE_OK = 0,
694 EFX_MON_STAT_STATE_WARNING = 1,
695 EFX_MON_STAT_STATE_FATAL = 2,
696 EFX_MON_STAT_STATE_BROKEN = 3,
697 EFX_MON_STAT_STATE_NO_READING = 4,
698 } efx_mon_stat_state_t;
700 typedef struct efx_mon_stat_value_s {
703 } efx_mon_stat_value_t;
710 __in efx_mon_stat_t id);
712 #endif /* EFSYS_OPT_NAMES */
714 extern __checkReturn efx_rc_t
715 efx_mon_stats_update(
717 __in efsys_mem_t *esmp,
718 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
720 #endif /* EFSYS_OPT_MON_STATS */
724 __in efx_nic_t *enp);
728 extern __checkReturn efx_rc_t
730 __in efx_nic_t *enp);
732 #if EFSYS_OPT_PHY_LED_CONTROL
734 typedef enum efx_phy_led_mode_e {
735 EFX_PHY_LED_DEFAULT = 0,
740 } efx_phy_led_mode_t;
742 extern __checkReturn efx_rc_t
745 __in efx_phy_led_mode_t mode);
747 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
749 extern __checkReturn efx_rc_t
751 __in efx_nic_t *enp);
753 #if EFSYS_OPT_LOOPBACK
755 typedef enum efx_loopback_type_e {
756 EFX_LOOPBACK_OFF = 0,
757 EFX_LOOPBACK_DATA = 1,
758 EFX_LOOPBACK_GMAC = 2,
759 EFX_LOOPBACK_XGMII = 3,
760 EFX_LOOPBACK_XGXS = 4,
761 EFX_LOOPBACK_XAUI = 5,
762 EFX_LOOPBACK_GMII = 6,
763 EFX_LOOPBACK_SGMII = 7,
764 EFX_LOOPBACK_XGBR = 8,
765 EFX_LOOPBACK_XFI = 9,
766 EFX_LOOPBACK_XAUI_FAR = 10,
767 EFX_LOOPBACK_GMII_FAR = 11,
768 EFX_LOOPBACK_SGMII_FAR = 12,
769 EFX_LOOPBACK_XFI_FAR = 13,
770 EFX_LOOPBACK_GPHY = 14,
771 EFX_LOOPBACK_PHY_XS = 15,
772 EFX_LOOPBACK_PCS = 16,
773 EFX_LOOPBACK_PMA_PMD = 17,
774 EFX_LOOPBACK_XPORT = 18,
775 EFX_LOOPBACK_XGMII_WS = 19,
776 EFX_LOOPBACK_XAUI_WS = 20,
777 EFX_LOOPBACK_XAUI_WS_FAR = 21,
778 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
779 EFX_LOOPBACK_GMII_WS = 23,
780 EFX_LOOPBACK_XFI_WS = 24,
781 EFX_LOOPBACK_XFI_WS_FAR = 25,
782 EFX_LOOPBACK_PHYXS_WS = 26,
783 EFX_LOOPBACK_PMA_INT = 27,
784 EFX_LOOPBACK_SD_NEAR = 28,
785 EFX_LOOPBACK_SD_FAR = 29,
786 EFX_LOOPBACK_PMA_INT_WS = 30,
787 EFX_LOOPBACK_SD_FEP2_WS = 31,
788 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
789 EFX_LOOPBACK_SD_FEP_WS = 33,
790 EFX_LOOPBACK_SD_FES_WS = 34,
792 } efx_loopback_type_t;
794 typedef enum efx_loopback_kind_e {
795 EFX_LOOPBACK_KIND_OFF = 0,
796 EFX_LOOPBACK_KIND_ALL,
797 EFX_LOOPBACK_KIND_MAC,
798 EFX_LOOPBACK_KIND_PHY,
800 } efx_loopback_kind_t;
804 __in efx_loopback_kind_t loopback_kind,
805 __out efx_qword_t *maskp);
807 extern __checkReturn efx_rc_t
808 efx_port_loopback_set(
810 __in efx_link_mode_t link_mode,
811 __in efx_loopback_type_t type);
815 extern __checkReturn const char *
816 efx_loopback_type_name(
818 __in efx_loopback_type_t type);
820 #endif /* EFSYS_OPT_NAMES */
822 #endif /* EFSYS_OPT_LOOPBACK */
824 extern __checkReturn efx_rc_t
827 __out_opt efx_link_mode_t *link_modep);
831 __in efx_nic_t *enp);
833 typedef enum efx_phy_cap_type_e {
834 EFX_PHY_CAP_INVALID = 0,
841 EFX_PHY_CAP_10000FDX,
845 EFX_PHY_CAP_40000FDX,
847 } efx_phy_cap_type_t;
850 #define EFX_PHY_CAP_CURRENT 0x00000000
851 #define EFX_PHY_CAP_DEFAULT 0x00000001
852 #define EFX_PHY_CAP_PERM 0x00000002
858 __out uint32_t *maskp);
860 extern __checkReturn efx_rc_t
868 __out uint32_t *maskp);
870 extern __checkReturn efx_rc_t
873 __out uint32_t *ouip);
875 typedef enum efx_phy_media_type_e {
876 EFX_PHY_MEDIA_INVALID = 0,
881 EFX_PHY_MEDIA_SFP_PLUS,
882 EFX_PHY_MEDIA_BASE_T,
883 EFX_PHY_MEDIA_QSFP_PLUS,
885 } efx_phy_media_type_t;
888 * Get the type of medium currently used. If the board has ports for
889 * modules, a module is present, and we recognise the media type of
890 * the module, then this will be the media type of the module.
891 * Otherwise it will be the media type of the port.
894 efx_phy_media_type_get(
896 __out efx_phy_media_type_t *typep);
898 extern __checkReturn efx_rc_t
899 efx_phy_module_get_info(
901 __in uint8_t dev_addr,
904 __out_bcount(len) uint8_t *data);
906 #if EFSYS_OPT_PHY_STATS
908 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
909 typedef enum efx_phy_stat_e {
911 EFX_PHY_STAT_PMA_PMD_LINK_UP,
912 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
913 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
914 EFX_PHY_STAT_PMA_PMD_REV_A,
915 EFX_PHY_STAT_PMA_PMD_REV_B,
916 EFX_PHY_STAT_PMA_PMD_REV_C,
917 EFX_PHY_STAT_PMA_PMD_REV_D,
918 EFX_PHY_STAT_PCS_LINK_UP,
919 EFX_PHY_STAT_PCS_RX_FAULT,
920 EFX_PHY_STAT_PCS_TX_FAULT,
921 EFX_PHY_STAT_PCS_BER,
922 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
923 EFX_PHY_STAT_PHY_XS_LINK_UP,
924 EFX_PHY_STAT_PHY_XS_RX_FAULT,
925 EFX_PHY_STAT_PHY_XS_TX_FAULT,
926 EFX_PHY_STAT_PHY_XS_ALIGN,
927 EFX_PHY_STAT_PHY_XS_SYNC_A,
928 EFX_PHY_STAT_PHY_XS_SYNC_B,
929 EFX_PHY_STAT_PHY_XS_SYNC_C,
930 EFX_PHY_STAT_PHY_XS_SYNC_D,
931 EFX_PHY_STAT_AN_LINK_UP,
932 EFX_PHY_STAT_AN_MASTER,
933 EFX_PHY_STAT_AN_LOCAL_RX_OK,
934 EFX_PHY_STAT_AN_REMOTE_RX_OK,
935 EFX_PHY_STAT_CL22EXT_LINK_UP,
940 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
941 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
942 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
943 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
944 EFX_PHY_STAT_AN_COMPLETE,
945 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
946 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
947 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
948 EFX_PHY_STAT_PCS_FW_VERSION_0,
949 EFX_PHY_STAT_PCS_FW_VERSION_1,
950 EFX_PHY_STAT_PCS_FW_VERSION_2,
951 EFX_PHY_STAT_PCS_FW_VERSION_3,
952 EFX_PHY_STAT_PCS_FW_BUILD_YY,
953 EFX_PHY_STAT_PCS_FW_BUILD_MM,
954 EFX_PHY_STAT_PCS_FW_BUILD_DD,
955 EFX_PHY_STAT_PCS_OP_MODE,
959 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
966 __in efx_phy_stat_t stat);
968 #endif /* EFSYS_OPT_NAMES */
970 #define EFX_PHY_STATS_SIZE 0x100
972 extern __checkReturn efx_rc_t
973 efx_phy_stats_update(
975 __in efsys_mem_t *esmp,
976 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
978 #endif /* EFSYS_OPT_PHY_STATS */
983 typedef enum efx_bist_type_e {
984 EFX_BIST_TYPE_UNKNOWN,
985 EFX_BIST_TYPE_PHY_NORMAL,
986 EFX_BIST_TYPE_PHY_CABLE_SHORT,
987 EFX_BIST_TYPE_PHY_CABLE_LONG,
988 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
989 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
990 EFX_BIST_TYPE_REG, /* Test the register memories */
991 EFX_BIST_TYPE_NTYPES,
994 typedef enum efx_bist_result_e {
995 EFX_BIST_RESULT_UNKNOWN,
996 EFX_BIST_RESULT_RUNNING,
997 EFX_BIST_RESULT_PASSED,
998 EFX_BIST_RESULT_FAILED,
1001 typedef enum efx_phy_cable_status_e {
1002 EFX_PHY_CABLE_STATUS_OK,
1003 EFX_PHY_CABLE_STATUS_INVALID,
1004 EFX_PHY_CABLE_STATUS_OPEN,
1005 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1006 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1007 EFX_PHY_CABLE_STATUS_BUSY,
1008 } efx_phy_cable_status_t;
1010 typedef enum efx_bist_value_e {
1011 EFX_BIST_PHY_CABLE_LENGTH_A,
1012 EFX_BIST_PHY_CABLE_LENGTH_B,
1013 EFX_BIST_PHY_CABLE_LENGTH_C,
1014 EFX_BIST_PHY_CABLE_LENGTH_D,
1015 EFX_BIST_PHY_CABLE_STATUS_A,
1016 EFX_BIST_PHY_CABLE_STATUS_B,
1017 EFX_BIST_PHY_CABLE_STATUS_C,
1018 EFX_BIST_PHY_CABLE_STATUS_D,
1019 EFX_BIST_FAULT_CODE,
1021 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1027 EFX_BIST_MEM_EXPECT,
1028 EFX_BIST_MEM_ACTUAL,
1030 EFX_BIST_MEM_ECC_PARITY,
1031 EFX_BIST_MEM_ECC_FATAL,
1035 extern __checkReturn efx_rc_t
1036 efx_bist_enable_offline(
1037 __in efx_nic_t *enp);
1039 extern __checkReturn efx_rc_t
1041 __in efx_nic_t *enp,
1042 __in efx_bist_type_t type);
1044 extern __checkReturn efx_rc_t
1046 __in efx_nic_t *enp,
1047 __in efx_bist_type_t type,
1048 __out efx_bist_result_t *resultp,
1049 __out_opt uint32_t *value_maskp,
1050 __out_ecount_opt(count) unsigned long *valuesp,
1055 __in efx_nic_t *enp,
1056 __in efx_bist_type_t type);
1058 #endif /* EFSYS_OPT_BIST */
1060 #define EFX_FEATURE_IPV6 0x00000001
1061 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1062 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1063 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1064 #define EFX_FEATURE_MCDI 0x00000020
1065 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1066 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1067 #define EFX_FEATURE_TURBO 0x00000100
1068 #define EFX_FEATURE_MCDI_DMA 0x00000200
1069 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1070 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1071 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1072 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1073 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1075 typedef enum efx_tunnel_protocol_e {
1076 EFX_TUNNEL_PROTOCOL_NONE = 0,
1077 EFX_TUNNEL_PROTOCOL_VXLAN,
1078 EFX_TUNNEL_PROTOCOL_GENEVE,
1079 EFX_TUNNEL_PROTOCOL_NVGRE,
1081 } efx_tunnel_protocol_t;
1083 typedef struct efx_nic_cfg_s {
1084 uint32_t enc_board_type;
1085 uint32_t enc_phy_type;
1087 char enc_phy_name[21];
1089 char enc_phy_revision[21];
1090 efx_mon_type_t enc_mon_type;
1091 #if EFSYS_OPT_MON_STATS
1092 uint32_t enc_mon_stat_dma_buf_size;
1093 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1095 unsigned int enc_features;
1096 uint8_t enc_mac_addr[6];
1097 uint8_t enc_port; /* PHY port number */
1098 uint32_t enc_intr_vec_base;
1099 uint32_t enc_intr_limit;
1100 uint32_t enc_evq_limit;
1101 uint32_t enc_txq_limit;
1102 uint32_t enc_rxq_limit;
1103 uint32_t enc_txq_max_ndescs;
1104 uint32_t enc_buftbl_limit;
1105 uint32_t enc_piobuf_limit;
1106 uint32_t enc_piobuf_size;
1107 uint32_t enc_piobuf_min_alloc_size;
1108 uint32_t enc_evq_timer_quantum_ns;
1109 uint32_t enc_evq_timer_max_us;
1110 uint32_t enc_clk_mult;
1111 uint32_t enc_rx_prefix_size;
1112 uint32_t enc_rx_buf_align_start;
1113 uint32_t enc_rx_buf_align_end;
1114 uint32_t enc_rx_scale_max_exclusive_contexts;
1115 #if EFSYS_OPT_LOOPBACK
1116 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1117 #endif /* EFSYS_OPT_LOOPBACK */
1118 #if EFSYS_OPT_PHY_FLAGS
1119 uint32_t enc_phy_flags_mask;
1120 #endif /* EFSYS_OPT_PHY_FLAGS */
1121 #if EFSYS_OPT_PHY_LED_CONTROL
1122 uint32_t enc_led_mask;
1123 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1124 #if EFSYS_OPT_PHY_STATS
1125 uint64_t enc_phy_stat_mask;
1126 #endif /* EFSYS_OPT_PHY_STATS */
1128 uint8_t enc_mcdi_mdio_channel;
1129 #if EFSYS_OPT_PHY_STATS
1130 uint32_t enc_mcdi_phy_stat_mask;
1131 #endif /* EFSYS_OPT_PHY_STATS */
1132 #if EFSYS_OPT_MON_STATS
1133 uint32_t *enc_mcdi_sensor_maskp;
1134 uint32_t enc_mcdi_sensor_mask_size;
1135 #endif /* EFSYS_OPT_MON_STATS */
1136 #endif /* EFSYS_OPT_MCDI */
1138 uint32_t enc_bist_mask;
1139 #endif /* EFSYS_OPT_BIST */
1140 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1143 uint32_t enc_privilege_mask;
1144 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1145 boolean_t enc_bug26807_workaround;
1146 boolean_t enc_bug35388_workaround;
1147 boolean_t enc_bug41750_workaround;
1148 boolean_t enc_bug61265_workaround;
1149 boolean_t enc_rx_batching_enabled;
1150 /* Maximum number of descriptors completed in an rx event. */
1151 uint32_t enc_rx_batch_max;
1152 /* Number of rx descriptors the hardware requires for a push. */
1153 uint32_t enc_rx_push_align;
1154 /* Maximum amount of data in DMA descriptor */
1155 uint32_t enc_tx_dma_desc_size_max;
1157 * Boundary which DMA descriptor data must not cross or 0 if no
1160 uint32_t enc_tx_dma_desc_boundary;
1162 * Maximum number of bytes into the packet the TCP header can start for
1163 * the hardware to apply TSO packet edits.
1165 uint32_t enc_tx_tso_tcp_header_offset_limit;
1166 boolean_t enc_fw_assisted_tso_enabled;
1167 boolean_t enc_fw_assisted_tso_v2_enabled;
1168 /* Number of TSO contexts on the NIC (FATSOv2) */
1169 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1170 boolean_t enc_hw_tx_insert_vlan_enabled;
1171 /* Number of PFs on the NIC */
1172 uint32_t enc_hw_pf_count;
1173 /* Datapath firmware vadapter/vport/vswitch support */
1174 boolean_t enc_datapath_cap_evb;
1175 boolean_t enc_rx_disable_scatter_supported;
1176 boolean_t enc_allow_set_mac_with_installed_filters;
1177 boolean_t enc_enhanced_set_mac_supported;
1178 boolean_t enc_init_evq_v2_supported;
1179 boolean_t enc_rx_packed_stream_supported;
1180 boolean_t enc_rx_var_packed_stream_supported;
1181 boolean_t enc_pm_and_rxdp_counters;
1182 boolean_t enc_mac_stats_40g_tx_size_bins;
1183 uint32_t enc_tunnel_encapsulations_supported;
1185 * NIC global maximum for unique UDP tunnel ports shared by all
1188 uint32_t enc_tunnel_config_udp_entries_max;
1189 /* External port identifier */
1190 uint8_t enc_external_port;
1191 uint32_t enc_mcdi_max_payload_length;
1192 /* VPD may be per-PF or global */
1193 boolean_t enc_vpd_is_global;
1194 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1195 uint32_t enc_required_pcie_bandwidth_mbps;
1196 uint32_t enc_max_pcie_link_gen;
1197 /* Firmware verifies integrity of NVRAM updates */
1198 uint32_t enc_nvram_update_verify_result_supported;
1201 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1202 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1204 #define EFX_PCI_FUNCTION(_encp) \
1205 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1207 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1209 extern const efx_nic_cfg_t *
1211 __in efx_nic_t *enp);
1213 typedef struct efx_nic_fw_info_s {
1214 /* Basic FW version information */
1215 uint16_t enfi_mc_fw_version[4];
1217 * If datapath capabilities can be detected,
1218 * additional FW information is to be shown
1220 boolean_t enfi_dpcpu_fw_ids_valid;
1221 /* Rx and Tx datapath CPU FW IDs */
1222 uint16_t enfi_rx_dpcpu_fw_id;
1223 uint16_t enfi_tx_dpcpu_fw_id;
1224 } efx_nic_fw_info_t;
1226 extern __checkReturn efx_rc_t
1227 efx_nic_get_fw_version(
1228 __in efx_nic_t *enp,
1229 __out efx_nic_fw_info_t *enfip);
1231 /* Driver resource limits (minimum required/maximum usable). */
1232 typedef struct efx_drv_limits_s {
1233 uint32_t edl_min_evq_count;
1234 uint32_t edl_max_evq_count;
1236 uint32_t edl_min_rxq_count;
1237 uint32_t edl_max_rxq_count;
1239 uint32_t edl_min_txq_count;
1240 uint32_t edl_max_txq_count;
1242 /* PIO blocks (sub-allocated from piobuf) */
1243 uint32_t edl_min_pio_alloc_size;
1244 uint32_t edl_max_pio_alloc_count;
1247 extern __checkReturn efx_rc_t
1248 efx_nic_set_drv_limits(
1249 __inout efx_nic_t *enp,
1250 __in efx_drv_limits_t *edlp);
1252 typedef enum efx_nic_region_e {
1253 EFX_REGION_VI, /* Memory BAR UC mapping */
1254 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1257 extern __checkReturn efx_rc_t
1258 efx_nic_get_bar_region(
1259 __in efx_nic_t *enp,
1260 __in efx_nic_region_t region,
1261 __out uint32_t *offsetp,
1262 __out size_t *sizep);
1264 extern __checkReturn efx_rc_t
1265 efx_nic_get_vi_pool(
1266 __in efx_nic_t *enp,
1267 __out uint32_t *evq_countp,
1268 __out uint32_t *rxq_countp,
1269 __out uint32_t *txq_countp);
1274 typedef enum efx_vpd_tag_e {
1281 typedef uint16_t efx_vpd_keyword_t;
1283 typedef struct efx_vpd_value_s {
1284 efx_vpd_tag_t evv_tag;
1285 efx_vpd_keyword_t evv_keyword;
1287 uint8_t evv_value[0x100];
1291 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1293 extern __checkReturn efx_rc_t
1295 __in efx_nic_t *enp);
1297 extern __checkReturn efx_rc_t
1299 __in efx_nic_t *enp,
1300 __out size_t *sizep);
1302 extern __checkReturn efx_rc_t
1304 __in efx_nic_t *enp,
1305 __out_bcount(size) caddr_t data,
1308 extern __checkReturn efx_rc_t
1310 __in efx_nic_t *enp,
1311 __in_bcount(size) caddr_t data,
1314 extern __checkReturn efx_rc_t
1316 __in efx_nic_t *enp,
1317 __in_bcount(size) caddr_t data,
1320 extern __checkReturn efx_rc_t
1322 __in efx_nic_t *enp,
1323 __in_bcount(size) caddr_t data,
1325 __inout efx_vpd_value_t *evvp);
1327 extern __checkReturn efx_rc_t
1329 __in efx_nic_t *enp,
1330 __inout_bcount(size) caddr_t data,
1332 __in efx_vpd_value_t *evvp);
1334 extern __checkReturn efx_rc_t
1336 __in efx_nic_t *enp,
1337 __inout_bcount(size) caddr_t data,
1339 __out efx_vpd_value_t *evvp,
1340 __inout unsigned int *contp);
1342 extern __checkReturn efx_rc_t
1344 __in efx_nic_t *enp,
1345 __in_bcount(size) caddr_t data,
1350 __in efx_nic_t *enp);
1352 #endif /* EFSYS_OPT_VPD */
1358 typedef enum efx_nvram_type_e {
1359 EFX_NVRAM_INVALID = 0,
1361 EFX_NVRAM_BOOTROM_CFG,
1362 EFX_NVRAM_MC_FIRMWARE,
1363 EFX_NVRAM_MC_GOLDEN,
1369 EFX_NVRAM_FPGA_BACKUP,
1370 EFX_NVRAM_DYNAMIC_CFG,
1373 EFX_NVRAM_MUM_FIRMWARE,
1377 extern __checkReturn efx_rc_t
1379 __in efx_nic_t *enp);
1383 extern __checkReturn efx_rc_t
1385 __in efx_nic_t *enp);
1387 #endif /* EFSYS_OPT_DIAG */
1389 extern __checkReturn efx_rc_t
1391 __in efx_nic_t *enp,
1392 __in efx_nvram_type_t type,
1393 __out size_t *sizep);
1395 extern __checkReturn efx_rc_t
1397 __in efx_nic_t *enp,
1398 __in efx_nvram_type_t type,
1399 __out_opt size_t *pref_chunkp);
1401 extern __checkReturn efx_rc_t
1402 efx_nvram_rw_finish(
1403 __in efx_nic_t *enp,
1404 __in efx_nvram_type_t type,
1405 __out_opt uint32_t *verify_resultp);
1407 extern __checkReturn efx_rc_t
1408 efx_nvram_get_version(
1409 __in efx_nic_t *enp,
1410 __in efx_nvram_type_t type,
1411 __out uint32_t *subtypep,
1412 __out_ecount(4) uint16_t version[4]);
1414 extern __checkReturn efx_rc_t
1415 efx_nvram_read_chunk(
1416 __in efx_nic_t *enp,
1417 __in efx_nvram_type_t type,
1418 __in unsigned int offset,
1419 __out_bcount(size) caddr_t data,
1422 extern __checkReturn efx_rc_t
1423 efx_nvram_read_backup(
1424 __in efx_nic_t *enp,
1425 __in efx_nvram_type_t type,
1426 __in unsigned int offset,
1427 __out_bcount(size) caddr_t data,
1430 extern __checkReturn efx_rc_t
1431 efx_nvram_set_version(
1432 __in efx_nic_t *enp,
1433 __in efx_nvram_type_t type,
1434 __in_ecount(4) uint16_t version[4]);
1436 extern __checkReturn efx_rc_t
1438 __in efx_nic_t *enp,
1439 __in efx_nvram_type_t type,
1440 __in_bcount(partn_size) caddr_t partn_data,
1441 __in size_t partn_size);
1443 extern __checkReturn efx_rc_t
1445 __in efx_nic_t *enp,
1446 __in efx_nvram_type_t type);
1448 extern __checkReturn efx_rc_t
1449 efx_nvram_write_chunk(
1450 __in efx_nic_t *enp,
1451 __in efx_nvram_type_t type,
1452 __in unsigned int offset,
1453 __in_bcount(size) caddr_t data,
1458 __in efx_nic_t *enp);
1460 #endif /* EFSYS_OPT_NVRAM */
1462 #if EFSYS_OPT_BOOTCFG
1464 /* Report size and offset of bootcfg sector in NVRAM partition. */
1465 extern __checkReturn efx_rc_t
1466 efx_bootcfg_sector_info(
1467 __in efx_nic_t *enp,
1469 __out_opt uint32_t *sector_countp,
1470 __out size_t *offsetp,
1471 __out size_t *max_sizep);
1474 * Copy bootcfg sector data to a target buffer which may differ in size.
1475 * Optionally corrects format errors in source buffer.
1478 efx_bootcfg_copy_sector(
1479 __in efx_nic_t *enp,
1480 __inout_bcount(sector_length)
1482 __in size_t sector_length,
1483 __out_bcount(data_size) uint8_t *data,
1484 __in size_t data_size,
1485 __in boolean_t handle_format_errors);
1489 __in efx_nic_t *enp,
1490 __out_bcount(size) uint8_t *data,
1495 __in efx_nic_t *enp,
1496 __in_bcount(size) uint8_t *data,
1499 #endif /* EFSYS_OPT_BOOTCFG */
1503 typedef enum efx_pattern_type_t {
1504 EFX_PATTERN_BYTE_INCREMENT = 0,
1505 EFX_PATTERN_ALL_THE_SAME,
1506 EFX_PATTERN_BIT_ALTERNATE,
1507 EFX_PATTERN_BYTE_ALTERNATE,
1508 EFX_PATTERN_BYTE_CHANGING,
1509 EFX_PATTERN_BIT_SWEEP,
1511 } efx_pattern_type_t;
1514 (*efx_sram_pattern_fn_t)(
1516 __in boolean_t negate,
1517 __out efx_qword_t *eqp);
1519 extern __checkReturn efx_rc_t
1521 __in efx_nic_t *enp,
1522 __in efx_pattern_type_t type);
1524 #endif /* EFSYS_OPT_DIAG */
1526 extern __checkReturn efx_rc_t
1527 efx_sram_buf_tbl_set(
1528 __in efx_nic_t *enp,
1530 __in efsys_mem_t *esmp,
1534 efx_sram_buf_tbl_clear(
1535 __in efx_nic_t *enp,
1539 #define EFX_BUF_TBL_SIZE 0x20000
1541 #define EFX_BUF_SIZE 4096
1545 typedef struct efx_evq_s efx_evq_t;
1547 #if EFSYS_OPT_QSTATS
1549 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1550 typedef enum efx_ev_qstat_e {
1556 EV_RX_PAUSE_FRM_ERR,
1557 EV_RX_BUF_OWNER_ID_ERR,
1558 EV_RX_IPV4_HDR_CHKSUM_ERR,
1559 EV_RX_TCP_UDP_CHKSUM_ERR,
1563 EV_RX_MCAST_HASH_MATCH,
1580 EV_DRIVER_SRM_UPD_DONE,
1581 EV_DRIVER_TX_DESCQ_FLS_DONE,
1582 EV_DRIVER_RX_DESCQ_FLS_DONE,
1583 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1584 EV_DRIVER_RX_DSC_ERROR,
1585 EV_DRIVER_TX_DSC_ERROR,
1591 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1593 #endif /* EFSYS_OPT_QSTATS */
1595 extern __checkReturn efx_rc_t
1597 __in efx_nic_t *enp);
1601 __in efx_nic_t *enp);
1603 #define EFX_EVQ_MAXNEVS 32768
1604 #define EFX_EVQ_MINNEVS 512
1606 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1607 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1609 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1610 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1611 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1612 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1614 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1615 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1616 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1618 extern __checkReturn efx_rc_t
1620 __in efx_nic_t *enp,
1621 __in unsigned int index,
1622 __in efsys_mem_t *esmp,
1626 __in uint32_t flags,
1627 __deref_out efx_evq_t **eepp);
1631 __in efx_evq_t *eep,
1632 __in uint16_t data);
1634 typedef __checkReturn boolean_t
1635 (*efx_initialized_ev_t)(
1636 __in_opt void *arg);
1638 #define EFX_PKT_UNICAST 0x0004
1639 #define EFX_PKT_START 0x0008
1641 #define EFX_PKT_VLAN_TAGGED 0x0010
1642 #define EFX_CKSUM_TCPUDP 0x0020
1643 #define EFX_CKSUM_IPV4 0x0040
1644 #define EFX_PKT_CONT 0x0080
1646 #define EFX_CHECK_VLAN 0x0100
1647 #define EFX_PKT_TCP 0x0200
1648 #define EFX_PKT_UDP 0x0400
1649 #define EFX_PKT_IPV4 0x0800
1651 #define EFX_PKT_IPV6 0x1000
1652 #define EFX_PKT_PREFIX_LEN 0x2000
1653 #define EFX_ADDR_MISMATCH 0x4000
1654 #define EFX_DISCARD 0x8000
1657 * The following flags are used only for packed stream
1658 * mode. The values for the flags are reused to fit into 16 bit,
1659 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1660 * packed stream mode
1662 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1663 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1666 #define EFX_EV_RX_NLABELS 32
1667 #define EFX_EV_TX_NLABELS 32
1669 typedef __checkReturn boolean_t
1672 __in uint32_t label,
1675 __in uint16_t flags);
1677 #if EFSYS_OPT_RX_PACKED_STREAM
1680 * Packed stream mode is documented in SF-112241-TC.
1681 * The general idea is that, instead of putting each incoming
1682 * packet into a separate buffer which is specified in a RX
1683 * descriptor, a large buffer is provided to the hardware and
1684 * packets are put there in a continuous stream.
1685 * The main advantage of such an approach is that RX queue refilling
1686 * happens much less frequently.
1689 typedef __checkReturn boolean_t
1692 __in uint32_t label,
1694 __in uint32_t pkt_count,
1695 __in uint16_t flags);
1699 typedef __checkReturn boolean_t
1702 __in uint32_t label,
1705 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1706 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1707 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1708 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1709 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1710 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1711 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1712 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1713 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1715 typedef __checkReturn boolean_t
1716 (*efx_exception_ev_t)(
1718 __in uint32_t label,
1719 __in uint32_t data);
1721 typedef __checkReturn boolean_t
1722 (*efx_rxq_flush_done_ev_t)(
1724 __in uint32_t rxq_index);
1726 typedef __checkReturn boolean_t
1727 (*efx_rxq_flush_failed_ev_t)(
1729 __in uint32_t rxq_index);
1731 typedef __checkReturn boolean_t
1732 (*efx_txq_flush_done_ev_t)(
1734 __in uint32_t txq_index);
1736 typedef __checkReturn boolean_t
1737 (*efx_software_ev_t)(
1739 __in uint16_t magic);
1741 typedef __checkReturn boolean_t
1744 __in uint32_t code);
1746 #define EFX_SRAM_CLEAR 0
1747 #define EFX_SRAM_UPDATE 1
1748 #define EFX_SRAM_ILLEGAL_CLEAR 2
1750 typedef __checkReturn boolean_t
1751 (*efx_wake_up_ev_t)(
1753 __in uint32_t label);
1755 typedef __checkReturn boolean_t
1758 __in uint32_t label);
1760 typedef __checkReturn boolean_t
1761 (*efx_link_change_ev_t)(
1763 __in efx_link_mode_t link_mode);
1765 #if EFSYS_OPT_MON_STATS
1767 typedef __checkReturn boolean_t
1768 (*efx_monitor_ev_t)(
1770 __in efx_mon_stat_t id,
1771 __in efx_mon_stat_value_t value);
1773 #endif /* EFSYS_OPT_MON_STATS */
1775 #if EFSYS_OPT_MAC_STATS
1777 typedef __checkReturn boolean_t
1778 (*efx_mac_stats_ev_t)(
1780 __in uint32_t generation);
1782 #endif /* EFSYS_OPT_MAC_STATS */
1784 typedef struct efx_ev_callbacks_s {
1785 efx_initialized_ev_t eec_initialized;
1787 #if EFSYS_OPT_RX_PACKED_STREAM
1788 efx_rx_ps_ev_t eec_rx_ps;
1791 efx_exception_ev_t eec_exception;
1792 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1793 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1794 efx_txq_flush_done_ev_t eec_txq_flush_done;
1795 efx_software_ev_t eec_software;
1796 efx_sram_ev_t eec_sram;
1797 efx_wake_up_ev_t eec_wake_up;
1798 efx_timer_ev_t eec_timer;
1799 efx_link_change_ev_t eec_link_change;
1800 #if EFSYS_OPT_MON_STATS
1801 efx_monitor_ev_t eec_monitor;
1802 #endif /* EFSYS_OPT_MON_STATS */
1803 #if EFSYS_OPT_MAC_STATS
1804 efx_mac_stats_ev_t eec_mac_stats;
1805 #endif /* EFSYS_OPT_MAC_STATS */
1806 } efx_ev_callbacks_t;
1808 extern __checkReturn boolean_t
1810 __in efx_evq_t *eep,
1811 __in unsigned int count);
1813 #if EFSYS_OPT_EV_PREFETCH
1817 __in efx_evq_t *eep,
1818 __in unsigned int count);
1820 #endif /* EFSYS_OPT_EV_PREFETCH */
1824 __in efx_evq_t *eep,
1825 __inout unsigned int *countp,
1826 __in const efx_ev_callbacks_t *eecp,
1827 __in_opt void *arg);
1829 extern __checkReturn efx_rc_t
1830 efx_ev_usecs_to_ticks(
1831 __in efx_nic_t *enp,
1832 __in unsigned int usecs,
1833 __out unsigned int *ticksp);
1835 extern __checkReturn efx_rc_t
1837 __in efx_evq_t *eep,
1838 __in unsigned int us);
1840 extern __checkReturn efx_rc_t
1842 __in efx_evq_t *eep,
1843 __in unsigned int count);
1845 #if EFSYS_OPT_QSTATS
1851 __in efx_nic_t *enp,
1852 __in unsigned int id);
1854 #endif /* EFSYS_OPT_NAMES */
1857 efx_ev_qstats_update(
1858 __in efx_evq_t *eep,
1859 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1861 #endif /* EFSYS_OPT_QSTATS */
1865 __in efx_evq_t *eep);
1869 extern __checkReturn efx_rc_t
1871 __inout efx_nic_t *enp);
1875 __in efx_nic_t *enp);
1877 #if EFSYS_OPT_RX_SCATTER
1878 __checkReturn efx_rc_t
1879 efx_rx_scatter_enable(
1880 __in efx_nic_t *enp,
1881 __in unsigned int buf_size);
1882 #endif /* EFSYS_OPT_RX_SCATTER */
1884 /* Handle to represent use of the default RSS context. */
1885 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
1887 #if EFSYS_OPT_RX_SCALE
1889 typedef enum efx_rx_hash_alg_e {
1890 EFX_RX_HASHALG_LFSR = 0,
1891 EFX_RX_HASHALG_TOEPLITZ
1892 } efx_rx_hash_alg_t;
1894 #define EFX_RX_HASH_IPV4 (1U << 0)
1895 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
1896 #define EFX_RX_HASH_IPV6 (1U << 2)
1897 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
1899 typedef unsigned int efx_rx_hash_type_t;
1901 typedef enum efx_rx_hash_support_e {
1902 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1903 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1904 } efx_rx_hash_support_t;
1906 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
1907 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1908 #define EFX_MAXRSS 64 /* RX indirection entry range */
1909 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1911 typedef enum efx_rx_scale_context_type_e {
1912 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
1913 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1914 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1915 } efx_rx_scale_context_type_t;
1917 extern __checkReturn efx_rc_t
1918 efx_rx_hash_default_support_get(
1919 __in efx_nic_t *enp,
1920 __out efx_rx_hash_support_t *supportp);
1923 extern __checkReturn efx_rc_t
1924 efx_rx_scale_default_support_get(
1925 __in efx_nic_t *enp,
1926 __out efx_rx_scale_context_type_t *typep);
1928 extern __checkReturn efx_rc_t
1929 efx_rx_scale_context_alloc(
1930 __in efx_nic_t *enp,
1931 __in efx_rx_scale_context_type_t type,
1932 __in uint32_t num_queues,
1933 __out uint32_t *rss_contextp);
1935 extern __checkReturn efx_rc_t
1936 efx_rx_scale_context_free(
1937 __in efx_nic_t *enp,
1938 __in uint32_t rss_context);
1940 extern __checkReturn efx_rc_t
1941 efx_rx_scale_mode_set(
1942 __in efx_nic_t *enp,
1943 __in uint32_t rss_context,
1944 __in efx_rx_hash_alg_t alg,
1945 __in efx_rx_hash_type_t type,
1946 __in boolean_t insert);
1948 extern __checkReturn efx_rc_t
1949 efx_rx_scale_tbl_set(
1950 __in efx_nic_t *enp,
1951 __in uint32_t rss_context,
1952 __in_ecount(n) unsigned int *table,
1955 extern __checkReturn efx_rc_t
1956 efx_rx_scale_key_set(
1957 __in efx_nic_t *enp,
1958 __in uint32_t rss_context,
1959 __in_ecount(n) uint8_t *key,
1962 extern __checkReturn uint32_t
1963 efx_pseudo_hdr_hash_get(
1964 __in efx_rxq_t *erp,
1965 __in efx_rx_hash_alg_t func,
1966 __in uint8_t *buffer);
1968 #endif /* EFSYS_OPT_RX_SCALE */
1970 extern __checkReturn efx_rc_t
1971 efx_pseudo_hdr_pkt_length_get(
1972 __in efx_rxq_t *erp,
1973 __in uint8_t *buffer,
1974 __out uint16_t *pkt_lengthp);
1976 #define EFX_RXQ_MAXNDESCS 4096
1977 #define EFX_RXQ_MINNDESCS 512
1979 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1980 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1981 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1982 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1984 typedef enum efx_rxq_type_e {
1985 EFX_RXQ_TYPE_DEFAULT,
1986 EFX_RXQ_TYPE_PACKED_STREAM,
1991 * Dummy flag to be used instead of 0 to make it clear that the argument
1992 * is receive queue flags.
1994 #define EFX_RXQ_FLAG_NONE 0x0
1995 #define EFX_RXQ_FLAG_SCATTER 0x1
1997 * If tunnels are supported and Rx event can provide information about
1998 * either outer or inner packet classes (e.g. SFN8xxx adapters with
1999 * full-feature firmware variant running), outer classes are requested by
2000 * default. However, if the driver supports tunnels, the flag allows to
2001 * request inner classes which are required to be able to interpret inner
2002 * Rx checksum offload results.
2004 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2006 extern __checkReturn efx_rc_t
2008 __in efx_nic_t *enp,
2009 __in unsigned int index,
2010 __in unsigned int label,
2011 __in efx_rxq_type_t type,
2012 __in efsys_mem_t *esmp,
2015 __in unsigned int flags,
2016 __in efx_evq_t *eep,
2017 __deref_out efx_rxq_t **erpp);
2019 #if EFSYS_OPT_RX_PACKED_STREAM
2021 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2022 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2023 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2024 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2025 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2027 extern __checkReturn efx_rc_t
2028 efx_rx_qcreate_packed_stream(
2029 __in efx_nic_t *enp,
2030 __in unsigned int index,
2031 __in unsigned int label,
2032 __in uint32_t ps_buf_size,
2033 __in efsys_mem_t *esmp,
2035 __in efx_evq_t *eep,
2036 __deref_out efx_rxq_t **erpp);
2040 typedef struct efx_buffer_s {
2041 efsys_dma_addr_t eb_addr;
2046 typedef struct efx_desc_s {
2052 __in efx_rxq_t *erp,
2053 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2055 __in unsigned int ndescs,
2056 __in unsigned int completed,
2057 __in unsigned int added);
2061 __in efx_rxq_t *erp,
2062 __in unsigned int added,
2063 __inout unsigned int *pushedp);
2065 #if EFSYS_OPT_RX_PACKED_STREAM
2068 efx_rx_qpush_ps_credits(
2069 __in efx_rxq_t *erp);
2071 extern __checkReturn uint8_t *
2072 efx_rx_qps_packet_info(
2073 __in efx_rxq_t *erp,
2074 __in uint8_t *buffer,
2075 __in uint32_t buffer_length,
2076 __in uint32_t current_offset,
2077 __out uint16_t *lengthp,
2078 __out uint32_t *next_offsetp,
2079 __out uint32_t *timestamp);
2082 extern __checkReturn efx_rc_t
2084 __in efx_rxq_t *erp);
2088 __in efx_rxq_t *erp);
2092 __in efx_rxq_t *erp);
2096 typedef struct efx_txq_s efx_txq_t;
2098 #if EFSYS_OPT_QSTATS
2100 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2101 typedef enum efx_tx_qstat_e {
2107 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2109 #endif /* EFSYS_OPT_QSTATS */
2111 extern __checkReturn efx_rc_t
2113 __in efx_nic_t *enp);
2117 __in efx_nic_t *enp);
2119 #define EFX_TXQ_MINNDESCS 512
2121 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2122 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2123 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2125 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2127 #define EFX_TXQ_CKSUM_IPV4 0x0001
2128 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2129 #define EFX_TXQ_FATSOV2 0x0004
2130 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2131 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2133 extern __checkReturn efx_rc_t
2135 __in efx_nic_t *enp,
2136 __in unsigned int index,
2137 __in unsigned int label,
2138 __in efsys_mem_t *esmp,
2141 __in uint16_t flags,
2142 __in efx_evq_t *eep,
2143 __deref_out efx_txq_t **etpp,
2144 __out unsigned int *addedp);
2146 extern __checkReturn efx_rc_t
2148 __in efx_txq_t *etp,
2149 __in_ecount(ndescs) efx_buffer_t *eb,
2150 __in unsigned int ndescs,
2151 __in unsigned int completed,
2152 __inout unsigned int *addedp);
2154 extern __checkReturn efx_rc_t
2156 __in efx_txq_t *etp,
2157 __in unsigned int ns);
2161 __in efx_txq_t *etp,
2162 __in unsigned int added,
2163 __in unsigned int pushed);
2165 extern __checkReturn efx_rc_t
2167 __in efx_txq_t *etp);
2171 __in efx_txq_t *etp);
2173 extern __checkReturn efx_rc_t
2175 __in efx_txq_t *etp);
2178 efx_tx_qpio_disable(
2179 __in efx_txq_t *etp);
2181 extern __checkReturn efx_rc_t
2183 __in efx_txq_t *etp,
2184 __in_ecount(buf_length) uint8_t *buffer,
2185 __in size_t buf_length,
2186 __in size_t pio_buf_offset);
2188 extern __checkReturn efx_rc_t
2190 __in efx_txq_t *etp,
2191 __in size_t pkt_length,
2192 __in unsigned int completed,
2193 __inout unsigned int *addedp);
2195 extern __checkReturn efx_rc_t
2197 __in efx_txq_t *etp,
2198 __in_ecount(n) efx_desc_t *ed,
2199 __in unsigned int n,
2200 __in unsigned int completed,
2201 __inout unsigned int *addedp);
2204 efx_tx_qdesc_dma_create(
2205 __in efx_txq_t *etp,
2206 __in efsys_dma_addr_t addr,
2209 __out efx_desc_t *edp);
2212 efx_tx_qdesc_tso_create(
2213 __in efx_txq_t *etp,
2214 __in uint16_t ipv4_id,
2215 __in uint32_t tcp_seq,
2216 __in uint8_t tcp_flags,
2217 __out efx_desc_t *edp);
2219 /* Number of FATSOv2 option descriptors */
2220 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2222 /* Maximum number of DMA segments per TSO packet (not superframe) */
2223 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2226 efx_tx_qdesc_tso2_create(
2227 __in efx_txq_t *etp,
2228 __in uint16_t ipv4_id,
2229 __in uint32_t tcp_seq,
2230 __in uint16_t tcp_mss,
2231 __out_ecount(count) efx_desc_t *edp,
2235 efx_tx_qdesc_vlantci_create(
2236 __in efx_txq_t *etp,
2238 __out efx_desc_t *edp);
2240 #if EFSYS_OPT_QSTATS
2246 __in efx_nic_t *etp,
2247 __in unsigned int id);
2249 #endif /* EFSYS_OPT_NAMES */
2252 efx_tx_qstats_update(
2253 __in efx_txq_t *etp,
2254 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2256 #endif /* EFSYS_OPT_QSTATS */
2260 __in efx_txq_t *etp);
2265 #if EFSYS_OPT_FILTER
2267 #define EFX_ETHER_TYPE_IPV4 0x0800
2268 #define EFX_ETHER_TYPE_IPV6 0x86DD
2270 #define EFX_IPPROTO_TCP 6
2271 #define EFX_IPPROTO_UDP 17
2272 #define EFX_IPPROTO_GRE 47
2274 /* Use RSS to spread across multiple queues */
2275 #define EFX_FILTER_FLAG_RX_RSS 0x01
2276 /* Enable RX scatter */
2277 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2279 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2280 * May only be set by the filter implementation for each type.
2281 * A removal request will restore the automatic filter in its place.
2283 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2284 /* Filter is for RX */
2285 #define EFX_FILTER_FLAG_RX 0x08
2286 /* Filter is for TX */
2287 #define EFX_FILTER_FLAG_TX 0x10
2289 typedef uint8_t efx_filter_flags_t;
2292 * Flags which specify the fields to match on. The values are the same as in the
2293 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2296 /* Match by remote IP host address */
2297 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2298 /* Match by local IP host address */
2299 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2300 /* Match by remote MAC address */
2301 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2302 /* Match by remote TCP/UDP port */
2303 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2304 /* Match by remote TCP/UDP port */
2305 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2306 /* Match by local TCP/UDP port */
2307 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2308 /* Match by Ether-type */
2309 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2310 /* Match by inner VLAN ID */
2311 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2312 /* Match by outer VLAN ID */
2313 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2314 /* Match by IP transport protocol */
2315 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2316 /* For encapsulated packets, match all multicast inner frames */
2317 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2318 /* For encapsulated packets, match all unicast inner frames */
2319 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2320 /* Match otherwise-unmatched multicast and broadcast packets */
2321 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2322 /* Match otherwise-unmatched unicast packets */
2323 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2325 typedef uint32_t efx_filter_match_flags_t;
2327 typedef enum efx_filter_priority_s {
2328 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2329 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2330 * address list or hardware
2331 * requirements. This may only be used
2332 * by the filter implementation for
2334 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2335 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2336 * client (e.g. SR-IOV, HyperV VMQ etc.)
2338 } efx_filter_priority_t;
2341 * FIXME: All these fields are assumed to be in little-endian byte order.
2342 * It may be better for some to be big-endian. See bug42804.
2345 typedef struct efx_filter_spec_s {
2346 efx_filter_match_flags_t efs_match_flags;
2347 uint8_t efs_priority;
2348 efx_filter_flags_t efs_flags;
2349 uint16_t efs_dmaq_id;
2350 uint32_t efs_rss_context;
2351 uint16_t efs_outer_vid;
2352 uint16_t efs_inner_vid;
2353 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2354 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2355 uint16_t efs_ether_type;
2356 uint8_t efs_ip_proto;
2357 efx_tunnel_protocol_t efs_encap_type;
2358 uint16_t efs_loc_port;
2359 uint16_t efs_rem_port;
2360 efx_oword_t efs_rem_host;
2361 efx_oword_t efs_loc_host;
2362 } efx_filter_spec_t;
2365 /* Default values for use in filter specifications */
2366 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2367 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2369 extern __checkReturn efx_rc_t
2371 __in efx_nic_t *enp);
2375 __in efx_nic_t *enp);
2377 extern __checkReturn efx_rc_t
2379 __in efx_nic_t *enp,
2380 __inout efx_filter_spec_t *spec);
2382 extern __checkReturn efx_rc_t
2384 __in efx_nic_t *enp,
2385 __inout efx_filter_spec_t *spec);
2387 extern __checkReturn efx_rc_t
2389 __in efx_nic_t *enp);
2391 extern __checkReturn efx_rc_t
2392 efx_filter_supported_filters(
2393 __in efx_nic_t *enp,
2394 __out_ecount(buffer_length) uint32_t *buffer,
2395 __in size_t buffer_length,
2396 __out size_t *list_lengthp);
2399 efx_filter_spec_init_rx(
2400 __out efx_filter_spec_t *spec,
2401 __in efx_filter_priority_t priority,
2402 __in efx_filter_flags_t flags,
2403 __in efx_rxq_t *erp);
2406 efx_filter_spec_init_tx(
2407 __out efx_filter_spec_t *spec,
2408 __in efx_txq_t *etp);
2410 extern __checkReturn efx_rc_t
2411 efx_filter_spec_set_ipv4_local(
2412 __inout efx_filter_spec_t *spec,
2415 __in uint16_t port);
2417 extern __checkReturn efx_rc_t
2418 efx_filter_spec_set_ipv4_full(
2419 __inout efx_filter_spec_t *spec,
2421 __in uint32_t lhost,
2422 __in uint16_t lport,
2423 __in uint32_t rhost,
2424 __in uint16_t rport);
2426 extern __checkReturn efx_rc_t
2427 efx_filter_spec_set_eth_local(
2428 __inout efx_filter_spec_t *spec,
2430 __in const uint8_t *addr);
2433 efx_filter_spec_set_ether_type(
2434 __inout efx_filter_spec_t *spec,
2435 __in uint16_t ether_type);
2437 extern __checkReturn efx_rc_t
2438 efx_filter_spec_set_uc_def(
2439 __inout efx_filter_spec_t *spec);
2441 extern __checkReturn efx_rc_t
2442 efx_filter_spec_set_mc_def(
2443 __inout efx_filter_spec_t *spec);
2445 typedef enum efx_filter_inner_frame_match_e {
2446 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2447 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2448 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2449 } efx_filter_inner_frame_match_t;
2451 extern __checkReturn efx_rc_t
2452 efx_filter_spec_set_encap_type(
2453 __inout efx_filter_spec_t *spec,
2454 __in efx_tunnel_protocol_t encap_type,
2455 __in efx_filter_inner_frame_match_t inner_frame_match);
2457 #if EFSYS_OPT_RX_SCALE
2458 extern __checkReturn efx_rc_t
2459 efx_filter_spec_set_rss_context(
2460 __inout efx_filter_spec_t *spec,
2461 __in uint32_t rss_context);
2463 #endif /* EFSYS_OPT_FILTER */
2467 extern __checkReturn uint32_t
2469 __in_ecount(count) uint32_t const *input,
2471 __in uint32_t init);
2473 extern __checkReturn uint32_t
2475 __in_ecount(length) uint8_t const *input,
2477 __in uint32_t init);
2479 #if EFSYS_OPT_LICENSING
2483 typedef struct efx_key_stats_s {
2485 uint32_t eks_invalid;
2486 uint32_t eks_blacklisted;
2487 uint32_t eks_unverifiable;
2488 uint32_t eks_wrong_node;
2489 uint32_t eks_licensed_apps_lo;
2490 uint32_t eks_licensed_apps_hi;
2491 uint32_t eks_licensed_features_lo;
2492 uint32_t eks_licensed_features_hi;
2495 extern __checkReturn efx_rc_t
2497 __in efx_nic_t *enp);
2501 __in efx_nic_t *enp);
2503 extern __checkReturn boolean_t
2504 efx_lic_check_support(
2505 __in efx_nic_t *enp);
2507 extern __checkReturn efx_rc_t
2508 efx_lic_update_licenses(
2509 __in efx_nic_t *enp);
2511 extern __checkReturn efx_rc_t
2512 efx_lic_get_key_stats(
2513 __in efx_nic_t *enp,
2514 __out efx_key_stats_t *ksp);
2516 extern __checkReturn efx_rc_t
2518 __in efx_nic_t *enp,
2519 __in uint64_t app_id,
2520 __out boolean_t *licensedp);
2522 extern __checkReturn efx_rc_t
2524 __in efx_nic_t *enp,
2525 __in size_t buffer_size,
2526 __out uint32_t *typep,
2527 __out size_t *lengthp,
2528 __out_opt uint8_t *bufferp);
2531 extern __checkReturn efx_rc_t
2533 __in efx_nic_t *enp,
2534 __in_bcount(buffer_size)
2536 __in size_t buffer_size,
2537 __out uint32_t *startp);
2539 extern __checkReturn efx_rc_t
2541 __in efx_nic_t *enp,
2542 __in_bcount(buffer_size)
2544 __in size_t buffer_size,
2545 __in uint32_t offset,
2546 __out uint32_t *endp);
2548 extern __checkReturn __success(return != B_FALSE) boolean_t
2550 __in efx_nic_t *enp,
2551 __in_bcount(buffer_size)
2553 __in size_t buffer_size,
2554 __in uint32_t offset,
2555 __out uint32_t *startp,
2556 __out uint32_t *lengthp);
2558 extern __checkReturn __success(return != B_FALSE) boolean_t
2559 efx_lic_validate_key(
2560 __in efx_nic_t *enp,
2561 __in_bcount(length) caddr_t keyp,
2562 __in uint32_t length);
2564 extern __checkReturn efx_rc_t
2566 __in efx_nic_t *enp,
2567 __in_bcount(buffer_size)
2569 __in size_t buffer_size,
2570 __in uint32_t offset,
2571 __in uint32_t length,
2572 __out_bcount_part(key_max_size, *lengthp)
2574 __in size_t key_max_size,
2575 __out uint32_t *lengthp);
2577 extern __checkReturn efx_rc_t
2579 __in efx_nic_t *enp,
2580 __in_bcount(buffer_size)
2582 __in size_t buffer_size,
2583 __in uint32_t offset,
2584 __in_bcount(length) caddr_t keyp,
2585 __in uint32_t length,
2586 __out uint32_t *lengthp);
2588 __checkReturn efx_rc_t
2590 __in efx_nic_t *enp,
2591 __in_bcount(buffer_size)
2593 __in size_t buffer_size,
2594 __in uint32_t offset,
2595 __in uint32_t length,
2597 __out uint32_t *deltap);
2599 extern __checkReturn efx_rc_t
2600 efx_lic_create_partition(
2601 __in efx_nic_t *enp,
2602 __in_bcount(buffer_size)
2604 __in size_t buffer_size);
2606 extern __checkReturn efx_rc_t
2607 efx_lic_finish_partition(
2608 __in efx_nic_t *enp,
2609 __in_bcount(buffer_size)
2611 __in size_t buffer_size);
2613 #endif /* EFSYS_OPT_LICENSING */
2617 #if EFSYS_OPT_TUNNEL
2619 extern __checkReturn efx_rc_t
2621 __in efx_nic_t *enp);
2625 __in efx_nic_t *enp);
2628 * For overlay network encapsulation using UDP, the firmware needs to know
2629 * the configured UDP port for the overlay so it can decode encapsulated
2631 * The UDP port/protocol list is global.
2634 extern __checkReturn efx_rc_t
2635 efx_tunnel_config_udp_add(
2636 __in efx_nic_t *enp,
2637 __in uint16_t port /* host/cpu-endian */,
2638 __in efx_tunnel_protocol_t protocol);
2640 extern __checkReturn efx_rc_t
2641 efx_tunnel_config_udp_remove(
2642 __in efx_nic_t *enp,
2643 __in uint16_t port /* host/cpu-endian */,
2644 __in efx_tunnel_protocol_t protocol);
2647 efx_tunnel_config_clear(
2648 __in efx_nic_t *enp);
2651 * Apply tunnel UDP ports configuration to hardware.
2653 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2656 extern __checkReturn efx_rc_t
2657 efx_tunnel_reconfigure(
2658 __in efx_nic_t *enp);
2660 #endif /* EFSYS_OPT_TUNNEL */
2667 #endif /* _SYS_EFX_H */