1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_check.h"
13 #include "efx_phy_ids.h"
19 #define EFX_STATIC_ASSERT(_cond) \
20 ((void)sizeof (char[(_cond) ? 1 : -1]))
22 #define EFX_ARRAY_SIZE(_array) \
23 (sizeof (_array) / sizeof ((_array)[0]))
25 #define EFX_FIELD_OFFSET(_type, _field) \
26 ((size_t)&(((_type *)0)->_field))
28 /* The macro expands divider twice */
29 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
33 typedef __success(return == 0) int efx_rc_t;
38 typedef enum efx_family_e {
40 EFX_FAMILY_FALCON, /* Obsolete and not supported */
42 EFX_FAMILY_HUNTINGTON,
48 extern __checkReturn efx_rc_t
52 __out efx_family_t *efp,
53 __out unsigned int *membarp);
56 #define EFX_PCI_VENID_SFC 0x1924
58 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
60 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
61 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
62 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
64 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
65 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
66 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
68 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
69 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
71 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
72 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
73 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
75 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
76 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
77 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
80 #define EFX_MEM_BAR_SIENA 2
82 #define EFX_MEM_BAR_HUNTINGTON_PF 2
83 #define EFX_MEM_BAR_HUNTINGTON_VF 0
85 #define EFX_MEM_BAR_MEDFORD_PF 2
86 #define EFX_MEM_BAR_MEDFORD_VF 0
88 #define EFX_MEM_BAR_MEDFORD2 0
109 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
110 extern __checkReturn uint32_t
112 __in uint32_t crc_init,
113 __in_ecount(length) uint8_t const *input,
117 /* Type prototypes */
119 typedef struct efx_rxq_s efx_rxq_t;
123 typedef struct efx_nic_s efx_nic_t;
125 extern __checkReturn efx_rc_t
127 __in efx_family_t family,
128 __in efsys_identifier_t *esip,
129 __in efsys_bar_t *esbp,
130 __in efsys_lock_t *eslp,
131 __deref_out efx_nic_t **enpp);
133 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
134 typedef enum efx_fw_variant_e {
135 EFX_FW_VARIANT_FULL_FEATURED,
136 EFX_FW_VARIANT_LOW_LATENCY,
137 EFX_FW_VARIANT_PACKED_STREAM,
138 EFX_FW_VARIANT_HIGH_TX_RATE,
139 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
140 EFX_FW_VARIANT_RULES_ENGINE,
142 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
145 extern __checkReturn efx_rc_t
148 __in efx_fw_variant_t efv);
150 extern __checkReturn efx_rc_t
152 __in efx_nic_t *enp);
154 extern __checkReturn efx_rc_t
156 __in efx_nic_t *enp);
160 extern __checkReturn efx_rc_t
161 efx_nic_register_test(
162 __in efx_nic_t *enp);
164 #endif /* EFSYS_OPT_DIAG */
168 __in efx_nic_t *enp);
172 __in efx_nic_t *enp);
176 __in efx_nic_t *enp);
178 #define EFX_PCIE_LINK_SPEED_GEN1 1
179 #define EFX_PCIE_LINK_SPEED_GEN2 2
180 #define EFX_PCIE_LINK_SPEED_GEN3 3
182 typedef enum efx_pcie_link_performance_e {
183 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
184 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
185 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
186 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
187 } efx_pcie_link_performance_t;
189 extern __checkReturn efx_rc_t
190 efx_nic_calculate_pcie_link_bandwidth(
191 __in uint32_t pcie_link_width,
192 __in uint32_t pcie_link_gen,
193 __out uint32_t *bandwidth_mbpsp);
195 extern __checkReturn efx_rc_t
196 efx_nic_check_pcie_link_speed(
198 __in uint32_t pcie_link_width,
199 __in uint32_t pcie_link_gen,
200 __out efx_pcie_link_performance_t *resultp);
204 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
205 /* Huntington and Medford require MCDIv2 commands */
206 #define WITH_MCDI_V2 1
209 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
211 typedef enum efx_mcdi_exception_e {
212 EFX_MCDI_EXCEPTION_MC_REBOOT,
213 EFX_MCDI_EXCEPTION_MC_BADASSERT,
214 } efx_mcdi_exception_t;
216 #if EFSYS_OPT_MCDI_LOGGING
217 typedef enum efx_log_msg_e {
219 EFX_LOG_MCDI_REQUEST,
220 EFX_LOG_MCDI_RESPONSE,
222 #endif /* EFSYS_OPT_MCDI_LOGGING */
224 typedef struct efx_mcdi_transport_s {
226 efsys_mem_t *emt_dma_mem;
227 void (*emt_execute)(void *, efx_mcdi_req_t *);
228 void (*emt_ev_cpl)(void *);
229 void (*emt_exception)(void *, efx_mcdi_exception_t);
230 #if EFSYS_OPT_MCDI_LOGGING
231 void (*emt_logger)(void *, efx_log_msg_t,
232 void *, size_t, void *, size_t);
233 #endif /* EFSYS_OPT_MCDI_LOGGING */
234 #if EFSYS_OPT_MCDI_PROXY_AUTH
235 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
236 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
237 } efx_mcdi_transport_t;
239 extern __checkReturn efx_rc_t
242 __in const efx_mcdi_transport_t *mtp);
244 extern __checkReturn efx_rc_t
246 __in efx_nic_t *enp);
250 __in efx_nic_t *enp);
253 efx_mcdi_get_timeout(
255 __in efx_mcdi_req_t *emrp,
256 __out uint32_t *usec_timeoutp);
259 efx_mcdi_request_start(
261 __in efx_mcdi_req_t *emrp,
262 __in boolean_t ev_cpl);
264 extern __checkReturn boolean_t
265 efx_mcdi_request_poll(
266 __in efx_nic_t *enp);
268 extern __checkReturn boolean_t
269 efx_mcdi_request_abort(
270 __in efx_nic_t *enp);
274 __in efx_nic_t *enp);
276 #endif /* EFSYS_OPT_MCDI */
280 #define EFX_NINTR_SIENA 1024
282 typedef enum efx_intr_type_e {
283 EFX_INTR_INVALID = 0,
289 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
291 extern __checkReturn efx_rc_t
294 __in efx_intr_type_t type,
295 __in efsys_mem_t *esmp);
299 __in efx_nic_t *enp);
303 __in efx_nic_t *enp);
306 efx_intr_disable_unlocked(
307 __in efx_nic_t *enp);
309 #define EFX_INTR_NEVQS 32
311 extern __checkReturn efx_rc_t
314 __in unsigned int level);
317 efx_intr_status_line(
319 __out boolean_t *fatalp,
320 __out uint32_t *maskp);
323 efx_intr_status_message(
325 __in unsigned int message,
326 __out boolean_t *fatalp);
330 __in efx_nic_t *enp);
334 __in efx_nic_t *enp);
338 #if EFSYS_OPT_MAC_STATS
340 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
341 typedef enum efx_mac_stat_e {
344 EFX_MAC_RX_UNICST_PKTS,
345 EFX_MAC_RX_MULTICST_PKTS,
346 EFX_MAC_RX_BRDCST_PKTS,
347 EFX_MAC_RX_PAUSE_PKTS,
348 EFX_MAC_RX_LE_64_PKTS,
349 EFX_MAC_RX_65_TO_127_PKTS,
350 EFX_MAC_RX_128_TO_255_PKTS,
351 EFX_MAC_RX_256_TO_511_PKTS,
352 EFX_MAC_RX_512_TO_1023_PKTS,
353 EFX_MAC_RX_1024_TO_15XX_PKTS,
354 EFX_MAC_RX_GE_15XX_PKTS,
356 EFX_MAC_RX_FCS_ERRORS,
357 EFX_MAC_RX_DROP_EVENTS,
358 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
359 EFX_MAC_RX_SYMBOL_ERRORS,
360 EFX_MAC_RX_ALIGN_ERRORS,
361 EFX_MAC_RX_INTERNAL_ERRORS,
362 EFX_MAC_RX_JABBER_PKTS,
363 EFX_MAC_RX_LANE0_CHAR_ERR,
364 EFX_MAC_RX_LANE1_CHAR_ERR,
365 EFX_MAC_RX_LANE2_CHAR_ERR,
366 EFX_MAC_RX_LANE3_CHAR_ERR,
367 EFX_MAC_RX_LANE0_DISP_ERR,
368 EFX_MAC_RX_LANE1_DISP_ERR,
369 EFX_MAC_RX_LANE2_DISP_ERR,
370 EFX_MAC_RX_LANE3_DISP_ERR,
371 EFX_MAC_RX_MATCH_FAULT,
372 EFX_MAC_RX_NODESC_DROP_CNT,
375 EFX_MAC_TX_UNICST_PKTS,
376 EFX_MAC_TX_MULTICST_PKTS,
377 EFX_MAC_TX_BRDCST_PKTS,
378 EFX_MAC_TX_PAUSE_PKTS,
379 EFX_MAC_TX_LE_64_PKTS,
380 EFX_MAC_TX_65_TO_127_PKTS,
381 EFX_MAC_TX_128_TO_255_PKTS,
382 EFX_MAC_TX_256_TO_511_PKTS,
383 EFX_MAC_TX_512_TO_1023_PKTS,
384 EFX_MAC_TX_1024_TO_15XX_PKTS,
385 EFX_MAC_TX_GE_15XX_PKTS,
387 EFX_MAC_TX_SGL_COL_PKTS,
388 EFX_MAC_TX_MULT_COL_PKTS,
389 EFX_MAC_TX_EX_COL_PKTS,
390 EFX_MAC_TX_LATE_COL_PKTS,
392 EFX_MAC_TX_EX_DEF_PKTS,
393 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
394 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
395 EFX_MAC_PM_TRUNC_VFIFO_FULL,
396 EFX_MAC_PM_DISCARD_VFIFO_FULL,
397 EFX_MAC_PM_TRUNC_QBB,
398 EFX_MAC_PM_DISCARD_QBB,
399 EFX_MAC_PM_DISCARD_MAPPING,
400 EFX_MAC_RXDP_Q_DISABLED_PKTS,
401 EFX_MAC_RXDP_DI_DROPPED_PKTS,
402 EFX_MAC_RXDP_STREAMING_PKTS,
403 EFX_MAC_RXDP_HLB_FETCH,
404 EFX_MAC_RXDP_HLB_WAIT,
405 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
406 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
407 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
408 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
409 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
410 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
411 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
412 EFX_MAC_VADAPTER_RX_BAD_BYTES,
413 EFX_MAC_VADAPTER_RX_OVERFLOW,
414 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
415 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
416 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
417 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
418 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
419 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
420 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
421 EFX_MAC_VADAPTER_TX_BAD_BYTES,
422 EFX_MAC_VADAPTER_TX_OVERFLOW,
423 EFX_MAC_FEC_UNCORRECTED_ERRORS,
424 EFX_MAC_FEC_CORRECTED_ERRORS,
425 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
426 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
427 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
428 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
429 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
430 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
431 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
432 EFX_MAC_CTPIO_OVERFLOW_FAIL,
433 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
434 EFX_MAC_CTPIO_TIMEOUT_FAIL,
435 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
436 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
437 EFX_MAC_CTPIO_INVALID_WR_FAIL,
438 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
439 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
440 EFX_MAC_CTPIO_RUNT_FALLBACK,
441 EFX_MAC_CTPIO_SUCCESS,
442 EFX_MAC_CTPIO_FALLBACK,
443 EFX_MAC_CTPIO_POISON,
445 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
446 EFX_MAC_RXDP_HLB_IDLE,
447 EFX_MAC_RXDP_HLB_TIMEOUT,
451 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
453 #endif /* EFSYS_OPT_MAC_STATS */
455 typedef enum efx_link_mode_e {
456 EFX_LINK_UNKNOWN = 0,
472 #define EFX_MAC_ADDR_LEN 6
474 #define EFX_VNI_OR_VSID_LEN 3
476 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
478 #define EFX_MAC_MULTICAST_LIST_MAX 256
480 #define EFX_MAC_SDU_MAX 9202
482 #define EFX_MAC_PDU_ADJUSTMENT \
486 + /* bug16011 */ 16) \
488 #define EFX_MAC_PDU(_sdu) \
489 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
492 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
493 * the SDU rounded up slightly.
495 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
497 #define EFX_MAC_PDU_MIN 60
498 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
500 extern __checkReturn efx_rc_t
505 extern __checkReturn efx_rc_t
510 extern __checkReturn efx_rc_t
515 extern __checkReturn efx_rc_t
518 __in boolean_t all_unicst,
519 __in boolean_t mulcst,
520 __in boolean_t all_mulcst,
521 __in boolean_t brdcst);
523 extern __checkReturn efx_rc_t
524 efx_mac_multicast_list_set(
526 __in_ecount(6*count) uint8_t const *addrs,
529 extern __checkReturn efx_rc_t
530 efx_mac_filter_default_rxq_set(
533 __in boolean_t using_rss);
536 efx_mac_filter_default_rxq_clear(
537 __in efx_nic_t *enp);
539 extern __checkReturn efx_rc_t
542 __in boolean_t enabled);
544 extern __checkReturn efx_rc_t
547 __out boolean_t *mac_upp);
549 #define EFX_FCNTL_RESPOND 0x00000001
550 #define EFX_FCNTL_GENERATE 0x00000002
552 extern __checkReturn efx_rc_t
555 __in unsigned int fcntl,
556 __in boolean_t autoneg);
561 __out unsigned int *fcntl_wantedp,
562 __out unsigned int *fcntl_linkp);
565 #if EFSYS_OPT_MAC_STATS
569 extern __checkReturn const char *
572 __in unsigned int id);
574 #endif /* EFSYS_OPT_NAMES */
576 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
578 #define EFX_MAC_STATS_MASK_NPAGES \
579 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
580 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
583 * Get mask of MAC statistics supported by the hardware.
585 * If mask_size is insufficient to return the mask, EINVAL error is
586 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
587 * (which is sizeof (uint32_t)) is sufficient.
589 extern __checkReturn efx_rc_t
590 efx_mac_stats_get_mask(
592 __out_bcount(mask_size) uint32_t *maskp,
593 __in size_t mask_size);
595 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
596 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
597 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
600 extern __checkReturn efx_rc_t
602 __in efx_nic_t *enp);
605 * Upload mac statistics supported by the hardware into the given buffer.
607 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
608 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
610 * The hardware will only DMA statistics that it understands (of course).
611 * Drivers should not make any assumptions about which statistics are
612 * supported, especially when the statistics are generated by firmware.
614 * Thus, drivers should zero this buffer before use, so that not-understood
615 * statistics read back as zero.
617 extern __checkReturn efx_rc_t
618 efx_mac_stats_upload(
620 __in efsys_mem_t *esmp);
622 extern __checkReturn efx_rc_t
623 efx_mac_stats_periodic(
625 __in efsys_mem_t *esmp,
626 __in uint16_t period_ms,
627 __in boolean_t events);
629 extern __checkReturn efx_rc_t
630 efx_mac_stats_update(
632 __in efsys_mem_t *esmp,
633 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
634 __inout_opt uint32_t *generationp);
636 #endif /* EFSYS_OPT_MAC_STATS */
640 typedef enum efx_mon_type_e {
652 __in efx_nic_t *enp);
654 #endif /* EFSYS_OPT_NAMES */
656 extern __checkReturn efx_rc_t
658 __in efx_nic_t *enp);
660 #if EFSYS_OPT_MON_STATS
662 #define EFX_MON_STATS_PAGE_SIZE 0x100
663 #define EFX_MON_MASK_ELEMENT_SIZE 32
665 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
666 typedef enum efx_mon_stat_e {
667 EFX_MON_STAT_CONTROLLER_TEMP,
668 EFX_MON_STAT_PHY_COMMON_TEMP,
669 EFX_MON_STAT_CONTROLLER_COOLING,
670 EFX_MON_STAT_PHY0_TEMP,
671 EFX_MON_STAT_PHY0_COOLING,
672 EFX_MON_STAT_PHY1_TEMP,
673 EFX_MON_STAT_PHY1_COOLING,
679 EFX_MON_STAT_IN_12V0,
680 EFX_MON_STAT_IN_1V2A,
681 EFX_MON_STAT_IN_VREF,
682 EFX_MON_STAT_OUT_VAOE,
683 EFX_MON_STAT_AOE_TEMP,
684 EFX_MON_STAT_PSU_AOE_TEMP,
685 EFX_MON_STAT_PSU_TEMP,
691 EFX_MON_STAT_IN_VAOE,
692 EFX_MON_STAT_OUT_IAOE,
693 EFX_MON_STAT_IN_IAOE,
694 EFX_MON_STAT_NIC_POWER,
696 EFX_MON_STAT_IN_I0V9,
697 EFX_MON_STAT_IN_I1V2,
698 EFX_MON_STAT_IN_0V9_ADC,
699 EFX_MON_STAT_CONTROLLER_2_TEMP,
700 EFX_MON_STAT_VREG_INTERNAL_TEMP,
701 EFX_MON_STAT_VREG_0V9_TEMP,
702 EFX_MON_STAT_VREG_1V2_TEMP,
703 EFX_MON_STAT_CONTROLLER_VPTAT,
704 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
705 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
706 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
707 EFX_MON_STAT_AMBIENT_TEMP,
708 EFX_MON_STAT_AIRFLOW,
709 EFX_MON_STAT_VDD08D_VSS08D_CSR,
710 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
711 EFX_MON_STAT_HOTPOINT_TEMP,
712 EFX_MON_STAT_PHY_POWER_PORT0,
713 EFX_MON_STAT_PHY_POWER_PORT1,
714 EFX_MON_STAT_MUM_VCC,
715 EFX_MON_STAT_IN_0V9_A,
716 EFX_MON_STAT_IN_I0V9_A,
717 EFX_MON_STAT_VREG_0V9_A_TEMP,
718 EFX_MON_STAT_IN_0V9_B,
719 EFX_MON_STAT_IN_I0V9_B,
720 EFX_MON_STAT_VREG_0V9_B_TEMP,
721 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
722 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
723 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
724 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
725 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
726 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
727 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
728 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
729 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
730 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
731 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
732 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
733 EFX_MON_STAT_SODIMM_VOUT,
734 EFX_MON_STAT_SODIMM_0_TEMP,
735 EFX_MON_STAT_SODIMM_1_TEMP,
736 EFX_MON_STAT_PHY0_VCC,
737 EFX_MON_STAT_PHY1_VCC,
738 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
739 EFX_MON_STAT_BOARD_FRONT_TEMP,
740 EFX_MON_STAT_BOARD_BACK_TEMP,
741 EFX_MON_STAT_IN_I1V8,
742 EFX_MON_STAT_IN_I2V5,
743 EFX_MON_STAT_IN_I3V3,
744 EFX_MON_STAT_IN_I12V0,
746 EFX_MON_STAT_IN_I1V3,
750 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
752 typedef enum efx_mon_stat_state_e {
753 EFX_MON_STAT_STATE_OK = 0,
754 EFX_MON_STAT_STATE_WARNING = 1,
755 EFX_MON_STAT_STATE_FATAL = 2,
756 EFX_MON_STAT_STATE_BROKEN = 3,
757 EFX_MON_STAT_STATE_NO_READING = 4,
758 } efx_mon_stat_state_t;
760 typedef enum efx_mon_stat_unit_e {
761 EFX_MON_STAT_UNIT_UNKNOWN = 0,
762 EFX_MON_STAT_UNIT_BOOL,
763 EFX_MON_STAT_UNIT_TEMP_C,
764 EFX_MON_STAT_UNIT_VOLTAGE_MV,
765 EFX_MON_STAT_UNIT_CURRENT_MA,
766 EFX_MON_STAT_UNIT_POWER_W,
767 EFX_MON_STAT_UNIT_RPM,
769 } efx_mon_stat_unit_t;
771 typedef struct efx_mon_stat_value_s {
773 efx_mon_stat_state_t emsv_state;
774 efx_mon_stat_unit_t emsv_unit;
775 } efx_mon_stat_value_t;
777 typedef enum efx_mon_stat_portmask_e {
778 EFX_MON_STAT_PORTMAP_NONE = 0,
779 EFX_MON_STAT_PORTMAP_PORT0 = 1,
780 EFX_MON_STAT_PORTMAP_PORT1 = 2,
781 EFX_MON_STAT_PORTMAP_PORT2 = 3,
782 EFX_MON_STAT_PORTMAP_PORT3 = 4,
783 EFX_MON_STAT_PORTMAP_ALL = (-1),
784 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
785 } efx_mon_stat_portmask_t;
792 __in efx_mon_stat_t id);
794 #endif /* EFSYS_OPT_NAMES */
796 extern __checkReturn boolean_t
797 efx_mon_mcdi_to_efx_stat(
799 __out efx_mon_stat_t *statp);
801 extern __checkReturn boolean_t
802 efx_mon_get_stat_unit(
803 __in efx_mon_stat_t stat,
804 __out efx_mon_stat_unit_t *unitp);
806 extern __checkReturn boolean_t
807 efx_mon_get_stat_portmap(
808 __in efx_mon_stat_t stat,
809 __out efx_mon_stat_portmask_t *maskp);
811 extern __checkReturn efx_rc_t
812 efx_mon_stats_update(
814 __in efsys_mem_t *esmp,
815 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
817 #endif /* EFSYS_OPT_MON_STATS */
821 __in efx_nic_t *enp);
825 extern __checkReturn efx_rc_t
827 __in efx_nic_t *enp);
829 #if EFSYS_OPT_PHY_LED_CONTROL
831 typedef enum efx_phy_led_mode_e {
832 EFX_PHY_LED_DEFAULT = 0,
837 } efx_phy_led_mode_t;
839 extern __checkReturn efx_rc_t
842 __in efx_phy_led_mode_t mode);
844 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
846 extern __checkReturn efx_rc_t
848 __in efx_nic_t *enp);
850 #if EFSYS_OPT_LOOPBACK
852 typedef enum efx_loopback_type_e {
853 EFX_LOOPBACK_OFF = 0,
854 EFX_LOOPBACK_DATA = 1,
855 EFX_LOOPBACK_GMAC = 2,
856 EFX_LOOPBACK_XGMII = 3,
857 EFX_LOOPBACK_XGXS = 4,
858 EFX_LOOPBACK_XAUI = 5,
859 EFX_LOOPBACK_GMII = 6,
860 EFX_LOOPBACK_SGMII = 7,
861 EFX_LOOPBACK_XGBR = 8,
862 EFX_LOOPBACK_XFI = 9,
863 EFX_LOOPBACK_XAUI_FAR = 10,
864 EFX_LOOPBACK_GMII_FAR = 11,
865 EFX_LOOPBACK_SGMII_FAR = 12,
866 EFX_LOOPBACK_XFI_FAR = 13,
867 EFX_LOOPBACK_GPHY = 14,
868 EFX_LOOPBACK_PHY_XS = 15,
869 EFX_LOOPBACK_PCS = 16,
870 EFX_LOOPBACK_PMA_PMD = 17,
871 EFX_LOOPBACK_XPORT = 18,
872 EFX_LOOPBACK_XGMII_WS = 19,
873 EFX_LOOPBACK_XAUI_WS = 20,
874 EFX_LOOPBACK_XAUI_WS_FAR = 21,
875 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
876 EFX_LOOPBACK_GMII_WS = 23,
877 EFX_LOOPBACK_XFI_WS = 24,
878 EFX_LOOPBACK_XFI_WS_FAR = 25,
879 EFX_LOOPBACK_PHYXS_WS = 26,
880 EFX_LOOPBACK_PMA_INT = 27,
881 EFX_LOOPBACK_SD_NEAR = 28,
882 EFX_LOOPBACK_SD_FAR = 29,
883 EFX_LOOPBACK_PMA_INT_WS = 30,
884 EFX_LOOPBACK_SD_FEP2_WS = 31,
885 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
886 EFX_LOOPBACK_SD_FEP_WS = 33,
887 EFX_LOOPBACK_SD_FES_WS = 34,
888 EFX_LOOPBACK_AOE_INT_NEAR = 35,
889 EFX_LOOPBACK_DATA_WS = 36,
890 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
892 } efx_loopback_type_t;
894 typedef enum efx_loopback_kind_e {
895 EFX_LOOPBACK_KIND_OFF = 0,
896 EFX_LOOPBACK_KIND_ALL,
897 EFX_LOOPBACK_KIND_MAC,
898 EFX_LOOPBACK_KIND_PHY,
900 } efx_loopback_kind_t;
904 __in efx_loopback_kind_t loopback_kind,
905 __out efx_qword_t *maskp);
907 extern __checkReturn efx_rc_t
908 efx_port_loopback_set(
910 __in efx_link_mode_t link_mode,
911 __in efx_loopback_type_t type);
915 extern __checkReturn const char *
916 efx_loopback_type_name(
918 __in efx_loopback_type_t type);
920 #endif /* EFSYS_OPT_NAMES */
922 #endif /* EFSYS_OPT_LOOPBACK */
924 extern __checkReturn efx_rc_t
927 __out_opt efx_link_mode_t *link_modep);
931 __in efx_nic_t *enp);
933 typedef enum efx_phy_cap_type_e {
934 EFX_PHY_CAP_INVALID = 0,
941 EFX_PHY_CAP_10000FDX,
945 EFX_PHY_CAP_40000FDX,
947 EFX_PHY_CAP_100000FDX,
948 EFX_PHY_CAP_25000FDX,
949 EFX_PHY_CAP_50000FDX,
950 EFX_PHY_CAP_BASER_FEC,
951 EFX_PHY_CAP_BASER_FEC_REQUESTED,
953 EFX_PHY_CAP_RS_FEC_REQUESTED,
954 EFX_PHY_CAP_25G_BASER_FEC,
955 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
957 } efx_phy_cap_type_t;
960 #define EFX_PHY_CAP_CURRENT 0x00000000
961 #define EFX_PHY_CAP_DEFAULT 0x00000001
962 #define EFX_PHY_CAP_PERM 0x00000002
968 __out uint32_t *maskp);
970 extern __checkReturn efx_rc_t
978 __out uint32_t *maskp);
980 extern __checkReturn efx_rc_t
983 __out uint32_t *ouip);
985 typedef enum efx_phy_media_type_e {
986 EFX_PHY_MEDIA_INVALID = 0,
991 EFX_PHY_MEDIA_SFP_PLUS,
992 EFX_PHY_MEDIA_BASE_T,
993 EFX_PHY_MEDIA_QSFP_PLUS,
995 } efx_phy_media_type_t;
998 * Get the type of medium currently used. If the board has ports for
999 * modules, a module is present, and we recognise the media type of
1000 * the module, then this will be the media type of the module.
1001 * Otherwise it will be the media type of the port.
1004 efx_phy_media_type_get(
1005 __in efx_nic_t *enp,
1006 __out efx_phy_media_type_t *typep);
1008 extern __checkReturn efx_rc_t
1009 efx_phy_module_get_info(
1010 __in efx_nic_t *enp,
1011 __in uint8_t dev_addr,
1012 __in uint8_t offset,
1014 __out_bcount(len) uint8_t *data);
1016 #if EFSYS_OPT_PHY_STATS
1018 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1019 typedef enum efx_phy_stat_e {
1021 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1022 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1023 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1024 EFX_PHY_STAT_PMA_PMD_REV_A,
1025 EFX_PHY_STAT_PMA_PMD_REV_B,
1026 EFX_PHY_STAT_PMA_PMD_REV_C,
1027 EFX_PHY_STAT_PMA_PMD_REV_D,
1028 EFX_PHY_STAT_PCS_LINK_UP,
1029 EFX_PHY_STAT_PCS_RX_FAULT,
1030 EFX_PHY_STAT_PCS_TX_FAULT,
1031 EFX_PHY_STAT_PCS_BER,
1032 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1033 EFX_PHY_STAT_PHY_XS_LINK_UP,
1034 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1035 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1036 EFX_PHY_STAT_PHY_XS_ALIGN,
1037 EFX_PHY_STAT_PHY_XS_SYNC_A,
1038 EFX_PHY_STAT_PHY_XS_SYNC_B,
1039 EFX_PHY_STAT_PHY_XS_SYNC_C,
1040 EFX_PHY_STAT_PHY_XS_SYNC_D,
1041 EFX_PHY_STAT_AN_LINK_UP,
1042 EFX_PHY_STAT_AN_MASTER,
1043 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1044 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1045 EFX_PHY_STAT_CL22EXT_LINK_UP,
1050 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1051 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1052 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1053 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1054 EFX_PHY_STAT_AN_COMPLETE,
1055 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1056 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1057 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1058 EFX_PHY_STAT_PCS_FW_VERSION_0,
1059 EFX_PHY_STAT_PCS_FW_VERSION_1,
1060 EFX_PHY_STAT_PCS_FW_VERSION_2,
1061 EFX_PHY_STAT_PCS_FW_VERSION_3,
1062 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1063 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1064 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1065 EFX_PHY_STAT_PCS_OP_MODE,
1069 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1075 __in efx_nic_t *enp,
1076 __in efx_phy_stat_t stat);
1078 #endif /* EFSYS_OPT_NAMES */
1080 #define EFX_PHY_STATS_SIZE 0x100
1082 extern __checkReturn efx_rc_t
1083 efx_phy_stats_update(
1084 __in efx_nic_t *enp,
1085 __in efsys_mem_t *esmp,
1086 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1088 #endif /* EFSYS_OPT_PHY_STATS */
1093 typedef enum efx_bist_type_e {
1094 EFX_BIST_TYPE_UNKNOWN,
1095 EFX_BIST_TYPE_PHY_NORMAL,
1096 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1097 EFX_BIST_TYPE_PHY_CABLE_LONG,
1098 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1099 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1100 EFX_BIST_TYPE_REG, /* Test the register memories */
1101 EFX_BIST_TYPE_NTYPES,
1104 typedef enum efx_bist_result_e {
1105 EFX_BIST_RESULT_UNKNOWN,
1106 EFX_BIST_RESULT_RUNNING,
1107 EFX_BIST_RESULT_PASSED,
1108 EFX_BIST_RESULT_FAILED,
1109 } efx_bist_result_t;
1111 typedef enum efx_phy_cable_status_e {
1112 EFX_PHY_CABLE_STATUS_OK,
1113 EFX_PHY_CABLE_STATUS_INVALID,
1114 EFX_PHY_CABLE_STATUS_OPEN,
1115 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1116 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1117 EFX_PHY_CABLE_STATUS_BUSY,
1118 } efx_phy_cable_status_t;
1120 typedef enum efx_bist_value_e {
1121 EFX_BIST_PHY_CABLE_LENGTH_A,
1122 EFX_BIST_PHY_CABLE_LENGTH_B,
1123 EFX_BIST_PHY_CABLE_LENGTH_C,
1124 EFX_BIST_PHY_CABLE_LENGTH_D,
1125 EFX_BIST_PHY_CABLE_STATUS_A,
1126 EFX_BIST_PHY_CABLE_STATUS_B,
1127 EFX_BIST_PHY_CABLE_STATUS_C,
1128 EFX_BIST_PHY_CABLE_STATUS_D,
1129 EFX_BIST_FAULT_CODE,
1131 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1137 EFX_BIST_MEM_EXPECT,
1138 EFX_BIST_MEM_ACTUAL,
1140 EFX_BIST_MEM_ECC_PARITY,
1141 EFX_BIST_MEM_ECC_FATAL,
1145 extern __checkReturn efx_rc_t
1146 efx_bist_enable_offline(
1147 __in efx_nic_t *enp);
1149 extern __checkReturn efx_rc_t
1151 __in efx_nic_t *enp,
1152 __in efx_bist_type_t type);
1154 extern __checkReturn efx_rc_t
1156 __in efx_nic_t *enp,
1157 __in efx_bist_type_t type,
1158 __out efx_bist_result_t *resultp,
1159 __out_opt uint32_t *value_maskp,
1160 __out_ecount_opt(count) unsigned long *valuesp,
1165 __in efx_nic_t *enp,
1166 __in efx_bist_type_t type);
1168 #endif /* EFSYS_OPT_BIST */
1170 #define EFX_FEATURE_IPV6 0x00000001
1171 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1172 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1173 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1174 #define EFX_FEATURE_MCDI 0x00000020
1175 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1176 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1177 #define EFX_FEATURE_TURBO 0x00000100
1178 #define EFX_FEATURE_MCDI_DMA 0x00000200
1179 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1180 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1181 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1182 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1183 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1185 typedef enum efx_tunnel_protocol_e {
1186 EFX_TUNNEL_PROTOCOL_NONE = 0,
1187 EFX_TUNNEL_PROTOCOL_VXLAN,
1188 EFX_TUNNEL_PROTOCOL_GENEVE,
1189 EFX_TUNNEL_PROTOCOL_NVGRE,
1191 } efx_tunnel_protocol_t;
1193 typedef enum efx_vi_window_shift_e {
1194 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1195 EFX_VI_WINDOW_SHIFT_8K = 13,
1196 EFX_VI_WINDOW_SHIFT_16K = 14,
1197 EFX_VI_WINDOW_SHIFT_64K = 16,
1198 } efx_vi_window_shift_t;
1200 typedef struct efx_nic_cfg_s {
1201 uint32_t enc_board_type;
1202 uint32_t enc_phy_type;
1204 char enc_phy_name[21];
1206 char enc_phy_revision[21];
1207 efx_mon_type_t enc_mon_type;
1208 #if EFSYS_OPT_MON_STATS
1209 uint32_t enc_mon_stat_dma_buf_size;
1210 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1212 unsigned int enc_features;
1213 efx_vi_window_shift_t enc_vi_window_shift;
1214 uint8_t enc_mac_addr[6];
1215 uint8_t enc_port; /* PHY port number */
1216 uint32_t enc_intr_vec_base;
1217 uint32_t enc_intr_limit;
1218 uint32_t enc_evq_limit;
1219 uint32_t enc_txq_limit;
1220 uint32_t enc_rxq_limit;
1221 uint32_t enc_txq_max_ndescs;
1222 uint32_t enc_buftbl_limit;
1223 uint32_t enc_piobuf_limit;
1224 uint32_t enc_piobuf_size;
1225 uint32_t enc_piobuf_min_alloc_size;
1226 uint32_t enc_evq_timer_quantum_ns;
1227 uint32_t enc_evq_timer_max_us;
1228 uint32_t enc_clk_mult;
1229 uint32_t enc_rx_prefix_size;
1230 uint32_t enc_rx_buf_align_start;
1231 uint32_t enc_rx_buf_align_end;
1232 uint32_t enc_rx_scale_max_exclusive_contexts;
1234 * Mask of supported hash algorithms.
1235 * Hash algorithm types are used as the bit indices.
1237 uint32_t enc_rx_scale_hash_alg_mask;
1239 * Indicates whether port numbers can be included to the
1240 * input data for hash computation.
1242 boolean_t enc_rx_scale_l4_hash_supported;
1243 boolean_t enc_rx_scale_additional_modes_supported;
1244 #if EFSYS_OPT_LOOPBACK
1245 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1246 #endif /* EFSYS_OPT_LOOPBACK */
1247 #if EFSYS_OPT_PHY_FLAGS
1248 uint32_t enc_phy_flags_mask;
1249 #endif /* EFSYS_OPT_PHY_FLAGS */
1250 #if EFSYS_OPT_PHY_LED_CONTROL
1251 uint32_t enc_led_mask;
1252 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1253 #if EFSYS_OPT_PHY_STATS
1254 uint64_t enc_phy_stat_mask;
1255 #endif /* EFSYS_OPT_PHY_STATS */
1257 uint8_t enc_mcdi_mdio_channel;
1258 #if EFSYS_OPT_PHY_STATS
1259 uint32_t enc_mcdi_phy_stat_mask;
1260 #endif /* EFSYS_OPT_PHY_STATS */
1261 #if EFSYS_OPT_MON_STATS
1262 uint32_t *enc_mcdi_sensor_maskp;
1263 uint32_t enc_mcdi_sensor_mask_size;
1264 #endif /* EFSYS_OPT_MON_STATS */
1265 #endif /* EFSYS_OPT_MCDI */
1267 uint32_t enc_bist_mask;
1268 #endif /* EFSYS_OPT_BIST */
1269 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1272 uint32_t enc_privilege_mask;
1273 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1274 boolean_t enc_bug26807_workaround;
1275 boolean_t enc_bug35388_workaround;
1276 boolean_t enc_bug41750_workaround;
1277 boolean_t enc_bug61265_workaround;
1278 boolean_t enc_rx_batching_enabled;
1279 /* Maximum number of descriptors completed in an rx event. */
1280 uint32_t enc_rx_batch_max;
1281 /* Number of rx descriptors the hardware requires for a push. */
1282 uint32_t enc_rx_push_align;
1283 /* Maximum amount of data in DMA descriptor */
1284 uint32_t enc_tx_dma_desc_size_max;
1286 * Boundary which DMA descriptor data must not cross or 0 if no
1289 uint32_t enc_tx_dma_desc_boundary;
1291 * Maximum number of bytes into the packet the TCP header can start for
1292 * the hardware to apply TSO packet edits.
1294 uint32_t enc_tx_tso_tcp_header_offset_limit;
1295 boolean_t enc_fw_assisted_tso_enabled;
1296 boolean_t enc_fw_assisted_tso_v2_enabled;
1297 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1298 /* Number of TSO contexts on the NIC (FATSOv2) */
1299 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1300 boolean_t enc_hw_tx_insert_vlan_enabled;
1301 /* Number of PFs on the NIC */
1302 uint32_t enc_hw_pf_count;
1303 /* Datapath firmware vadapter/vport/vswitch support */
1304 boolean_t enc_datapath_cap_evb;
1305 boolean_t enc_rx_disable_scatter_supported;
1306 boolean_t enc_allow_set_mac_with_installed_filters;
1307 boolean_t enc_enhanced_set_mac_supported;
1308 boolean_t enc_init_evq_v2_supported;
1309 boolean_t enc_rx_packed_stream_supported;
1310 boolean_t enc_rx_var_packed_stream_supported;
1311 boolean_t enc_rx_es_super_buffer_supported;
1312 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1313 boolean_t enc_pm_and_rxdp_counters;
1314 boolean_t enc_mac_stats_40g_tx_size_bins;
1315 uint32_t enc_tunnel_encapsulations_supported;
1317 * NIC global maximum for unique UDP tunnel ports shared by all
1320 uint32_t enc_tunnel_config_udp_entries_max;
1321 /* External port identifier */
1322 uint8_t enc_external_port;
1323 uint32_t enc_mcdi_max_payload_length;
1324 /* VPD may be per-PF or global */
1325 boolean_t enc_vpd_is_global;
1326 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1327 uint32_t enc_required_pcie_bandwidth_mbps;
1328 uint32_t enc_max_pcie_link_gen;
1329 /* Firmware verifies integrity of NVRAM updates */
1330 uint32_t enc_nvram_update_verify_result_supported;
1331 /* Firmware support for extended MAC_STATS buffer */
1332 uint32_t enc_mac_stats_nstats;
1333 boolean_t enc_fec_counters;
1334 boolean_t enc_hlb_counters;
1335 /* Firmware support for "FLAG" and "MARK" filter actions */
1336 boolean_t enc_filter_action_flag_supported;
1337 boolean_t enc_filter_action_mark_supported;
1338 uint32_t enc_filter_action_mark_max;
1341 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1342 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1344 #define EFX_PCI_FUNCTION(_encp) \
1345 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1347 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1349 extern const efx_nic_cfg_t *
1351 __in efx_nic_t *enp);
1353 /* RxDPCPU firmware id values by which FW variant can be identified */
1354 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1355 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1356 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1357 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1358 #define EFX_RXDP_DPDK_FW_ID 0x6
1360 typedef struct efx_nic_fw_info_s {
1361 /* Basic FW version information */
1362 uint16_t enfi_mc_fw_version[4];
1364 * If datapath capabilities can be detected,
1365 * additional FW information is to be shown
1367 boolean_t enfi_dpcpu_fw_ids_valid;
1368 /* Rx and Tx datapath CPU FW IDs */
1369 uint16_t enfi_rx_dpcpu_fw_id;
1370 uint16_t enfi_tx_dpcpu_fw_id;
1371 } efx_nic_fw_info_t;
1373 extern __checkReturn efx_rc_t
1374 efx_nic_get_fw_version(
1375 __in efx_nic_t *enp,
1376 __out efx_nic_fw_info_t *enfip);
1378 /* Driver resource limits (minimum required/maximum usable). */
1379 typedef struct efx_drv_limits_s {
1380 uint32_t edl_min_evq_count;
1381 uint32_t edl_max_evq_count;
1383 uint32_t edl_min_rxq_count;
1384 uint32_t edl_max_rxq_count;
1386 uint32_t edl_min_txq_count;
1387 uint32_t edl_max_txq_count;
1389 /* PIO blocks (sub-allocated from piobuf) */
1390 uint32_t edl_min_pio_alloc_size;
1391 uint32_t edl_max_pio_alloc_count;
1394 extern __checkReturn efx_rc_t
1395 efx_nic_set_drv_limits(
1396 __inout efx_nic_t *enp,
1397 __in efx_drv_limits_t *edlp);
1399 typedef enum efx_nic_region_e {
1400 EFX_REGION_VI, /* Memory BAR UC mapping */
1401 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1404 extern __checkReturn efx_rc_t
1405 efx_nic_get_bar_region(
1406 __in efx_nic_t *enp,
1407 __in efx_nic_region_t region,
1408 __out uint32_t *offsetp,
1409 __out size_t *sizep);
1411 extern __checkReturn efx_rc_t
1412 efx_nic_get_vi_pool(
1413 __in efx_nic_t *enp,
1414 __out uint32_t *evq_countp,
1415 __out uint32_t *rxq_countp,
1416 __out uint32_t *txq_countp);
1421 typedef enum efx_vpd_tag_e {
1428 typedef uint16_t efx_vpd_keyword_t;
1430 typedef struct efx_vpd_value_s {
1431 efx_vpd_tag_t evv_tag;
1432 efx_vpd_keyword_t evv_keyword;
1434 uint8_t evv_value[0x100];
1438 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1440 extern __checkReturn efx_rc_t
1442 __in efx_nic_t *enp);
1444 extern __checkReturn efx_rc_t
1446 __in efx_nic_t *enp,
1447 __out size_t *sizep);
1449 extern __checkReturn efx_rc_t
1451 __in efx_nic_t *enp,
1452 __out_bcount(size) caddr_t data,
1455 extern __checkReturn efx_rc_t
1457 __in efx_nic_t *enp,
1458 __in_bcount(size) caddr_t data,
1461 extern __checkReturn efx_rc_t
1463 __in efx_nic_t *enp,
1464 __in_bcount(size) caddr_t data,
1467 extern __checkReturn efx_rc_t
1469 __in efx_nic_t *enp,
1470 __in_bcount(size) caddr_t data,
1472 __inout efx_vpd_value_t *evvp);
1474 extern __checkReturn efx_rc_t
1476 __in efx_nic_t *enp,
1477 __inout_bcount(size) caddr_t data,
1479 __in efx_vpd_value_t *evvp);
1481 extern __checkReturn efx_rc_t
1483 __in efx_nic_t *enp,
1484 __inout_bcount(size) caddr_t data,
1486 __out efx_vpd_value_t *evvp,
1487 __inout unsigned int *contp);
1489 extern __checkReturn efx_rc_t
1491 __in efx_nic_t *enp,
1492 __in_bcount(size) caddr_t data,
1497 __in efx_nic_t *enp);
1499 #endif /* EFSYS_OPT_VPD */
1505 typedef enum efx_nvram_type_e {
1506 EFX_NVRAM_INVALID = 0,
1508 EFX_NVRAM_BOOTROM_CFG,
1509 EFX_NVRAM_MC_FIRMWARE,
1510 EFX_NVRAM_MC_GOLDEN,
1516 EFX_NVRAM_FPGA_BACKUP,
1517 EFX_NVRAM_DYNAMIC_CFG,
1520 EFX_NVRAM_MUM_FIRMWARE,
1521 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1522 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1526 extern __checkReturn efx_rc_t
1528 __in efx_nic_t *enp);
1532 extern __checkReturn efx_rc_t
1534 __in efx_nic_t *enp);
1536 #endif /* EFSYS_OPT_DIAG */
1538 extern __checkReturn efx_rc_t
1540 __in efx_nic_t *enp,
1541 __in efx_nvram_type_t type,
1542 __out size_t *sizep);
1544 extern __checkReturn efx_rc_t
1546 __in efx_nic_t *enp,
1547 __in efx_nvram_type_t type,
1548 __out_opt size_t *pref_chunkp);
1550 extern __checkReturn efx_rc_t
1551 efx_nvram_rw_finish(
1552 __in efx_nic_t *enp,
1553 __in efx_nvram_type_t type,
1554 __out_opt uint32_t *verify_resultp);
1556 extern __checkReturn efx_rc_t
1557 efx_nvram_get_version(
1558 __in efx_nic_t *enp,
1559 __in efx_nvram_type_t type,
1560 __out uint32_t *subtypep,
1561 __out_ecount(4) uint16_t version[4]);
1563 extern __checkReturn efx_rc_t
1564 efx_nvram_read_chunk(
1565 __in efx_nic_t *enp,
1566 __in efx_nvram_type_t type,
1567 __in unsigned int offset,
1568 __out_bcount(size) caddr_t data,
1571 extern __checkReturn efx_rc_t
1572 efx_nvram_read_backup(
1573 __in efx_nic_t *enp,
1574 __in efx_nvram_type_t type,
1575 __in unsigned int offset,
1576 __out_bcount(size) caddr_t data,
1579 extern __checkReturn efx_rc_t
1580 efx_nvram_set_version(
1581 __in efx_nic_t *enp,
1582 __in efx_nvram_type_t type,
1583 __in_ecount(4) uint16_t version[4]);
1585 extern __checkReturn efx_rc_t
1587 __in efx_nic_t *enp,
1588 __in efx_nvram_type_t type,
1589 __in_bcount(partn_size) caddr_t partn_data,
1590 __in size_t partn_size);
1592 extern __checkReturn efx_rc_t
1594 __in efx_nic_t *enp,
1595 __in efx_nvram_type_t type);
1597 extern __checkReturn efx_rc_t
1598 efx_nvram_write_chunk(
1599 __in efx_nic_t *enp,
1600 __in efx_nvram_type_t type,
1601 __in unsigned int offset,
1602 __in_bcount(size) caddr_t data,
1607 __in efx_nic_t *enp);
1609 #endif /* EFSYS_OPT_NVRAM */
1611 #if EFSYS_OPT_BOOTCFG
1613 /* Report size and offset of bootcfg sector in NVRAM partition. */
1614 extern __checkReturn efx_rc_t
1615 efx_bootcfg_sector_info(
1616 __in efx_nic_t *enp,
1618 __out_opt uint32_t *sector_countp,
1619 __out size_t *offsetp,
1620 __out size_t *max_sizep);
1623 * Copy bootcfg sector data to a target buffer which may differ in size.
1624 * Optionally corrects format errors in source buffer.
1627 efx_bootcfg_copy_sector(
1628 __in efx_nic_t *enp,
1629 __inout_bcount(sector_length)
1631 __in size_t sector_length,
1632 __out_bcount(data_size) uint8_t *data,
1633 __in size_t data_size,
1634 __in boolean_t handle_format_errors);
1638 __in efx_nic_t *enp,
1639 __out_bcount(size) uint8_t *data,
1644 __in efx_nic_t *enp,
1645 __in_bcount(size) uint8_t *data,
1648 #endif /* EFSYS_OPT_BOOTCFG */
1650 #if EFSYS_OPT_IMAGE_LAYOUT
1652 #include "ef10_signed_image_layout.h"
1655 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1658 * The image header format is extensible. However, older drivers require an
1659 * exact match of image header version and header length when validating and
1660 * writing firmware images.
1662 * To avoid breaking backward compatibility, we use the upper bits of the
1663 * controller version fields to contain an extra version number used for
1664 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1665 * version). See bug39254 and SF-102785-PS for details.
1667 typedef struct efx_image_header_s {
1669 uint32_t eih_version;
1671 uint32_t eih_subtype;
1672 uint32_t eih_code_size;
1675 uint32_t eih_controller_version_min;
1677 uint16_t eih_controller_version_min_short;
1678 uint8_t eih_extra_version_a;
1679 uint8_t eih_extra_version_b;
1683 uint32_t eih_controller_version_max;
1685 uint16_t eih_controller_version_max_short;
1686 uint8_t eih_extra_version_c;
1687 uint8_t eih_extra_version_d;
1690 uint16_t eih_code_version_a;
1691 uint16_t eih_code_version_b;
1692 uint16_t eih_code_version_c;
1693 uint16_t eih_code_version_d;
1694 } efx_image_header_t;
1696 #define EFX_IMAGE_HEADER_SIZE (40)
1697 #define EFX_IMAGE_HEADER_VERSION (4)
1698 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1701 typedef struct efx_image_trailer_s {
1703 } efx_image_trailer_t;
1705 #define EFX_IMAGE_TRAILER_SIZE (4)
1707 typedef enum efx_image_format_e {
1708 EFX_IMAGE_FORMAT_NO_IMAGE,
1709 EFX_IMAGE_FORMAT_INVALID,
1710 EFX_IMAGE_FORMAT_UNSIGNED,
1711 EFX_IMAGE_FORMAT_SIGNED,
1712 } efx_image_format_t;
1714 typedef struct efx_image_info_s {
1715 efx_image_format_t eii_format;
1716 uint8_t * eii_imagep;
1717 size_t eii_image_size;
1718 efx_image_header_t * eii_headerp;
1721 extern __checkReturn efx_rc_t
1722 efx_check_reflash_image(
1724 __in uint32_t buffer_size,
1725 __out efx_image_info_t *infop);
1727 extern __checkReturn efx_rc_t
1728 efx_build_signed_image_write_buffer(
1729 __out_bcount(buffer_size)
1731 __in uint32_t buffer_size,
1732 __in efx_image_info_t *infop,
1733 __out efx_image_header_t **headerpp);
1735 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1739 typedef enum efx_pattern_type_t {
1740 EFX_PATTERN_BYTE_INCREMENT = 0,
1741 EFX_PATTERN_ALL_THE_SAME,
1742 EFX_PATTERN_BIT_ALTERNATE,
1743 EFX_PATTERN_BYTE_ALTERNATE,
1744 EFX_PATTERN_BYTE_CHANGING,
1745 EFX_PATTERN_BIT_SWEEP,
1747 } efx_pattern_type_t;
1750 (*efx_sram_pattern_fn_t)(
1752 __in boolean_t negate,
1753 __out efx_qword_t *eqp);
1755 extern __checkReturn efx_rc_t
1757 __in efx_nic_t *enp,
1758 __in efx_pattern_type_t type);
1760 #endif /* EFSYS_OPT_DIAG */
1762 extern __checkReturn efx_rc_t
1763 efx_sram_buf_tbl_set(
1764 __in efx_nic_t *enp,
1766 __in efsys_mem_t *esmp,
1770 efx_sram_buf_tbl_clear(
1771 __in efx_nic_t *enp,
1775 #define EFX_BUF_TBL_SIZE 0x20000
1777 #define EFX_BUF_SIZE 4096
1781 typedef struct efx_evq_s efx_evq_t;
1783 #if EFSYS_OPT_QSTATS
1785 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1786 typedef enum efx_ev_qstat_e {
1792 EV_RX_PAUSE_FRM_ERR,
1793 EV_RX_BUF_OWNER_ID_ERR,
1794 EV_RX_IPV4_HDR_CHKSUM_ERR,
1795 EV_RX_TCP_UDP_CHKSUM_ERR,
1799 EV_RX_MCAST_HASH_MATCH,
1816 EV_DRIVER_SRM_UPD_DONE,
1817 EV_DRIVER_TX_DESCQ_FLS_DONE,
1818 EV_DRIVER_RX_DESCQ_FLS_DONE,
1819 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1820 EV_DRIVER_RX_DSC_ERROR,
1821 EV_DRIVER_TX_DSC_ERROR,
1827 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1829 #endif /* EFSYS_OPT_QSTATS */
1831 extern __checkReturn efx_rc_t
1833 __in efx_nic_t *enp);
1837 __in efx_nic_t *enp);
1839 #define EFX_EVQ_MAXNEVS 32768
1840 #define EFX_EVQ_MINNEVS 512
1842 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1843 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1845 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1846 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1847 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1848 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1850 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1851 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1852 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1854 extern __checkReturn efx_rc_t
1856 __in efx_nic_t *enp,
1857 __in unsigned int index,
1858 __in efsys_mem_t *esmp,
1862 __in uint32_t flags,
1863 __deref_out efx_evq_t **eepp);
1867 __in efx_evq_t *eep,
1868 __in uint16_t data);
1870 typedef __checkReturn boolean_t
1871 (*efx_initialized_ev_t)(
1872 __in_opt void *arg);
1874 #define EFX_PKT_UNICAST 0x0004
1875 #define EFX_PKT_START 0x0008
1877 #define EFX_PKT_VLAN_TAGGED 0x0010
1878 #define EFX_CKSUM_TCPUDP 0x0020
1879 #define EFX_CKSUM_IPV4 0x0040
1880 #define EFX_PKT_CONT 0x0080
1882 #define EFX_CHECK_VLAN 0x0100
1883 #define EFX_PKT_TCP 0x0200
1884 #define EFX_PKT_UDP 0x0400
1885 #define EFX_PKT_IPV4 0x0800
1887 #define EFX_PKT_IPV6 0x1000
1888 #define EFX_PKT_PREFIX_LEN 0x2000
1889 #define EFX_ADDR_MISMATCH 0x4000
1890 #define EFX_DISCARD 0x8000
1893 * The following flags are used only for packed stream
1894 * mode. The values for the flags are reused to fit into 16 bit,
1895 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1896 * packed stream mode
1898 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1899 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1902 #define EFX_EV_RX_NLABELS 32
1903 #define EFX_EV_TX_NLABELS 32
1905 typedef __checkReturn boolean_t
1908 __in uint32_t label,
1911 __in uint16_t flags);
1913 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1916 * Packed stream mode is documented in SF-112241-TC.
1917 * The general idea is that, instead of putting each incoming
1918 * packet into a separate buffer which is specified in a RX
1919 * descriptor, a large buffer is provided to the hardware and
1920 * packets are put there in a continuous stream.
1921 * The main advantage of such an approach is that RX queue refilling
1922 * happens much less frequently.
1924 * Equal stride packed stream mode is documented in SF-119419-TC.
1925 * The general idea is to utilize advantages of the packed stream,
1926 * but avoid indirection in packets representation.
1927 * The main advantage of such an approach is that RX queue refilling
1928 * happens much less frequently and packets buffers are independent
1929 * from upper layers point of view.
1932 typedef __checkReturn boolean_t
1935 __in uint32_t label,
1937 __in uint32_t pkt_count,
1938 __in uint16_t flags);
1942 typedef __checkReturn boolean_t
1945 __in uint32_t label,
1948 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1949 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1950 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1951 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1952 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1953 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1954 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1955 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1956 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1958 typedef __checkReturn boolean_t
1959 (*efx_exception_ev_t)(
1961 __in uint32_t label,
1962 __in uint32_t data);
1964 typedef __checkReturn boolean_t
1965 (*efx_rxq_flush_done_ev_t)(
1967 __in uint32_t rxq_index);
1969 typedef __checkReturn boolean_t
1970 (*efx_rxq_flush_failed_ev_t)(
1972 __in uint32_t rxq_index);
1974 typedef __checkReturn boolean_t
1975 (*efx_txq_flush_done_ev_t)(
1977 __in uint32_t txq_index);
1979 typedef __checkReturn boolean_t
1980 (*efx_software_ev_t)(
1982 __in uint16_t magic);
1984 typedef __checkReturn boolean_t
1987 __in uint32_t code);
1989 #define EFX_SRAM_CLEAR 0
1990 #define EFX_SRAM_UPDATE 1
1991 #define EFX_SRAM_ILLEGAL_CLEAR 2
1993 typedef __checkReturn boolean_t
1994 (*efx_wake_up_ev_t)(
1996 __in uint32_t label);
1998 typedef __checkReturn boolean_t
2001 __in uint32_t label);
2003 typedef __checkReturn boolean_t
2004 (*efx_link_change_ev_t)(
2006 __in efx_link_mode_t link_mode);
2008 #if EFSYS_OPT_MON_STATS
2010 typedef __checkReturn boolean_t
2011 (*efx_monitor_ev_t)(
2013 __in efx_mon_stat_t id,
2014 __in efx_mon_stat_value_t value);
2016 #endif /* EFSYS_OPT_MON_STATS */
2018 #if EFSYS_OPT_MAC_STATS
2020 typedef __checkReturn boolean_t
2021 (*efx_mac_stats_ev_t)(
2023 __in uint32_t generation);
2025 #endif /* EFSYS_OPT_MAC_STATS */
2027 typedef struct efx_ev_callbacks_s {
2028 efx_initialized_ev_t eec_initialized;
2030 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2031 efx_rx_ps_ev_t eec_rx_ps;
2034 efx_exception_ev_t eec_exception;
2035 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2036 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2037 efx_txq_flush_done_ev_t eec_txq_flush_done;
2038 efx_software_ev_t eec_software;
2039 efx_sram_ev_t eec_sram;
2040 efx_wake_up_ev_t eec_wake_up;
2041 efx_timer_ev_t eec_timer;
2042 efx_link_change_ev_t eec_link_change;
2043 #if EFSYS_OPT_MON_STATS
2044 efx_monitor_ev_t eec_monitor;
2045 #endif /* EFSYS_OPT_MON_STATS */
2046 #if EFSYS_OPT_MAC_STATS
2047 efx_mac_stats_ev_t eec_mac_stats;
2048 #endif /* EFSYS_OPT_MAC_STATS */
2049 } efx_ev_callbacks_t;
2051 extern __checkReturn boolean_t
2053 __in efx_evq_t *eep,
2054 __in unsigned int count);
2056 #if EFSYS_OPT_EV_PREFETCH
2060 __in efx_evq_t *eep,
2061 __in unsigned int count);
2063 #endif /* EFSYS_OPT_EV_PREFETCH */
2067 __in efx_evq_t *eep,
2068 __inout unsigned int *countp,
2069 __in const efx_ev_callbacks_t *eecp,
2070 __in_opt void *arg);
2072 extern __checkReturn efx_rc_t
2073 efx_ev_usecs_to_ticks(
2074 __in efx_nic_t *enp,
2075 __in unsigned int usecs,
2076 __out unsigned int *ticksp);
2078 extern __checkReturn efx_rc_t
2080 __in efx_evq_t *eep,
2081 __in unsigned int us);
2083 extern __checkReturn efx_rc_t
2085 __in efx_evq_t *eep,
2086 __in unsigned int count);
2088 #if EFSYS_OPT_QSTATS
2094 __in efx_nic_t *enp,
2095 __in unsigned int id);
2097 #endif /* EFSYS_OPT_NAMES */
2100 efx_ev_qstats_update(
2101 __in efx_evq_t *eep,
2102 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2104 #endif /* EFSYS_OPT_QSTATS */
2108 __in efx_evq_t *eep);
2112 extern __checkReturn efx_rc_t
2114 __inout efx_nic_t *enp);
2118 __in efx_nic_t *enp);
2120 #if EFSYS_OPT_RX_SCATTER
2121 __checkReturn efx_rc_t
2122 efx_rx_scatter_enable(
2123 __in efx_nic_t *enp,
2124 __in unsigned int buf_size);
2125 #endif /* EFSYS_OPT_RX_SCATTER */
2127 /* Handle to represent use of the default RSS context. */
2128 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2130 #if EFSYS_OPT_RX_SCALE
2132 typedef enum efx_rx_hash_alg_e {
2133 EFX_RX_HASHALG_LFSR = 0,
2134 EFX_RX_HASHALG_TOEPLITZ,
2135 EFX_RX_HASHALG_PACKED_STREAM,
2137 } efx_rx_hash_alg_t;
2140 * Legacy hash type flags.
2142 * They represent standard tuples for distinct traffic classes.
2144 #define EFX_RX_HASH_IPV4 (1U << 0)
2145 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2146 #define EFX_RX_HASH_IPV6 (1U << 2)
2147 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2149 #define EFX_RX_HASH_LEGACY_MASK \
2150 (EFX_RX_HASH_IPV4 | \
2151 EFX_RX_HASH_TCPIPV4 | \
2152 EFX_RX_HASH_IPV6 | \
2153 EFX_RX_HASH_TCPIPV6)
2156 * The type of the argument used by efx_rx_scale_mode_set() to
2157 * provide a means for the client drivers to configure hashing.
2159 * A properly constructed value can either be:
2160 * - a combination of legacy flags
2161 * - a combination of EFX_RX_HASH() flags
2163 typedef unsigned int efx_rx_hash_type_t;
2165 typedef enum efx_rx_hash_support_e {
2166 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2167 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2168 } efx_rx_hash_support_t;
2170 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2171 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2172 #define EFX_MAXRSS 64 /* RX indirection entry range */
2173 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2175 typedef enum efx_rx_scale_context_type_e {
2176 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2177 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2178 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2179 } efx_rx_scale_context_type_t;
2182 * Traffic classes eligible for hash computation.
2184 * Select packet headers used in computing the receive hash.
2185 * This uses the same encoding as the RSS_MODES field of
2186 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2188 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2189 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2190 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2191 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2192 #define EFX_RX_CLASS_IPV4_LBN 16
2193 #define EFX_RX_CLASS_IPV4_WIDTH 4
2194 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2195 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2196 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2197 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2198 #define EFX_RX_CLASS_IPV6_LBN 28
2199 #define EFX_RX_CLASS_IPV6_WIDTH 4
2201 #define EFX_RX_NCLASSES 6
2204 * Ancillary flags used to construct generic hash tuples.
2205 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2207 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2208 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2209 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2210 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2213 * Generic hash tuples.
2215 * They express combinations of packet fields
2216 * which can contribute to the hash value for
2217 * a particular traffic class.
2219 #define EFX_RX_CLASS_HASH_DISABLE 0
2221 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2222 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2224 #define EFX_RX_CLASS_HASH_2TUPLE \
2225 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2226 EFX_RX_CLASS_HASH_DST_ADDR)
2228 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2229 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2230 EFX_RX_CLASS_HASH_SRC_PORT)
2232 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2233 (EFX_RX_CLASS_HASH_DST_ADDR | \
2234 EFX_RX_CLASS_HASH_DST_PORT)
2236 #define EFX_RX_CLASS_HASH_4TUPLE \
2237 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2238 EFX_RX_CLASS_HASH_DST_ADDR | \
2239 EFX_RX_CLASS_HASH_SRC_PORT | \
2240 EFX_RX_CLASS_HASH_DST_PORT)
2242 #define EFX_RX_CLASS_HASH_NTUPLES 7
2245 * Hash flag constructor.
2247 * Resulting flags encode hash tuples for specific traffic classes.
2248 * The client drivers are encouraged to use these flags to form
2249 * a hash type value.
2251 #define EFX_RX_HASH(_class, _tuple) \
2252 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2253 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2256 * The maximum number of EFX_RX_HASH() flags.
2258 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2260 extern __checkReturn efx_rc_t
2261 efx_rx_scale_hash_flags_get(
2262 __in efx_nic_t *enp,
2263 __in efx_rx_hash_alg_t hash_alg,
2264 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
2265 __out unsigned int *nflagsp);
2267 extern __checkReturn efx_rc_t
2268 efx_rx_hash_default_support_get(
2269 __in efx_nic_t *enp,
2270 __out efx_rx_hash_support_t *supportp);
2273 extern __checkReturn efx_rc_t
2274 efx_rx_scale_default_support_get(
2275 __in efx_nic_t *enp,
2276 __out efx_rx_scale_context_type_t *typep);
2278 extern __checkReturn efx_rc_t
2279 efx_rx_scale_context_alloc(
2280 __in efx_nic_t *enp,
2281 __in efx_rx_scale_context_type_t type,
2282 __in uint32_t num_queues,
2283 __out uint32_t *rss_contextp);
2285 extern __checkReturn efx_rc_t
2286 efx_rx_scale_context_free(
2287 __in efx_nic_t *enp,
2288 __in uint32_t rss_context);
2290 extern __checkReturn efx_rc_t
2291 efx_rx_scale_mode_set(
2292 __in efx_nic_t *enp,
2293 __in uint32_t rss_context,
2294 __in efx_rx_hash_alg_t alg,
2295 __in efx_rx_hash_type_t type,
2296 __in boolean_t insert);
2298 extern __checkReturn efx_rc_t
2299 efx_rx_scale_tbl_set(
2300 __in efx_nic_t *enp,
2301 __in uint32_t rss_context,
2302 __in_ecount(n) unsigned int *table,
2305 extern __checkReturn efx_rc_t
2306 efx_rx_scale_key_set(
2307 __in efx_nic_t *enp,
2308 __in uint32_t rss_context,
2309 __in_ecount(n) uint8_t *key,
2312 extern __checkReturn uint32_t
2313 efx_pseudo_hdr_hash_get(
2314 __in efx_rxq_t *erp,
2315 __in efx_rx_hash_alg_t func,
2316 __in uint8_t *buffer);
2318 #endif /* EFSYS_OPT_RX_SCALE */
2320 extern __checkReturn efx_rc_t
2321 efx_pseudo_hdr_pkt_length_get(
2322 __in efx_rxq_t *erp,
2323 __in uint8_t *buffer,
2324 __out uint16_t *pkt_lengthp);
2326 #define EFX_RXQ_MAXNDESCS 4096
2327 #define EFX_RXQ_MINNDESCS 512
2329 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2330 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2331 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2332 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2334 typedef enum efx_rxq_type_e {
2335 EFX_RXQ_TYPE_DEFAULT,
2336 EFX_RXQ_TYPE_PACKED_STREAM,
2337 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2342 * Dummy flag to be used instead of 0 to make it clear that the argument
2343 * is receive queue flags.
2345 #define EFX_RXQ_FLAG_NONE 0x0
2346 #define EFX_RXQ_FLAG_SCATTER 0x1
2348 * If tunnels are supported and Rx event can provide information about
2349 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2350 * full-feature firmware variant running), outer classes are requested by
2351 * default. However, if the driver supports tunnels, the flag allows to
2352 * request inner classes which are required to be able to interpret inner
2353 * Rx checksum offload results.
2355 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2357 extern __checkReturn efx_rc_t
2359 __in efx_nic_t *enp,
2360 __in unsigned int index,
2361 __in unsigned int label,
2362 __in efx_rxq_type_t type,
2363 __in efsys_mem_t *esmp,
2366 __in unsigned int flags,
2367 __in efx_evq_t *eep,
2368 __deref_out efx_rxq_t **erpp);
2370 #if EFSYS_OPT_RX_PACKED_STREAM
2372 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2373 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2374 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2375 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2376 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2378 extern __checkReturn efx_rc_t
2379 efx_rx_qcreate_packed_stream(
2380 __in efx_nic_t *enp,
2381 __in unsigned int index,
2382 __in unsigned int label,
2383 __in uint32_t ps_buf_size,
2384 __in efsys_mem_t *esmp,
2386 __in efx_evq_t *eep,
2387 __deref_out efx_rxq_t **erpp);
2391 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2393 /* Maximum head-of-line block timeout in nanoseconds */
2394 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2396 extern __checkReturn efx_rc_t
2397 efx_rx_qcreate_es_super_buffer(
2398 __in efx_nic_t *enp,
2399 __in unsigned int index,
2400 __in unsigned int label,
2401 __in uint32_t n_bufs_per_desc,
2402 __in uint32_t max_dma_len,
2403 __in uint32_t buf_stride,
2404 __in uint32_t hol_block_timeout,
2405 __in efsys_mem_t *esmp,
2407 __in unsigned int flags,
2408 __in efx_evq_t *eep,
2409 __deref_out efx_rxq_t **erpp);
2413 typedef struct efx_buffer_s {
2414 efsys_dma_addr_t eb_addr;
2419 typedef struct efx_desc_s {
2425 __in efx_rxq_t *erp,
2426 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2428 __in unsigned int ndescs,
2429 __in unsigned int completed,
2430 __in unsigned int added);
2434 __in efx_rxq_t *erp,
2435 __in unsigned int added,
2436 __inout unsigned int *pushedp);
2438 #if EFSYS_OPT_RX_PACKED_STREAM
2441 efx_rx_qpush_ps_credits(
2442 __in efx_rxq_t *erp);
2444 extern __checkReturn uint8_t *
2445 efx_rx_qps_packet_info(
2446 __in efx_rxq_t *erp,
2447 __in uint8_t *buffer,
2448 __in uint32_t buffer_length,
2449 __in uint32_t current_offset,
2450 __out uint16_t *lengthp,
2451 __out uint32_t *next_offsetp,
2452 __out uint32_t *timestamp);
2455 extern __checkReturn efx_rc_t
2457 __in efx_rxq_t *erp);
2461 __in efx_rxq_t *erp);
2465 __in efx_rxq_t *erp);
2469 typedef struct efx_txq_s efx_txq_t;
2471 #if EFSYS_OPT_QSTATS
2473 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2474 typedef enum efx_tx_qstat_e {
2480 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2482 #endif /* EFSYS_OPT_QSTATS */
2484 extern __checkReturn efx_rc_t
2486 __in efx_nic_t *enp);
2490 __in efx_nic_t *enp);
2492 #define EFX_TXQ_MINNDESCS 512
2494 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2495 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2496 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2498 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2500 #define EFX_TXQ_CKSUM_IPV4 0x0001
2501 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2502 #define EFX_TXQ_FATSOV2 0x0004
2503 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2504 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2506 extern __checkReturn efx_rc_t
2508 __in efx_nic_t *enp,
2509 __in unsigned int index,
2510 __in unsigned int label,
2511 __in efsys_mem_t *esmp,
2514 __in uint16_t flags,
2515 __in efx_evq_t *eep,
2516 __deref_out efx_txq_t **etpp,
2517 __out unsigned int *addedp);
2519 extern __checkReturn efx_rc_t
2521 __in efx_txq_t *etp,
2522 __in_ecount(ndescs) efx_buffer_t *eb,
2523 __in unsigned int ndescs,
2524 __in unsigned int completed,
2525 __inout unsigned int *addedp);
2527 extern __checkReturn efx_rc_t
2529 __in efx_txq_t *etp,
2530 __in unsigned int ns);
2534 __in efx_txq_t *etp,
2535 __in unsigned int added,
2536 __in unsigned int pushed);
2538 extern __checkReturn efx_rc_t
2540 __in efx_txq_t *etp);
2544 __in efx_txq_t *etp);
2546 extern __checkReturn efx_rc_t
2548 __in efx_txq_t *etp);
2551 efx_tx_qpio_disable(
2552 __in efx_txq_t *etp);
2554 extern __checkReturn efx_rc_t
2556 __in efx_txq_t *etp,
2557 __in_ecount(buf_length) uint8_t *buffer,
2558 __in size_t buf_length,
2559 __in size_t pio_buf_offset);
2561 extern __checkReturn efx_rc_t
2563 __in efx_txq_t *etp,
2564 __in size_t pkt_length,
2565 __in unsigned int completed,
2566 __inout unsigned int *addedp);
2568 extern __checkReturn efx_rc_t
2570 __in efx_txq_t *etp,
2571 __in_ecount(n) efx_desc_t *ed,
2572 __in unsigned int n,
2573 __in unsigned int completed,
2574 __inout unsigned int *addedp);
2577 efx_tx_qdesc_dma_create(
2578 __in efx_txq_t *etp,
2579 __in efsys_dma_addr_t addr,
2582 __out efx_desc_t *edp);
2585 efx_tx_qdesc_tso_create(
2586 __in efx_txq_t *etp,
2587 __in uint16_t ipv4_id,
2588 __in uint32_t tcp_seq,
2589 __in uint8_t tcp_flags,
2590 __out efx_desc_t *edp);
2592 /* Number of FATSOv2 option descriptors */
2593 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2595 /* Maximum number of DMA segments per TSO packet (not superframe) */
2596 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2599 efx_tx_qdesc_tso2_create(
2600 __in efx_txq_t *etp,
2601 __in uint16_t ipv4_id,
2602 __in uint16_t outer_ipv4_id,
2603 __in uint32_t tcp_seq,
2604 __in uint16_t tcp_mss,
2605 __out_ecount(count) efx_desc_t *edp,
2609 efx_tx_qdesc_vlantci_create(
2610 __in efx_txq_t *etp,
2612 __out efx_desc_t *edp);
2615 efx_tx_qdesc_checksum_create(
2616 __in efx_txq_t *etp,
2617 __in uint16_t flags,
2618 __out efx_desc_t *edp);
2620 #if EFSYS_OPT_QSTATS
2626 __in efx_nic_t *etp,
2627 __in unsigned int id);
2629 #endif /* EFSYS_OPT_NAMES */
2632 efx_tx_qstats_update(
2633 __in efx_txq_t *etp,
2634 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2636 #endif /* EFSYS_OPT_QSTATS */
2640 __in efx_txq_t *etp);
2645 #if EFSYS_OPT_FILTER
2647 #define EFX_ETHER_TYPE_IPV4 0x0800
2648 #define EFX_ETHER_TYPE_IPV6 0x86DD
2650 #define EFX_IPPROTO_TCP 6
2651 #define EFX_IPPROTO_UDP 17
2652 #define EFX_IPPROTO_GRE 47
2654 /* Use RSS to spread across multiple queues */
2655 #define EFX_FILTER_FLAG_RX_RSS 0x01
2656 /* Enable RX scatter */
2657 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2659 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2660 * May only be set by the filter implementation for each type.
2661 * A removal request will restore the automatic filter in its place.
2663 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2664 /* Filter is for RX */
2665 #define EFX_FILTER_FLAG_RX 0x08
2666 /* Filter is for TX */
2667 #define EFX_FILTER_FLAG_TX 0x10
2668 /* Set match flag on the received packet */
2669 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2670 /* Set match mark on the received packet */
2671 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2673 typedef uint8_t efx_filter_flags_t;
2676 * Flags which specify the fields to match on. The values are the same as in the
2677 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2680 /* Match by remote IP host address */
2681 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2682 /* Match by local IP host address */
2683 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2684 /* Match by remote MAC address */
2685 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2686 /* Match by remote TCP/UDP port */
2687 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2688 /* Match by remote TCP/UDP port */
2689 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2690 /* Match by local TCP/UDP port */
2691 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2692 /* Match by Ether-type */
2693 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2694 /* Match by inner VLAN ID */
2695 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2696 /* Match by outer VLAN ID */
2697 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2698 /* Match by IP transport protocol */
2699 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2700 /* Match by VNI or VSID */
2701 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2702 /* For encapsulated packets, match by inner frame local MAC address */
2703 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2704 /* For encapsulated packets, match all multicast inner frames */
2705 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2706 /* For encapsulated packets, match all unicast inner frames */
2707 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2709 * Match by encap type, this flag does not correspond to
2710 * the MCDI match flags and any unoccupied value may be used
2712 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2713 /* Match otherwise-unmatched multicast and broadcast packets */
2714 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2715 /* Match otherwise-unmatched unicast packets */
2716 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2718 typedef uint32_t efx_filter_match_flags_t;
2720 typedef enum efx_filter_priority_s {
2721 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2722 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2723 * address list or hardware
2724 * requirements. This may only be used
2725 * by the filter implementation for
2727 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2728 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2729 * client (e.g. SR-IOV, HyperV VMQ etc.)
2731 } efx_filter_priority_t;
2734 * FIXME: All these fields are assumed to be in little-endian byte order.
2735 * It may be better for some to be big-endian. See bug42804.
2738 typedef struct efx_filter_spec_s {
2739 efx_filter_match_flags_t efs_match_flags;
2740 uint8_t efs_priority;
2741 efx_filter_flags_t efs_flags;
2742 uint16_t efs_dmaq_id;
2743 uint32_t efs_rss_context;
2744 uint16_t efs_outer_vid;
2745 uint16_t efs_inner_vid;
2746 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2747 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2748 uint16_t efs_ether_type;
2749 uint8_t efs_ip_proto;
2750 efx_tunnel_protocol_t efs_encap_type;
2751 uint16_t efs_loc_port;
2752 uint16_t efs_rem_port;
2753 efx_oword_t efs_rem_host;
2754 efx_oword_t efs_loc_host;
2755 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2756 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2758 } efx_filter_spec_t;
2761 /* Default values for use in filter specifications */
2762 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2763 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2765 extern __checkReturn efx_rc_t
2767 __in efx_nic_t *enp);
2771 __in efx_nic_t *enp);
2773 extern __checkReturn efx_rc_t
2775 __in efx_nic_t *enp,
2776 __inout efx_filter_spec_t *spec);
2778 extern __checkReturn efx_rc_t
2780 __in efx_nic_t *enp,
2781 __inout efx_filter_spec_t *spec);
2783 extern __checkReturn efx_rc_t
2785 __in efx_nic_t *enp);
2787 extern __checkReturn efx_rc_t
2788 efx_filter_supported_filters(
2789 __in efx_nic_t *enp,
2790 __out_ecount(buffer_length) uint32_t *buffer,
2791 __in size_t buffer_length,
2792 __out size_t *list_lengthp);
2795 efx_filter_spec_init_rx(
2796 __out efx_filter_spec_t *spec,
2797 __in efx_filter_priority_t priority,
2798 __in efx_filter_flags_t flags,
2799 __in efx_rxq_t *erp);
2802 efx_filter_spec_init_tx(
2803 __out efx_filter_spec_t *spec,
2804 __in efx_txq_t *etp);
2806 extern __checkReturn efx_rc_t
2807 efx_filter_spec_set_ipv4_local(
2808 __inout efx_filter_spec_t *spec,
2811 __in uint16_t port);
2813 extern __checkReturn efx_rc_t
2814 efx_filter_spec_set_ipv4_full(
2815 __inout efx_filter_spec_t *spec,
2817 __in uint32_t lhost,
2818 __in uint16_t lport,
2819 __in uint32_t rhost,
2820 __in uint16_t rport);
2822 extern __checkReturn efx_rc_t
2823 efx_filter_spec_set_eth_local(
2824 __inout efx_filter_spec_t *spec,
2826 __in const uint8_t *addr);
2829 efx_filter_spec_set_ether_type(
2830 __inout efx_filter_spec_t *spec,
2831 __in uint16_t ether_type);
2833 extern __checkReturn efx_rc_t
2834 efx_filter_spec_set_uc_def(
2835 __inout efx_filter_spec_t *spec);
2837 extern __checkReturn efx_rc_t
2838 efx_filter_spec_set_mc_def(
2839 __inout efx_filter_spec_t *spec);
2841 typedef enum efx_filter_inner_frame_match_e {
2842 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2843 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2844 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2845 } efx_filter_inner_frame_match_t;
2847 extern __checkReturn efx_rc_t
2848 efx_filter_spec_set_encap_type(
2849 __inout efx_filter_spec_t *spec,
2850 __in efx_tunnel_protocol_t encap_type,
2851 __in efx_filter_inner_frame_match_t inner_frame_match);
2853 extern __checkReturn efx_rc_t
2854 efx_filter_spec_set_vxlan_full(
2855 __inout efx_filter_spec_t *spec,
2856 __in const uint8_t *vxlan_id,
2857 __in const uint8_t *inner_addr,
2858 __in const uint8_t *outer_addr);
2860 #if EFSYS_OPT_RX_SCALE
2861 extern __checkReturn efx_rc_t
2862 efx_filter_spec_set_rss_context(
2863 __inout efx_filter_spec_t *spec,
2864 __in uint32_t rss_context);
2866 #endif /* EFSYS_OPT_FILTER */
2870 extern __checkReturn uint32_t
2872 __in_ecount(count) uint32_t const *input,
2874 __in uint32_t init);
2876 extern __checkReturn uint32_t
2878 __in_ecount(length) uint8_t const *input,
2880 __in uint32_t init);
2882 #if EFSYS_OPT_LICENSING
2886 typedef struct efx_key_stats_s {
2888 uint32_t eks_invalid;
2889 uint32_t eks_blacklisted;
2890 uint32_t eks_unverifiable;
2891 uint32_t eks_wrong_node;
2892 uint32_t eks_licensed_apps_lo;
2893 uint32_t eks_licensed_apps_hi;
2894 uint32_t eks_licensed_features_lo;
2895 uint32_t eks_licensed_features_hi;
2898 extern __checkReturn efx_rc_t
2900 __in efx_nic_t *enp);
2904 __in efx_nic_t *enp);
2906 extern __checkReturn boolean_t
2907 efx_lic_check_support(
2908 __in efx_nic_t *enp);
2910 extern __checkReturn efx_rc_t
2911 efx_lic_update_licenses(
2912 __in efx_nic_t *enp);
2914 extern __checkReturn efx_rc_t
2915 efx_lic_get_key_stats(
2916 __in efx_nic_t *enp,
2917 __out efx_key_stats_t *ksp);
2919 extern __checkReturn efx_rc_t
2921 __in efx_nic_t *enp,
2922 __in uint64_t app_id,
2923 __out boolean_t *licensedp);
2925 extern __checkReturn efx_rc_t
2927 __in efx_nic_t *enp,
2928 __in size_t buffer_size,
2929 __out uint32_t *typep,
2930 __out size_t *lengthp,
2931 __out_opt uint8_t *bufferp);
2934 extern __checkReturn efx_rc_t
2936 __in efx_nic_t *enp,
2937 __in_bcount(buffer_size)
2939 __in size_t buffer_size,
2940 __out uint32_t *startp);
2942 extern __checkReturn efx_rc_t
2944 __in efx_nic_t *enp,
2945 __in_bcount(buffer_size)
2947 __in size_t buffer_size,
2948 __in uint32_t offset,
2949 __out uint32_t *endp);
2951 extern __checkReturn __success(return != B_FALSE) boolean_t
2953 __in efx_nic_t *enp,
2954 __in_bcount(buffer_size)
2956 __in size_t buffer_size,
2957 __in uint32_t offset,
2958 __out uint32_t *startp,
2959 __out uint32_t *lengthp);
2961 extern __checkReturn __success(return != B_FALSE) boolean_t
2962 efx_lic_validate_key(
2963 __in efx_nic_t *enp,
2964 __in_bcount(length) caddr_t keyp,
2965 __in uint32_t length);
2967 extern __checkReturn efx_rc_t
2969 __in efx_nic_t *enp,
2970 __in_bcount(buffer_size)
2972 __in size_t buffer_size,
2973 __in uint32_t offset,
2974 __in uint32_t length,
2975 __out_bcount_part(key_max_size, *lengthp)
2977 __in size_t key_max_size,
2978 __out uint32_t *lengthp);
2980 extern __checkReturn efx_rc_t
2982 __in efx_nic_t *enp,
2983 __in_bcount(buffer_size)
2985 __in size_t buffer_size,
2986 __in uint32_t offset,
2987 __in_bcount(length) caddr_t keyp,
2988 __in uint32_t length,
2989 __out uint32_t *lengthp);
2991 __checkReturn efx_rc_t
2993 __in efx_nic_t *enp,
2994 __in_bcount(buffer_size)
2996 __in size_t buffer_size,
2997 __in uint32_t offset,
2998 __in uint32_t length,
3000 __out uint32_t *deltap);
3002 extern __checkReturn efx_rc_t
3003 efx_lic_create_partition(
3004 __in efx_nic_t *enp,
3005 __in_bcount(buffer_size)
3007 __in size_t buffer_size);
3009 extern __checkReturn efx_rc_t
3010 efx_lic_finish_partition(
3011 __in efx_nic_t *enp,
3012 __in_bcount(buffer_size)
3014 __in size_t buffer_size);
3016 #endif /* EFSYS_OPT_LICENSING */
3020 #if EFSYS_OPT_TUNNEL
3022 extern __checkReturn efx_rc_t
3024 __in efx_nic_t *enp);
3028 __in efx_nic_t *enp);
3031 * For overlay network encapsulation using UDP, the firmware needs to know
3032 * the configured UDP port for the overlay so it can decode encapsulated
3034 * The UDP port/protocol list is global.
3037 extern __checkReturn efx_rc_t
3038 efx_tunnel_config_udp_add(
3039 __in efx_nic_t *enp,
3040 __in uint16_t port /* host/cpu-endian */,
3041 __in efx_tunnel_protocol_t protocol);
3043 extern __checkReturn efx_rc_t
3044 efx_tunnel_config_udp_remove(
3045 __in efx_nic_t *enp,
3046 __in uint16_t port /* host/cpu-endian */,
3047 __in efx_tunnel_protocol_t protocol);
3050 efx_tunnel_config_clear(
3051 __in efx_nic_t *enp);
3054 * Apply tunnel UDP ports configuration to hardware.
3056 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3059 extern __checkReturn efx_rc_t
3060 efx_tunnel_reconfigure(
3061 __in efx_nic_t *enp);
3063 #endif /* EFSYS_OPT_TUNNEL */
3065 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3068 * Firmware subvariant choice options.
3070 * It may be switched to no Tx checksum if attached drivers are either
3071 * preboot or firmware subvariant aware and no VIS are allocated.
3072 * If may be always switched to default explicitly using set request or
3073 * implicitly if unaware driver is attaching. If switching is done when
3074 * a driver is attached, it gets MC_REBOOT event and should recreate its
3077 * See SF-119419-TC DPDK Firmware Driver Interface and
3078 * SF-109306-TC EF10 for Driver Writers for details.
3080 typedef enum efx_nic_fw_subvariant_e {
3081 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3082 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3083 EFX_NIC_FW_SUBVARIANT_NTYPES
3084 } efx_nic_fw_subvariant_t;
3086 extern __checkReturn efx_rc_t
3087 efx_nic_get_fw_subvariant(
3088 __in efx_nic_t *enp,
3089 __out efx_nic_fw_subvariant_t *subvariantp);
3091 extern __checkReturn efx_rc_t
3092 efx_nic_set_fw_subvariant(
3093 __in efx_nic_t *enp,
3094 __in efx_nic_fw_subvariant_t subvariant);
3096 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3102 #endif /* _SYS_EFX_H */