2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 __in efx_nic_t *enp);
155 __in efx_nic_t *enp);
159 __in efx_nic_t *enp);
161 #define EFX_PCIE_LINK_SPEED_GEN1 1
162 #define EFX_PCIE_LINK_SPEED_GEN2 2
163 #define EFX_PCIE_LINK_SPEED_GEN3 3
165 typedef enum efx_pcie_link_performance_e {
166 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
167 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
168 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
169 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
170 } efx_pcie_link_performance_t;
172 extern __checkReturn efx_rc_t
173 efx_nic_calculate_pcie_link_bandwidth(
174 __in uint32_t pcie_link_width,
175 __in uint32_t pcie_link_gen,
176 __out uint32_t *bandwidth_mbpsp);
178 extern __checkReturn efx_rc_t
179 efx_nic_check_pcie_link_speed(
181 __in uint32_t pcie_link_width,
182 __in uint32_t pcie_link_gen,
183 __out efx_pcie_link_performance_t *resultp);
187 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
189 typedef enum efx_mcdi_exception_e {
190 EFX_MCDI_EXCEPTION_MC_REBOOT,
191 EFX_MCDI_EXCEPTION_MC_BADASSERT,
192 } efx_mcdi_exception_t;
194 #if EFSYS_OPT_MCDI_LOGGING
195 typedef enum efx_log_msg_e {
197 EFX_LOG_MCDI_REQUEST,
198 EFX_LOG_MCDI_RESPONSE,
200 #endif /* EFSYS_OPT_MCDI_LOGGING */
202 typedef struct efx_mcdi_transport_s {
204 efsys_mem_t *emt_dma_mem;
205 void (*emt_execute)(void *, efx_mcdi_req_t *);
206 void (*emt_ev_cpl)(void *);
207 void (*emt_exception)(void *, efx_mcdi_exception_t);
208 #if EFSYS_OPT_MCDI_LOGGING
209 void (*emt_logger)(void *, efx_log_msg_t,
210 void *, size_t, void *, size_t);
211 #endif /* EFSYS_OPT_MCDI_LOGGING */
212 #if EFSYS_OPT_MCDI_PROXY_AUTH
213 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
214 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
215 } efx_mcdi_transport_t;
217 extern __checkReturn efx_rc_t
220 __in const efx_mcdi_transport_t *mtp);
222 extern __checkReturn efx_rc_t
224 __in efx_nic_t *enp);
228 __in efx_nic_t *enp);
231 efx_mcdi_get_timeout(
233 __in efx_mcdi_req_t *emrp,
234 __out uint32_t *usec_timeoutp);
237 efx_mcdi_request_start(
239 __in efx_mcdi_req_t *emrp,
240 __in boolean_t ev_cpl);
242 extern __checkReturn boolean_t
243 efx_mcdi_request_poll(
244 __in efx_nic_t *enp);
246 extern __checkReturn boolean_t
247 efx_mcdi_request_abort(
248 __in efx_nic_t *enp);
252 __in efx_nic_t *enp);
254 #endif /* EFSYS_OPT_MCDI */
258 #define EFX_NINTR_SIENA 1024
260 typedef enum efx_intr_type_e {
261 EFX_INTR_INVALID = 0,
267 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
269 extern __checkReturn efx_rc_t
272 __in efx_intr_type_t type,
273 __in efsys_mem_t *esmp);
277 __in efx_nic_t *enp);
281 __in efx_nic_t *enp);
284 efx_intr_disable_unlocked(
285 __in efx_nic_t *enp);
287 #define EFX_INTR_NEVQS 32
289 extern __checkReturn efx_rc_t
292 __in unsigned int level);
295 efx_intr_status_line(
297 __out boolean_t *fatalp,
298 __out uint32_t *maskp);
301 efx_intr_status_message(
303 __in unsigned int message,
304 __out boolean_t *fatalp);
308 __in efx_nic_t *enp);
312 __in efx_nic_t *enp);
316 typedef enum efx_link_mode_e {
317 EFX_LINK_UNKNOWN = 0,
330 #define EFX_MAC_ADDR_LEN 6
332 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
334 #define EFX_MAC_MULTICAST_LIST_MAX 256
336 #define EFX_MAC_SDU_MAX 9202
338 #define EFX_MAC_PDU_ADJUSTMENT \
342 + /* bug16011 */ 16) \
344 #define EFX_MAC_PDU(_sdu) \
345 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
348 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
349 * the SDU rounded up slightly.
351 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
353 #define EFX_MAC_PDU_MIN 60
354 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
356 extern __checkReturn efx_rc_t
361 extern __checkReturn efx_rc_t
366 extern __checkReturn efx_rc_t
371 extern __checkReturn efx_rc_t
374 __in boolean_t all_unicst,
375 __in boolean_t mulcst,
376 __in boolean_t all_mulcst,
377 __in boolean_t brdcst);
379 extern __checkReturn efx_rc_t
380 efx_mac_multicast_list_set(
382 __in_ecount(6*count) uint8_t const *addrs,
385 extern __checkReturn efx_rc_t
386 efx_mac_filter_default_rxq_set(
389 __in boolean_t using_rss);
392 efx_mac_filter_default_rxq_clear(
393 __in efx_nic_t *enp);
395 extern __checkReturn efx_rc_t
398 __in boolean_t enabled);
400 extern __checkReturn efx_rc_t
403 __out boolean_t *mac_upp);
405 #define EFX_FCNTL_RESPOND 0x00000001
406 #define EFX_FCNTL_GENERATE 0x00000002
408 extern __checkReturn efx_rc_t
411 __in unsigned int fcntl,
412 __in boolean_t autoneg);
417 __out unsigned int *fcntl_wantedp,
418 __out unsigned int *fcntl_linkp);
423 typedef enum efx_mon_type_e {
435 __in efx_nic_t *enp);
437 #endif /* EFSYS_OPT_NAMES */
439 extern __checkReturn efx_rc_t
441 __in efx_nic_t *enp);
445 __in efx_nic_t *enp);
449 extern __checkReturn efx_rc_t
451 __in efx_nic_t *enp);
453 extern __checkReturn efx_rc_t
455 __in efx_nic_t *enp);
457 extern __checkReturn efx_rc_t
460 __out_opt efx_link_mode_t *link_modep);
464 __in efx_nic_t *enp);
466 typedef enum efx_phy_cap_type_e {
467 EFX_PHY_CAP_INVALID = 0,
474 EFX_PHY_CAP_10000FDX,
478 EFX_PHY_CAP_40000FDX,
480 } efx_phy_cap_type_t;
483 #define EFX_PHY_CAP_CURRENT 0x00000000
484 #define EFX_PHY_CAP_DEFAULT 0x00000001
485 #define EFX_PHY_CAP_PERM 0x00000002
491 __out uint32_t *maskp);
493 extern __checkReturn efx_rc_t
501 __out uint32_t *maskp);
503 extern __checkReturn efx_rc_t
506 __out uint32_t *ouip);
508 typedef enum efx_phy_media_type_e {
509 EFX_PHY_MEDIA_INVALID = 0,
514 EFX_PHY_MEDIA_SFP_PLUS,
515 EFX_PHY_MEDIA_BASE_T,
516 EFX_PHY_MEDIA_QSFP_PLUS,
518 } efx_phy_media_type_t;
520 /* Get the type of medium currently used. If the board has ports for
521 * modules, a module is present, and we recognise the media type of
522 * the module, then this will be the media type of the module.
523 * Otherwise it will be the media type of the port.
526 efx_phy_media_type_get(
528 __out efx_phy_media_type_t *typep);
531 efx_phy_module_get_info(
533 __in uint8_t dev_addr,
536 __out_bcount(len) uint8_t *data);
539 #define EFX_FEATURE_IPV6 0x00000001
540 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
541 #define EFX_FEATURE_LINK_EVENTS 0x00000004
542 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
543 #define EFX_FEATURE_MCDI 0x00000020
544 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
545 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
546 #define EFX_FEATURE_TURBO 0x00000100
547 #define EFX_FEATURE_MCDI_DMA 0x00000200
548 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
549 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
550 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
551 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
552 #define EFX_FEATURE_PACKED_STREAM 0x00004000
554 typedef struct efx_nic_cfg_s {
555 uint32_t enc_board_type;
556 uint32_t enc_phy_type;
558 char enc_phy_name[21];
560 char enc_phy_revision[21];
561 efx_mon_type_t enc_mon_type;
562 unsigned int enc_features;
563 uint8_t enc_mac_addr[6];
564 uint8_t enc_port; /* PHY port number */
565 uint32_t enc_intr_vec_base;
566 uint32_t enc_intr_limit;
567 uint32_t enc_evq_limit;
568 uint32_t enc_txq_limit;
569 uint32_t enc_rxq_limit;
570 uint32_t enc_txq_max_ndescs;
571 uint32_t enc_buftbl_limit;
572 uint32_t enc_piobuf_limit;
573 uint32_t enc_piobuf_size;
574 uint32_t enc_piobuf_min_alloc_size;
575 uint32_t enc_evq_timer_quantum_ns;
576 uint32_t enc_evq_timer_max_us;
577 uint32_t enc_clk_mult;
578 uint32_t enc_rx_prefix_size;
579 uint32_t enc_rx_buf_align_start;
580 uint32_t enc_rx_buf_align_end;
582 uint8_t enc_mcdi_mdio_channel;
583 #endif /* EFSYS_OPT_MCDI */
584 boolean_t enc_bug26807_workaround;
585 boolean_t enc_bug35388_workaround;
586 boolean_t enc_bug41750_workaround;
587 boolean_t enc_bug61265_workaround;
588 boolean_t enc_rx_batching_enabled;
589 /* Maximum number of descriptors completed in an rx event. */
590 uint32_t enc_rx_batch_max;
591 /* Number of rx descriptors the hardware requires for a push. */
592 uint32_t enc_rx_push_align;
594 * Maximum number of bytes into the packet the TCP header can start for
595 * the hardware to apply TSO packet edits.
597 uint32_t enc_tx_tso_tcp_header_offset_limit;
598 boolean_t enc_fw_assisted_tso_enabled;
599 boolean_t enc_fw_assisted_tso_v2_enabled;
600 /* Number of TSO contexts on the NIC (FATSOv2) */
601 uint32_t enc_fw_assisted_tso_v2_n_contexts;
602 boolean_t enc_hw_tx_insert_vlan_enabled;
603 /* Number of PFs on the NIC */
604 uint32_t enc_hw_pf_count;
605 /* Datapath firmware vadapter/vport/vswitch support */
606 boolean_t enc_datapath_cap_evb;
607 boolean_t enc_rx_disable_scatter_supported;
608 boolean_t enc_allow_set_mac_with_installed_filters;
609 boolean_t enc_enhanced_set_mac_supported;
610 boolean_t enc_init_evq_v2_supported;
611 boolean_t enc_rx_packed_stream_supported;
612 boolean_t enc_rx_var_packed_stream_supported;
613 boolean_t enc_pm_and_rxdp_counters;
614 boolean_t enc_mac_stats_40g_tx_size_bins;
615 /* External port identifier */
616 uint8_t enc_external_port;
617 uint32_t enc_mcdi_max_payload_length;
618 /* VPD may be per-PF or global */
619 boolean_t enc_vpd_is_global;
620 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
621 uint32_t enc_required_pcie_bandwidth_mbps;
622 uint32_t enc_max_pcie_link_gen;
623 /* Firmware verifies integrity of NVRAM updates */
624 uint32_t enc_fw_verified_nvram_update_required;
627 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
628 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
630 #define EFX_PCI_FUNCTION(_encp) \
631 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
633 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
635 extern const efx_nic_cfg_t *
637 __in efx_nic_t *enp);
639 /* Driver resource limits (minimum required/maximum usable). */
640 typedef struct efx_drv_limits_s {
641 uint32_t edl_min_evq_count;
642 uint32_t edl_max_evq_count;
644 uint32_t edl_min_rxq_count;
645 uint32_t edl_max_rxq_count;
647 uint32_t edl_min_txq_count;
648 uint32_t edl_max_txq_count;
650 /* PIO blocks (sub-allocated from piobuf) */
651 uint32_t edl_min_pio_alloc_size;
652 uint32_t edl_max_pio_alloc_count;
655 extern __checkReturn efx_rc_t
656 efx_nic_set_drv_limits(
657 __inout efx_nic_t *enp,
658 __in efx_drv_limits_t *edlp);
660 typedef enum efx_nic_region_e {
661 EFX_REGION_VI, /* Memory BAR UC mapping */
662 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
665 extern __checkReturn efx_rc_t
666 efx_nic_get_bar_region(
668 __in efx_nic_region_t region,
669 __out uint32_t *offsetp,
670 __out size_t *sizep);
672 extern __checkReturn efx_rc_t
675 __out uint32_t *evq_countp,
676 __out uint32_t *rxq_countp,
677 __out uint32_t *txq_countp);
682 extern __checkReturn efx_rc_t
683 efx_sram_buf_tbl_set(
686 __in efsys_mem_t *esmp,
690 efx_sram_buf_tbl_clear(
695 #define EFX_BUF_TBL_SIZE 0x20000
697 #define EFX_BUF_SIZE 4096
701 typedef struct efx_evq_s efx_evq_t;
703 extern __checkReturn efx_rc_t
705 __in efx_nic_t *enp);
709 __in efx_nic_t *enp);
711 #define EFX_EVQ_MAXNEVS 32768
712 #define EFX_EVQ_MINNEVS 512
714 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
715 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
717 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
718 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
719 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
720 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
722 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
723 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
724 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
726 extern __checkReturn efx_rc_t
729 __in unsigned int index,
730 __in efsys_mem_t *esmp,
735 __deref_out efx_evq_t **eepp);
742 typedef __checkReturn boolean_t
743 (*efx_initialized_ev_t)(
746 #define EFX_PKT_UNICAST 0x0004
747 #define EFX_PKT_START 0x0008
749 #define EFX_PKT_VLAN_TAGGED 0x0010
750 #define EFX_CKSUM_TCPUDP 0x0020
751 #define EFX_CKSUM_IPV4 0x0040
752 #define EFX_PKT_CONT 0x0080
754 #define EFX_CHECK_VLAN 0x0100
755 #define EFX_PKT_TCP 0x0200
756 #define EFX_PKT_UDP 0x0400
757 #define EFX_PKT_IPV4 0x0800
759 #define EFX_PKT_IPV6 0x1000
760 #define EFX_PKT_PREFIX_LEN 0x2000
761 #define EFX_ADDR_MISMATCH 0x4000
762 #define EFX_DISCARD 0x8000
765 * The following flags are used only for packed stream
766 * mode. The values for the flags are reused to fit into 16 bit,
767 * since EFX_PKT_START and EFX_PKT_CONT are never used in
770 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
771 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
774 #define EFX_EV_RX_NLABELS 32
775 #define EFX_EV_TX_NLABELS 32
777 typedef __checkReturn boolean_t
783 __in uint16_t flags);
785 typedef __checkReturn boolean_t
791 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
792 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
793 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
794 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
795 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
796 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
797 #define EFX_EXCEPTION_RX_ERROR 0x00000007
798 #define EFX_EXCEPTION_TX_ERROR 0x00000008
799 #define EFX_EXCEPTION_EV_ERROR 0x00000009
801 typedef __checkReturn boolean_t
802 (*efx_exception_ev_t)(
807 typedef __checkReturn boolean_t
808 (*efx_rxq_flush_done_ev_t)(
810 __in uint32_t rxq_index);
812 typedef __checkReturn boolean_t
813 (*efx_rxq_flush_failed_ev_t)(
815 __in uint32_t rxq_index);
817 typedef __checkReturn boolean_t
818 (*efx_txq_flush_done_ev_t)(
820 __in uint32_t txq_index);
822 typedef __checkReturn boolean_t
823 (*efx_software_ev_t)(
825 __in uint16_t magic);
827 typedef __checkReturn boolean_t
832 #define EFX_SRAM_CLEAR 0
833 #define EFX_SRAM_UPDATE 1
834 #define EFX_SRAM_ILLEGAL_CLEAR 2
836 typedef __checkReturn boolean_t
839 __in uint32_t label);
841 typedef __checkReturn boolean_t
844 __in uint32_t label);
846 typedef __checkReturn boolean_t
847 (*efx_link_change_ev_t)(
849 __in efx_link_mode_t link_mode);
851 typedef struct efx_ev_callbacks_s {
852 efx_initialized_ev_t eec_initialized;
855 efx_exception_ev_t eec_exception;
856 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
857 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
858 efx_txq_flush_done_ev_t eec_txq_flush_done;
859 efx_software_ev_t eec_software;
860 efx_sram_ev_t eec_sram;
861 efx_wake_up_ev_t eec_wake_up;
862 efx_timer_ev_t eec_timer;
863 efx_link_change_ev_t eec_link_change;
864 } efx_ev_callbacks_t;
866 extern __checkReturn boolean_t
869 __in unsigned int count);
874 __inout unsigned int *countp,
875 __in const efx_ev_callbacks_t *eecp,
878 extern __checkReturn efx_rc_t
879 efx_ev_usecs_to_ticks(
881 __in unsigned int usecs,
882 __out unsigned int *ticksp);
884 extern __checkReturn efx_rc_t
887 __in unsigned int us);
889 extern __checkReturn efx_rc_t
892 __in unsigned int count);
896 __in efx_evq_t *eep);
900 extern __checkReturn efx_rc_t
902 __inout efx_nic_t *enp);
906 __in efx_nic_t *enp);
908 extern __checkReturn efx_rc_t
909 efx_pseudo_hdr_pkt_length_get(
911 __in uint8_t *buffer,
912 __out uint16_t *pkt_lengthp);
914 #define EFX_RXQ_MAXNDESCS 4096
915 #define EFX_RXQ_MINNDESCS 512
917 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
918 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
919 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
920 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
922 typedef enum efx_rxq_type_e {
923 EFX_RXQ_TYPE_DEFAULT,
924 EFX_RXQ_TYPE_SCATTER,
925 EFX_RXQ_TYPE_PACKED_STREAM_1M,
926 EFX_RXQ_TYPE_PACKED_STREAM_512K,
927 EFX_RXQ_TYPE_PACKED_STREAM_256K,
928 EFX_RXQ_TYPE_PACKED_STREAM_128K,
929 EFX_RXQ_TYPE_PACKED_STREAM_64K,
933 extern __checkReturn efx_rc_t
936 __in unsigned int index,
937 __in unsigned int label,
938 __in efx_rxq_type_t type,
939 __in efsys_mem_t *esmp,
943 __deref_out efx_rxq_t **erpp);
945 typedef struct efx_buffer_s {
946 efsys_dma_addr_t eb_addr;
951 typedef struct efx_desc_s {
958 __in_ecount(n) efsys_dma_addr_t *addrp,
961 __in unsigned int completed,
962 __in unsigned int added);
967 __in unsigned int added,
968 __inout unsigned int *pushedp);
970 extern __checkReturn efx_rc_t
972 __in efx_rxq_t *erp);
976 __in efx_rxq_t *erp);
980 __in efx_rxq_t *erp);
984 typedef struct efx_txq_s efx_txq_t;
986 extern __checkReturn efx_rc_t
988 __in efx_nic_t *enp);
992 __in efx_nic_t *enp);
994 #define EFX_TXQ_MINNDESCS 512
996 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
997 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
998 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
999 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1001 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1003 #define EFX_TXQ_CKSUM_IPV4 0x0001
1004 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1005 #define EFX_TXQ_FATSOV2 0x0004
1007 extern __checkReturn efx_rc_t
1009 __in efx_nic_t *enp,
1010 __in unsigned int index,
1011 __in unsigned int label,
1012 __in efsys_mem_t *esmp,
1015 __in uint16_t flags,
1016 __in efx_evq_t *eep,
1017 __deref_out efx_txq_t **etpp,
1018 __out unsigned int *addedp);
1020 extern __checkReturn efx_rc_t
1022 __in efx_txq_t *etp,
1023 __in_ecount(n) efx_buffer_t *eb,
1024 __in unsigned int n,
1025 __in unsigned int completed,
1026 __inout unsigned int *addedp);
1028 extern __checkReturn efx_rc_t
1030 __in efx_txq_t *etp,
1031 __in unsigned int ns);
1035 __in efx_txq_t *etp,
1036 __in unsigned int added,
1037 __in unsigned int pushed);
1039 extern __checkReturn efx_rc_t
1041 __in efx_txq_t *etp);
1045 __in efx_txq_t *etp);
1047 extern __checkReturn efx_rc_t
1049 __in efx_txq_t *etp);
1052 efx_tx_qpio_disable(
1053 __in efx_txq_t *etp);
1055 extern __checkReturn efx_rc_t
1057 __in efx_txq_t *etp,
1058 __in_ecount(buf_length) uint8_t *buffer,
1059 __in size_t buf_length,
1060 __in size_t pio_buf_offset);
1062 extern __checkReturn efx_rc_t
1064 __in efx_txq_t *etp,
1065 __in size_t pkt_length,
1066 __in unsigned int completed,
1067 __inout unsigned int *addedp);
1069 extern __checkReturn efx_rc_t
1071 __in efx_txq_t *etp,
1072 __in_ecount(n) efx_desc_t *ed,
1073 __in unsigned int n,
1074 __in unsigned int completed,
1075 __inout unsigned int *addedp);
1078 efx_tx_qdesc_dma_create(
1079 __in efx_txq_t *etp,
1080 __in efsys_dma_addr_t addr,
1083 __out efx_desc_t *edp);
1086 efx_tx_qdesc_tso_create(
1087 __in efx_txq_t *etp,
1088 __in uint16_t ipv4_id,
1089 __in uint32_t tcp_seq,
1090 __in uint8_t tcp_flags,
1091 __out efx_desc_t *edp);
1093 /* Number of FATSOv2 option descriptors */
1094 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1096 /* Maximum number of DMA segments per TSO packet (not superframe) */
1097 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1100 efx_tx_qdesc_tso2_create(
1101 __in efx_txq_t *etp,
1102 __in uint16_t ipv4_id,
1103 __in uint32_t tcp_seq,
1104 __in uint16_t tcp_mss,
1105 __out_ecount(count) efx_desc_t *edp,
1109 efx_tx_qdesc_vlantci_create(
1110 __in efx_txq_t *etp,
1112 __out efx_desc_t *edp);
1116 __in efx_txq_t *etp);
1121 #if EFSYS_OPT_FILTER
1123 #define EFX_ETHER_TYPE_IPV4 0x0800
1124 #define EFX_ETHER_TYPE_IPV6 0x86DD
1126 #define EFX_IPPROTO_TCP 6
1127 #define EFX_IPPROTO_UDP 17
1129 /* Use RSS to spread across multiple queues */
1130 #define EFX_FILTER_FLAG_RX_RSS 0x01
1131 /* Enable RX scatter */
1132 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1134 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1135 * May only be set by the filter implementation for each type.
1136 * A removal request will restore the automatic filter in its place.
1138 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1139 /* Filter is for RX */
1140 #define EFX_FILTER_FLAG_RX 0x08
1141 /* Filter is for TX */
1142 #define EFX_FILTER_FLAG_TX 0x10
1144 typedef unsigned int efx_filter_flags_t;
1146 typedef enum efx_filter_match_flags_e {
1147 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1149 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1151 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1152 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1153 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1154 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1155 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1156 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1157 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1158 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1160 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1161 * I/G bit. Used for RX default
1162 * unicast and multicast/
1163 * broadcast filters. */
1164 } efx_filter_match_flags_t;
1166 typedef enum efx_filter_priority_s {
1167 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1168 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1169 * address list or hardware
1170 * requirements. This may only be used
1171 * by the filter implementation for
1173 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1174 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1175 * client (e.g. SR-IOV, HyperV VMQ etc.)
1177 } efx_filter_priority_t;
1180 * FIXME: All these fields are assumed to be in little-endian byte order.
1181 * It may be better for some to be big-endian. See bug42804.
1184 typedef struct efx_filter_spec_s {
1185 uint32_t efs_match_flags:12;
1186 uint32_t efs_priority:2;
1187 uint32_t efs_flags:6;
1188 uint32_t efs_dmaq_id:12;
1189 uint32_t efs_rss_context;
1190 uint16_t efs_outer_vid;
1191 uint16_t efs_inner_vid;
1192 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1193 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1194 uint16_t efs_ether_type;
1195 uint8_t efs_ip_proto;
1196 uint16_t efs_loc_port;
1197 uint16_t efs_rem_port;
1198 efx_oword_t efs_rem_host;
1199 efx_oword_t efs_loc_host;
1200 } efx_filter_spec_t;
1203 /* Default values for use in filter specifications */
1204 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1205 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1206 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1208 extern __checkReturn efx_rc_t
1210 __in efx_nic_t *enp);
1214 __in efx_nic_t *enp);
1216 extern __checkReturn efx_rc_t
1218 __in efx_nic_t *enp,
1219 __inout efx_filter_spec_t *spec);
1221 extern __checkReturn efx_rc_t
1223 __in efx_nic_t *enp,
1224 __inout efx_filter_spec_t *spec);
1226 extern __checkReturn efx_rc_t
1228 __in efx_nic_t *enp);
1230 extern __checkReturn efx_rc_t
1231 efx_filter_supported_filters(
1232 __in efx_nic_t *enp,
1233 __out uint32_t *list,
1234 __out size_t *length);
1237 efx_filter_spec_init_rx(
1238 __out efx_filter_spec_t *spec,
1239 __in efx_filter_priority_t priority,
1240 __in efx_filter_flags_t flags,
1241 __in efx_rxq_t *erp);
1244 efx_filter_spec_init_tx(
1245 __out efx_filter_spec_t *spec,
1246 __in efx_txq_t *etp);
1248 extern __checkReturn efx_rc_t
1249 efx_filter_spec_set_ipv4_local(
1250 __inout efx_filter_spec_t *spec,
1253 __in uint16_t port);
1255 extern __checkReturn efx_rc_t
1256 efx_filter_spec_set_ipv4_full(
1257 __inout efx_filter_spec_t *spec,
1259 __in uint32_t lhost,
1260 __in uint16_t lport,
1261 __in uint32_t rhost,
1262 __in uint16_t rport);
1264 extern __checkReturn efx_rc_t
1265 efx_filter_spec_set_eth_local(
1266 __inout efx_filter_spec_t *spec,
1268 __in const uint8_t *addr);
1270 extern __checkReturn efx_rc_t
1271 efx_filter_spec_set_uc_def(
1272 __inout efx_filter_spec_t *spec);
1274 extern __checkReturn efx_rc_t
1275 efx_filter_spec_set_mc_def(
1276 __inout efx_filter_spec_t *spec);
1278 #endif /* EFSYS_OPT_FILTER */
1282 extern __checkReturn uint32_t
1284 __in_ecount(count) uint32_t const *input,
1286 __in uint32_t init);
1288 extern __checkReturn uint32_t
1290 __in_ecount(length) uint8_t const *input,
1292 __in uint32_t init);
1300 #endif /* _SYS_EFX_H */