1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_check.h"
13 #include "efx_phy_ids.h"
19 #define EFX_STATIC_ASSERT(_cond) \
20 ((void)sizeof (char[(_cond) ? 1 : -1]))
22 #define EFX_ARRAY_SIZE(_array) \
23 (sizeof (_array) / sizeof ((_array)[0]))
25 #define EFX_FIELD_OFFSET(_type, _field) \
26 ((size_t)&(((_type *)0)->_field))
28 /* The macro expands divider twice */
29 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
33 typedef __success(return == 0) int efx_rc_t;
38 typedef enum efx_family_e {
40 EFX_FAMILY_FALCON, /* Obsolete and not supported */
42 EFX_FAMILY_HUNTINGTON,
48 extern __checkReturn efx_rc_t
52 __out efx_family_t *efp,
53 __out unsigned int *membarp);
56 #define EFX_PCI_VENID_SFC 0x1924
58 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
60 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
61 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
62 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
64 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
65 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
66 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
68 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
69 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
71 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
72 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
73 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
75 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
76 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
77 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
80 #define EFX_MEM_BAR_SIENA 2
82 #define EFX_MEM_BAR_HUNTINGTON_PF 2
83 #define EFX_MEM_BAR_HUNTINGTON_VF 0
85 #define EFX_MEM_BAR_MEDFORD_PF 2
86 #define EFX_MEM_BAR_MEDFORD_VF 0
88 #define EFX_MEM_BAR_MEDFORD2 0
109 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
110 extern __checkReturn uint32_t
112 __in uint32_t crc_init,
113 __in_ecount(length) uint8_t const *input,
117 /* Type prototypes */
119 typedef struct efx_rxq_s efx_rxq_t;
123 typedef struct efx_nic_s efx_nic_t;
125 extern __checkReturn efx_rc_t
127 __in efx_family_t family,
128 __in efsys_identifier_t *esip,
129 __in efsys_bar_t *esbp,
130 __in efsys_lock_t *eslp,
131 __deref_out efx_nic_t **enpp);
133 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
134 typedef enum efx_fw_variant_e {
135 EFX_FW_VARIANT_FULL_FEATURED,
136 EFX_FW_VARIANT_LOW_LATENCY,
137 EFX_FW_VARIANT_PACKED_STREAM,
138 EFX_FW_VARIANT_HIGH_TX_RATE,
139 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
140 EFX_FW_VARIANT_RULES_ENGINE,
142 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
145 extern __checkReturn efx_rc_t
148 __in efx_fw_variant_t efv);
150 extern __checkReturn efx_rc_t
152 __in efx_nic_t *enp);
154 extern __checkReturn efx_rc_t
156 __in efx_nic_t *enp);
160 extern __checkReturn efx_rc_t
161 efx_nic_register_test(
162 __in efx_nic_t *enp);
164 #endif /* EFSYS_OPT_DIAG */
168 __in efx_nic_t *enp);
172 __in efx_nic_t *enp);
176 __in efx_nic_t *enp);
178 #define EFX_PCIE_LINK_SPEED_GEN1 1
179 #define EFX_PCIE_LINK_SPEED_GEN2 2
180 #define EFX_PCIE_LINK_SPEED_GEN3 3
182 typedef enum efx_pcie_link_performance_e {
183 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
184 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
185 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
186 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
187 } efx_pcie_link_performance_t;
189 extern __checkReturn efx_rc_t
190 efx_nic_calculate_pcie_link_bandwidth(
191 __in uint32_t pcie_link_width,
192 __in uint32_t pcie_link_gen,
193 __out uint32_t *bandwidth_mbpsp);
195 extern __checkReturn efx_rc_t
196 efx_nic_check_pcie_link_speed(
198 __in uint32_t pcie_link_width,
199 __in uint32_t pcie_link_gen,
200 __out efx_pcie_link_performance_t *resultp);
204 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
205 /* Huntington and Medford require MCDIv2 commands */
206 #define WITH_MCDI_V2 1
209 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
211 typedef enum efx_mcdi_exception_e {
212 EFX_MCDI_EXCEPTION_MC_REBOOT,
213 EFX_MCDI_EXCEPTION_MC_BADASSERT,
214 } efx_mcdi_exception_t;
216 #if EFSYS_OPT_MCDI_LOGGING
217 typedef enum efx_log_msg_e {
219 EFX_LOG_MCDI_REQUEST,
220 EFX_LOG_MCDI_RESPONSE,
222 #endif /* EFSYS_OPT_MCDI_LOGGING */
224 typedef struct efx_mcdi_transport_s {
226 efsys_mem_t *emt_dma_mem;
227 void (*emt_execute)(void *, efx_mcdi_req_t *);
228 void (*emt_ev_cpl)(void *);
229 void (*emt_exception)(void *, efx_mcdi_exception_t);
230 #if EFSYS_OPT_MCDI_LOGGING
231 void (*emt_logger)(void *, efx_log_msg_t,
232 void *, size_t, void *, size_t);
233 #endif /* EFSYS_OPT_MCDI_LOGGING */
234 #if EFSYS_OPT_MCDI_PROXY_AUTH
235 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
236 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
237 } efx_mcdi_transport_t;
239 extern __checkReturn efx_rc_t
242 __in const efx_mcdi_transport_t *mtp);
244 extern __checkReturn efx_rc_t
246 __in efx_nic_t *enp);
250 __in efx_nic_t *enp);
253 efx_mcdi_get_timeout(
255 __in efx_mcdi_req_t *emrp,
256 __out uint32_t *usec_timeoutp);
259 efx_mcdi_request_start(
261 __in efx_mcdi_req_t *emrp,
262 __in boolean_t ev_cpl);
264 extern __checkReturn boolean_t
265 efx_mcdi_request_poll(
266 __in efx_nic_t *enp);
268 extern __checkReturn boolean_t
269 efx_mcdi_request_abort(
270 __in efx_nic_t *enp);
274 __in efx_nic_t *enp);
276 #endif /* EFSYS_OPT_MCDI */
280 #define EFX_NINTR_SIENA 1024
282 typedef enum efx_intr_type_e {
283 EFX_INTR_INVALID = 0,
289 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
291 extern __checkReturn efx_rc_t
294 __in efx_intr_type_t type,
295 __in efsys_mem_t *esmp);
299 __in efx_nic_t *enp);
303 __in efx_nic_t *enp);
306 efx_intr_disable_unlocked(
307 __in efx_nic_t *enp);
309 #define EFX_INTR_NEVQS 32
311 extern __checkReturn efx_rc_t
314 __in unsigned int level);
317 efx_intr_status_line(
319 __out boolean_t *fatalp,
320 __out uint32_t *maskp);
323 efx_intr_status_message(
325 __in unsigned int message,
326 __out boolean_t *fatalp);
330 __in efx_nic_t *enp);
334 __in efx_nic_t *enp);
338 #if EFSYS_OPT_MAC_STATS
340 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
341 typedef enum efx_mac_stat_e {
344 EFX_MAC_RX_UNICST_PKTS,
345 EFX_MAC_RX_MULTICST_PKTS,
346 EFX_MAC_RX_BRDCST_PKTS,
347 EFX_MAC_RX_PAUSE_PKTS,
348 EFX_MAC_RX_LE_64_PKTS,
349 EFX_MAC_RX_65_TO_127_PKTS,
350 EFX_MAC_RX_128_TO_255_PKTS,
351 EFX_MAC_RX_256_TO_511_PKTS,
352 EFX_MAC_RX_512_TO_1023_PKTS,
353 EFX_MAC_RX_1024_TO_15XX_PKTS,
354 EFX_MAC_RX_GE_15XX_PKTS,
356 EFX_MAC_RX_FCS_ERRORS,
357 EFX_MAC_RX_DROP_EVENTS,
358 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
359 EFX_MAC_RX_SYMBOL_ERRORS,
360 EFX_MAC_RX_ALIGN_ERRORS,
361 EFX_MAC_RX_INTERNAL_ERRORS,
362 EFX_MAC_RX_JABBER_PKTS,
363 EFX_MAC_RX_LANE0_CHAR_ERR,
364 EFX_MAC_RX_LANE1_CHAR_ERR,
365 EFX_MAC_RX_LANE2_CHAR_ERR,
366 EFX_MAC_RX_LANE3_CHAR_ERR,
367 EFX_MAC_RX_LANE0_DISP_ERR,
368 EFX_MAC_RX_LANE1_DISP_ERR,
369 EFX_MAC_RX_LANE2_DISP_ERR,
370 EFX_MAC_RX_LANE3_DISP_ERR,
371 EFX_MAC_RX_MATCH_FAULT,
372 EFX_MAC_RX_NODESC_DROP_CNT,
375 EFX_MAC_TX_UNICST_PKTS,
376 EFX_MAC_TX_MULTICST_PKTS,
377 EFX_MAC_TX_BRDCST_PKTS,
378 EFX_MAC_TX_PAUSE_PKTS,
379 EFX_MAC_TX_LE_64_PKTS,
380 EFX_MAC_TX_65_TO_127_PKTS,
381 EFX_MAC_TX_128_TO_255_PKTS,
382 EFX_MAC_TX_256_TO_511_PKTS,
383 EFX_MAC_TX_512_TO_1023_PKTS,
384 EFX_MAC_TX_1024_TO_15XX_PKTS,
385 EFX_MAC_TX_GE_15XX_PKTS,
387 EFX_MAC_TX_SGL_COL_PKTS,
388 EFX_MAC_TX_MULT_COL_PKTS,
389 EFX_MAC_TX_EX_COL_PKTS,
390 EFX_MAC_TX_LATE_COL_PKTS,
392 EFX_MAC_TX_EX_DEF_PKTS,
393 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
394 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
395 EFX_MAC_PM_TRUNC_VFIFO_FULL,
396 EFX_MAC_PM_DISCARD_VFIFO_FULL,
397 EFX_MAC_PM_TRUNC_QBB,
398 EFX_MAC_PM_DISCARD_QBB,
399 EFX_MAC_PM_DISCARD_MAPPING,
400 EFX_MAC_RXDP_Q_DISABLED_PKTS,
401 EFX_MAC_RXDP_DI_DROPPED_PKTS,
402 EFX_MAC_RXDP_STREAMING_PKTS,
403 EFX_MAC_RXDP_HLB_FETCH,
404 EFX_MAC_RXDP_HLB_WAIT,
405 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
406 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
407 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
408 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
409 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
410 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
411 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
412 EFX_MAC_VADAPTER_RX_BAD_BYTES,
413 EFX_MAC_VADAPTER_RX_OVERFLOW,
414 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
415 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
416 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
417 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
418 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
419 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
420 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
421 EFX_MAC_VADAPTER_TX_BAD_BYTES,
422 EFX_MAC_VADAPTER_TX_OVERFLOW,
423 EFX_MAC_FEC_UNCORRECTED_ERRORS,
424 EFX_MAC_FEC_CORRECTED_ERRORS,
425 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
426 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
427 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
428 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
429 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
430 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
431 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
432 EFX_MAC_CTPIO_OVERFLOW_FAIL,
433 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
434 EFX_MAC_CTPIO_TIMEOUT_FAIL,
435 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
436 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
437 EFX_MAC_CTPIO_INVALID_WR_FAIL,
438 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
439 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
440 EFX_MAC_CTPIO_RUNT_FALLBACK,
441 EFX_MAC_CTPIO_SUCCESS,
442 EFX_MAC_CTPIO_FALLBACK,
443 EFX_MAC_CTPIO_POISON,
445 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
446 EFX_MAC_RXDP_HLB_IDLE,
447 EFX_MAC_RXDP_HLB_TIMEOUT,
451 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
453 #endif /* EFSYS_OPT_MAC_STATS */
455 typedef enum efx_link_mode_e {
456 EFX_LINK_UNKNOWN = 0,
472 #define EFX_MAC_ADDR_LEN 6
474 #define EFX_VNI_OR_VSID_LEN 3
476 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
478 #define EFX_MAC_MULTICAST_LIST_MAX 256
480 #define EFX_MAC_SDU_MAX 9202
482 #define EFX_MAC_PDU_ADJUSTMENT \
486 + /* bug16011 */ 16) \
488 #define EFX_MAC_PDU(_sdu) \
489 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
492 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
493 * the SDU rounded up slightly.
495 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
497 #define EFX_MAC_PDU_MIN 60
498 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
500 extern __checkReturn efx_rc_t
505 extern __checkReturn efx_rc_t
510 extern __checkReturn efx_rc_t
515 extern __checkReturn efx_rc_t
518 __in boolean_t all_unicst,
519 __in boolean_t mulcst,
520 __in boolean_t all_mulcst,
521 __in boolean_t brdcst);
523 extern __checkReturn efx_rc_t
524 efx_mac_multicast_list_set(
526 __in_ecount(6*count) uint8_t const *addrs,
529 extern __checkReturn efx_rc_t
530 efx_mac_filter_default_rxq_set(
533 __in boolean_t using_rss);
536 efx_mac_filter_default_rxq_clear(
537 __in efx_nic_t *enp);
539 extern __checkReturn efx_rc_t
542 __in boolean_t enabled);
544 extern __checkReturn efx_rc_t
547 __out boolean_t *mac_upp);
549 #define EFX_FCNTL_RESPOND 0x00000001
550 #define EFX_FCNTL_GENERATE 0x00000002
552 extern __checkReturn efx_rc_t
555 __in unsigned int fcntl,
556 __in boolean_t autoneg);
561 __out unsigned int *fcntl_wantedp,
562 __out unsigned int *fcntl_linkp);
565 #if EFSYS_OPT_MAC_STATS
569 extern __checkReturn const char *
572 __in unsigned int id);
574 #endif /* EFSYS_OPT_NAMES */
576 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
578 #define EFX_MAC_STATS_MASK_NPAGES \
579 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
580 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
583 * Get mask of MAC statistics supported by the hardware.
585 * If mask_size is insufficient to return the mask, EINVAL error is
586 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
587 * (which is sizeof (uint32_t)) is sufficient.
589 extern __checkReturn efx_rc_t
590 efx_mac_stats_get_mask(
592 __out_bcount(mask_size) uint32_t *maskp,
593 __in size_t mask_size);
595 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
596 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
597 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
600 extern __checkReturn efx_rc_t
602 __in efx_nic_t *enp);
605 * Upload mac statistics supported by the hardware into the given buffer.
607 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
608 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
610 * The hardware will only DMA statistics that it understands (of course).
611 * Drivers should not make any assumptions about which statistics are
612 * supported, especially when the statistics are generated by firmware.
614 * Thus, drivers should zero this buffer before use, so that not-understood
615 * statistics read back as zero.
617 extern __checkReturn efx_rc_t
618 efx_mac_stats_upload(
620 __in efsys_mem_t *esmp);
622 extern __checkReturn efx_rc_t
623 efx_mac_stats_periodic(
625 __in efsys_mem_t *esmp,
626 __in uint16_t period_ms,
627 __in boolean_t events);
629 extern __checkReturn efx_rc_t
630 efx_mac_stats_update(
632 __in efsys_mem_t *esmp,
633 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
634 __inout_opt uint32_t *generationp);
636 #endif /* EFSYS_OPT_MAC_STATS */
640 typedef enum efx_mon_type_e {
652 __in efx_nic_t *enp);
654 #endif /* EFSYS_OPT_NAMES */
656 extern __checkReturn efx_rc_t
658 __in efx_nic_t *enp);
660 #if EFSYS_OPT_MON_STATS
662 #define EFX_MON_STATS_PAGE_SIZE 0x100
663 #define EFX_MON_MASK_ELEMENT_SIZE 32
665 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
666 typedef enum efx_mon_stat_e {
667 EFX_MON_STAT_CONTROLLER_TEMP,
668 EFX_MON_STAT_PHY_COMMON_TEMP,
669 EFX_MON_STAT_CONTROLLER_COOLING,
670 EFX_MON_STAT_PHY0_TEMP,
671 EFX_MON_STAT_PHY0_COOLING,
672 EFX_MON_STAT_PHY1_TEMP,
673 EFX_MON_STAT_PHY1_COOLING,
679 EFX_MON_STAT_IN_12V0,
680 EFX_MON_STAT_IN_1V2A,
681 EFX_MON_STAT_IN_VREF,
682 EFX_MON_STAT_OUT_VAOE,
683 EFX_MON_STAT_AOE_TEMP,
684 EFX_MON_STAT_PSU_AOE_TEMP,
685 EFX_MON_STAT_PSU_TEMP,
691 EFX_MON_STAT_IN_VAOE,
692 EFX_MON_STAT_OUT_IAOE,
693 EFX_MON_STAT_IN_IAOE,
694 EFX_MON_STAT_NIC_POWER,
696 EFX_MON_STAT_IN_I0V9,
697 EFX_MON_STAT_IN_I1V2,
698 EFX_MON_STAT_IN_0V9_ADC,
699 EFX_MON_STAT_CONTROLLER_2_TEMP,
700 EFX_MON_STAT_VREG_INTERNAL_TEMP,
701 EFX_MON_STAT_VREG_0V9_TEMP,
702 EFX_MON_STAT_VREG_1V2_TEMP,
703 EFX_MON_STAT_CONTROLLER_VPTAT,
704 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
705 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
706 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
707 EFX_MON_STAT_AMBIENT_TEMP,
708 EFX_MON_STAT_AIRFLOW,
709 EFX_MON_STAT_VDD08D_VSS08D_CSR,
710 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
711 EFX_MON_STAT_HOTPOINT_TEMP,
712 EFX_MON_STAT_PHY_POWER_PORT0,
713 EFX_MON_STAT_PHY_POWER_PORT1,
714 EFX_MON_STAT_MUM_VCC,
715 EFX_MON_STAT_IN_0V9_A,
716 EFX_MON_STAT_IN_I0V9_A,
717 EFX_MON_STAT_VREG_0V9_A_TEMP,
718 EFX_MON_STAT_IN_0V9_B,
719 EFX_MON_STAT_IN_I0V9_B,
720 EFX_MON_STAT_VREG_0V9_B_TEMP,
721 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
722 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
723 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
724 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
725 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
726 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
727 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
728 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
729 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
730 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
731 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
732 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
733 EFX_MON_STAT_SODIMM_VOUT,
734 EFX_MON_STAT_SODIMM_0_TEMP,
735 EFX_MON_STAT_SODIMM_1_TEMP,
736 EFX_MON_STAT_PHY0_VCC,
737 EFX_MON_STAT_PHY1_VCC,
738 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
739 EFX_MON_STAT_BOARD_FRONT_TEMP,
740 EFX_MON_STAT_BOARD_BACK_TEMP,
741 EFX_MON_STAT_IN_I1V8,
742 EFX_MON_STAT_IN_I2V5,
743 EFX_MON_STAT_IN_I3V3,
744 EFX_MON_STAT_IN_I12V0,
746 EFX_MON_STAT_IN_I1V3,
750 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
752 typedef enum efx_mon_stat_state_e {
753 EFX_MON_STAT_STATE_OK = 0,
754 EFX_MON_STAT_STATE_WARNING = 1,
755 EFX_MON_STAT_STATE_FATAL = 2,
756 EFX_MON_STAT_STATE_BROKEN = 3,
757 EFX_MON_STAT_STATE_NO_READING = 4,
758 } efx_mon_stat_state_t;
760 typedef enum efx_mon_stat_unit_e {
761 EFX_MON_STAT_UNIT_UNKNOWN = 0,
762 EFX_MON_STAT_UNIT_BOOL,
763 EFX_MON_STAT_UNIT_TEMP_C,
764 EFX_MON_STAT_UNIT_VOLTAGE_MV,
765 EFX_MON_STAT_UNIT_CURRENT_MA,
766 EFX_MON_STAT_UNIT_POWER_W,
767 EFX_MON_STAT_UNIT_RPM,
769 } efx_mon_stat_unit_t;
771 typedef struct efx_mon_stat_value_s {
773 efx_mon_stat_state_t emsv_state;
774 efx_mon_stat_unit_t emsv_unit;
775 } efx_mon_stat_value_t;
777 typedef enum efx_mon_stat_portmask_e {
778 EFX_MON_STAT_PORTMAP_NONE = 0,
779 EFX_MON_STAT_PORTMAP_PORT0 = 1,
780 EFX_MON_STAT_PORTMAP_PORT1 = 2,
781 EFX_MON_STAT_PORTMAP_PORT2 = 3,
782 EFX_MON_STAT_PORTMAP_PORT3 = 4,
783 EFX_MON_STAT_PORTMAP_ALL = (-1),
784 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
785 } efx_mon_stat_portmask_t;
792 __in efx_mon_stat_t id);
795 efx_mon_stat_description(
797 __in efx_mon_stat_t id);
799 #endif /* EFSYS_OPT_NAMES */
801 extern __checkReturn boolean_t
802 efx_mon_mcdi_to_efx_stat(
804 __out efx_mon_stat_t *statp);
806 extern __checkReturn boolean_t
807 efx_mon_get_stat_unit(
808 __in efx_mon_stat_t stat,
809 __out efx_mon_stat_unit_t *unitp);
811 extern __checkReturn boolean_t
812 efx_mon_get_stat_portmap(
813 __in efx_mon_stat_t stat,
814 __out efx_mon_stat_portmask_t *maskp);
816 extern __checkReturn efx_rc_t
817 efx_mon_stats_update(
819 __in efsys_mem_t *esmp,
820 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
822 #endif /* EFSYS_OPT_MON_STATS */
826 __in efx_nic_t *enp);
830 extern __checkReturn efx_rc_t
832 __in efx_nic_t *enp);
834 #if EFSYS_OPT_PHY_LED_CONTROL
836 typedef enum efx_phy_led_mode_e {
837 EFX_PHY_LED_DEFAULT = 0,
842 } efx_phy_led_mode_t;
844 extern __checkReturn efx_rc_t
847 __in efx_phy_led_mode_t mode);
849 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
851 extern __checkReturn efx_rc_t
853 __in efx_nic_t *enp);
855 #if EFSYS_OPT_LOOPBACK
857 typedef enum efx_loopback_type_e {
858 EFX_LOOPBACK_OFF = 0,
859 EFX_LOOPBACK_DATA = 1,
860 EFX_LOOPBACK_GMAC = 2,
861 EFX_LOOPBACK_XGMII = 3,
862 EFX_LOOPBACK_XGXS = 4,
863 EFX_LOOPBACK_XAUI = 5,
864 EFX_LOOPBACK_GMII = 6,
865 EFX_LOOPBACK_SGMII = 7,
866 EFX_LOOPBACK_XGBR = 8,
867 EFX_LOOPBACK_XFI = 9,
868 EFX_LOOPBACK_XAUI_FAR = 10,
869 EFX_LOOPBACK_GMII_FAR = 11,
870 EFX_LOOPBACK_SGMII_FAR = 12,
871 EFX_LOOPBACK_XFI_FAR = 13,
872 EFX_LOOPBACK_GPHY = 14,
873 EFX_LOOPBACK_PHY_XS = 15,
874 EFX_LOOPBACK_PCS = 16,
875 EFX_LOOPBACK_PMA_PMD = 17,
876 EFX_LOOPBACK_XPORT = 18,
877 EFX_LOOPBACK_XGMII_WS = 19,
878 EFX_LOOPBACK_XAUI_WS = 20,
879 EFX_LOOPBACK_XAUI_WS_FAR = 21,
880 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
881 EFX_LOOPBACK_GMII_WS = 23,
882 EFX_LOOPBACK_XFI_WS = 24,
883 EFX_LOOPBACK_XFI_WS_FAR = 25,
884 EFX_LOOPBACK_PHYXS_WS = 26,
885 EFX_LOOPBACK_PMA_INT = 27,
886 EFX_LOOPBACK_SD_NEAR = 28,
887 EFX_LOOPBACK_SD_FAR = 29,
888 EFX_LOOPBACK_PMA_INT_WS = 30,
889 EFX_LOOPBACK_SD_FEP2_WS = 31,
890 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
891 EFX_LOOPBACK_SD_FEP_WS = 33,
892 EFX_LOOPBACK_SD_FES_WS = 34,
893 EFX_LOOPBACK_AOE_INT_NEAR = 35,
894 EFX_LOOPBACK_DATA_WS = 36,
895 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
897 } efx_loopback_type_t;
899 typedef enum efx_loopback_kind_e {
900 EFX_LOOPBACK_KIND_OFF = 0,
901 EFX_LOOPBACK_KIND_ALL,
902 EFX_LOOPBACK_KIND_MAC,
903 EFX_LOOPBACK_KIND_PHY,
905 } efx_loopback_kind_t;
909 __in efx_loopback_kind_t loopback_kind,
910 __out efx_qword_t *maskp);
912 extern __checkReturn efx_rc_t
913 efx_port_loopback_set(
915 __in efx_link_mode_t link_mode,
916 __in efx_loopback_type_t type);
920 extern __checkReturn const char *
921 efx_loopback_type_name(
923 __in efx_loopback_type_t type);
925 #endif /* EFSYS_OPT_NAMES */
927 #endif /* EFSYS_OPT_LOOPBACK */
929 extern __checkReturn efx_rc_t
932 __out_opt efx_link_mode_t *link_modep);
936 __in efx_nic_t *enp);
938 typedef enum efx_phy_cap_type_e {
939 EFX_PHY_CAP_INVALID = 0,
946 EFX_PHY_CAP_10000FDX,
950 EFX_PHY_CAP_40000FDX,
952 EFX_PHY_CAP_100000FDX,
953 EFX_PHY_CAP_25000FDX,
954 EFX_PHY_CAP_50000FDX,
955 EFX_PHY_CAP_BASER_FEC,
956 EFX_PHY_CAP_BASER_FEC_REQUESTED,
958 EFX_PHY_CAP_RS_FEC_REQUESTED,
959 EFX_PHY_CAP_25G_BASER_FEC,
960 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
962 } efx_phy_cap_type_t;
965 #define EFX_PHY_CAP_CURRENT 0x00000000
966 #define EFX_PHY_CAP_DEFAULT 0x00000001
967 #define EFX_PHY_CAP_PERM 0x00000002
973 __out uint32_t *maskp);
975 extern __checkReturn efx_rc_t
983 __out uint32_t *maskp);
985 extern __checkReturn efx_rc_t
988 __out uint32_t *ouip);
990 typedef enum efx_phy_media_type_e {
991 EFX_PHY_MEDIA_INVALID = 0,
996 EFX_PHY_MEDIA_SFP_PLUS,
997 EFX_PHY_MEDIA_BASE_T,
998 EFX_PHY_MEDIA_QSFP_PLUS,
1000 } efx_phy_media_type_t;
1003 * Get the type of medium currently used. If the board has ports for
1004 * modules, a module is present, and we recognise the media type of
1005 * the module, then this will be the media type of the module.
1006 * Otherwise it will be the media type of the port.
1009 efx_phy_media_type_get(
1010 __in efx_nic_t *enp,
1011 __out efx_phy_media_type_t *typep);
1013 extern __checkReturn efx_rc_t
1014 efx_phy_module_get_info(
1015 __in efx_nic_t *enp,
1016 __in uint8_t dev_addr,
1017 __in uint8_t offset,
1019 __out_bcount(len) uint8_t *data);
1021 #if EFSYS_OPT_PHY_STATS
1023 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1024 typedef enum efx_phy_stat_e {
1026 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1027 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1028 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1029 EFX_PHY_STAT_PMA_PMD_REV_A,
1030 EFX_PHY_STAT_PMA_PMD_REV_B,
1031 EFX_PHY_STAT_PMA_PMD_REV_C,
1032 EFX_PHY_STAT_PMA_PMD_REV_D,
1033 EFX_PHY_STAT_PCS_LINK_UP,
1034 EFX_PHY_STAT_PCS_RX_FAULT,
1035 EFX_PHY_STAT_PCS_TX_FAULT,
1036 EFX_PHY_STAT_PCS_BER,
1037 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1038 EFX_PHY_STAT_PHY_XS_LINK_UP,
1039 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1040 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1041 EFX_PHY_STAT_PHY_XS_ALIGN,
1042 EFX_PHY_STAT_PHY_XS_SYNC_A,
1043 EFX_PHY_STAT_PHY_XS_SYNC_B,
1044 EFX_PHY_STAT_PHY_XS_SYNC_C,
1045 EFX_PHY_STAT_PHY_XS_SYNC_D,
1046 EFX_PHY_STAT_AN_LINK_UP,
1047 EFX_PHY_STAT_AN_MASTER,
1048 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1049 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1050 EFX_PHY_STAT_CL22EXT_LINK_UP,
1055 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1056 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1057 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1058 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1059 EFX_PHY_STAT_AN_COMPLETE,
1060 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1061 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1062 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1063 EFX_PHY_STAT_PCS_FW_VERSION_0,
1064 EFX_PHY_STAT_PCS_FW_VERSION_1,
1065 EFX_PHY_STAT_PCS_FW_VERSION_2,
1066 EFX_PHY_STAT_PCS_FW_VERSION_3,
1067 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1068 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1069 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1070 EFX_PHY_STAT_PCS_OP_MODE,
1074 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1080 __in efx_nic_t *enp,
1081 __in efx_phy_stat_t stat);
1083 #endif /* EFSYS_OPT_NAMES */
1085 #define EFX_PHY_STATS_SIZE 0x100
1087 extern __checkReturn efx_rc_t
1088 efx_phy_stats_update(
1089 __in efx_nic_t *enp,
1090 __in efsys_mem_t *esmp,
1091 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1093 #endif /* EFSYS_OPT_PHY_STATS */
1098 typedef enum efx_bist_type_e {
1099 EFX_BIST_TYPE_UNKNOWN,
1100 EFX_BIST_TYPE_PHY_NORMAL,
1101 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1102 EFX_BIST_TYPE_PHY_CABLE_LONG,
1103 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1104 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1105 EFX_BIST_TYPE_REG, /* Test the register memories */
1106 EFX_BIST_TYPE_NTYPES,
1109 typedef enum efx_bist_result_e {
1110 EFX_BIST_RESULT_UNKNOWN,
1111 EFX_BIST_RESULT_RUNNING,
1112 EFX_BIST_RESULT_PASSED,
1113 EFX_BIST_RESULT_FAILED,
1114 } efx_bist_result_t;
1116 typedef enum efx_phy_cable_status_e {
1117 EFX_PHY_CABLE_STATUS_OK,
1118 EFX_PHY_CABLE_STATUS_INVALID,
1119 EFX_PHY_CABLE_STATUS_OPEN,
1120 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1121 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1122 EFX_PHY_CABLE_STATUS_BUSY,
1123 } efx_phy_cable_status_t;
1125 typedef enum efx_bist_value_e {
1126 EFX_BIST_PHY_CABLE_LENGTH_A,
1127 EFX_BIST_PHY_CABLE_LENGTH_B,
1128 EFX_BIST_PHY_CABLE_LENGTH_C,
1129 EFX_BIST_PHY_CABLE_LENGTH_D,
1130 EFX_BIST_PHY_CABLE_STATUS_A,
1131 EFX_BIST_PHY_CABLE_STATUS_B,
1132 EFX_BIST_PHY_CABLE_STATUS_C,
1133 EFX_BIST_PHY_CABLE_STATUS_D,
1134 EFX_BIST_FAULT_CODE,
1136 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1142 EFX_BIST_MEM_EXPECT,
1143 EFX_BIST_MEM_ACTUAL,
1145 EFX_BIST_MEM_ECC_PARITY,
1146 EFX_BIST_MEM_ECC_FATAL,
1150 extern __checkReturn efx_rc_t
1151 efx_bist_enable_offline(
1152 __in efx_nic_t *enp);
1154 extern __checkReturn efx_rc_t
1156 __in efx_nic_t *enp,
1157 __in efx_bist_type_t type);
1159 extern __checkReturn efx_rc_t
1161 __in efx_nic_t *enp,
1162 __in efx_bist_type_t type,
1163 __out efx_bist_result_t *resultp,
1164 __out_opt uint32_t *value_maskp,
1165 __out_ecount_opt(count) unsigned long *valuesp,
1170 __in efx_nic_t *enp,
1171 __in efx_bist_type_t type);
1173 #endif /* EFSYS_OPT_BIST */
1175 #define EFX_FEATURE_IPV6 0x00000001
1176 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1177 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1178 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1179 #define EFX_FEATURE_MCDI 0x00000020
1180 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1181 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1182 #define EFX_FEATURE_TURBO 0x00000100
1183 #define EFX_FEATURE_MCDI_DMA 0x00000200
1184 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1185 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1186 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1187 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1188 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1190 typedef enum efx_tunnel_protocol_e {
1191 EFX_TUNNEL_PROTOCOL_NONE = 0,
1192 EFX_TUNNEL_PROTOCOL_VXLAN,
1193 EFX_TUNNEL_PROTOCOL_GENEVE,
1194 EFX_TUNNEL_PROTOCOL_NVGRE,
1196 } efx_tunnel_protocol_t;
1198 typedef enum efx_vi_window_shift_e {
1199 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1200 EFX_VI_WINDOW_SHIFT_8K = 13,
1201 EFX_VI_WINDOW_SHIFT_16K = 14,
1202 EFX_VI_WINDOW_SHIFT_64K = 16,
1203 } efx_vi_window_shift_t;
1205 typedef struct efx_nic_cfg_s {
1206 uint32_t enc_board_type;
1207 uint32_t enc_phy_type;
1209 char enc_phy_name[21];
1211 char enc_phy_revision[21];
1212 efx_mon_type_t enc_mon_type;
1213 #if EFSYS_OPT_MON_STATS
1214 uint32_t enc_mon_stat_dma_buf_size;
1215 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1217 unsigned int enc_features;
1218 efx_vi_window_shift_t enc_vi_window_shift;
1219 uint8_t enc_mac_addr[6];
1220 uint8_t enc_port; /* PHY port number */
1221 uint32_t enc_intr_vec_base;
1222 uint32_t enc_intr_limit;
1223 uint32_t enc_evq_limit;
1224 uint32_t enc_txq_limit;
1225 uint32_t enc_rxq_limit;
1226 uint32_t enc_txq_max_ndescs;
1227 uint32_t enc_buftbl_limit;
1228 uint32_t enc_piobuf_limit;
1229 uint32_t enc_piobuf_size;
1230 uint32_t enc_piobuf_min_alloc_size;
1231 uint32_t enc_evq_timer_quantum_ns;
1232 uint32_t enc_evq_timer_max_us;
1233 uint32_t enc_clk_mult;
1234 uint32_t enc_rx_prefix_size;
1235 uint32_t enc_rx_buf_align_start;
1236 uint32_t enc_rx_buf_align_end;
1237 uint32_t enc_rx_scale_max_exclusive_contexts;
1239 * Mask of supported hash algorithms.
1240 * Hash algorithm types are used as the bit indices.
1242 uint32_t enc_rx_scale_hash_alg_mask;
1244 * Indicates whether port numbers can be included to the
1245 * input data for hash computation.
1247 boolean_t enc_rx_scale_l4_hash_supported;
1248 boolean_t enc_rx_scale_additional_modes_supported;
1249 #if EFSYS_OPT_LOOPBACK
1250 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1251 #endif /* EFSYS_OPT_LOOPBACK */
1252 #if EFSYS_OPT_PHY_FLAGS
1253 uint32_t enc_phy_flags_mask;
1254 #endif /* EFSYS_OPT_PHY_FLAGS */
1255 #if EFSYS_OPT_PHY_LED_CONTROL
1256 uint32_t enc_led_mask;
1257 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1258 #if EFSYS_OPT_PHY_STATS
1259 uint64_t enc_phy_stat_mask;
1260 #endif /* EFSYS_OPT_PHY_STATS */
1262 uint8_t enc_mcdi_mdio_channel;
1263 #if EFSYS_OPT_PHY_STATS
1264 uint32_t enc_mcdi_phy_stat_mask;
1265 #endif /* EFSYS_OPT_PHY_STATS */
1266 #if EFSYS_OPT_MON_STATS
1267 uint32_t *enc_mcdi_sensor_maskp;
1268 uint32_t enc_mcdi_sensor_mask_size;
1269 #endif /* EFSYS_OPT_MON_STATS */
1270 #endif /* EFSYS_OPT_MCDI */
1272 uint32_t enc_bist_mask;
1273 #endif /* EFSYS_OPT_BIST */
1274 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1277 uint32_t enc_privilege_mask;
1278 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1279 boolean_t enc_bug26807_workaround;
1280 boolean_t enc_bug35388_workaround;
1281 boolean_t enc_bug41750_workaround;
1282 boolean_t enc_bug61265_workaround;
1283 boolean_t enc_rx_batching_enabled;
1284 /* Maximum number of descriptors completed in an rx event. */
1285 uint32_t enc_rx_batch_max;
1286 /* Number of rx descriptors the hardware requires for a push. */
1287 uint32_t enc_rx_push_align;
1288 /* Maximum amount of data in DMA descriptor */
1289 uint32_t enc_tx_dma_desc_size_max;
1291 * Boundary which DMA descriptor data must not cross or 0 if no
1294 uint32_t enc_tx_dma_desc_boundary;
1296 * Maximum number of bytes into the packet the TCP header can start for
1297 * the hardware to apply TSO packet edits.
1299 uint32_t enc_tx_tso_tcp_header_offset_limit;
1300 boolean_t enc_fw_assisted_tso_enabled;
1301 boolean_t enc_fw_assisted_tso_v2_enabled;
1302 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1303 /* Number of TSO contexts on the NIC (FATSOv2) */
1304 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1305 boolean_t enc_hw_tx_insert_vlan_enabled;
1306 /* Number of PFs on the NIC */
1307 uint32_t enc_hw_pf_count;
1308 /* Datapath firmware vadapter/vport/vswitch support */
1309 boolean_t enc_datapath_cap_evb;
1310 boolean_t enc_rx_disable_scatter_supported;
1311 boolean_t enc_allow_set_mac_with_installed_filters;
1312 boolean_t enc_enhanced_set_mac_supported;
1313 boolean_t enc_init_evq_v2_supported;
1314 boolean_t enc_rx_packed_stream_supported;
1315 boolean_t enc_rx_var_packed_stream_supported;
1316 boolean_t enc_rx_es_super_buffer_supported;
1317 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1318 boolean_t enc_pm_and_rxdp_counters;
1319 boolean_t enc_mac_stats_40g_tx_size_bins;
1320 uint32_t enc_tunnel_encapsulations_supported;
1322 * NIC global maximum for unique UDP tunnel ports shared by all
1325 uint32_t enc_tunnel_config_udp_entries_max;
1326 /* External port identifier */
1327 uint8_t enc_external_port;
1328 uint32_t enc_mcdi_max_payload_length;
1329 /* VPD may be per-PF or global */
1330 boolean_t enc_vpd_is_global;
1331 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1332 uint32_t enc_required_pcie_bandwidth_mbps;
1333 uint32_t enc_max_pcie_link_gen;
1334 /* Firmware verifies integrity of NVRAM updates */
1335 uint32_t enc_nvram_update_verify_result_supported;
1336 /* Firmware support for extended MAC_STATS buffer */
1337 uint32_t enc_mac_stats_nstats;
1338 boolean_t enc_fec_counters;
1339 boolean_t enc_hlb_counters;
1340 /* Firmware support for "FLAG" and "MARK" filter actions */
1341 boolean_t enc_filter_action_flag_supported;
1342 boolean_t enc_filter_action_mark_supported;
1343 uint32_t enc_filter_action_mark_max;
1346 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1347 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1349 #define EFX_PCI_FUNCTION(_encp) \
1350 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1352 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1354 extern const efx_nic_cfg_t *
1356 __in efx_nic_t *enp);
1358 /* RxDPCPU firmware id values by which FW variant can be identified */
1359 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1360 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1361 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1362 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1363 #define EFX_RXDP_DPDK_FW_ID 0x6
1365 typedef struct efx_nic_fw_info_s {
1366 /* Basic FW version information */
1367 uint16_t enfi_mc_fw_version[4];
1369 * If datapath capabilities can be detected,
1370 * additional FW information is to be shown
1372 boolean_t enfi_dpcpu_fw_ids_valid;
1373 /* Rx and Tx datapath CPU FW IDs */
1374 uint16_t enfi_rx_dpcpu_fw_id;
1375 uint16_t enfi_tx_dpcpu_fw_id;
1376 } efx_nic_fw_info_t;
1378 extern __checkReturn efx_rc_t
1379 efx_nic_get_fw_version(
1380 __in efx_nic_t *enp,
1381 __out efx_nic_fw_info_t *enfip);
1383 /* Driver resource limits (minimum required/maximum usable). */
1384 typedef struct efx_drv_limits_s {
1385 uint32_t edl_min_evq_count;
1386 uint32_t edl_max_evq_count;
1388 uint32_t edl_min_rxq_count;
1389 uint32_t edl_max_rxq_count;
1391 uint32_t edl_min_txq_count;
1392 uint32_t edl_max_txq_count;
1394 /* PIO blocks (sub-allocated from piobuf) */
1395 uint32_t edl_min_pio_alloc_size;
1396 uint32_t edl_max_pio_alloc_count;
1399 extern __checkReturn efx_rc_t
1400 efx_nic_set_drv_limits(
1401 __inout efx_nic_t *enp,
1402 __in efx_drv_limits_t *edlp);
1404 typedef enum efx_nic_region_e {
1405 EFX_REGION_VI, /* Memory BAR UC mapping */
1406 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1409 extern __checkReturn efx_rc_t
1410 efx_nic_get_bar_region(
1411 __in efx_nic_t *enp,
1412 __in efx_nic_region_t region,
1413 __out uint32_t *offsetp,
1414 __out size_t *sizep);
1416 extern __checkReturn efx_rc_t
1417 efx_nic_get_vi_pool(
1418 __in efx_nic_t *enp,
1419 __out uint32_t *evq_countp,
1420 __out uint32_t *rxq_countp,
1421 __out uint32_t *txq_countp);
1426 typedef enum efx_vpd_tag_e {
1433 typedef uint16_t efx_vpd_keyword_t;
1435 typedef struct efx_vpd_value_s {
1436 efx_vpd_tag_t evv_tag;
1437 efx_vpd_keyword_t evv_keyword;
1439 uint8_t evv_value[0x100];
1443 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1445 extern __checkReturn efx_rc_t
1447 __in efx_nic_t *enp);
1449 extern __checkReturn efx_rc_t
1451 __in efx_nic_t *enp,
1452 __out size_t *sizep);
1454 extern __checkReturn efx_rc_t
1456 __in efx_nic_t *enp,
1457 __out_bcount(size) caddr_t data,
1460 extern __checkReturn efx_rc_t
1462 __in efx_nic_t *enp,
1463 __in_bcount(size) caddr_t data,
1466 extern __checkReturn efx_rc_t
1468 __in efx_nic_t *enp,
1469 __in_bcount(size) caddr_t data,
1472 extern __checkReturn efx_rc_t
1474 __in efx_nic_t *enp,
1475 __in_bcount(size) caddr_t data,
1477 __inout efx_vpd_value_t *evvp);
1479 extern __checkReturn efx_rc_t
1481 __in efx_nic_t *enp,
1482 __inout_bcount(size) caddr_t data,
1484 __in efx_vpd_value_t *evvp);
1486 extern __checkReturn efx_rc_t
1488 __in efx_nic_t *enp,
1489 __inout_bcount(size) caddr_t data,
1491 __out efx_vpd_value_t *evvp,
1492 __inout unsigned int *contp);
1494 extern __checkReturn efx_rc_t
1496 __in efx_nic_t *enp,
1497 __in_bcount(size) caddr_t data,
1502 __in efx_nic_t *enp);
1504 #endif /* EFSYS_OPT_VPD */
1510 typedef enum efx_nvram_type_e {
1511 EFX_NVRAM_INVALID = 0,
1513 EFX_NVRAM_BOOTROM_CFG,
1514 EFX_NVRAM_MC_FIRMWARE,
1515 EFX_NVRAM_MC_GOLDEN,
1521 EFX_NVRAM_FPGA_BACKUP,
1522 EFX_NVRAM_DYNAMIC_CFG,
1525 EFX_NVRAM_MUM_FIRMWARE,
1526 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1527 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1531 extern __checkReturn efx_rc_t
1533 __in efx_nic_t *enp);
1537 extern __checkReturn efx_rc_t
1539 __in efx_nic_t *enp);
1541 #endif /* EFSYS_OPT_DIAG */
1543 extern __checkReturn efx_rc_t
1545 __in efx_nic_t *enp,
1546 __in efx_nvram_type_t type,
1547 __out size_t *sizep);
1549 extern __checkReturn efx_rc_t
1551 __in efx_nic_t *enp,
1552 __in efx_nvram_type_t type,
1553 __out_opt size_t *pref_chunkp);
1555 extern __checkReturn efx_rc_t
1556 efx_nvram_rw_finish(
1557 __in efx_nic_t *enp,
1558 __in efx_nvram_type_t type,
1559 __out_opt uint32_t *verify_resultp);
1561 extern __checkReturn efx_rc_t
1562 efx_nvram_get_version(
1563 __in efx_nic_t *enp,
1564 __in efx_nvram_type_t type,
1565 __out uint32_t *subtypep,
1566 __out_ecount(4) uint16_t version[4]);
1568 extern __checkReturn efx_rc_t
1569 efx_nvram_read_chunk(
1570 __in efx_nic_t *enp,
1571 __in efx_nvram_type_t type,
1572 __in unsigned int offset,
1573 __out_bcount(size) caddr_t data,
1576 extern __checkReturn efx_rc_t
1577 efx_nvram_read_backup(
1578 __in efx_nic_t *enp,
1579 __in efx_nvram_type_t type,
1580 __in unsigned int offset,
1581 __out_bcount(size) caddr_t data,
1584 extern __checkReturn efx_rc_t
1585 efx_nvram_set_version(
1586 __in efx_nic_t *enp,
1587 __in efx_nvram_type_t type,
1588 __in_ecount(4) uint16_t version[4]);
1590 extern __checkReturn efx_rc_t
1592 __in efx_nic_t *enp,
1593 __in efx_nvram_type_t type,
1594 __in_bcount(partn_size) caddr_t partn_data,
1595 __in size_t partn_size);
1597 extern __checkReturn efx_rc_t
1599 __in efx_nic_t *enp,
1600 __in efx_nvram_type_t type);
1602 extern __checkReturn efx_rc_t
1603 efx_nvram_write_chunk(
1604 __in efx_nic_t *enp,
1605 __in efx_nvram_type_t type,
1606 __in unsigned int offset,
1607 __in_bcount(size) caddr_t data,
1612 __in efx_nic_t *enp);
1614 #endif /* EFSYS_OPT_NVRAM */
1616 #if EFSYS_OPT_BOOTCFG
1618 /* Report size and offset of bootcfg sector in NVRAM partition. */
1619 extern __checkReturn efx_rc_t
1620 efx_bootcfg_sector_info(
1621 __in efx_nic_t *enp,
1623 __out_opt uint32_t *sector_countp,
1624 __out size_t *offsetp,
1625 __out size_t *max_sizep);
1628 * Copy bootcfg sector data to a target buffer which may differ in size.
1629 * Optionally corrects format errors in source buffer.
1632 efx_bootcfg_copy_sector(
1633 __in efx_nic_t *enp,
1634 __inout_bcount(sector_length)
1636 __in size_t sector_length,
1637 __out_bcount(data_size) uint8_t *data,
1638 __in size_t data_size,
1639 __in boolean_t handle_format_errors);
1643 __in efx_nic_t *enp,
1644 __out_bcount(size) uint8_t *data,
1649 __in efx_nic_t *enp,
1650 __in_bcount(size) uint8_t *data,
1653 #endif /* EFSYS_OPT_BOOTCFG */
1655 #if EFSYS_OPT_IMAGE_LAYOUT
1657 #include "ef10_signed_image_layout.h"
1660 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1663 * The image header format is extensible. However, older drivers require an
1664 * exact match of image header version and header length when validating and
1665 * writing firmware images.
1667 * To avoid breaking backward compatibility, we use the upper bits of the
1668 * controller version fields to contain an extra version number used for
1669 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1670 * version). See bug39254 and SF-102785-PS for details.
1672 typedef struct efx_image_header_s {
1674 uint32_t eih_version;
1676 uint32_t eih_subtype;
1677 uint32_t eih_code_size;
1680 uint32_t eih_controller_version_min;
1682 uint16_t eih_controller_version_min_short;
1683 uint8_t eih_extra_version_a;
1684 uint8_t eih_extra_version_b;
1688 uint32_t eih_controller_version_max;
1690 uint16_t eih_controller_version_max_short;
1691 uint8_t eih_extra_version_c;
1692 uint8_t eih_extra_version_d;
1695 uint16_t eih_code_version_a;
1696 uint16_t eih_code_version_b;
1697 uint16_t eih_code_version_c;
1698 uint16_t eih_code_version_d;
1699 } efx_image_header_t;
1701 #define EFX_IMAGE_HEADER_SIZE (40)
1702 #define EFX_IMAGE_HEADER_VERSION (4)
1703 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1706 typedef struct efx_image_trailer_s {
1708 } efx_image_trailer_t;
1710 #define EFX_IMAGE_TRAILER_SIZE (4)
1712 typedef enum efx_image_format_e {
1713 EFX_IMAGE_FORMAT_NO_IMAGE,
1714 EFX_IMAGE_FORMAT_INVALID,
1715 EFX_IMAGE_FORMAT_UNSIGNED,
1716 EFX_IMAGE_FORMAT_SIGNED,
1717 } efx_image_format_t;
1719 typedef struct efx_image_info_s {
1720 efx_image_format_t eii_format;
1721 uint8_t * eii_imagep;
1722 size_t eii_image_size;
1723 efx_image_header_t * eii_headerp;
1726 extern __checkReturn efx_rc_t
1727 efx_check_reflash_image(
1729 __in uint32_t buffer_size,
1730 __out efx_image_info_t *infop);
1732 extern __checkReturn efx_rc_t
1733 efx_build_signed_image_write_buffer(
1734 __out_bcount(buffer_size)
1736 __in uint32_t buffer_size,
1737 __in efx_image_info_t *infop,
1738 __out efx_image_header_t **headerpp);
1740 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1744 typedef enum efx_pattern_type_t {
1745 EFX_PATTERN_BYTE_INCREMENT = 0,
1746 EFX_PATTERN_ALL_THE_SAME,
1747 EFX_PATTERN_BIT_ALTERNATE,
1748 EFX_PATTERN_BYTE_ALTERNATE,
1749 EFX_PATTERN_BYTE_CHANGING,
1750 EFX_PATTERN_BIT_SWEEP,
1752 } efx_pattern_type_t;
1755 (*efx_sram_pattern_fn_t)(
1757 __in boolean_t negate,
1758 __out efx_qword_t *eqp);
1760 extern __checkReturn efx_rc_t
1762 __in efx_nic_t *enp,
1763 __in efx_pattern_type_t type);
1765 #endif /* EFSYS_OPT_DIAG */
1767 extern __checkReturn efx_rc_t
1768 efx_sram_buf_tbl_set(
1769 __in efx_nic_t *enp,
1771 __in efsys_mem_t *esmp,
1775 efx_sram_buf_tbl_clear(
1776 __in efx_nic_t *enp,
1780 #define EFX_BUF_TBL_SIZE 0x20000
1782 #define EFX_BUF_SIZE 4096
1786 typedef struct efx_evq_s efx_evq_t;
1788 #if EFSYS_OPT_QSTATS
1790 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1791 typedef enum efx_ev_qstat_e {
1797 EV_RX_PAUSE_FRM_ERR,
1798 EV_RX_BUF_OWNER_ID_ERR,
1799 EV_RX_IPV4_HDR_CHKSUM_ERR,
1800 EV_RX_TCP_UDP_CHKSUM_ERR,
1804 EV_RX_MCAST_HASH_MATCH,
1821 EV_DRIVER_SRM_UPD_DONE,
1822 EV_DRIVER_TX_DESCQ_FLS_DONE,
1823 EV_DRIVER_RX_DESCQ_FLS_DONE,
1824 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1825 EV_DRIVER_RX_DSC_ERROR,
1826 EV_DRIVER_TX_DSC_ERROR,
1832 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1834 #endif /* EFSYS_OPT_QSTATS */
1836 extern __checkReturn efx_rc_t
1838 __in efx_nic_t *enp);
1842 __in efx_nic_t *enp);
1844 #define EFX_EVQ_MAXNEVS 32768
1845 #define EFX_EVQ_MINNEVS 512
1847 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1848 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1850 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1851 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1852 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1853 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1855 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1856 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1857 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1859 extern __checkReturn efx_rc_t
1861 __in efx_nic_t *enp,
1862 __in unsigned int index,
1863 __in efsys_mem_t *esmp,
1867 __in uint32_t flags,
1868 __deref_out efx_evq_t **eepp);
1872 __in efx_evq_t *eep,
1873 __in uint16_t data);
1875 typedef __checkReturn boolean_t
1876 (*efx_initialized_ev_t)(
1877 __in_opt void *arg);
1879 #define EFX_PKT_UNICAST 0x0004
1880 #define EFX_PKT_START 0x0008
1882 #define EFX_PKT_VLAN_TAGGED 0x0010
1883 #define EFX_CKSUM_TCPUDP 0x0020
1884 #define EFX_CKSUM_IPV4 0x0040
1885 #define EFX_PKT_CONT 0x0080
1887 #define EFX_CHECK_VLAN 0x0100
1888 #define EFX_PKT_TCP 0x0200
1889 #define EFX_PKT_UDP 0x0400
1890 #define EFX_PKT_IPV4 0x0800
1892 #define EFX_PKT_IPV6 0x1000
1893 #define EFX_PKT_PREFIX_LEN 0x2000
1894 #define EFX_ADDR_MISMATCH 0x4000
1895 #define EFX_DISCARD 0x8000
1898 * The following flags are used only for packed stream
1899 * mode. The values for the flags are reused to fit into 16 bit,
1900 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1901 * packed stream mode
1903 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1904 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1907 #define EFX_EV_RX_NLABELS 32
1908 #define EFX_EV_TX_NLABELS 32
1910 typedef __checkReturn boolean_t
1913 __in uint32_t label,
1916 __in uint16_t flags);
1918 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1921 * Packed stream mode is documented in SF-112241-TC.
1922 * The general idea is that, instead of putting each incoming
1923 * packet into a separate buffer which is specified in a RX
1924 * descriptor, a large buffer is provided to the hardware and
1925 * packets are put there in a continuous stream.
1926 * The main advantage of such an approach is that RX queue refilling
1927 * happens much less frequently.
1929 * Equal stride packed stream mode is documented in SF-119419-TC.
1930 * The general idea is to utilize advantages of the packed stream,
1931 * but avoid indirection in packets representation.
1932 * The main advantage of such an approach is that RX queue refilling
1933 * happens much less frequently and packets buffers are independent
1934 * from upper layers point of view.
1937 typedef __checkReturn boolean_t
1940 __in uint32_t label,
1942 __in uint32_t pkt_count,
1943 __in uint16_t flags);
1947 typedef __checkReturn boolean_t
1950 __in uint32_t label,
1953 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1954 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1955 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1956 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1957 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1958 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1959 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1960 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1961 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1963 typedef __checkReturn boolean_t
1964 (*efx_exception_ev_t)(
1966 __in uint32_t label,
1967 __in uint32_t data);
1969 typedef __checkReturn boolean_t
1970 (*efx_rxq_flush_done_ev_t)(
1972 __in uint32_t rxq_index);
1974 typedef __checkReturn boolean_t
1975 (*efx_rxq_flush_failed_ev_t)(
1977 __in uint32_t rxq_index);
1979 typedef __checkReturn boolean_t
1980 (*efx_txq_flush_done_ev_t)(
1982 __in uint32_t txq_index);
1984 typedef __checkReturn boolean_t
1985 (*efx_software_ev_t)(
1987 __in uint16_t magic);
1989 typedef __checkReturn boolean_t
1992 __in uint32_t code);
1994 #define EFX_SRAM_CLEAR 0
1995 #define EFX_SRAM_UPDATE 1
1996 #define EFX_SRAM_ILLEGAL_CLEAR 2
1998 typedef __checkReturn boolean_t
1999 (*efx_wake_up_ev_t)(
2001 __in uint32_t label);
2003 typedef __checkReturn boolean_t
2006 __in uint32_t label);
2008 typedef __checkReturn boolean_t
2009 (*efx_link_change_ev_t)(
2011 __in efx_link_mode_t link_mode);
2013 #if EFSYS_OPT_MON_STATS
2015 typedef __checkReturn boolean_t
2016 (*efx_monitor_ev_t)(
2018 __in efx_mon_stat_t id,
2019 __in efx_mon_stat_value_t value);
2021 #endif /* EFSYS_OPT_MON_STATS */
2023 #if EFSYS_OPT_MAC_STATS
2025 typedef __checkReturn boolean_t
2026 (*efx_mac_stats_ev_t)(
2028 __in uint32_t generation);
2030 #endif /* EFSYS_OPT_MAC_STATS */
2032 typedef struct efx_ev_callbacks_s {
2033 efx_initialized_ev_t eec_initialized;
2035 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2036 efx_rx_ps_ev_t eec_rx_ps;
2039 efx_exception_ev_t eec_exception;
2040 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2041 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2042 efx_txq_flush_done_ev_t eec_txq_flush_done;
2043 efx_software_ev_t eec_software;
2044 efx_sram_ev_t eec_sram;
2045 efx_wake_up_ev_t eec_wake_up;
2046 efx_timer_ev_t eec_timer;
2047 efx_link_change_ev_t eec_link_change;
2048 #if EFSYS_OPT_MON_STATS
2049 efx_monitor_ev_t eec_monitor;
2050 #endif /* EFSYS_OPT_MON_STATS */
2051 #if EFSYS_OPT_MAC_STATS
2052 efx_mac_stats_ev_t eec_mac_stats;
2053 #endif /* EFSYS_OPT_MAC_STATS */
2054 } efx_ev_callbacks_t;
2056 extern __checkReturn boolean_t
2058 __in efx_evq_t *eep,
2059 __in unsigned int count);
2061 #if EFSYS_OPT_EV_PREFETCH
2065 __in efx_evq_t *eep,
2066 __in unsigned int count);
2068 #endif /* EFSYS_OPT_EV_PREFETCH */
2072 __in efx_evq_t *eep,
2073 __inout unsigned int *countp,
2074 __in const efx_ev_callbacks_t *eecp,
2075 __in_opt void *arg);
2077 extern __checkReturn efx_rc_t
2078 efx_ev_usecs_to_ticks(
2079 __in efx_nic_t *enp,
2080 __in unsigned int usecs,
2081 __out unsigned int *ticksp);
2083 extern __checkReturn efx_rc_t
2085 __in efx_evq_t *eep,
2086 __in unsigned int us);
2088 extern __checkReturn efx_rc_t
2090 __in efx_evq_t *eep,
2091 __in unsigned int count);
2093 #if EFSYS_OPT_QSTATS
2099 __in efx_nic_t *enp,
2100 __in unsigned int id);
2102 #endif /* EFSYS_OPT_NAMES */
2105 efx_ev_qstats_update(
2106 __in efx_evq_t *eep,
2107 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2109 #endif /* EFSYS_OPT_QSTATS */
2113 __in efx_evq_t *eep);
2117 extern __checkReturn efx_rc_t
2119 __inout efx_nic_t *enp);
2123 __in efx_nic_t *enp);
2125 #if EFSYS_OPT_RX_SCATTER
2126 __checkReturn efx_rc_t
2127 efx_rx_scatter_enable(
2128 __in efx_nic_t *enp,
2129 __in unsigned int buf_size);
2130 #endif /* EFSYS_OPT_RX_SCATTER */
2132 /* Handle to represent use of the default RSS context. */
2133 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2135 #if EFSYS_OPT_RX_SCALE
2137 typedef enum efx_rx_hash_alg_e {
2138 EFX_RX_HASHALG_LFSR = 0,
2139 EFX_RX_HASHALG_TOEPLITZ,
2140 EFX_RX_HASHALG_PACKED_STREAM,
2142 } efx_rx_hash_alg_t;
2145 * Legacy hash type flags.
2147 * They represent standard tuples for distinct traffic classes.
2149 #define EFX_RX_HASH_IPV4 (1U << 0)
2150 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2151 #define EFX_RX_HASH_IPV6 (1U << 2)
2152 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2154 #define EFX_RX_HASH_LEGACY_MASK \
2155 (EFX_RX_HASH_IPV4 | \
2156 EFX_RX_HASH_TCPIPV4 | \
2157 EFX_RX_HASH_IPV6 | \
2158 EFX_RX_HASH_TCPIPV6)
2161 * The type of the argument used by efx_rx_scale_mode_set() to
2162 * provide a means for the client drivers to configure hashing.
2164 * A properly constructed value can either be:
2165 * - a combination of legacy flags
2166 * - a combination of EFX_RX_HASH() flags
2168 typedef unsigned int efx_rx_hash_type_t;
2170 typedef enum efx_rx_hash_support_e {
2171 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2172 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2173 } efx_rx_hash_support_t;
2175 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2176 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2177 #define EFX_MAXRSS 64 /* RX indirection entry range */
2178 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2180 typedef enum efx_rx_scale_context_type_e {
2181 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2182 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2183 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2184 } efx_rx_scale_context_type_t;
2187 * Traffic classes eligible for hash computation.
2189 * Select packet headers used in computing the receive hash.
2190 * This uses the same encoding as the RSS_MODES field of
2191 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2193 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2194 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2195 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2196 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2197 #define EFX_RX_CLASS_IPV4_LBN 16
2198 #define EFX_RX_CLASS_IPV4_WIDTH 4
2199 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2200 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2201 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2202 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2203 #define EFX_RX_CLASS_IPV6_LBN 28
2204 #define EFX_RX_CLASS_IPV6_WIDTH 4
2206 #define EFX_RX_NCLASSES 6
2209 * Ancillary flags used to construct generic hash tuples.
2210 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2212 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2213 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2214 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2215 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2218 * Generic hash tuples.
2220 * They express combinations of packet fields
2221 * which can contribute to the hash value for
2222 * a particular traffic class.
2224 #define EFX_RX_CLASS_HASH_DISABLE 0
2226 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2227 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2229 #define EFX_RX_CLASS_HASH_2TUPLE \
2230 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2231 EFX_RX_CLASS_HASH_DST_ADDR)
2233 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2234 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2235 EFX_RX_CLASS_HASH_SRC_PORT)
2237 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2238 (EFX_RX_CLASS_HASH_DST_ADDR | \
2239 EFX_RX_CLASS_HASH_DST_PORT)
2241 #define EFX_RX_CLASS_HASH_4TUPLE \
2242 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2243 EFX_RX_CLASS_HASH_DST_ADDR | \
2244 EFX_RX_CLASS_HASH_SRC_PORT | \
2245 EFX_RX_CLASS_HASH_DST_PORT)
2247 #define EFX_RX_CLASS_HASH_NTUPLES 7
2250 * Hash flag constructor.
2252 * Resulting flags encode hash tuples for specific traffic classes.
2253 * The client drivers are encouraged to use these flags to form
2254 * a hash type value.
2256 #define EFX_RX_HASH(_class, _tuple) \
2257 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2258 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2261 * The maximum number of EFX_RX_HASH() flags.
2263 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2265 extern __checkReturn efx_rc_t
2266 efx_rx_scale_hash_flags_get(
2267 __in efx_nic_t *enp,
2268 __in efx_rx_hash_alg_t hash_alg,
2269 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
2270 __out unsigned int *nflagsp);
2272 extern __checkReturn efx_rc_t
2273 efx_rx_hash_default_support_get(
2274 __in efx_nic_t *enp,
2275 __out efx_rx_hash_support_t *supportp);
2278 extern __checkReturn efx_rc_t
2279 efx_rx_scale_default_support_get(
2280 __in efx_nic_t *enp,
2281 __out efx_rx_scale_context_type_t *typep);
2283 extern __checkReturn efx_rc_t
2284 efx_rx_scale_context_alloc(
2285 __in efx_nic_t *enp,
2286 __in efx_rx_scale_context_type_t type,
2287 __in uint32_t num_queues,
2288 __out uint32_t *rss_contextp);
2290 extern __checkReturn efx_rc_t
2291 efx_rx_scale_context_free(
2292 __in efx_nic_t *enp,
2293 __in uint32_t rss_context);
2295 extern __checkReturn efx_rc_t
2296 efx_rx_scale_mode_set(
2297 __in efx_nic_t *enp,
2298 __in uint32_t rss_context,
2299 __in efx_rx_hash_alg_t alg,
2300 __in efx_rx_hash_type_t type,
2301 __in boolean_t insert);
2303 extern __checkReturn efx_rc_t
2304 efx_rx_scale_tbl_set(
2305 __in efx_nic_t *enp,
2306 __in uint32_t rss_context,
2307 __in_ecount(n) unsigned int *table,
2310 extern __checkReturn efx_rc_t
2311 efx_rx_scale_key_set(
2312 __in efx_nic_t *enp,
2313 __in uint32_t rss_context,
2314 __in_ecount(n) uint8_t *key,
2317 extern __checkReturn uint32_t
2318 efx_pseudo_hdr_hash_get(
2319 __in efx_rxq_t *erp,
2320 __in efx_rx_hash_alg_t func,
2321 __in uint8_t *buffer);
2323 #endif /* EFSYS_OPT_RX_SCALE */
2325 extern __checkReturn efx_rc_t
2326 efx_pseudo_hdr_pkt_length_get(
2327 __in efx_rxq_t *erp,
2328 __in uint8_t *buffer,
2329 __out uint16_t *pkt_lengthp);
2331 #define EFX_RXQ_MAXNDESCS 4096
2332 #define EFX_RXQ_MINNDESCS 512
2334 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2335 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2336 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2337 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2339 typedef enum efx_rxq_type_e {
2340 EFX_RXQ_TYPE_DEFAULT,
2341 EFX_RXQ_TYPE_PACKED_STREAM,
2342 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2347 * Dummy flag to be used instead of 0 to make it clear that the argument
2348 * is receive queue flags.
2350 #define EFX_RXQ_FLAG_NONE 0x0
2351 #define EFX_RXQ_FLAG_SCATTER 0x1
2353 * If tunnels are supported and Rx event can provide information about
2354 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2355 * full-feature firmware variant running), outer classes are requested by
2356 * default. However, if the driver supports tunnels, the flag allows to
2357 * request inner classes which are required to be able to interpret inner
2358 * Rx checksum offload results.
2360 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2362 extern __checkReturn efx_rc_t
2364 __in efx_nic_t *enp,
2365 __in unsigned int index,
2366 __in unsigned int label,
2367 __in efx_rxq_type_t type,
2368 __in efsys_mem_t *esmp,
2371 __in unsigned int flags,
2372 __in efx_evq_t *eep,
2373 __deref_out efx_rxq_t **erpp);
2375 #if EFSYS_OPT_RX_PACKED_STREAM
2377 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2378 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2379 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2380 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2381 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2383 extern __checkReturn efx_rc_t
2384 efx_rx_qcreate_packed_stream(
2385 __in efx_nic_t *enp,
2386 __in unsigned int index,
2387 __in unsigned int label,
2388 __in uint32_t ps_buf_size,
2389 __in efsys_mem_t *esmp,
2391 __in efx_evq_t *eep,
2392 __deref_out efx_rxq_t **erpp);
2396 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2398 /* Maximum head-of-line block timeout in nanoseconds */
2399 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2401 extern __checkReturn efx_rc_t
2402 efx_rx_qcreate_es_super_buffer(
2403 __in efx_nic_t *enp,
2404 __in unsigned int index,
2405 __in unsigned int label,
2406 __in uint32_t n_bufs_per_desc,
2407 __in uint32_t max_dma_len,
2408 __in uint32_t buf_stride,
2409 __in uint32_t hol_block_timeout,
2410 __in efsys_mem_t *esmp,
2412 __in unsigned int flags,
2413 __in efx_evq_t *eep,
2414 __deref_out efx_rxq_t **erpp);
2418 typedef struct efx_buffer_s {
2419 efsys_dma_addr_t eb_addr;
2424 typedef struct efx_desc_s {
2430 __in efx_rxq_t *erp,
2431 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2433 __in unsigned int ndescs,
2434 __in unsigned int completed,
2435 __in unsigned int added);
2439 __in efx_rxq_t *erp,
2440 __in unsigned int added,
2441 __inout unsigned int *pushedp);
2443 #if EFSYS_OPT_RX_PACKED_STREAM
2446 efx_rx_qpush_ps_credits(
2447 __in efx_rxq_t *erp);
2449 extern __checkReturn uint8_t *
2450 efx_rx_qps_packet_info(
2451 __in efx_rxq_t *erp,
2452 __in uint8_t *buffer,
2453 __in uint32_t buffer_length,
2454 __in uint32_t current_offset,
2455 __out uint16_t *lengthp,
2456 __out uint32_t *next_offsetp,
2457 __out uint32_t *timestamp);
2460 extern __checkReturn efx_rc_t
2462 __in efx_rxq_t *erp);
2466 __in efx_rxq_t *erp);
2470 __in efx_rxq_t *erp);
2474 typedef struct efx_txq_s efx_txq_t;
2476 #if EFSYS_OPT_QSTATS
2478 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2479 typedef enum efx_tx_qstat_e {
2485 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2487 #endif /* EFSYS_OPT_QSTATS */
2489 extern __checkReturn efx_rc_t
2491 __in efx_nic_t *enp);
2495 __in efx_nic_t *enp);
2497 #define EFX_TXQ_MINNDESCS 512
2499 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2500 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2501 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2503 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2505 #define EFX_TXQ_CKSUM_IPV4 0x0001
2506 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2507 #define EFX_TXQ_FATSOV2 0x0004
2508 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2509 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2511 extern __checkReturn efx_rc_t
2513 __in efx_nic_t *enp,
2514 __in unsigned int index,
2515 __in unsigned int label,
2516 __in efsys_mem_t *esmp,
2519 __in uint16_t flags,
2520 __in efx_evq_t *eep,
2521 __deref_out efx_txq_t **etpp,
2522 __out unsigned int *addedp);
2524 extern __checkReturn efx_rc_t
2526 __in efx_txq_t *etp,
2527 __in_ecount(ndescs) efx_buffer_t *eb,
2528 __in unsigned int ndescs,
2529 __in unsigned int completed,
2530 __inout unsigned int *addedp);
2532 extern __checkReturn efx_rc_t
2534 __in efx_txq_t *etp,
2535 __in unsigned int ns);
2539 __in efx_txq_t *etp,
2540 __in unsigned int added,
2541 __in unsigned int pushed);
2543 extern __checkReturn efx_rc_t
2545 __in efx_txq_t *etp);
2549 __in efx_txq_t *etp);
2551 extern __checkReturn efx_rc_t
2553 __in efx_txq_t *etp);
2556 efx_tx_qpio_disable(
2557 __in efx_txq_t *etp);
2559 extern __checkReturn efx_rc_t
2561 __in efx_txq_t *etp,
2562 __in_ecount(buf_length) uint8_t *buffer,
2563 __in size_t buf_length,
2564 __in size_t pio_buf_offset);
2566 extern __checkReturn efx_rc_t
2568 __in efx_txq_t *etp,
2569 __in size_t pkt_length,
2570 __in unsigned int completed,
2571 __inout unsigned int *addedp);
2573 extern __checkReturn efx_rc_t
2575 __in efx_txq_t *etp,
2576 __in_ecount(n) efx_desc_t *ed,
2577 __in unsigned int n,
2578 __in unsigned int completed,
2579 __inout unsigned int *addedp);
2582 efx_tx_qdesc_dma_create(
2583 __in efx_txq_t *etp,
2584 __in efsys_dma_addr_t addr,
2587 __out efx_desc_t *edp);
2590 efx_tx_qdesc_tso_create(
2591 __in efx_txq_t *etp,
2592 __in uint16_t ipv4_id,
2593 __in uint32_t tcp_seq,
2594 __in uint8_t tcp_flags,
2595 __out efx_desc_t *edp);
2597 /* Number of FATSOv2 option descriptors */
2598 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2600 /* Maximum number of DMA segments per TSO packet (not superframe) */
2601 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2604 efx_tx_qdesc_tso2_create(
2605 __in efx_txq_t *etp,
2606 __in uint16_t ipv4_id,
2607 __in uint16_t outer_ipv4_id,
2608 __in uint32_t tcp_seq,
2609 __in uint16_t tcp_mss,
2610 __out_ecount(count) efx_desc_t *edp,
2614 efx_tx_qdesc_vlantci_create(
2615 __in efx_txq_t *etp,
2617 __out efx_desc_t *edp);
2620 efx_tx_qdesc_checksum_create(
2621 __in efx_txq_t *etp,
2622 __in uint16_t flags,
2623 __out efx_desc_t *edp);
2625 #if EFSYS_OPT_QSTATS
2631 __in efx_nic_t *etp,
2632 __in unsigned int id);
2634 #endif /* EFSYS_OPT_NAMES */
2637 efx_tx_qstats_update(
2638 __in efx_txq_t *etp,
2639 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2641 #endif /* EFSYS_OPT_QSTATS */
2645 __in efx_txq_t *etp);
2650 #if EFSYS_OPT_FILTER
2652 #define EFX_ETHER_TYPE_IPV4 0x0800
2653 #define EFX_ETHER_TYPE_IPV6 0x86DD
2655 #define EFX_IPPROTO_TCP 6
2656 #define EFX_IPPROTO_UDP 17
2657 #define EFX_IPPROTO_GRE 47
2659 /* Use RSS to spread across multiple queues */
2660 #define EFX_FILTER_FLAG_RX_RSS 0x01
2661 /* Enable RX scatter */
2662 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2664 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2665 * May only be set by the filter implementation for each type.
2666 * A removal request will restore the automatic filter in its place.
2668 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2669 /* Filter is for RX */
2670 #define EFX_FILTER_FLAG_RX 0x08
2671 /* Filter is for TX */
2672 #define EFX_FILTER_FLAG_TX 0x10
2673 /* Set match flag on the received packet */
2674 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2675 /* Set match mark on the received packet */
2676 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2678 typedef uint8_t efx_filter_flags_t;
2681 * Flags which specify the fields to match on. The values are the same as in the
2682 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2685 /* Match by remote IP host address */
2686 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2687 /* Match by local IP host address */
2688 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2689 /* Match by remote MAC address */
2690 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2691 /* Match by remote TCP/UDP port */
2692 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2693 /* Match by remote TCP/UDP port */
2694 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2695 /* Match by local TCP/UDP port */
2696 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2697 /* Match by Ether-type */
2698 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2699 /* Match by inner VLAN ID */
2700 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2701 /* Match by outer VLAN ID */
2702 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2703 /* Match by IP transport protocol */
2704 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2705 /* Match by VNI or VSID */
2706 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2707 /* For encapsulated packets, match by inner frame local MAC address */
2708 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2709 /* For encapsulated packets, match all multicast inner frames */
2710 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2711 /* For encapsulated packets, match all unicast inner frames */
2712 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2714 * Match by encap type, this flag does not correspond to
2715 * the MCDI match flags and any unoccupied value may be used
2717 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2718 /* Match otherwise-unmatched multicast and broadcast packets */
2719 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2720 /* Match otherwise-unmatched unicast packets */
2721 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2723 typedef uint32_t efx_filter_match_flags_t;
2725 typedef enum efx_filter_priority_s {
2726 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2727 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2728 * address list or hardware
2729 * requirements. This may only be used
2730 * by the filter implementation for
2732 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2733 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2734 * client (e.g. SR-IOV, HyperV VMQ etc.)
2736 } efx_filter_priority_t;
2739 * FIXME: All these fields are assumed to be in little-endian byte order.
2740 * It may be better for some to be big-endian. See bug42804.
2743 typedef struct efx_filter_spec_s {
2744 efx_filter_match_flags_t efs_match_flags;
2745 uint8_t efs_priority;
2746 efx_filter_flags_t efs_flags;
2747 uint16_t efs_dmaq_id;
2748 uint32_t efs_rss_context;
2749 uint16_t efs_outer_vid;
2750 uint16_t efs_inner_vid;
2751 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2752 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2753 uint16_t efs_ether_type;
2754 uint8_t efs_ip_proto;
2755 efx_tunnel_protocol_t efs_encap_type;
2756 uint16_t efs_loc_port;
2757 uint16_t efs_rem_port;
2758 efx_oword_t efs_rem_host;
2759 efx_oword_t efs_loc_host;
2760 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2761 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2763 } efx_filter_spec_t;
2766 /* Default values for use in filter specifications */
2767 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2768 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2770 extern __checkReturn efx_rc_t
2772 __in efx_nic_t *enp);
2776 __in efx_nic_t *enp);
2778 extern __checkReturn efx_rc_t
2780 __in efx_nic_t *enp,
2781 __inout efx_filter_spec_t *spec);
2783 extern __checkReturn efx_rc_t
2785 __in efx_nic_t *enp,
2786 __inout efx_filter_spec_t *spec);
2788 extern __checkReturn efx_rc_t
2790 __in efx_nic_t *enp);
2792 extern __checkReturn efx_rc_t
2793 efx_filter_supported_filters(
2794 __in efx_nic_t *enp,
2795 __out_ecount(buffer_length) uint32_t *buffer,
2796 __in size_t buffer_length,
2797 __out size_t *list_lengthp);
2800 efx_filter_spec_init_rx(
2801 __out efx_filter_spec_t *spec,
2802 __in efx_filter_priority_t priority,
2803 __in efx_filter_flags_t flags,
2804 __in efx_rxq_t *erp);
2807 efx_filter_spec_init_tx(
2808 __out efx_filter_spec_t *spec,
2809 __in efx_txq_t *etp);
2811 extern __checkReturn efx_rc_t
2812 efx_filter_spec_set_ipv4_local(
2813 __inout efx_filter_spec_t *spec,
2816 __in uint16_t port);
2818 extern __checkReturn efx_rc_t
2819 efx_filter_spec_set_ipv4_full(
2820 __inout efx_filter_spec_t *spec,
2822 __in uint32_t lhost,
2823 __in uint16_t lport,
2824 __in uint32_t rhost,
2825 __in uint16_t rport);
2827 extern __checkReturn efx_rc_t
2828 efx_filter_spec_set_eth_local(
2829 __inout efx_filter_spec_t *spec,
2831 __in const uint8_t *addr);
2834 efx_filter_spec_set_ether_type(
2835 __inout efx_filter_spec_t *spec,
2836 __in uint16_t ether_type);
2838 extern __checkReturn efx_rc_t
2839 efx_filter_spec_set_uc_def(
2840 __inout efx_filter_spec_t *spec);
2842 extern __checkReturn efx_rc_t
2843 efx_filter_spec_set_mc_def(
2844 __inout efx_filter_spec_t *spec);
2846 typedef enum efx_filter_inner_frame_match_e {
2847 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2848 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2849 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2850 } efx_filter_inner_frame_match_t;
2852 extern __checkReturn efx_rc_t
2853 efx_filter_spec_set_encap_type(
2854 __inout efx_filter_spec_t *spec,
2855 __in efx_tunnel_protocol_t encap_type,
2856 __in efx_filter_inner_frame_match_t inner_frame_match);
2858 extern __checkReturn efx_rc_t
2859 efx_filter_spec_set_vxlan_full(
2860 __inout efx_filter_spec_t *spec,
2861 __in const uint8_t *vxlan_id,
2862 __in const uint8_t *inner_addr,
2863 __in const uint8_t *outer_addr);
2865 #if EFSYS_OPT_RX_SCALE
2866 extern __checkReturn efx_rc_t
2867 efx_filter_spec_set_rss_context(
2868 __inout efx_filter_spec_t *spec,
2869 __in uint32_t rss_context);
2871 #endif /* EFSYS_OPT_FILTER */
2875 extern __checkReturn uint32_t
2877 __in_ecount(count) uint32_t const *input,
2879 __in uint32_t init);
2881 extern __checkReturn uint32_t
2883 __in_ecount(length) uint8_t const *input,
2885 __in uint32_t init);
2887 #if EFSYS_OPT_LICENSING
2891 typedef struct efx_key_stats_s {
2893 uint32_t eks_invalid;
2894 uint32_t eks_blacklisted;
2895 uint32_t eks_unverifiable;
2896 uint32_t eks_wrong_node;
2897 uint32_t eks_licensed_apps_lo;
2898 uint32_t eks_licensed_apps_hi;
2899 uint32_t eks_licensed_features_lo;
2900 uint32_t eks_licensed_features_hi;
2903 extern __checkReturn efx_rc_t
2905 __in efx_nic_t *enp);
2909 __in efx_nic_t *enp);
2911 extern __checkReturn boolean_t
2912 efx_lic_check_support(
2913 __in efx_nic_t *enp);
2915 extern __checkReturn efx_rc_t
2916 efx_lic_update_licenses(
2917 __in efx_nic_t *enp);
2919 extern __checkReturn efx_rc_t
2920 efx_lic_get_key_stats(
2921 __in efx_nic_t *enp,
2922 __out efx_key_stats_t *ksp);
2924 extern __checkReturn efx_rc_t
2926 __in efx_nic_t *enp,
2927 __in uint64_t app_id,
2928 __out boolean_t *licensedp);
2930 extern __checkReturn efx_rc_t
2932 __in efx_nic_t *enp,
2933 __in size_t buffer_size,
2934 __out uint32_t *typep,
2935 __out size_t *lengthp,
2936 __out_opt uint8_t *bufferp);
2939 extern __checkReturn efx_rc_t
2941 __in efx_nic_t *enp,
2942 __in_bcount(buffer_size)
2944 __in size_t buffer_size,
2945 __out uint32_t *startp);
2947 extern __checkReturn efx_rc_t
2949 __in efx_nic_t *enp,
2950 __in_bcount(buffer_size)
2952 __in size_t buffer_size,
2953 __in uint32_t offset,
2954 __out uint32_t *endp);
2956 extern __checkReturn __success(return != B_FALSE) boolean_t
2958 __in efx_nic_t *enp,
2959 __in_bcount(buffer_size)
2961 __in size_t buffer_size,
2962 __in uint32_t offset,
2963 __out uint32_t *startp,
2964 __out uint32_t *lengthp);
2966 extern __checkReturn __success(return != B_FALSE) boolean_t
2967 efx_lic_validate_key(
2968 __in efx_nic_t *enp,
2969 __in_bcount(length) caddr_t keyp,
2970 __in uint32_t length);
2972 extern __checkReturn efx_rc_t
2974 __in efx_nic_t *enp,
2975 __in_bcount(buffer_size)
2977 __in size_t buffer_size,
2978 __in uint32_t offset,
2979 __in uint32_t length,
2980 __out_bcount_part(key_max_size, *lengthp)
2982 __in size_t key_max_size,
2983 __out uint32_t *lengthp);
2985 extern __checkReturn efx_rc_t
2987 __in efx_nic_t *enp,
2988 __in_bcount(buffer_size)
2990 __in size_t buffer_size,
2991 __in uint32_t offset,
2992 __in_bcount(length) caddr_t keyp,
2993 __in uint32_t length,
2994 __out uint32_t *lengthp);
2996 __checkReturn efx_rc_t
2998 __in efx_nic_t *enp,
2999 __in_bcount(buffer_size)
3001 __in size_t buffer_size,
3002 __in uint32_t offset,
3003 __in uint32_t length,
3005 __out uint32_t *deltap);
3007 extern __checkReturn efx_rc_t
3008 efx_lic_create_partition(
3009 __in efx_nic_t *enp,
3010 __in_bcount(buffer_size)
3012 __in size_t buffer_size);
3014 extern __checkReturn efx_rc_t
3015 efx_lic_finish_partition(
3016 __in efx_nic_t *enp,
3017 __in_bcount(buffer_size)
3019 __in size_t buffer_size);
3021 #endif /* EFSYS_OPT_LICENSING */
3025 #if EFSYS_OPT_TUNNEL
3027 extern __checkReturn efx_rc_t
3029 __in efx_nic_t *enp);
3033 __in efx_nic_t *enp);
3036 * For overlay network encapsulation using UDP, the firmware needs to know
3037 * the configured UDP port for the overlay so it can decode encapsulated
3039 * The UDP port/protocol list is global.
3042 extern __checkReturn efx_rc_t
3043 efx_tunnel_config_udp_add(
3044 __in efx_nic_t *enp,
3045 __in uint16_t port /* host/cpu-endian */,
3046 __in efx_tunnel_protocol_t protocol);
3048 extern __checkReturn efx_rc_t
3049 efx_tunnel_config_udp_remove(
3050 __in efx_nic_t *enp,
3051 __in uint16_t port /* host/cpu-endian */,
3052 __in efx_tunnel_protocol_t protocol);
3055 efx_tunnel_config_clear(
3056 __in efx_nic_t *enp);
3059 * Apply tunnel UDP ports configuration to hardware.
3061 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3064 extern __checkReturn efx_rc_t
3065 efx_tunnel_reconfigure(
3066 __in efx_nic_t *enp);
3068 #endif /* EFSYS_OPT_TUNNEL */
3070 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3073 * Firmware subvariant choice options.
3075 * It may be switched to no Tx checksum if attached drivers are either
3076 * preboot or firmware subvariant aware and no VIS are allocated.
3077 * If may be always switched to default explicitly using set request or
3078 * implicitly if unaware driver is attaching. If switching is done when
3079 * a driver is attached, it gets MC_REBOOT event and should recreate its
3082 * See SF-119419-TC DPDK Firmware Driver Interface and
3083 * SF-109306-TC EF10 for Driver Writers for details.
3085 typedef enum efx_nic_fw_subvariant_e {
3086 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3087 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3088 EFX_NIC_FW_SUBVARIANT_NTYPES
3089 } efx_nic_fw_subvariant_t;
3091 extern __checkReturn efx_rc_t
3092 efx_nic_get_fw_subvariant(
3093 __in efx_nic_t *enp,
3094 __out efx_nic_fw_subvariant_t *subvariantp);
3096 extern __checkReturn efx_rc_t
3097 efx_nic_set_fw_subvariant(
3098 __in efx_nic_t *enp,
3099 __in efx_nic_fw_subvariant_t subvariant);
3101 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3107 #endif /* _SYS_EFX_H */