1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_check.h"
13 #include "efx_phy_ids.h"
19 #define EFX_STATIC_ASSERT(_cond) \
20 ((void)sizeof (char[(_cond) ? 1 : -1]))
22 #define EFX_ARRAY_SIZE(_array) \
23 (sizeof (_array) / sizeof ((_array)[0]))
25 #define EFX_FIELD_OFFSET(_type, _field) \
26 ((size_t)&(((_type *)0)->_field))
28 /* The macro expands divider twice */
29 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
33 typedef __success(return == 0) int efx_rc_t;
38 typedef enum efx_family_e {
40 EFX_FAMILY_FALCON, /* Obsolete and not supported */
42 EFX_FAMILY_HUNTINGTON,
48 extern __checkReturn efx_rc_t
52 __out efx_family_t *efp,
53 __out unsigned int *membarp);
56 #define EFX_PCI_VENID_SFC 0x1924
58 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
60 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
61 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
62 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
64 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
65 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
66 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
68 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
69 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
71 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
72 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
73 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
75 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
76 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
77 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
80 #define EFX_MEM_BAR_SIENA 2
82 #define EFX_MEM_BAR_HUNTINGTON_PF 2
83 #define EFX_MEM_BAR_HUNTINGTON_VF 0
85 #define EFX_MEM_BAR_MEDFORD_PF 2
86 #define EFX_MEM_BAR_MEDFORD_VF 0
88 #define EFX_MEM_BAR_MEDFORD2 0
109 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
110 extern __checkReturn uint32_t
112 __in uint32_t crc_init,
113 __in_ecount(length) uint8_t const *input,
117 /* Type prototypes */
119 typedef struct efx_rxq_s efx_rxq_t;
123 typedef struct efx_nic_s efx_nic_t;
125 extern __checkReturn efx_rc_t
127 __in efx_family_t family,
128 __in efsys_identifier_t *esip,
129 __in efsys_bar_t *esbp,
130 __in efsys_lock_t *eslp,
131 __deref_out efx_nic_t **enpp);
133 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
134 typedef enum efx_fw_variant_e {
135 EFX_FW_VARIANT_FULL_FEATURED,
136 EFX_FW_VARIANT_LOW_LATENCY,
137 EFX_FW_VARIANT_PACKED_STREAM,
138 EFX_FW_VARIANT_HIGH_TX_RATE,
139 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
140 EFX_FW_VARIANT_RULES_ENGINE,
142 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
145 extern __checkReturn efx_rc_t
148 __in efx_fw_variant_t efv);
150 extern __checkReturn efx_rc_t
152 __in efx_nic_t *enp);
154 extern __checkReturn efx_rc_t
156 __in efx_nic_t *enp);
158 extern __checkReturn boolean_t
159 efx_nic_hw_unavailable(
160 __in efx_nic_t *enp);
164 extern __checkReturn efx_rc_t
165 efx_nic_register_test(
166 __in efx_nic_t *enp);
168 #endif /* EFSYS_OPT_DIAG */
172 __in efx_nic_t *enp);
176 __in efx_nic_t *enp);
180 __in efx_nic_t *enp);
182 #define EFX_PCIE_LINK_SPEED_GEN1 1
183 #define EFX_PCIE_LINK_SPEED_GEN2 2
184 #define EFX_PCIE_LINK_SPEED_GEN3 3
186 typedef enum efx_pcie_link_performance_e {
187 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
188 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
189 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
190 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
191 } efx_pcie_link_performance_t;
193 extern __checkReturn efx_rc_t
194 efx_nic_calculate_pcie_link_bandwidth(
195 __in uint32_t pcie_link_width,
196 __in uint32_t pcie_link_gen,
197 __out uint32_t *bandwidth_mbpsp);
199 extern __checkReturn efx_rc_t
200 efx_nic_check_pcie_link_speed(
202 __in uint32_t pcie_link_width,
203 __in uint32_t pcie_link_gen,
204 __out efx_pcie_link_performance_t *resultp);
208 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
209 /* Huntington and Medford require MCDIv2 commands */
210 #define WITH_MCDI_V2 1
213 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
215 typedef enum efx_mcdi_exception_e {
216 EFX_MCDI_EXCEPTION_MC_REBOOT,
217 EFX_MCDI_EXCEPTION_MC_BADASSERT,
218 } efx_mcdi_exception_t;
220 #if EFSYS_OPT_MCDI_LOGGING
221 typedef enum efx_log_msg_e {
223 EFX_LOG_MCDI_REQUEST,
224 EFX_LOG_MCDI_RESPONSE,
226 #endif /* EFSYS_OPT_MCDI_LOGGING */
228 typedef struct efx_mcdi_transport_s {
230 efsys_mem_t *emt_dma_mem;
231 void (*emt_execute)(void *, efx_mcdi_req_t *);
232 void (*emt_ev_cpl)(void *);
233 void (*emt_exception)(void *, efx_mcdi_exception_t);
234 #if EFSYS_OPT_MCDI_LOGGING
235 void (*emt_logger)(void *, efx_log_msg_t,
236 void *, size_t, void *, size_t);
237 #endif /* EFSYS_OPT_MCDI_LOGGING */
238 #if EFSYS_OPT_MCDI_PROXY_AUTH
239 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
240 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
241 } efx_mcdi_transport_t;
243 extern __checkReturn efx_rc_t
246 __in const efx_mcdi_transport_t *mtp);
248 extern __checkReturn efx_rc_t
250 __in efx_nic_t *enp);
254 __in efx_nic_t *enp);
257 efx_mcdi_get_timeout(
259 __in efx_mcdi_req_t *emrp,
260 __out uint32_t *usec_timeoutp);
263 efx_mcdi_request_start(
265 __in efx_mcdi_req_t *emrp,
266 __in boolean_t ev_cpl);
268 extern __checkReturn boolean_t
269 efx_mcdi_request_poll(
270 __in efx_nic_t *enp);
272 extern __checkReturn boolean_t
273 efx_mcdi_request_abort(
274 __in efx_nic_t *enp);
278 __in efx_nic_t *enp);
280 #endif /* EFSYS_OPT_MCDI */
284 #define EFX_NINTR_SIENA 1024
286 typedef enum efx_intr_type_e {
287 EFX_INTR_INVALID = 0,
293 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
295 extern __checkReturn efx_rc_t
298 __in efx_intr_type_t type,
299 __in efsys_mem_t *esmp);
303 __in efx_nic_t *enp);
307 __in efx_nic_t *enp);
310 efx_intr_disable_unlocked(
311 __in efx_nic_t *enp);
313 #define EFX_INTR_NEVQS 32
315 extern __checkReturn efx_rc_t
318 __in unsigned int level);
321 efx_intr_status_line(
323 __out boolean_t *fatalp,
324 __out uint32_t *maskp);
327 efx_intr_status_message(
329 __in unsigned int message,
330 __out boolean_t *fatalp);
334 __in efx_nic_t *enp);
338 __in efx_nic_t *enp);
342 #if EFSYS_OPT_MAC_STATS
344 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
345 typedef enum efx_mac_stat_e {
348 EFX_MAC_RX_UNICST_PKTS,
349 EFX_MAC_RX_MULTICST_PKTS,
350 EFX_MAC_RX_BRDCST_PKTS,
351 EFX_MAC_RX_PAUSE_PKTS,
352 EFX_MAC_RX_LE_64_PKTS,
353 EFX_MAC_RX_65_TO_127_PKTS,
354 EFX_MAC_RX_128_TO_255_PKTS,
355 EFX_MAC_RX_256_TO_511_PKTS,
356 EFX_MAC_RX_512_TO_1023_PKTS,
357 EFX_MAC_RX_1024_TO_15XX_PKTS,
358 EFX_MAC_RX_GE_15XX_PKTS,
360 EFX_MAC_RX_FCS_ERRORS,
361 EFX_MAC_RX_DROP_EVENTS,
362 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
363 EFX_MAC_RX_SYMBOL_ERRORS,
364 EFX_MAC_RX_ALIGN_ERRORS,
365 EFX_MAC_RX_INTERNAL_ERRORS,
366 EFX_MAC_RX_JABBER_PKTS,
367 EFX_MAC_RX_LANE0_CHAR_ERR,
368 EFX_MAC_RX_LANE1_CHAR_ERR,
369 EFX_MAC_RX_LANE2_CHAR_ERR,
370 EFX_MAC_RX_LANE3_CHAR_ERR,
371 EFX_MAC_RX_LANE0_DISP_ERR,
372 EFX_MAC_RX_LANE1_DISP_ERR,
373 EFX_MAC_RX_LANE2_DISP_ERR,
374 EFX_MAC_RX_LANE3_DISP_ERR,
375 EFX_MAC_RX_MATCH_FAULT,
376 EFX_MAC_RX_NODESC_DROP_CNT,
379 EFX_MAC_TX_UNICST_PKTS,
380 EFX_MAC_TX_MULTICST_PKTS,
381 EFX_MAC_TX_BRDCST_PKTS,
382 EFX_MAC_TX_PAUSE_PKTS,
383 EFX_MAC_TX_LE_64_PKTS,
384 EFX_MAC_TX_65_TO_127_PKTS,
385 EFX_MAC_TX_128_TO_255_PKTS,
386 EFX_MAC_TX_256_TO_511_PKTS,
387 EFX_MAC_TX_512_TO_1023_PKTS,
388 EFX_MAC_TX_1024_TO_15XX_PKTS,
389 EFX_MAC_TX_GE_15XX_PKTS,
391 EFX_MAC_TX_SGL_COL_PKTS,
392 EFX_MAC_TX_MULT_COL_PKTS,
393 EFX_MAC_TX_EX_COL_PKTS,
394 EFX_MAC_TX_LATE_COL_PKTS,
396 EFX_MAC_TX_EX_DEF_PKTS,
397 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
398 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
399 EFX_MAC_PM_TRUNC_VFIFO_FULL,
400 EFX_MAC_PM_DISCARD_VFIFO_FULL,
401 EFX_MAC_PM_TRUNC_QBB,
402 EFX_MAC_PM_DISCARD_QBB,
403 EFX_MAC_PM_DISCARD_MAPPING,
404 EFX_MAC_RXDP_Q_DISABLED_PKTS,
405 EFX_MAC_RXDP_DI_DROPPED_PKTS,
406 EFX_MAC_RXDP_STREAMING_PKTS,
407 EFX_MAC_RXDP_HLB_FETCH,
408 EFX_MAC_RXDP_HLB_WAIT,
409 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
410 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
411 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
412 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
413 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
414 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
415 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
416 EFX_MAC_VADAPTER_RX_BAD_BYTES,
417 EFX_MAC_VADAPTER_RX_OVERFLOW,
418 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
419 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
420 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
421 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
422 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
423 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
424 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
425 EFX_MAC_VADAPTER_TX_BAD_BYTES,
426 EFX_MAC_VADAPTER_TX_OVERFLOW,
427 EFX_MAC_FEC_UNCORRECTED_ERRORS,
428 EFX_MAC_FEC_CORRECTED_ERRORS,
429 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
430 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
431 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
432 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
433 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
434 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
435 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
436 EFX_MAC_CTPIO_OVERFLOW_FAIL,
437 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
438 EFX_MAC_CTPIO_TIMEOUT_FAIL,
439 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
440 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
441 EFX_MAC_CTPIO_INVALID_WR_FAIL,
442 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
443 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
444 EFX_MAC_CTPIO_RUNT_FALLBACK,
445 EFX_MAC_CTPIO_SUCCESS,
446 EFX_MAC_CTPIO_FALLBACK,
447 EFX_MAC_CTPIO_POISON,
449 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
450 EFX_MAC_RXDP_HLB_IDLE,
451 EFX_MAC_RXDP_HLB_TIMEOUT,
455 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
457 #endif /* EFSYS_OPT_MAC_STATS */
459 typedef enum efx_link_mode_e {
460 EFX_LINK_UNKNOWN = 0,
476 #define EFX_MAC_ADDR_LEN 6
478 #define EFX_VNI_OR_VSID_LEN 3
480 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
482 #define EFX_MAC_MULTICAST_LIST_MAX 256
484 #define EFX_MAC_SDU_MAX 9202
486 #define EFX_MAC_PDU_ADJUSTMENT \
490 + /* bug16011 */ 16) \
492 #define EFX_MAC_PDU(_sdu) \
493 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
496 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
497 * the SDU rounded up slightly.
499 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
501 #define EFX_MAC_PDU_MIN 60
502 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
504 extern __checkReturn efx_rc_t
509 extern __checkReturn efx_rc_t
514 extern __checkReturn efx_rc_t
519 extern __checkReturn efx_rc_t
522 __in boolean_t all_unicst,
523 __in boolean_t mulcst,
524 __in boolean_t all_mulcst,
525 __in boolean_t brdcst);
527 extern __checkReturn efx_rc_t
528 efx_mac_multicast_list_set(
530 __in_ecount(6*count) uint8_t const *addrs,
533 extern __checkReturn efx_rc_t
534 efx_mac_filter_default_rxq_set(
537 __in boolean_t using_rss);
540 efx_mac_filter_default_rxq_clear(
541 __in efx_nic_t *enp);
543 extern __checkReturn efx_rc_t
546 __in boolean_t enabled);
548 extern __checkReturn efx_rc_t
551 __out boolean_t *mac_upp);
553 #define EFX_FCNTL_RESPOND 0x00000001
554 #define EFX_FCNTL_GENERATE 0x00000002
556 extern __checkReturn efx_rc_t
559 __in unsigned int fcntl,
560 __in boolean_t autoneg);
565 __out unsigned int *fcntl_wantedp,
566 __out unsigned int *fcntl_linkp);
569 #if EFSYS_OPT_MAC_STATS
573 extern __checkReturn const char *
576 __in unsigned int id);
578 #endif /* EFSYS_OPT_NAMES */
580 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
582 #define EFX_MAC_STATS_MASK_NPAGES \
583 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
584 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
587 * Get mask of MAC statistics supported by the hardware.
589 * If mask_size is insufficient to return the mask, EINVAL error is
590 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
591 * (which is sizeof (uint32_t)) is sufficient.
593 extern __checkReturn efx_rc_t
594 efx_mac_stats_get_mask(
596 __out_bcount(mask_size) uint32_t *maskp,
597 __in size_t mask_size);
599 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
600 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
601 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
604 extern __checkReturn efx_rc_t
606 __in efx_nic_t *enp);
609 * Upload mac statistics supported by the hardware into the given buffer.
611 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
612 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
614 * The hardware will only DMA statistics that it understands (of course).
615 * Drivers should not make any assumptions about which statistics are
616 * supported, especially when the statistics are generated by firmware.
618 * Thus, drivers should zero this buffer before use, so that not-understood
619 * statistics read back as zero.
621 extern __checkReturn efx_rc_t
622 efx_mac_stats_upload(
624 __in efsys_mem_t *esmp);
626 extern __checkReturn efx_rc_t
627 efx_mac_stats_periodic(
629 __in efsys_mem_t *esmp,
630 __in uint16_t period_ms,
631 __in boolean_t events);
633 extern __checkReturn efx_rc_t
634 efx_mac_stats_update(
636 __in efsys_mem_t *esmp,
637 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
638 __inout_opt uint32_t *generationp);
640 #endif /* EFSYS_OPT_MAC_STATS */
644 typedef enum efx_mon_type_e {
656 __in efx_nic_t *enp);
658 #endif /* EFSYS_OPT_NAMES */
660 extern __checkReturn efx_rc_t
662 __in efx_nic_t *enp);
664 #if EFSYS_OPT_MON_STATS
666 #define EFX_MON_STATS_PAGE_SIZE 0x100
667 #define EFX_MON_MASK_ELEMENT_SIZE 32
669 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
670 typedef enum efx_mon_stat_e {
671 EFX_MON_STAT_CONTROLLER_TEMP,
672 EFX_MON_STAT_PHY_COMMON_TEMP,
673 EFX_MON_STAT_CONTROLLER_COOLING,
674 EFX_MON_STAT_PHY0_TEMP,
675 EFX_MON_STAT_PHY0_COOLING,
676 EFX_MON_STAT_PHY1_TEMP,
677 EFX_MON_STAT_PHY1_COOLING,
683 EFX_MON_STAT_IN_12V0,
684 EFX_MON_STAT_IN_1V2A,
685 EFX_MON_STAT_IN_VREF,
686 EFX_MON_STAT_OUT_VAOE,
687 EFX_MON_STAT_AOE_TEMP,
688 EFX_MON_STAT_PSU_AOE_TEMP,
689 EFX_MON_STAT_PSU_TEMP,
695 EFX_MON_STAT_IN_VAOE,
696 EFX_MON_STAT_OUT_IAOE,
697 EFX_MON_STAT_IN_IAOE,
698 EFX_MON_STAT_NIC_POWER,
700 EFX_MON_STAT_IN_I0V9,
701 EFX_MON_STAT_IN_I1V2,
702 EFX_MON_STAT_IN_0V9_ADC,
703 EFX_MON_STAT_CONTROLLER_2_TEMP,
704 EFX_MON_STAT_VREG_INTERNAL_TEMP,
705 EFX_MON_STAT_VREG_0V9_TEMP,
706 EFX_MON_STAT_VREG_1V2_TEMP,
707 EFX_MON_STAT_CONTROLLER_VPTAT,
708 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
709 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
710 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
711 EFX_MON_STAT_AMBIENT_TEMP,
712 EFX_MON_STAT_AIRFLOW,
713 EFX_MON_STAT_VDD08D_VSS08D_CSR,
714 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
715 EFX_MON_STAT_HOTPOINT_TEMP,
716 EFX_MON_STAT_PHY_POWER_PORT0,
717 EFX_MON_STAT_PHY_POWER_PORT1,
718 EFX_MON_STAT_MUM_VCC,
719 EFX_MON_STAT_IN_0V9_A,
720 EFX_MON_STAT_IN_I0V9_A,
721 EFX_MON_STAT_VREG_0V9_A_TEMP,
722 EFX_MON_STAT_IN_0V9_B,
723 EFX_MON_STAT_IN_I0V9_B,
724 EFX_MON_STAT_VREG_0V9_B_TEMP,
725 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
726 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
727 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
728 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
729 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
730 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
731 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
732 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
733 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
734 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
735 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
736 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
737 EFX_MON_STAT_SODIMM_VOUT,
738 EFX_MON_STAT_SODIMM_0_TEMP,
739 EFX_MON_STAT_SODIMM_1_TEMP,
740 EFX_MON_STAT_PHY0_VCC,
741 EFX_MON_STAT_PHY1_VCC,
742 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
743 EFX_MON_STAT_BOARD_FRONT_TEMP,
744 EFX_MON_STAT_BOARD_BACK_TEMP,
745 EFX_MON_STAT_IN_I1V8,
746 EFX_MON_STAT_IN_I2V5,
747 EFX_MON_STAT_IN_I3V3,
748 EFX_MON_STAT_IN_I12V0,
750 EFX_MON_STAT_IN_I1V3,
754 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
756 typedef enum efx_mon_stat_state_e {
757 EFX_MON_STAT_STATE_OK = 0,
758 EFX_MON_STAT_STATE_WARNING = 1,
759 EFX_MON_STAT_STATE_FATAL = 2,
760 EFX_MON_STAT_STATE_BROKEN = 3,
761 EFX_MON_STAT_STATE_NO_READING = 4,
762 } efx_mon_stat_state_t;
764 typedef enum efx_mon_stat_unit_e {
765 EFX_MON_STAT_UNIT_UNKNOWN = 0,
766 EFX_MON_STAT_UNIT_BOOL,
767 EFX_MON_STAT_UNIT_TEMP_C,
768 EFX_MON_STAT_UNIT_VOLTAGE_MV,
769 EFX_MON_STAT_UNIT_CURRENT_MA,
770 EFX_MON_STAT_UNIT_POWER_W,
771 EFX_MON_STAT_UNIT_RPM,
773 } efx_mon_stat_unit_t;
775 typedef struct efx_mon_stat_value_s {
777 efx_mon_stat_state_t emsv_state;
778 efx_mon_stat_unit_t emsv_unit;
779 } efx_mon_stat_value_t;
781 typedef struct efx_mon_limit_value_s {
782 uint16_t emlv_warning_min;
783 uint16_t emlv_warning_max;
784 uint16_t emlv_fatal_min;
785 uint16_t emlv_fatal_max;
786 } efx_mon_stat_limits_t;
788 typedef enum efx_mon_stat_portmask_e {
789 EFX_MON_STAT_PORTMAP_NONE = 0,
790 EFX_MON_STAT_PORTMAP_PORT0 = 1,
791 EFX_MON_STAT_PORTMAP_PORT1 = 2,
792 EFX_MON_STAT_PORTMAP_PORT2 = 3,
793 EFX_MON_STAT_PORTMAP_PORT3 = 4,
794 EFX_MON_STAT_PORTMAP_ALL = (-1),
795 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
796 } efx_mon_stat_portmask_t;
803 __in efx_mon_stat_t id);
806 efx_mon_stat_description(
808 __in efx_mon_stat_t id);
810 #endif /* EFSYS_OPT_NAMES */
812 extern __checkReturn boolean_t
813 efx_mon_mcdi_to_efx_stat(
815 __out efx_mon_stat_t *statp);
817 extern __checkReturn boolean_t
818 efx_mon_get_stat_unit(
819 __in efx_mon_stat_t stat,
820 __out efx_mon_stat_unit_t *unitp);
822 extern __checkReturn boolean_t
823 efx_mon_get_stat_portmap(
824 __in efx_mon_stat_t stat,
825 __out efx_mon_stat_portmask_t *maskp);
827 extern __checkReturn efx_rc_t
828 efx_mon_stats_update(
830 __in efsys_mem_t *esmp,
831 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
833 extern __checkReturn efx_rc_t
834 efx_mon_limits_update(
836 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
838 #endif /* EFSYS_OPT_MON_STATS */
842 __in efx_nic_t *enp);
846 extern __checkReturn efx_rc_t
848 __in efx_nic_t *enp);
850 #if EFSYS_OPT_PHY_LED_CONTROL
852 typedef enum efx_phy_led_mode_e {
853 EFX_PHY_LED_DEFAULT = 0,
858 } efx_phy_led_mode_t;
860 extern __checkReturn efx_rc_t
863 __in efx_phy_led_mode_t mode);
865 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
867 extern __checkReturn efx_rc_t
869 __in efx_nic_t *enp);
871 #if EFSYS_OPT_LOOPBACK
873 typedef enum efx_loopback_type_e {
874 EFX_LOOPBACK_OFF = 0,
875 EFX_LOOPBACK_DATA = 1,
876 EFX_LOOPBACK_GMAC = 2,
877 EFX_LOOPBACK_XGMII = 3,
878 EFX_LOOPBACK_XGXS = 4,
879 EFX_LOOPBACK_XAUI = 5,
880 EFX_LOOPBACK_GMII = 6,
881 EFX_LOOPBACK_SGMII = 7,
882 EFX_LOOPBACK_XGBR = 8,
883 EFX_LOOPBACK_XFI = 9,
884 EFX_LOOPBACK_XAUI_FAR = 10,
885 EFX_LOOPBACK_GMII_FAR = 11,
886 EFX_LOOPBACK_SGMII_FAR = 12,
887 EFX_LOOPBACK_XFI_FAR = 13,
888 EFX_LOOPBACK_GPHY = 14,
889 EFX_LOOPBACK_PHY_XS = 15,
890 EFX_LOOPBACK_PCS = 16,
891 EFX_LOOPBACK_PMA_PMD = 17,
892 EFX_LOOPBACK_XPORT = 18,
893 EFX_LOOPBACK_XGMII_WS = 19,
894 EFX_LOOPBACK_XAUI_WS = 20,
895 EFX_LOOPBACK_XAUI_WS_FAR = 21,
896 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
897 EFX_LOOPBACK_GMII_WS = 23,
898 EFX_LOOPBACK_XFI_WS = 24,
899 EFX_LOOPBACK_XFI_WS_FAR = 25,
900 EFX_LOOPBACK_PHYXS_WS = 26,
901 EFX_LOOPBACK_PMA_INT = 27,
902 EFX_LOOPBACK_SD_NEAR = 28,
903 EFX_LOOPBACK_SD_FAR = 29,
904 EFX_LOOPBACK_PMA_INT_WS = 30,
905 EFX_LOOPBACK_SD_FEP2_WS = 31,
906 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
907 EFX_LOOPBACK_SD_FEP_WS = 33,
908 EFX_LOOPBACK_SD_FES_WS = 34,
909 EFX_LOOPBACK_AOE_INT_NEAR = 35,
910 EFX_LOOPBACK_DATA_WS = 36,
911 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
913 } efx_loopback_type_t;
915 typedef enum efx_loopback_kind_e {
916 EFX_LOOPBACK_KIND_OFF = 0,
917 EFX_LOOPBACK_KIND_ALL,
918 EFX_LOOPBACK_KIND_MAC,
919 EFX_LOOPBACK_KIND_PHY,
921 } efx_loopback_kind_t;
925 __in efx_loopback_kind_t loopback_kind,
926 __out efx_qword_t *maskp);
928 extern __checkReturn efx_rc_t
929 efx_port_loopback_set(
931 __in efx_link_mode_t link_mode,
932 __in efx_loopback_type_t type);
936 extern __checkReturn const char *
937 efx_loopback_type_name(
939 __in efx_loopback_type_t type);
941 #endif /* EFSYS_OPT_NAMES */
943 #endif /* EFSYS_OPT_LOOPBACK */
945 extern __checkReturn efx_rc_t
948 __out_opt efx_link_mode_t *link_modep);
952 __in efx_nic_t *enp);
954 typedef enum efx_phy_cap_type_e {
955 EFX_PHY_CAP_INVALID = 0,
962 EFX_PHY_CAP_10000FDX,
966 EFX_PHY_CAP_40000FDX,
968 EFX_PHY_CAP_100000FDX,
969 EFX_PHY_CAP_25000FDX,
970 EFX_PHY_CAP_50000FDX,
971 EFX_PHY_CAP_BASER_FEC,
972 EFX_PHY_CAP_BASER_FEC_REQUESTED,
974 EFX_PHY_CAP_RS_FEC_REQUESTED,
975 EFX_PHY_CAP_25G_BASER_FEC,
976 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
978 } efx_phy_cap_type_t;
981 #define EFX_PHY_CAP_CURRENT 0x00000000
982 #define EFX_PHY_CAP_DEFAULT 0x00000001
983 #define EFX_PHY_CAP_PERM 0x00000002
989 __out uint32_t *maskp);
991 extern __checkReturn efx_rc_t
999 __out uint32_t *maskp);
1001 extern __checkReturn efx_rc_t
1003 __in efx_nic_t *enp,
1004 __out uint32_t *ouip);
1006 typedef enum efx_phy_media_type_e {
1007 EFX_PHY_MEDIA_INVALID = 0,
1012 EFX_PHY_MEDIA_SFP_PLUS,
1013 EFX_PHY_MEDIA_BASE_T,
1014 EFX_PHY_MEDIA_QSFP_PLUS,
1015 EFX_PHY_MEDIA_NTYPES
1016 } efx_phy_media_type_t;
1019 * Get the type of medium currently used. If the board has ports for
1020 * modules, a module is present, and we recognise the media type of
1021 * the module, then this will be the media type of the module.
1022 * Otherwise it will be the media type of the port.
1025 efx_phy_media_type_get(
1026 __in efx_nic_t *enp,
1027 __out efx_phy_media_type_t *typep);
1029 extern __checkReturn efx_rc_t
1030 efx_phy_module_get_info(
1031 __in efx_nic_t *enp,
1032 __in uint8_t dev_addr,
1033 __in uint8_t offset,
1035 __out_bcount(len) uint8_t *data);
1037 #if EFSYS_OPT_PHY_STATS
1039 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1040 typedef enum efx_phy_stat_e {
1042 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1043 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1044 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1045 EFX_PHY_STAT_PMA_PMD_REV_A,
1046 EFX_PHY_STAT_PMA_PMD_REV_B,
1047 EFX_PHY_STAT_PMA_PMD_REV_C,
1048 EFX_PHY_STAT_PMA_PMD_REV_D,
1049 EFX_PHY_STAT_PCS_LINK_UP,
1050 EFX_PHY_STAT_PCS_RX_FAULT,
1051 EFX_PHY_STAT_PCS_TX_FAULT,
1052 EFX_PHY_STAT_PCS_BER,
1053 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1054 EFX_PHY_STAT_PHY_XS_LINK_UP,
1055 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1056 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1057 EFX_PHY_STAT_PHY_XS_ALIGN,
1058 EFX_PHY_STAT_PHY_XS_SYNC_A,
1059 EFX_PHY_STAT_PHY_XS_SYNC_B,
1060 EFX_PHY_STAT_PHY_XS_SYNC_C,
1061 EFX_PHY_STAT_PHY_XS_SYNC_D,
1062 EFX_PHY_STAT_AN_LINK_UP,
1063 EFX_PHY_STAT_AN_MASTER,
1064 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1065 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1066 EFX_PHY_STAT_CL22EXT_LINK_UP,
1071 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1072 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1073 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1074 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1075 EFX_PHY_STAT_AN_COMPLETE,
1076 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1077 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1078 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1079 EFX_PHY_STAT_PCS_FW_VERSION_0,
1080 EFX_PHY_STAT_PCS_FW_VERSION_1,
1081 EFX_PHY_STAT_PCS_FW_VERSION_2,
1082 EFX_PHY_STAT_PCS_FW_VERSION_3,
1083 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1084 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1085 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1086 EFX_PHY_STAT_PCS_OP_MODE,
1090 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1096 __in efx_nic_t *enp,
1097 __in efx_phy_stat_t stat);
1099 #endif /* EFSYS_OPT_NAMES */
1101 #define EFX_PHY_STATS_SIZE 0x100
1103 extern __checkReturn efx_rc_t
1104 efx_phy_stats_update(
1105 __in efx_nic_t *enp,
1106 __in efsys_mem_t *esmp,
1107 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1109 #endif /* EFSYS_OPT_PHY_STATS */
1114 typedef enum efx_bist_type_e {
1115 EFX_BIST_TYPE_UNKNOWN,
1116 EFX_BIST_TYPE_PHY_NORMAL,
1117 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1118 EFX_BIST_TYPE_PHY_CABLE_LONG,
1119 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1120 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1121 EFX_BIST_TYPE_REG, /* Test the register memories */
1122 EFX_BIST_TYPE_NTYPES,
1125 typedef enum efx_bist_result_e {
1126 EFX_BIST_RESULT_UNKNOWN,
1127 EFX_BIST_RESULT_RUNNING,
1128 EFX_BIST_RESULT_PASSED,
1129 EFX_BIST_RESULT_FAILED,
1130 } efx_bist_result_t;
1132 typedef enum efx_phy_cable_status_e {
1133 EFX_PHY_CABLE_STATUS_OK,
1134 EFX_PHY_CABLE_STATUS_INVALID,
1135 EFX_PHY_CABLE_STATUS_OPEN,
1136 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1137 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1138 EFX_PHY_CABLE_STATUS_BUSY,
1139 } efx_phy_cable_status_t;
1141 typedef enum efx_bist_value_e {
1142 EFX_BIST_PHY_CABLE_LENGTH_A,
1143 EFX_BIST_PHY_CABLE_LENGTH_B,
1144 EFX_BIST_PHY_CABLE_LENGTH_C,
1145 EFX_BIST_PHY_CABLE_LENGTH_D,
1146 EFX_BIST_PHY_CABLE_STATUS_A,
1147 EFX_BIST_PHY_CABLE_STATUS_B,
1148 EFX_BIST_PHY_CABLE_STATUS_C,
1149 EFX_BIST_PHY_CABLE_STATUS_D,
1150 EFX_BIST_FAULT_CODE,
1152 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1158 EFX_BIST_MEM_EXPECT,
1159 EFX_BIST_MEM_ACTUAL,
1161 EFX_BIST_MEM_ECC_PARITY,
1162 EFX_BIST_MEM_ECC_FATAL,
1166 extern __checkReturn efx_rc_t
1167 efx_bist_enable_offline(
1168 __in efx_nic_t *enp);
1170 extern __checkReturn efx_rc_t
1172 __in efx_nic_t *enp,
1173 __in efx_bist_type_t type);
1175 extern __checkReturn efx_rc_t
1177 __in efx_nic_t *enp,
1178 __in efx_bist_type_t type,
1179 __out efx_bist_result_t *resultp,
1180 __out_opt uint32_t *value_maskp,
1181 __out_ecount_opt(count) unsigned long *valuesp,
1186 __in efx_nic_t *enp,
1187 __in efx_bist_type_t type);
1189 #endif /* EFSYS_OPT_BIST */
1191 #define EFX_FEATURE_IPV6 0x00000001
1192 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1193 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1194 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1195 #define EFX_FEATURE_MCDI 0x00000020
1196 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1197 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1198 #define EFX_FEATURE_TURBO 0x00000100
1199 #define EFX_FEATURE_MCDI_DMA 0x00000200
1200 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1201 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1202 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1203 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1204 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1206 typedef enum efx_tunnel_protocol_e {
1207 EFX_TUNNEL_PROTOCOL_NONE = 0,
1208 EFX_TUNNEL_PROTOCOL_VXLAN,
1209 EFX_TUNNEL_PROTOCOL_GENEVE,
1210 EFX_TUNNEL_PROTOCOL_NVGRE,
1212 } efx_tunnel_protocol_t;
1214 typedef enum efx_vi_window_shift_e {
1215 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1216 EFX_VI_WINDOW_SHIFT_8K = 13,
1217 EFX_VI_WINDOW_SHIFT_16K = 14,
1218 EFX_VI_WINDOW_SHIFT_64K = 16,
1219 } efx_vi_window_shift_t;
1221 typedef struct efx_nic_cfg_s {
1222 uint32_t enc_board_type;
1223 uint32_t enc_phy_type;
1225 char enc_phy_name[21];
1227 char enc_phy_revision[21];
1228 efx_mon_type_t enc_mon_type;
1229 #if EFSYS_OPT_MON_STATS
1230 uint32_t enc_mon_stat_dma_buf_size;
1231 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1233 unsigned int enc_features;
1234 efx_vi_window_shift_t enc_vi_window_shift;
1235 uint8_t enc_mac_addr[6];
1236 uint8_t enc_port; /* PHY port number */
1237 uint32_t enc_intr_vec_base;
1238 uint32_t enc_intr_limit;
1239 uint32_t enc_evq_limit;
1240 uint32_t enc_txq_limit;
1241 uint32_t enc_rxq_limit;
1242 uint32_t enc_txq_max_ndescs;
1243 uint32_t enc_buftbl_limit;
1244 uint32_t enc_piobuf_limit;
1245 uint32_t enc_piobuf_size;
1246 uint32_t enc_piobuf_min_alloc_size;
1247 uint32_t enc_evq_timer_quantum_ns;
1248 uint32_t enc_evq_timer_max_us;
1249 uint32_t enc_clk_mult;
1250 uint32_t enc_rx_prefix_size;
1251 uint32_t enc_rx_buf_align_start;
1252 uint32_t enc_rx_buf_align_end;
1253 uint32_t enc_rx_scale_max_exclusive_contexts;
1255 * Mask of supported hash algorithms.
1256 * Hash algorithm types are used as the bit indices.
1258 uint32_t enc_rx_scale_hash_alg_mask;
1260 * Indicates whether port numbers can be included to the
1261 * input data for hash computation.
1263 boolean_t enc_rx_scale_l4_hash_supported;
1264 boolean_t enc_rx_scale_additional_modes_supported;
1265 #if EFSYS_OPT_LOOPBACK
1266 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1267 #endif /* EFSYS_OPT_LOOPBACK */
1268 #if EFSYS_OPT_PHY_FLAGS
1269 uint32_t enc_phy_flags_mask;
1270 #endif /* EFSYS_OPT_PHY_FLAGS */
1271 #if EFSYS_OPT_PHY_LED_CONTROL
1272 uint32_t enc_led_mask;
1273 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1274 #if EFSYS_OPT_PHY_STATS
1275 uint64_t enc_phy_stat_mask;
1276 #endif /* EFSYS_OPT_PHY_STATS */
1278 uint8_t enc_mcdi_mdio_channel;
1279 #if EFSYS_OPT_PHY_STATS
1280 uint32_t enc_mcdi_phy_stat_mask;
1281 #endif /* EFSYS_OPT_PHY_STATS */
1282 #if EFSYS_OPT_MON_STATS
1283 uint32_t *enc_mcdi_sensor_maskp;
1284 uint32_t enc_mcdi_sensor_mask_size;
1285 #endif /* EFSYS_OPT_MON_STATS */
1286 #endif /* EFSYS_OPT_MCDI */
1288 uint32_t enc_bist_mask;
1289 #endif /* EFSYS_OPT_BIST */
1290 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1293 uint32_t enc_privilege_mask;
1294 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1295 boolean_t enc_bug26807_workaround;
1296 boolean_t enc_bug35388_workaround;
1297 boolean_t enc_bug41750_workaround;
1298 boolean_t enc_bug61265_workaround;
1299 boolean_t enc_bug61297_workaround;
1300 boolean_t enc_rx_batching_enabled;
1301 /* Maximum number of descriptors completed in an rx event. */
1302 uint32_t enc_rx_batch_max;
1303 /* Number of rx descriptors the hardware requires for a push. */
1304 uint32_t enc_rx_push_align;
1305 /* Maximum amount of data in DMA descriptor */
1306 uint32_t enc_tx_dma_desc_size_max;
1308 * Boundary which DMA descriptor data must not cross or 0 if no
1311 uint32_t enc_tx_dma_desc_boundary;
1313 * Maximum number of bytes into the packet the TCP header can start for
1314 * the hardware to apply TSO packet edits.
1316 uint32_t enc_tx_tso_tcp_header_offset_limit;
1317 boolean_t enc_fw_assisted_tso_enabled;
1318 boolean_t enc_fw_assisted_tso_v2_enabled;
1319 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1320 /* Number of TSO contexts on the NIC (FATSOv2) */
1321 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1322 boolean_t enc_hw_tx_insert_vlan_enabled;
1323 /* Number of PFs on the NIC */
1324 uint32_t enc_hw_pf_count;
1325 /* Datapath firmware vadapter/vport/vswitch support */
1326 boolean_t enc_datapath_cap_evb;
1327 boolean_t enc_rx_disable_scatter_supported;
1328 boolean_t enc_allow_set_mac_with_installed_filters;
1329 boolean_t enc_enhanced_set_mac_supported;
1330 boolean_t enc_init_evq_v2_supported;
1331 boolean_t enc_rx_packed_stream_supported;
1332 boolean_t enc_rx_var_packed_stream_supported;
1333 boolean_t enc_rx_es_super_buffer_supported;
1334 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1335 boolean_t enc_pm_and_rxdp_counters;
1336 boolean_t enc_mac_stats_40g_tx_size_bins;
1337 uint32_t enc_tunnel_encapsulations_supported;
1339 * NIC global maximum for unique UDP tunnel ports shared by all
1342 uint32_t enc_tunnel_config_udp_entries_max;
1343 /* External port identifier */
1344 uint8_t enc_external_port;
1345 uint32_t enc_mcdi_max_payload_length;
1346 /* VPD may be per-PF or global */
1347 boolean_t enc_vpd_is_global;
1348 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1349 uint32_t enc_required_pcie_bandwidth_mbps;
1350 uint32_t enc_max_pcie_link_gen;
1351 /* Firmware verifies integrity of NVRAM updates */
1352 uint32_t enc_nvram_update_verify_result_supported;
1353 /* Firmware support for extended MAC_STATS buffer */
1354 uint32_t enc_mac_stats_nstats;
1355 boolean_t enc_fec_counters;
1356 boolean_t enc_hlb_counters;
1357 /* Firmware support for "FLAG" and "MARK" filter actions */
1358 boolean_t enc_filter_action_flag_supported;
1359 boolean_t enc_filter_action_mark_supported;
1360 uint32_t enc_filter_action_mark_max;
1363 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1364 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1366 #define EFX_PCI_FUNCTION(_encp) \
1367 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1369 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1371 extern const efx_nic_cfg_t *
1373 __in efx_nic_t *enp);
1375 /* RxDPCPU firmware id values by which FW variant can be identified */
1376 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1377 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1378 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1379 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1380 #define EFX_RXDP_DPDK_FW_ID 0x6
1382 typedef struct efx_nic_fw_info_s {
1383 /* Basic FW version information */
1384 uint16_t enfi_mc_fw_version[4];
1386 * If datapath capabilities can be detected,
1387 * additional FW information is to be shown
1389 boolean_t enfi_dpcpu_fw_ids_valid;
1390 /* Rx and Tx datapath CPU FW IDs */
1391 uint16_t enfi_rx_dpcpu_fw_id;
1392 uint16_t enfi_tx_dpcpu_fw_id;
1393 } efx_nic_fw_info_t;
1395 extern __checkReturn efx_rc_t
1396 efx_nic_get_fw_version(
1397 __in efx_nic_t *enp,
1398 __out efx_nic_fw_info_t *enfip);
1400 /* Driver resource limits (minimum required/maximum usable). */
1401 typedef struct efx_drv_limits_s {
1402 uint32_t edl_min_evq_count;
1403 uint32_t edl_max_evq_count;
1405 uint32_t edl_min_rxq_count;
1406 uint32_t edl_max_rxq_count;
1408 uint32_t edl_min_txq_count;
1409 uint32_t edl_max_txq_count;
1411 /* PIO blocks (sub-allocated from piobuf) */
1412 uint32_t edl_min_pio_alloc_size;
1413 uint32_t edl_max_pio_alloc_count;
1416 extern __checkReturn efx_rc_t
1417 efx_nic_set_drv_limits(
1418 __inout efx_nic_t *enp,
1419 __in efx_drv_limits_t *edlp);
1421 typedef enum efx_nic_region_e {
1422 EFX_REGION_VI, /* Memory BAR UC mapping */
1423 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1426 extern __checkReturn efx_rc_t
1427 efx_nic_get_bar_region(
1428 __in efx_nic_t *enp,
1429 __in efx_nic_region_t region,
1430 __out uint32_t *offsetp,
1431 __out size_t *sizep);
1433 extern __checkReturn efx_rc_t
1434 efx_nic_get_vi_pool(
1435 __in efx_nic_t *enp,
1436 __out uint32_t *evq_countp,
1437 __out uint32_t *rxq_countp,
1438 __out uint32_t *txq_countp);
1443 typedef enum efx_vpd_tag_e {
1450 typedef uint16_t efx_vpd_keyword_t;
1452 typedef struct efx_vpd_value_s {
1453 efx_vpd_tag_t evv_tag;
1454 efx_vpd_keyword_t evv_keyword;
1456 uint8_t evv_value[0x100];
1460 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1462 extern __checkReturn efx_rc_t
1464 __in efx_nic_t *enp);
1466 extern __checkReturn efx_rc_t
1468 __in efx_nic_t *enp,
1469 __out size_t *sizep);
1471 extern __checkReturn efx_rc_t
1473 __in efx_nic_t *enp,
1474 __out_bcount(size) caddr_t data,
1477 extern __checkReturn efx_rc_t
1479 __in efx_nic_t *enp,
1480 __in_bcount(size) caddr_t data,
1483 extern __checkReturn efx_rc_t
1485 __in efx_nic_t *enp,
1486 __in_bcount(size) caddr_t data,
1489 extern __checkReturn efx_rc_t
1491 __in efx_nic_t *enp,
1492 __in_bcount(size) caddr_t data,
1494 __inout efx_vpd_value_t *evvp);
1496 extern __checkReturn efx_rc_t
1498 __in efx_nic_t *enp,
1499 __inout_bcount(size) caddr_t data,
1501 __in efx_vpd_value_t *evvp);
1503 extern __checkReturn efx_rc_t
1505 __in efx_nic_t *enp,
1506 __inout_bcount(size) caddr_t data,
1508 __out efx_vpd_value_t *evvp,
1509 __inout unsigned int *contp);
1511 extern __checkReturn efx_rc_t
1513 __in efx_nic_t *enp,
1514 __in_bcount(size) caddr_t data,
1519 __in efx_nic_t *enp);
1521 #endif /* EFSYS_OPT_VPD */
1527 typedef enum efx_nvram_type_e {
1528 EFX_NVRAM_INVALID = 0,
1530 EFX_NVRAM_BOOTROM_CFG,
1531 EFX_NVRAM_MC_FIRMWARE,
1532 EFX_NVRAM_MC_GOLDEN,
1538 EFX_NVRAM_FPGA_BACKUP,
1539 EFX_NVRAM_DYNAMIC_CFG,
1542 EFX_NVRAM_MUM_FIRMWARE,
1543 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1544 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1548 extern __checkReturn efx_rc_t
1550 __in efx_nic_t *enp);
1554 extern __checkReturn efx_rc_t
1556 __in efx_nic_t *enp);
1558 #endif /* EFSYS_OPT_DIAG */
1560 extern __checkReturn efx_rc_t
1562 __in efx_nic_t *enp,
1563 __in efx_nvram_type_t type,
1564 __out size_t *sizep);
1566 extern __checkReturn efx_rc_t
1568 __in efx_nic_t *enp,
1569 __in efx_nvram_type_t type,
1570 __out_opt size_t *pref_chunkp);
1572 extern __checkReturn efx_rc_t
1573 efx_nvram_rw_finish(
1574 __in efx_nic_t *enp,
1575 __in efx_nvram_type_t type,
1576 __out_opt uint32_t *verify_resultp);
1578 extern __checkReturn efx_rc_t
1579 efx_nvram_get_version(
1580 __in efx_nic_t *enp,
1581 __in efx_nvram_type_t type,
1582 __out uint32_t *subtypep,
1583 __out_ecount(4) uint16_t version[4]);
1585 extern __checkReturn efx_rc_t
1586 efx_nvram_read_chunk(
1587 __in efx_nic_t *enp,
1588 __in efx_nvram_type_t type,
1589 __in unsigned int offset,
1590 __out_bcount(size) caddr_t data,
1593 extern __checkReturn efx_rc_t
1594 efx_nvram_read_backup(
1595 __in efx_nic_t *enp,
1596 __in efx_nvram_type_t type,
1597 __in unsigned int offset,
1598 __out_bcount(size) caddr_t data,
1601 extern __checkReturn efx_rc_t
1602 efx_nvram_set_version(
1603 __in efx_nic_t *enp,
1604 __in efx_nvram_type_t type,
1605 __in_ecount(4) uint16_t version[4]);
1607 extern __checkReturn efx_rc_t
1609 __in efx_nic_t *enp,
1610 __in efx_nvram_type_t type,
1611 __in_bcount(partn_size) caddr_t partn_data,
1612 __in size_t partn_size);
1614 extern __checkReturn efx_rc_t
1616 __in efx_nic_t *enp,
1617 __in efx_nvram_type_t type);
1619 extern __checkReturn efx_rc_t
1620 efx_nvram_write_chunk(
1621 __in efx_nic_t *enp,
1622 __in efx_nvram_type_t type,
1623 __in unsigned int offset,
1624 __in_bcount(size) caddr_t data,
1629 __in efx_nic_t *enp);
1631 #endif /* EFSYS_OPT_NVRAM */
1633 #if EFSYS_OPT_BOOTCFG
1635 /* Report size and offset of bootcfg sector in NVRAM partition. */
1636 extern __checkReturn efx_rc_t
1637 efx_bootcfg_sector_info(
1638 __in efx_nic_t *enp,
1640 __out_opt uint32_t *sector_countp,
1641 __out size_t *offsetp,
1642 __out size_t *max_sizep);
1645 * Copy bootcfg sector data to a target buffer which may differ in size.
1646 * Optionally corrects format errors in source buffer.
1649 efx_bootcfg_copy_sector(
1650 __in efx_nic_t *enp,
1651 __inout_bcount(sector_length)
1653 __in size_t sector_length,
1654 __out_bcount(data_size) uint8_t *data,
1655 __in size_t data_size,
1656 __in boolean_t handle_format_errors);
1660 __in efx_nic_t *enp,
1661 __out_bcount(size) uint8_t *data,
1666 __in efx_nic_t *enp,
1667 __in_bcount(size) uint8_t *data,
1672 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1673 * (see https://tools.ietf.org/html/rfc1533)
1675 * Summarising the format: the buffer is a sequence of options. All options
1676 * begin with a tag octet, which uniquely identifies the option. Fixed-
1677 * length options without data consist of only a tag octet. Only options PAD
1678 * (0) and END (255) are fixed length. All other options are variable-length
1679 * with a length octet following the tag octet. The value of the length
1680 * octet does not include the two octets specifying the tag and length. The
1681 * length octet is followed by "length" octets of data.
1683 * Option data may be a sequence of sub-options in the same format. The data
1684 * content of the encapsulating option is one or more encapsulated sub-options,
1685 * with no terminating END tag is required.
1687 * To be valid, the top-level sequence of options should be terminated by an
1688 * END tag. The buffer should be padded with the PAD byte.
1690 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1691 * checksum octet. The full buffer (including after the END tag) contributes
1692 * to the checksum, hence the need to fill the buffer to the end with PAD.
1695 #define EFX_DHCP_END ((uint8_t)0xff)
1696 #define EFX_DHCP_PAD ((uint8_t)0)
1698 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
1699 (uint16_t)(((encapsulator) << 8) | (encapsulated))
1701 extern __checkReturn uint8_t
1703 __in_bcount(size) uint8_t const *data,
1706 extern __checkReturn efx_rc_t
1708 __in_bcount(size) uint8_t const *data,
1710 __out_opt size_t *usedp);
1712 extern __checkReturn efx_rc_t
1714 __in_bcount(buffer_length) uint8_t *bufferp,
1715 __in size_t buffer_length,
1717 __deref_out uint8_t **valuepp,
1718 __out size_t *value_lengthp);
1720 extern __checkReturn efx_rc_t
1722 __in_bcount(buffer_length) uint8_t *bufferp,
1723 __in size_t buffer_length,
1724 __deref_out uint8_t **endpp);
1727 extern __checkReturn efx_rc_t
1728 efx_dhcp_delete_tag(
1729 __inout_bcount(buffer_length) uint8_t *bufferp,
1730 __in size_t buffer_length,
1733 extern __checkReturn efx_rc_t
1735 __inout_bcount(buffer_length) uint8_t *bufferp,
1736 __in size_t buffer_length,
1738 __in_bcount_opt(value_length) uint8_t *valuep,
1739 __in size_t value_length);
1741 extern __checkReturn efx_rc_t
1742 efx_dhcp_update_tag(
1743 __inout_bcount(buffer_length) uint8_t *bufferp,
1744 __in size_t buffer_length,
1746 __in uint8_t *value_locationp,
1747 __in_bcount_opt(value_length) uint8_t *valuep,
1748 __in size_t value_length);
1751 #endif /* EFSYS_OPT_BOOTCFG */
1753 #if EFSYS_OPT_IMAGE_LAYOUT
1755 #include "ef10_signed_image_layout.h"
1758 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1761 * The image header format is extensible. However, older drivers require an
1762 * exact match of image header version and header length when validating and
1763 * writing firmware images.
1765 * To avoid breaking backward compatibility, we use the upper bits of the
1766 * controller version fields to contain an extra version number used for
1767 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1768 * version). See bug39254 and SF-102785-PS for details.
1770 typedef struct efx_image_header_s {
1772 uint32_t eih_version;
1774 uint32_t eih_subtype;
1775 uint32_t eih_code_size;
1778 uint32_t eih_controller_version_min;
1780 uint16_t eih_controller_version_min_short;
1781 uint8_t eih_extra_version_a;
1782 uint8_t eih_extra_version_b;
1786 uint32_t eih_controller_version_max;
1788 uint16_t eih_controller_version_max_short;
1789 uint8_t eih_extra_version_c;
1790 uint8_t eih_extra_version_d;
1793 uint16_t eih_code_version_a;
1794 uint16_t eih_code_version_b;
1795 uint16_t eih_code_version_c;
1796 uint16_t eih_code_version_d;
1797 } efx_image_header_t;
1799 #define EFX_IMAGE_HEADER_SIZE (40)
1800 #define EFX_IMAGE_HEADER_VERSION (4)
1801 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1804 typedef struct efx_image_trailer_s {
1806 } efx_image_trailer_t;
1808 #define EFX_IMAGE_TRAILER_SIZE (4)
1810 typedef enum efx_image_format_e {
1811 EFX_IMAGE_FORMAT_NO_IMAGE,
1812 EFX_IMAGE_FORMAT_INVALID,
1813 EFX_IMAGE_FORMAT_UNSIGNED,
1814 EFX_IMAGE_FORMAT_SIGNED,
1815 } efx_image_format_t;
1817 typedef struct efx_image_info_s {
1818 efx_image_format_t eii_format;
1819 uint8_t * eii_imagep;
1820 size_t eii_image_size;
1821 efx_image_header_t * eii_headerp;
1824 extern __checkReturn efx_rc_t
1825 efx_check_reflash_image(
1827 __in uint32_t buffer_size,
1828 __out efx_image_info_t *infop);
1830 extern __checkReturn efx_rc_t
1831 efx_build_signed_image_write_buffer(
1832 __out_bcount(buffer_size)
1834 __in uint32_t buffer_size,
1835 __in efx_image_info_t *infop,
1836 __out efx_image_header_t **headerpp);
1838 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1842 typedef enum efx_pattern_type_t {
1843 EFX_PATTERN_BYTE_INCREMENT = 0,
1844 EFX_PATTERN_ALL_THE_SAME,
1845 EFX_PATTERN_BIT_ALTERNATE,
1846 EFX_PATTERN_BYTE_ALTERNATE,
1847 EFX_PATTERN_BYTE_CHANGING,
1848 EFX_PATTERN_BIT_SWEEP,
1850 } efx_pattern_type_t;
1853 (*efx_sram_pattern_fn_t)(
1855 __in boolean_t negate,
1856 __out efx_qword_t *eqp);
1858 extern __checkReturn efx_rc_t
1860 __in efx_nic_t *enp,
1861 __in efx_pattern_type_t type);
1863 #endif /* EFSYS_OPT_DIAG */
1865 extern __checkReturn efx_rc_t
1866 efx_sram_buf_tbl_set(
1867 __in efx_nic_t *enp,
1869 __in efsys_mem_t *esmp,
1873 efx_sram_buf_tbl_clear(
1874 __in efx_nic_t *enp,
1878 #define EFX_BUF_TBL_SIZE 0x20000
1880 #define EFX_BUF_SIZE 4096
1884 typedef struct efx_evq_s efx_evq_t;
1886 #if EFSYS_OPT_QSTATS
1888 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1889 typedef enum efx_ev_qstat_e {
1895 EV_RX_PAUSE_FRM_ERR,
1896 EV_RX_BUF_OWNER_ID_ERR,
1897 EV_RX_IPV4_HDR_CHKSUM_ERR,
1898 EV_RX_TCP_UDP_CHKSUM_ERR,
1902 EV_RX_MCAST_HASH_MATCH,
1919 EV_DRIVER_SRM_UPD_DONE,
1920 EV_DRIVER_TX_DESCQ_FLS_DONE,
1921 EV_DRIVER_RX_DESCQ_FLS_DONE,
1922 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1923 EV_DRIVER_RX_DSC_ERROR,
1924 EV_DRIVER_TX_DSC_ERROR,
1930 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1932 #endif /* EFSYS_OPT_QSTATS */
1934 extern __checkReturn efx_rc_t
1936 __in efx_nic_t *enp);
1940 __in efx_nic_t *enp);
1942 #define EFX_EVQ_MAXNEVS 32768
1943 #define EFX_EVQ_MINNEVS 512
1945 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1946 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1948 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1949 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1950 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1951 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1953 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1954 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1955 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1957 extern __checkReturn efx_rc_t
1959 __in efx_nic_t *enp,
1960 __in unsigned int index,
1961 __in efsys_mem_t *esmp,
1965 __in uint32_t flags,
1966 __deref_out efx_evq_t **eepp);
1970 __in efx_evq_t *eep,
1971 __in uint16_t data);
1973 typedef __checkReturn boolean_t
1974 (*efx_initialized_ev_t)(
1975 __in_opt void *arg);
1977 #define EFX_PKT_UNICAST 0x0004
1978 #define EFX_PKT_START 0x0008
1980 #define EFX_PKT_VLAN_TAGGED 0x0010
1981 #define EFX_CKSUM_TCPUDP 0x0020
1982 #define EFX_CKSUM_IPV4 0x0040
1983 #define EFX_PKT_CONT 0x0080
1985 #define EFX_CHECK_VLAN 0x0100
1986 #define EFX_PKT_TCP 0x0200
1987 #define EFX_PKT_UDP 0x0400
1988 #define EFX_PKT_IPV4 0x0800
1990 #define EFX_PKT_IPV6 0x1000
1991 #define EFX_PKT_PREFIX_LEN 0x2000
1992 #define EFX_ADDR_MISMATCH 0x4000
1993 #define EFX_DISCARD 0x8000
1996 * The following flags are used only for packed stream
1997 * mode. The values for the flags are reused to fit into 16 bit,
1998 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1999 * packed stream mode
2001 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2002 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2005 #define EFX_EV_RX_NLABELS 32
2006 #define EFX_EV_TX_NLABELS 32
2008 typedef __checkReturn boolean_t
2011 __in uint32_t label,
2014 __in uint16_t flags);
2016 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2019 * Packed stream mode is documented in SF-112241-TC.
2020 * The general idea is that, instead of putting each incoming
2021 * packet into a separate buffer which is specified in a RX
2022 * descriptor, a large buffer is provided to the hardware and
2023 * packets are put there in a continuous stream.
2024 * The main advantage of such an approach is that RX queue refilling
2025 * happens much less frequently.
2027 * Equal stride packed stream mode is documented in SF-119419-TC.
2028 * The general idea is to utilize advantages of the packed stream,
2029 * but avoid indirection in packets representation.
2030 * The main advantage of such an approach is that RX queue refilling
2031 * happens much less frequently and packets buffers are independent
2032 * from upper layers point of view.
2035 typedef __checkReturn boolean_t
2038 __in uint32_t label,
2040 __in uint32_t pkt_count,
2041 __in uint16_t flags);
2045 typedef __checkReturn boolean_t
2048 __in uint32_t label,
2051 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2052 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2053 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2054 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2055 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2056 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2057 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2058 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2059 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2061 typedef __checkReturn boolean_t
2062 (*efx_exception_ev_t)(
2064 __in uint32_t label,
2065 __in uint32_t data);
2067 typedef __checkReturn boolean_t
2068 (*efx_rxq_flush_done_ev_t)(
2070 __in uint32_t rxq_index);
2072 typedef __checkReturn boolean_t
2073 (*efx_rxq_flush_failed_ev_t)(
2075 __in uint32_t rxq_index);
2077 typedef __checkReturn boolean_t
2078 (*efx_txq_flush_done_ev_t)(
2080 __in uint32_t txq_index);
2082 typedef __checkReturn boolean_t
2083 (*efx_software_ev_t)(
2085 __in uint16_t magic);
2087 typedef __checkReturn boolean_t
2090 __in uint32_t code);
2092 #define EFX_SRAM_CLEAR 0
2093 #define EFX_SRAM_UPDATE 1
2094 #define EFX_SRAM_ILLEGAL_CLEAR 2
2096 typedef __checkReturn boolean_t
2097 (*efx_wake_up_ev_t)(
2099 __in uint32_t label);
2101 typedef __checkReturn boolean_t
2104 __in uint32_t label);
2106 typedef __checkReturn boolean_t
2107 (*efx_link_change_ev_t)(
2109 __in efx_link_mode_t link_mode);
2111 #if EFSYS_OPT_MON_STATS
2113 typedef __checkReturn boolean_t
2114 (*efx_monitor_ev_t)(
2116 __in efx_mon_stat_t id,
2117 __in efx_mon_stat_value_t value);
2119 #endif /* EFSYS_OPT_MON_STATS */
2121 #if EFSYS_OPT_MAC_STATS
2123 typedef __checkReturn boolean_t
2124 (*efx_mac_stats_ev_t)(
2126 __in uint32_t generation);
2128 #endif /* EFSYS_OPT_MAC_STATS */
2130 typedef struct efx_ev_callbacks_s {
2131 efx_initialized_ev_t eec_initialized;
2133 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2134 efx_rx_ps_ev_t eec_rx_ps;
2137 efx_exception_ev_t eec_exception;
2138 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2139 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2140 efx_txq_flush_done_ev_t eec_txq_flush_done;
2141 efx_software_ev_t eec_software;
2142 efx_sram_ev_t eec_sram;
2143 efx_wake_up_ev_t eec_wake_up;
2144 efx_timer_ev_t eec_timer;
2145 efx_link_change_ev_t eec_link_change;
2146 #if EFSYS_OPT_MON_STATS
2147 efx_monitor_ev_t eec_monitor;
2148 #endif /* EFSYS_OPT_MON_STATS */
2149 #if EFSYS_OPT_MAC_STATS
2150 efx_mac_stats_ev_t eec_mac_stats;
2151 #endif /* EFSYS_OPT_MAC_STATS */
2152 } efx_ev_callbacks_t;
2154 extern __checkReturn boolean_t
2156 __in efx_evq_t *eep,
2157 __in unsigned int count);
2159 #if EFSYS_OPT_EV_PREFETCH
2163 __in efx_evq_t *eep,
2164 __in unsigned int count);
2166 #endif /* EFSYS_OPT_EV_PREFETCH */
2170 __in efx_evq_t *eep,
2171 __inout unsigned int *countp,
2172 __in const efx_ev_callbacks_t *eecp,
2173 __in_opt void *arg);
2175 extern __checkReturn efx_rc_t
2176 efx_ev_usecs_to_ticks(
2177 __in efx_nic_t *enp,
2178 __in unsigned int usecs,
2179 __out unsigned int *ticksp);
2181 extern __checkReturn efx_rc_t
2183 __in efx_evq_t *eep,
2184 __in unsigned int us);
2186 extern __checkReturn efx_rc_t
2188 __in efx_evq_t *eep,
2189 __in unsigned int count);
2191 #if EFSYS_OPT_QSTATS
2197 __in efx_nic_t *enp,
2198 __in unsigned int id);
2200 #endif /* EFSYS_OPT_NAMES */
2203 efx_ev_qstats_update(
2204 __in efx_evq_t *eep,
2205 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2207 #endif /* EFSYS_OPT_QSTATS */
2211 __in efx_evq_t *eep);
2215 extern __checkReturn efx_rc_t
2217 __inout efx_nic_t *enp);
2221 __in efx_nic_t *enp);
2223 #if EFSYS_OPT_RX_SCATTER
2224 __checkReturn efx_rc_t
2225 efx_rx_scatter_enable(
2226 __in efx_nic_t *enp,
2227 __in unsigned int buf_size);
2228 #endif /* EFSYS_OPT_RX_SCATTER */
2230 /* Handle to represent use of the default RSS context. */
2231 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2233 #if EFSYS_OPT_RX_SCALE
2235 typedef enum efx_rx_hash_alg_e {
2236 EFX_RX_HASHALG_LFSR = 0,
2237 EFX_RX_HASHALG_TOEPLITZ,
2238 EFX_RX_HASHALG_PACKED_STREAM,
2240 } efx_rx_hash_alg_t;
2243 * Legacy hash type flags.
2245 * They represent standard tuples for distinct traffic classes.
2247 #define EFX_RX_HASH_IPV4 (1U << 0)
2248 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2249 #define EFX_RX_HASH_IPV6 (1U << 2)
2250 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2252 #define EFX_RX_HASH_LEGACY_MASK \
2253 (EFX_RX_HASH_IPV4 | \
2254 EFX_RX_HASH_TCPIPV4 | \
2255 EFX_RX_HASH_IPV6 | \
2256 EFX_RX_HASH_TCPIPV6)
2259 * The type of the argument used by efx_rx_scale_mode_set() to
2260 * provide a means for the client drivers to configure hashing.
2262 * A properly constructed value can either be:
2263 * - a combination of legacy flags
2264 * - a combination of EFX_RX_HASH() flags
2266 typedef unsigned int efx_rx_hash_type_t;
2268 typedef enum efx_rx_hash_support_e {
2269 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2270 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2271 } efx_rx_hash_support_t;
2273 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2274 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2275 #define EFX_MAXRSS 64 /* RX indirection entry range */
2276 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2278 typedef enum efx_rx_scale_context_type_e {
2279 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2280 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2281 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2282 } efx_rx_scale_context_type_t;
2285 * Traffic classes eligible for hash computation.
2287 * Select packet headers used in computing the receive hash.
2288 * This uses the same encoding as the RSS_MODES field of
2289 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2291 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2292 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2293 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2294 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2295 #define EFX_RX_CLASS_IPV4_LBN 16
2296 #define EFX_RX_CLASS_IPV4_WIDTH 4
2297 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2298 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2299 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2300 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2301 #define EFX_RX_CLASS_IPV6_LBN 28
2302 #define EFX_RX_CLASS_IPV6_WIDTH 4
2304 #define EFX_RX_NCLASSES 6
2307 * Ancillary flags used to construct generic hash tuples.
2308 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2310 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2311 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2312 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2313 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2316 * Generic hash tuples.
2318 * They express combinations of packet fields
2319 * which can contribute to the hash value for
2320 * a particular traffic class.
2322 #define EFX_RX_CLASS_HASH_DISABLE 0
2324 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2325 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2327 #define EFX_RX_CLASS_HASH_2TUPLE \
2328 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2329 EFX_RX_CLASS_HASH_DST_ADDR)
2331 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2332 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2333 EFX_RX_CLASS_HASH_SRC_PORT)
2335 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2336 (EFX_RX_CLASS_HASH_DST_ADDR | \
2337 EFX_RX_CLASS_HASH_DST_PORT)
2339 #define EFX_RX_CLASS_HASH_4TUPLE \
2340 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2341 EFX_RX_CLASS_HASH_DST_ADDR | \
2342 EFX_RX_CLASS_HASH_SRC_PORT | \
2343 EFX_RX_CLASS_HASH_DST_PORT)
2345 #define EFX_RX_CLASS_HASH_NTUPLES 7
2348 * Hash flag constructor.
2350 * Resulting flags encode hash tuples for specific traffic classes.
2351 * The client drivers are encouraged to use these flags to form
2352 * a hash type value.
2354 #define EFX_RX_HASH(_class, _tuple) \
2355 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2356 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2359 * The maximum number of EFX_RX_HASH() flags.
2361 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2363 extern __checkReturn efx_rc_t
2364 efx_rx_scale_hash_flags_get(
2365 __in efx_nic_t *enp,
2366 __in efx_rx_hash_alg_t hash_alg,
2367 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
2368 __out unsigned int *nflagsp);
2370 extern __checkReturn efx_rc_t
2371 efx_rx_hash_default_support_get(
2372 __in efx_nic_t *enp,
2373 __out efx_rx_hash_support_t *supportp);
2376 extern __checkReturn efx_rc_t
2377 efx_rx_scale_default_support_get(
2378 __in efx_nic_t *enp,
2379 __out efx_rx_scale_context_type_t *typep);
2381 extern __checkReturn efx_rc_t
2382 efx_rx_scale_context_alloc(
2383 __in efx_nic_t *enp,
2384 __in efx_rx_scale_context_type_t type,
2385 __in uint32_t num_queues,
2386 __out uint32_t *rss_contextp);
2388 extern __checkReturn efx_rc_t
2389 efx_rx_scale_context_free(
2390 __in efx_nic_t *enp,
2391 __in uint32_t rss_context);
2393 extern __checkReturn efx_rc_t
2394 efx_rx_scale_mode_set(
2395 __in efx_nic_t *enp,
2396 __in uint32_t rss_context,
2397 __in efx_rx_hash_alg_t alg,
2398 __in efx_rx_hash_type_t type,
2399 __in boolean_t insert);
2401 extern __checkReturn efx_rc_t
2402 efx_rx_scale_tbl_set(
2403 __in efx_nic_t *enp,
2404 __in uint32_t rss_context,
2405 __in_ecount(n) unsigned int *table,
2408 extern __checkReturn efx_rc_t
2409 efx_rx_scale_key_set(
2410 __in efx_nic_t *enp,
2411 __in uint32_t rss_context,
2412 __in_ecount(n) uint8_t *key,
2415 extern __checkReturn uint32_t
2416 efx_pseudo_hdr_hash_get(
2417 __in efx_rxq_t *erp,
2418 __in efx_rx_hash_alg_t func,
2419 __in uint8_t *buffer);
2421 #endif /* EFSYS_OPT_RX_SCALE */
2423 extern __checkReturn efx_rc_t
2424 efx_pseudo_hdr_pkt_length_get(
2425 __in efx_rxq_t *erp,
2426 __in uint8_t *buffer,
2427 __out uint16_t *pkt_lengthp);
2429 #define EFX_RXQ_MAXNDESCS 4096
2430 #define EFX_RXQ_MINNDESCS 512
2432 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2433 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2434 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2435 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2437 typedef enum efx_rxq_type_e {
2438 EFX_RXQ_TYPE_DEFAULT,
2439 EFX_RXQ_TYPE_PACKED_STREAM,
2440 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2445 * Dummy flag to be used instead of 0 to make it clear that the argument
2446 * is receive queue flags.
2448 #define EFX_RXQ_FLAG_NONE 0x0
2449 #define EFX_RXQ_FLAG_SCATTER 0x1
2451 * If tunnels are supported and Rx event can provide information about
2452 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2453 * full-feature firmware variant running), outer classes are requested by
2454 * default. However, if the driver supports tunnels, the flag allows to
2455 * request inner classes which are required to be able to interpret inner
2456 * Rx checksum offload results.
2458 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2460 extern __checkReturn efx_rc_t
2462 __in efx_nic_t *enp,
2463 __in unsigned int index,
2464 __in unsigned int label,
2465 __in efx_rxq_type_t type,
2466 __in efsys_mem_t *esmp,
2469 __in unsigned int flags,
2470 __in efx_evq_t *eep,
2471 __deref_out efx_rxq_t **erpp);
2473 #if EFSYS_OPT_RX_PACKED_STREAM
2475 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2476 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2477 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2478 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2479 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2481 extern __checkReturn efx_rc_t
2482 efx_rx_qcreate_packed_stream(
2483 __in efx_nic_t *enp,
2484 __in unsigned int index,
2485 __in unsigned int label,
2486 __in uint32_t ps_buf_size,
2487 __in efsys_mem_t *esmp,
2489 __in efx_evq_t *eep,
2490 __deref_out efx_rxq_t **erpp);
2494 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2496 /* Maximum head-of-line block timeout in nanoseconds */
2497 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2499 extern __checkReturn efx_rc_t
2500 efx_rx_qcreate_es_super_buffer(
2501 __in efx_nic_t *enp,
2502 __in unsigned int index,
2503 __in unsigned int label,
2504 __in uint32_t n_bufs_per_desc,
2505 __in uint32_t max_dma_len,
2506 __in uint32_t buf_stride,
2507 __in uint32_t hol_block_timeout,
2508 __in efsys_mem_t *esmp,
2510 __in unsigned int flags,
2511 __in efx_evq_t *eep,
2512 __deref_out efx_rxq_t **erpp);
2516 typedef struct efx_buffer_s {
2517 efsys_dma_addr_t eb_addr;
2522 typedef struct efx_desc_s {
2528 __in efx_rxq_t *erp,
2529 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2531 __in unsigned int ndescs,
2532 __in unsigned int completed,
2533 __in unsigned int added);
2537 __in efx_rxq_t *erp,
2538 __in unsigned int added,
2539 __inout unsigned int *pushedp);
2541 #if EFSYS_OPT_RX_PACKED_STREAM
2544 efx_rx_qpush_ps_credits(
2545 __in efx_rxq_t *erp);
2547 extern __checkReturn uint8_t *
2548 efx_rx_qps_packet_info(
2549 __in efx_rxq_t *erp,
2550 __in uint8_t *buffer,
2551 __in uint32_t buffer_length,
2552 __in uint32_t current_offset,
2553 __out uint16_t *lengthp,
2554 __out uint32_t *next_offsetp,
2555 __out uint32_t *timestamp);
2558 extern __checkReturn efx_rc_t
2560 __in efx_rxq_t *erp);
2564 __in efx_rxq_t *erp);
2568 __in efx_rxq_t *erp);
2572 typedef struct efx_txq_s efx_txq_t;
2574 #if EFSYS_OPT_QSTATS
2576 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2577 typedef enum efx_tx_qstat_e {
2583 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2585 #endif /* EFSYS_OPT_QSTATS */
2587 extern __checkReturn efx_rc_t
2589 __in efx_nic_t *enp);
2593 __in efx_nic_t *enp);
2595 #define EFX_TXQ_MINNDESCS 512
2597 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2598 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2599 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2601 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2603 #define EFX_TXQ_CKSUM_IPV4 0x0001
2604 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2605 #define EFX_TXQ_FATSOV2 0x0004
2606 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2607 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2609 extern __checkReturn efx_rc_t
2611 __in efx_nic_t *enp,
2612 __in unsigned int index,
2613 __in unsigned int label,
2614 __in efsys_mem_t *esmp,
2617 __in uint16_t flags,
2618 __in efx_evq_t *eep,
2619 __deref_out efx_txq_t **etpp,
2620 __out unsigned int *addedp);
2622 extern __checkReturn efx_rc_t
2624 __in efx_txq_t *etp,
2625 __in_ecount(ndescs) efx_buffer_t *eb,
2626 __in unsigned int ndescs,
2627 __in unsigned int completed,
2628 __inout unsigned int *addedp);
2630 extern __checkReturn efx_rc_t
2632 __in efx_txq_t *etp,
2633 __in unsigned int ns);
2637 __in efx_txq_t *etp,
2638 __in unsigned int added,
2639 __in unsigned int pushed);
2641 extern __checkReturn efx_rc_t
2643 __in efx_txq_t *etp);
2647 __in efx_txq_t *etp);
2649 extern __checkReturn efx_rc_t
2651 __in efx_txq_t *etp);
2654 efx_tx_qpio_disable(
2655 __in efx_txq_t *etp);
2657 extern __checkReturn efx_rc_t
2659 __in efx_txq_t *etp,
2660 __in_ecount(buf_length) uint8_t *buffer,
2661 __in size_t buf_length,
2662 __in size_t pio_buf_offset);
2664 extern __checkReturn efx_rc_t
2666 __in efx_txq_t *etp,
2667 __in size_t pkt_length,
2668 __in unsigned int completed,
2669 __inout unsigned int *addedp);
2671 extern __checkReturn efx_rc_t
2673 __in efx_txq_t *etp,
2674 __in_ecount(n) efx_desc_t *ed,
2675 __in unsigned int n,
2676 __in unsigned int completed,
2677 __inout unsigned int *addedp);
2680 efx_tx_qdesc_dma_create(
2681 __in efx_txq_t *etp,
2682 __in efsys_dma_addr_t addr,
2685 __out efx_desc_t *edp);
2688 efx_tx_qdesc_tso_create(
2689 __in efx_txq_t *etp,
2690 __in uint16_t ipv4_id,
2691 __in uint32_t tcp_seq,
2692 __in uint8_t tcp_flags,
2693 __out efx_desc_t *edp);
2695 /* Number of FATSOv2 option descriptors */
2696 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2698 /* Maximum number of DMA segments per TSO packet (not superframe) */
2699 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2702 efx_tx_qdesc_tso2_create(
2703 __in efx_txq_t *etp,
2704 __in uint16_t ipv4_id,
2705 __in uint16_t outer_ipv4_id,
2706 __in uint32_t tcp_seq,
2707 __in uint16_t tcp_mss,
2708 __out_ecount(count) efx_desc_t *edp,
2712 efx_tx_qdesc_vlantci_create(
2713 __in efx_txq_t *etp,
2715 __out efx_desc_t *edp);
2718 efx_tx_qdesc_checksum_create(
2719 __in efx_txq_t *etp,
2720 __in uint16_t flags,
2721 __out efx_desc_t *edp);
2723 #if EFSYS_OPT_QSTATS
2729 __in efx_nic_t *etp,
2730 __in unsigned int id);
2732 #endif /* EFSYS_OPT_NAMES */
2735 efx_tx_qstats_update(
2736 __in efx_txq_t *etp,
2737 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2739 #endif /* EFSYS_OPT_QSTATS */
2743 __in efx_txq_t *etp);
2748 #if EFSYS_OPT_FILTER
2750 #define EFX_ETHER_TYPE_IPV4 0x0800
2751 #define EFX_ETHER_TYPE_IPV6 0x86DD
2753 #define EFX_IPPROTO_TCP 6
2754 #define EFX_IPPROTO_UDP 17
2755 #define EFX_IPPROTO_GRE 47
2757 /* Use RSS to spread across multiple queues */
2758 #define EFX_FILTER_FLAG_RX_RSS 0x01
2759 /* Enable RX scatter */
2760 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2762 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2763 * May only be set by the filter implementation for each type.
2764 * A removal request will restore the automatic filter in its place.
2766 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2767 /* Filter is for RX */
2768 #define EFX_FILTER_FLAG_RX 0x08
2769 /* Filter is for TX */
2770 #define EFX_FILTER_FLAG_TX 0x10
2771 /* Set match flag on the received packet */
2772 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2773 /* Set match mark on the received packet */
2774 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2776 typedef uint8_t efx_filter_flags_t;
2779 * Flags which specify the fields to match on. The values are the same as in the
2780 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2783 /* Match by remote IP host address */
2784 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2785 /* Match by local IP host address */
2786 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2787 /* Match by remote MAC address */
2788 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2789 /* Match by remote TCP/UDP port */
2790 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2791 /* Match by remote TCP/UDP port */
2792 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2793 /* Match by local TCP/UDP port */
2794 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2795 /* Match by Ether-type */
2796 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2797 /* Match by inner VLAN ID */
2798 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2799 /* Match by outer VLAN ID */
2800 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2801 /* Match by IP transport protocol */
2802 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2803 /* Match by VNI or VSID */
2804 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2805 /* For encapsulated packets, match by inner frame local MAC address */
2806 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2807 /* For encapsulated packets, match all multicast inner frames */
2808 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2809 /* For encapsulated packets, match all unicast inner frames */
2810 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2812 * Match by encap type, this flag does not correspond to
2813 * the MCDI match flags and any unoccupied value may be used
2815 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2816 /* Match otherwise-unmatched multicast and broadcast packets */
2817 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2818 /* Match otherwise-unmatched unicast packets */
2819 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2821 typedef uint32_t efx_filter_match_flags_t;
2823 typedef enum efx_filter_priority_s {
2824 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2825 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2826 * address list or hardware
2827 * requirements. This may only be used
2828 * by the filter implementation for
2830 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2831 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2832 * client (e.g. SR-IOV, HyperV VMQ etc.)
2834 } efx_filter_priority_t;
2837 * FIXME: All these fields are assumed to be in little-endian byte order.
2838 * It may be better for some to be big-endian. See bug42804.
2841 typedef struct efx_filter_spec_s {
2842 efx_filter_match_flags_t efs_match_flags;
2843 uint8_t efs_priority;
2844 efx_filter_flags_t efs_flags;
2845 uint16_t efs_dmaq_id;
2846 uint32_t efs_rss_context;
2847 uint16_t efs_outer_vid;
2848 uint16_t efs_inner_vid;
2849 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2850 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2851 uint16_t efs_ether_type;
2852 uint8_t efs_ip_proto;
2853 efx_tunnel_protocol_t efs_encap_type;
2854 uint16_t efs_loc_port;
2855 uint16_t efs_rem_port;
2856 efx_oword_t efs_rem_host;
2857 efx_oword_t efs_loc_host;
2858 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2859 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2861 } efx_filter_spec_t;
2864 /* Default values for use in filter specifications */
2865 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2866 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2868 extern __checkReturn efx_rc_t
2870 __in efx_nic_t *enp);
2874 __in efx_nic_t *enp);
2876 extern __checkReturn efx_rc_t
2878 __in efx_nic_t *enp,
2879 __inout efx_filter_spec_t *spec);
2881 extern __checkReturn efx_rc_t
2883 __in efx_nic_t *enp,
2884 __inout efx_filter_spec_t *spec);
2886 extern __checkReturn efx_rc_t
2888 __in efx_nic_t *enp);
2890 extern __checkReturn efx_rc_t
2891 efx_filter_supported_filters(
2892 __in efx_nic_t *enp,
2893 __out_ecount(buffer_length) uint32_t *buffer,
2894 __in size_t buffer_length,
2895 __out size_t *list_lengthp);
2898 efx_filter_spec_init_rx(
2899 __out efx_filter_spec_t *spec,
2900 __in efx_filter_priority_t priority,
2901 __in efx_filter_flags_t flags,
2902 __in efx_rxq_t *erp);
2905 efx_filter_spec_init_tx(
2906 __out efx_filter_spec_t *spec,
2907 __in efx_txq_t *etp);
2909 extern __checkReturn efx_rc_t
2910 efx_filter_spec_set_ipv4_local(
2911 __inout efx_filter_spec_t *spec,
2914 __in uint16_t port);
2916 extern __checkReturn efx_rc_t
2917 efx_filter_spec_set_ipv4_full(
2918 __inout efx_filter_spec_t *spec,
2920 __in uint32_t lhost,
2921 __in uint16_t lport,
2922 __in uint32_t rhost,
2923 __in uint16_t rport);
2925 extern __checkReturn efx_rc_t
2926 efx_filter_spec_set_eth_local(
2927 __inout efx_filter_spec_t *spec,
2929 __in const uint8_t *addr);
2932 efx_filter_spec_set_ether_type(
2933 __inout efx_filter_spec_t *spec,
2934 __in uint16_t ether_type);
2936 extern __checkReturn efx_rc_t
2937 efx_filter_spec_set_uc_def(
2938 __inout efx_filter_spec_t *spec);
2940 extern __checkReturn efx_rc_t
2941 efx_filter_spec_set_mc_def(
2942 __inout efx_filter_spec_t *spec);
2944 typedef enum efx_filter_inner_frame_match_e {
2945 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2946 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2947 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2948 } efx_filter_inner_frame_match_t;
2950 extern __checkReturn efx_rc_t
2951 efx_filter_spec_set_encap_type(
2952 __inout efx_filter_spec_t *spec,
2953 __in efx_tunnel_protocol_t encap_type,
2954 __in efx_filter_inner_frame_match_t inner_frame_match);
2956 extern __checkReturn efx_rc_t
2957 efx_filter_spec_set_vxlan_full(
2958 __inout efx_filter_spec_t *spec,
2959 __in const uint8_t *vxlan_id,
2960 __in const uint8_t *inner_addr,
2961 __in const uint8_t *outer_addr);
2963 #if EFSYS_OPT_RX_SCALE
2964 extern __checkReturn efx_rc_t
2965 efx_filter_spec_set_rss_context(
2966 __inout efx_filter_spec_t *spec,
2967 __in uint32_t rss_context);
2969 #endif /* EFSYS_OPT_FILTER */
2973 extern __checkReturn uint32_t
2975 __in_ecount(count) uint32_t const *input,
2977 __in uint32_t init);
2979 extern __checkReturn uint32_t
2981 __in_ecount(length) uint8_t const *input,
2983 __in uint32_t init);
2985 #if EFSYS_OPT_LICENSING
2989 typedef struct efx_key_stats_s {
2991 uint32_t eks_invalid;
2992 uint32_t eks_blacklisted;
2993 uint32_t eks_unverifiable;
2994 uint32_t eks_wrong_node;
2995 uint32_t eks_licensed_apps_lo;
2996 uint32_t eks_licensed_apps_hi;
2997 uint32_t eks_licensed_features_lo;
2998 uint32_t eks_licensed_features_hi;
3001 extern __checkReturn efx_rc_t
3003 __in efx_nic_t *enp);
3007 __in efx_nic_t *enp);
3009 extern __checkReturn boolean_t
3010 efx_lic_check_support(
3011 __in efx_nic_t *enp);
3013 extern __checkReturn efx_rc_t
3014 efx_lic_update_licenses(
3015 __in efx_nic_t *enp);
3017 extern __checkReturn efx_rc_t
3018 efx_lic_get_key_stats(
3019 __in efx_nic_t *enp,
3020 __out efx_key_stats_t *ksp);
3022 extern __checkReturn efx_rc_t
3024 __in efx_nic_t *enp,
3025 __in uint64_t app_id,
3026 __out boolean_t *licensedp);
3028 extern __checkReturn efx_rc_t
3030 __in efx_nic_t *enp,
3031 __in size_t buffer_size,
3032 __out uint32_t *typep,
3033 __out size_t *lengthp,
3034 __out_opt uint8_t *bufferp);
3037 extern __checkReturn efx_rc_t
3039 __in efx_nic_t *enp,
3040 __in_bcount(buffer_size)
3042 __in size_t buffer_size,
3043 __out uint32_t *startp);
3045 extern __checkReturn efx_rc_t
3047 __in efx_nic_t *enp,
3048 __in_bcount(buffer_size)
3050 __in size_t buffer_size,
3051 __in uint32_t offset,
3052 __out uint32_t *endp);
3054 extern __checkReturn __success(return != B_FALSE) boolean_t
3056 __in efx_nic_t *enp,
3057 __in_bcount(buffer_size)
3059 __in size_t buffer_size,
3060 __in uint32_t offset,
3061 __out uint32_t *startp,
3062 __out uint32_t *lengthp);
3064 extern __checkReturn __success(return != B_FALSE) boolean_t
3065 efx_lic_validate_key(
3066 __in efx_nic_t *enp,
3067 __in_bcount(length) caddr_t keyp,
3068 __in uint32_t length);
3070 extern __checkReturn efx_rc_t
3072 __in efx_nic_t *enp,
3073 __in_bcount(buffer_size)
3075 __in size_t buffer_size,
3076 __in uint32_t offset,
3077 __in uint32_t length,
3078 __out_bcount_part(key_max_size, *lengthp)
3080 __in size_t key_max_size,
3081 __out uint32_t *lengthp);
3083 extern __checkReturn efx_rc_t
3085 __in efx_nic_t *enp,
3086 __in_bcount(buffer_size)
3088 __in size_t buffer_size,
3089 __in uint32_t offset,
3090 __in_bcount(length) caddr_t keyp,
3091 __in uint32_t length,
3092 __out uint32_t *lengthp);
3094 __checkReturn efx_rc_t
3096 __in efx_nic_t *enp,
3097 __in_bcount(buffer_size)
3099 __in size_t buffer_size,
3100 __in uint32_t offset,
3101 __in uint32_t length,
3103 __out uint32_t *deltap);
3105 extern __checkReturn efx_rc_t
3106 efx_lic_create_partition(
3107 __in efx_nic_t *enp,
3108 __in_bcount(buffer_size)
3110 __in size_t buffer_size);
3112 extern __checkReturn efx_rc_t
3113 efx_lic_finish_partition(
3114 __in efx_nic_t *enp,
3115 __in_bcount(buffer_size)
3117 __in size_t buffer_size);
3119 #endif /* EFSYS_OPT_LICENSING */
3123 #if EFSYS_OPT_TUNNEL
3125 extern __checkReturn efx_rc_t
3127 __in efx_nic_t *enp);
3131 __in efx_nic_t *enp);
3134 * For overlay network encapsulation using UDP, the firmware needs to know
3135 * the configured UDP port for the overlay so it can decode encapsulated
3137 * The UDP port/protocol list is global.
3140 extern __checkReturn efx_rc_t
3141 efx_tunnel_config_udp_add(
3142 __in efx_nic_t *enp,
3143 __in uint16_t port /* host/cpu-endian */,
3144 __in efx_tunnel_protocol_t protocol);
3146 extern __checkReturn efx_rc_t
3147 efx_tunnel_config_udp_remove(
3148 __in efx_nic_t *enp,
3149 __in uint16_t port /* host/cpu-endian */,
3150 __in efx_tunnel_protocol_t protocol);
3153 efx_tunnel_config_clear(
3154 __in efx_nic_t *enp);
3157 * Apply tunnel UDP ports configuration to hardware.
3159 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3162 extern __checkReturn efx_rc_t
3163 efx_tunnel_reconfigure(
3164 __in efx_nic_t *enp);
3166 #endif /* EFSYS_OPT_TUNNEL */
3168 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3171 * Firmware subvariant choice options.
3173 * It may be switched to no Tx checksum if attached drivers are either
3174 * preboot or firmware subvariant aware and no VIS are allocated.
3175 * If may be always switched to default explicitly using set request or
3176 * implicitly if unaware driver is attaching. If switching is done when
3177 * a driver is attached, it gets MC_REBOOT event and should recreate its
3180 * See SF-119419-TC DPDK Firmware Driver Interface and
3181 * SF-109306-TC EF10 for Driver Writers for details.
3183 typedef enum efx_nic_fw_subvariant_e {
3184 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3185 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3186 EFX_NIC_FW_SUBVARIANT_NTYPES
3187 } efx_nic_fw_subvariant_t;
3189 extern __checkReturn efx_rc_t
3190 efx_nic_get_fw_subvariant(
3191 __in efx_nic_t *enp,
3192 __out efx_nic_fw_subvariant_t *subvariantp);
3194 extern __checkReturn efx_rc_t
3195 efx_nic_set_fw_subvariant(
3196 __in efx_nic_t *enp,
3197 __in efx_nic_fw_subvariant_t subvariant);
3199 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3205 #endif /* _SYS_EFX_H */