2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 __in efx_nic_t *enp);
155 __in efx_nic_t *enp);
159 __in efx_nic_t *enp);
161 #define EFX_PCIE_LINK_SPEED_GEN1 1
162 #define EFX_PCIE_LINK_SPEED_GEN2 2
163 #define EFX_PCIE_LINK_SPEED_GEN3 3
165 typedef enum efx_pcie_link_performance_e {
166 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
167 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
168 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
169 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
170 } efx_pcie_link_performance_t;
172 extern __checkReturn efx_rc_t
173 efx_nic_calculate_pcie_link_bandwidth(
174 __in uint32_t pcie_link_width,
175 __in uint32_t pcie_link_gen,
176 __out uint32_t *bandwidth_mbpsp);
178 extern __checkReturn efx_rc_t
179 efx_nic_check_pcie_link_speed(
181 __in uint32_t pcie_link_width,
182 __in uint32_t pcie_link_gen,
183 __out efx_pcie_link_performance_t *resultp);
187 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
189 typedef enum efx_mcdi_exception_e {
190 EFX_MCDI_EXCEPTION_MC_REBOOT,
191 EFX_MCDI_EXCEPTION_MC_BADASSERT,
192 } efx_mcdi_exception_t;
194 typedef struct efx_mcdi_transport_s {
196 efsys_mem_t *emt_dma_mem;
197 void (*emt_execute)(void *, efx_mcdi_req_t *);
198 void (*emt_ev_cpl)(void *);
199 void (*emt_exception)(void *, efx_mcdi_exception_t);
200 } efx_mcdi_transport_t;
202 extern __checkReturn efx_rc_t
205 __in const efx_mcdi_transport_t *mtp);
207 extern __checkReturn efx_rc_t
209 __in efx_nic_t *enp);
213 __in efx_nic_t *enp);
216 efx_mcdi_get_timeout(
218 __in efx_mcdi_req_t *emrp,
219 __out uint32_t *usec_timeoutp);
222 efx_mcdi_request_start(
224 __in efx_mcdi_req_t *emrp,
225 __in boolean_t ev_cpl);
227 extern __checkReturn boolean_t
228 efx_mcdi_request_poll(
229 __in efx_nic_t *enp);
231 extern __checkReturn boolean_t
232 efx_mcdi_request_abort(
233 __in efx_nic_t *enp);
237 __in efx_nic_t *enp);
239 #endif /* EFSYS_OPT_MCDI */
243 #define EFX_NINTR_SIENA 1024
245 typedef enum efx_intr_type_e {
246 EFX_INTR_INVALID = 0,
252 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
254 extern __checkReturn efx_rc_t
257 __in efx_intr_type_t type,
258 __in efsys_mem_t *esmp);
262 __in efx_nic_t *enp);
266 __in efx_nic_t *enp);
269 efx_intr_disable_unlocked(
270 __in efx_nic_t *enp);
272 #define EFX_INTR_NEVQS 32
274 extern __checkReturn efx_rc_t
277 __in unsigned int level);
280 efx_intr_status_line(
282 __out boolean_t *fatalp,
283 __out uint32_t *maskp);
286 efx_intr_status_message(
288 __in unsigned int message,
289 __out boolean_t *fatalp);
293 __in efx_nic_t *enp);
297 __in efx_nic_t *enp);
301 typedef enum efx_link_mode_e {
302 EFX_LINK_UNKNOWN = 0,
315 #define EFX_MAC_ADDR_LEN 6
317 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
319 #define EFX_MAC_MULTICAST_LIST_MAX 256
321 #define EFX_MAC_SDU_MAX 9202
323 #define EFX_MAC_PDU_ADJUSTMENT \
327 + /* bug16011 */ 16) \
329 #define EFX_MAC_PDU(_sdu) \
330 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
333 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
334 * the SDU rounded up slightly.
336 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
338 #define EFX_MAC_PDU_MIN 60
339 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
341 extern __checkReturn efx_rc_t
346 extern __checkReturn efx_rc_t
351 extern __checkReturn efx_rc_t
356 extern __checkReturn efx_rc_t
359 __in boolean_t all_unicst,
360 __in boolean_t mulcst,
361 __in boolean_t all_mulcst,
362 __in boolean_t brdcst);
364 extern __checkReturn efx_rc_t
365 efx_mac_multicast_list_set(
367 __in_ecount(6*count) uint8_t const *addrs,
370 extern __checkReturn efx_rc_t
371 efx_mac_filter_default_rxq_set(
374 __in boolean_t using_rss);
377 efx_mac_filter_default_rxq_clear(
378 __in efx_nic_t *enp);
380 extern __checkReturn efx_rc_t
383 __in boolean_t enabled);
385 extern __checkReturn efx_rc_t
388 __out boolean_t *mac_upp);
390 #define EFX_FCNTL_RESPOND 0x00000001
391 #define EFX_FCNTL_GENERATE 0x00000002
393 extern __checkReturn efx_rc_t
396 __in unsigned int fcntl,
397 __in boolean_t autoneg);
402 __out unsigned int *fcntl_wantedp,
403 __out unsigned int *fcntl_linkp);
408 typedef enum efx_mon_type_e {
420 __in efx_nic_t *enp);
422 #endif /* EFSYS_OPT_NAMES */
424 extern __checkReturn efx_rc_t
426 __in efx_nic_t *enp);
430 __in efx_nic_t *enp);
434 extern __checkReturn efx_rc_t
436 __in efx_nic_t *enp);
438 extern __checkReturn efx_rc_t
440 __in efx_nic_t *enp);
442 extern __checkReturn efx_rc_t
445 __out_opt efx_link_mode_t *link_modep);
449 __in efx_nic_t *enp);
451 typedef enum efx_phy_cap_type_e {
452 EFX_PHY_CAP_INVALID = 0,
459 EFX_PHY_CAP_10000FDX,
463 EFX_PHY_CAP_40000FDX,
465 } efx_phy_cap_type_t;
468 #define EFX_PHY_CAP_CURRENT 0x00000000
469 #define EFX_PHY_CAP_DEFAULT 0x00000001
470 #define EFX_PHY_CAP_PERM 0x00000002
476 __out uint32_t *maskp);
478 extern __checkReturn efx_rc_t
486 __out uint32_t *maskp);
488 extern __checkReturn efx_rc_t
491 __out uint32_t *ouip);
493 typedef enum efx_phy_media_type_e {
494 EFX_PHY_MEDIA_INVALID = 0,
499 EFX_PHY_MEDIA_SFP_PLUS,
500 EFX_PHY_MEDIA_BASE_T,
501 EFX_PHY_MEDIA_QSFP_PLUS,
503 } efx_phy_media_type_t;
505 /* Get the type of medium currently used. If the board has ports for
506 * modules, a module is present, and we recognise the media type of
507 * the module, then this will be the media type of the module.
508 * Otherwise it will be the media type of the port.
511 efx_phy_media_type_get(
513 __out efx_phy_media_type_t *typep);
516 efx_phy_module_get_info(
518 __in uint8_t dev_addr,
521 __out_bcount(len) uint8_t *data);
524 #define EFX_FEATURE_IPV6 0x00000001
525 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
526 #define EFX_FEATURE_LINK_EVENTS 0x00000004
527 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
528 #define EFX_FEATURE_MCDI 0x00000020
529 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
530 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
531 #define EFX_FEATURE_TURBO 0x00000100
532 #define EFX_FEATURE_MCDI_DMA 0x00000200
533 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
534 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
535 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
536 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
537 #define EFX_FEATURE_PACKED_STREAM 0x00004000
539 typedef struct efx_nic_cfg_s {
540 uint32_t enc_board_type;
541 uint32_t enc_phy_type;
543 char enc_phy_name[21];
545 char enc_phy_revision[21];
546 efx_mon_type_t enc_mon_type;
547 unsigned int enc_features;
548 uint8_t enc_mac_addr[6];
549 uint8_t enc_port; /* PHY port number */
550 uint32_t enc_intr_vec_base;
551 uint32_t enc_intr_limit;
552 uint32_t enc_evq_limit;
553 uint32_t enc_txq_limit;
554 uint32_t enc_rxq_limit;
555 uint32_t enc_txq_max_ndescs;
556 uint32_t enc_buftbl_limit;
557 uint32_t enc_piobuf_limit;
558 uint32_t enc_piobuf_size;
559 uint32_t enc_piobuf_min_alloc_size;
560 uint32_t enc_evq_timer_quantum_ns;
561 uint32_t enc_evq_timer_max_us;
562 uint32_t enc_clk_mult;
563 uint32_t enc_rx_prefix_size;
564 uint32_t enc_rx_buf_align_start;
565 uint32_t enc_rx_buf_align_end;
567 uint8_t enc_mcdi_mdio_channel;
568 #endif /* EFSYS_OPT_MCDI */
569 boolean_t enc_bug26807_workaround;
570 boolean_t enc_bug35388_workaround;
571 boolean_t enc_bug41750_workaround;
572 boolean_t enc_bug61265_workaround;
573 boolean_t enc_rx_batching_enabled;
574 /* Maximum number of descriptors completed in an rx event. */
575 uint32_t enc_rx_batch_max;
576 /* Number of rx descriptors the hardware requires for a push. */
577 uint32_t enc_rx_push_align;
579 * Maximum number of bytes into the packet the TCP header can start for
580 * the hardware to apply TSO packet edits.
582 uint32_t enc_tx_tso_tcp_header_offset_limit;
583 boolean_t enc_fw_assisted_tso_enabled;
584 boolean_t enc_fw_assisted_tso_v2_enabled;
585 /* Number of TSO contexts on the NIC (FATSOv2) */
586 uint32_t enc_fw_assisted_tso_v2_n_contexts;
587 boolean_t enc_hw_tx_insert_vlan_enabled;
588 /* Number of PFs on the NIC */
589 uint32_t enc_hw_pf_count;
590 /* Datapath firmware vadapter/vport/vswitch support */
591 boolean_t enc_datapath_cap_evb;
592 boolean_t enc_rx_disable_scatter_supported;
593 boolean_t enc_allow_set_mac_with_installed_filters;
594 boolean_t enc_enhanced_set_mac_supported;
595 boolean_t enc_init_evq_v2_supported;
596 boolean_t enc_rx_packed_stream_supported;
597 boolean_t enc_rx_var_packed_stream_supported;
598 boolean_t enc_pm_and_rxdp_counters;
599 boolean_t enc_mac_stats_40g_tx_size_bins;
600 /* External port identifier */
601 uint8_t enc_external_port;
602 uint32_t enc_mcdi_max_payload_length;
603 /* VPD may be per-PF or global */
604 boolean_t enc_vpd_is_global;
605 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
606 uint32_t enc_required_pcie_bandwidth_mbps;
607 uint32_t enc_max_pcie_link_gen;
608 /* Firmware verifies integrity of NVRAM updates */
609 uint32_t enc_fw_verified_nvram_update_required;
612 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
613 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
615 #define EFX_PCI_FUNCTION(_encp) \
616 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
618 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
620 extern const efx_nic_cfg_t *
622 __in efx_nic_t *enp);
624 /* Driver resource limits (minimum required/maximum usable). */
625 typedef struct efx_drv_limits_s {
626 uint32_t edl_min_evq_count;
627 uint32_t edl_max_evq_count;
629 uint32_t edl_min_rxq_count;
630 uint32_t edl_max_rxq_count;
632 uint32_t edl_min_txq_count;
633 uint32_t edl_max_txq_count;
635 /* PIO blocks (sub-allocated from piobuf) */
636 uint32_t edl_min_pio_alloc_size;
637 uint32_t edl_max_pio_alloc_count;
640 extern __checkReturn efx_rc_t
641 efx_nic_set_drv_limits(
642 __inout efx_nic_t *enp,
643 __in efx_drv_limits_t *edlp);
645 typedef enum efx_nic_region_e {
646 EFX_REGION_VI, /* Memory BAR UC mapping */
647 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
650 extern __checkReturn efx_rc_t
651 efx_nic_get_bar_region(
653 __in efx_nic_region_t region,
654 __out uint32_t *offsetp,
655 __out size_t *sizep);
657 extern __checkReturn efx_rc_t
660 __out uint32_t *evq_countp,
661 __out uint32_t *rxq_countp,
662 __out uint32_t *txq_countp);
667 extern __checkReturn efx_rc_t
668 efx_sram_buf_tbl_set(
671 __in efsys_mem_t *esmp,
675 efx_sram_buf_tbl_clear(
680 #define EFX_BUF_TBL_SIZE 0x20000
682 #define EFX_BUF_SIZE 4096
686 typedef struct efx_evq_s efx_evq_t;
688 extern __checkReturn efx_rc_t
690 __in efx_nic_t *enp);
694 __in efx_nic_t *enp);
696 #define EFX_EVQ_MAXNEVS 32768
697 #define EFX_EVQ_MINNEVS 512
699 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
700 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
702 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
703 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
704 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
705 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
707 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
708 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
709 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
711 extern __checkReturn efx_rc_t
714 __in unsigned int index,
715 __in efsys_mem_t *esmp,
720 __deref_out efx_evq_t **eepp);
727 typedef __checkReturn boolean_t
728 (*efx_initialized_ev_t)(
731 #define EFX_PKT_UNICAST 0x0004
732 #define EFX_PKT_START 0x0008
734 #define EFX_PKT_VLAN_TAGGED 0x0010
735 #define EFX_CKSUM_TCPUDP 0x0020
736 #define EFX_CKSUM_IPV4 0x0040
737 #define EFX_PKT_CONT 0x0080
739 #define EFX_CHECK_VLAN 0x0100
740 #define EFX_PKT_TCP 0x0200
741 #define EFX_PKT_UDP 0x0400
742 #define EFX_PKT_IPV4 0x0800
744 #define EFX_PKT_IPV6 0x1000
745 #define EFX_PKT_PREFIX_LEN 0x2000
746 #define EFX_ADDR_MISMATCH 0x4000
747 #define EFX_DISCARD 0x8000
750 * The following flags are used only for packed stream
751 * mode. The values for the flags are reused to fit into 16 bit,
752 * since EFX_PKT_START and EFX_PKT_CONT are never used in
755 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
756 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
759 #define EFX_EV_RX_NLABELS 32
760 #define EFX_EV_TX_NLABELS 32
762 typedef __checkReturn boolean_t
768 __in uint16_t flags);
770 typedef __checkReturn boolean_t
776 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
777 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
778 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
779 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
780 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
781 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
782 #define EFX_EXCEPTION_RX_ERROR 0x00000007
783 #define EFX_EXCEPTION_TX_ERROR 0x00000008
784 #define EFX_EXCEPTION_EV_ERROR 0x00000009
786 typedef __checkReturn boolean_t
787 (*efx_exception_ev_t)(
792 typedef __checkReturn boolean_t
793 (*efx_rxq_flush_done_ev_t)(
795 __in uint32_t rxq_index);
797 typedef __checkReturn boolean_t
798 (*efx_rxq_flush_failed_ev_t)(
800 __in uint32_t rxq_index);
802 typedef __checkReturn boolean_t
803 (*efx_txq_flush_done_ev_t)(
805 __in uint32_t txq_index);
807 typedef __checkReturn boolean_t
808 (*efx_software_ev_t)(
810 __in uint16_t magic);
812 typedef __checkReturn boolean_t
817 #define EFX_SRAM_CLEAR 0
818 #define EFX_SRAM_UPDATE 1
819 #define EFX_SRAM_ILLEGAL_CLEAR 2
821 typedef __checkReturn boolean_t
824 __in uint32_t label);
826 typedef __checkReturn boolean_t
829 __in uint32_t label);
831 typedef __checkReturn boolean_t
832 (*efx_link_change_ev_t)(
834 __in efx_link_mode_t link_mode);
836 typedef struct efx_ev_callbacks_s {
837 efx_initialized_ev_t eec_initialized;
840 efx_exception_ev_t eec_exception;
841 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
842 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
843 efx_txq_flush_done_ev_t eec_txq_flush_done;
844 efx_software_ev_t eec_software;
845 efx_sram_ev_t eec_sram;
846 efx_wake_up_ev_t eec_wake_up;
847 efx_timer_ev_t eec_timer;
848 efx_link_change_ev_t eec_link_change;
849 } efx_ev_callbacks_t;
851 extern __checkReturn boolean_t
854 __in unsigned int count);
859 __inout unsigned int *countp,
860 __in const efx_ev_callbacks_t *eecp,
863 extern __checkReturn efx_rc_t
864 efx_ev_usecs_to_ticks(
866 __in unsigned int usecs,
867 __out unsigned int *ticksp);
869 extern __checkReturn efx_rc_t
872 __in unsigned int us);
874 extern __checkReturn efx_rc_t
877 __in unsigned int count);
881 __in efx_evq_t *eep);
885 extern __checkReturn efx_rc_t
887 __inout efx_nic_t *enp);
891 __in efx_nic_t *enp);
893 extern __checkReturn efx_rc_t
894 efx_pseudo_hdr_pkt_length_get(
896 __in uint8_t *buffer,
897 __out uint16_t *pkt_lengthp);
899 #define EFX_RXQ_MAXNDESCS 4096
900 #define EFX_RXQ_MINNDESCS 512
902 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
903 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
904 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
905 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
907 typedef enum efx_rxq_type_e {
908 EFX_RXQ_TYPE_DEFAULT,
909 EFX_RXQ_TYPE_SCATTER,
910 EFX_RXQ_TYPE_PACKED_STREAM_1M,
911 EFX_RXQ_TYPE_PACKED_STREAM_512K,
912 EFX_RXQ_TYPE_PACKED_STREAM_256K,
913 EFX_RXQ_TYPE_PACKED_STREAM_128K,
914 EFX_RXQ_TYPE_PACKED_STREAM_64K,
918 extern __checkReturn efx_rc_t
921 __in unsigned int index,
922 __in unsigned int label,
923 __in efx_rxq_type_t type,
924 __in efsys_mem_t *esmp,
928 __deref_out efx_rxq_t **erpp);
930 typedef struct efx_buffer_s {
931 efsys_dma_addr_t eb_addr;
936 typedef struct efx_desc_s {
943 __in_ecount(n) efsys_dma_addr_t *addrp,
946 __in unsigned int completed,
947 __in unsigned int added);
952 __in unsigned int added,
953 __inout unsigned int *pushedp);
955 extern __checkReturn efx_rc_t
957 __in efx_rxq_t *erp);
961 __in efx_rxq_t *erp);
965 __in efx_rxq_t *erp);
969 typedef struct efx_txq_s efx_txq_t;
971 extern __checkReturn efx_rc_t
973 __in efx_nic_t *enp);
977 __in efx_nic_t *enp);
979 #define EFX_TXQ_MINNDESCS 512
981 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
982 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
983 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
984 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
986 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
988 #define EFX_TXQ_CKSUM_IPV4 0x0001
989 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
990 #define EFX_TXQ_FATSOV2 0x0004
992 extern __checkReturn efx_rc_t
995 __in unsigned int index,
996 __in unsigned int label,
997 __in efsys_mem_t *esmp,
1000 __in uint16_t flags,
1001 __in efx_evq_t *eep,
1002 __deref_out efx_txq_t **etpp,
1003 __out unsigned int *addedp);
1005 extern __checkReturn efx_rc_t
1007 __in efx_txq_t *etp,
1008 __in_ecount(n) efx_buffer_t *eb,
1009 __in unsigned int n,
1010 __in unsigned int completed,
1011 __inout unsigned int *addedp);
1013 extern __checkReturn efx_rc_t
1015 __in efx_txq_t *etp,
1016 __in unsigned int ns);
1020 __in efx_txq_t *etp,
1021 __in unsigned int added,
1022 __in unsigned int pushed);
1024 extern __checkReturn efx_rc_t
1026 __in efx_txq_t *etp);
1030 __in efx_txq_t *etp);
1032 extern __checkReturn efx_rc_t
1034 __in efx_txq_t *etp);
1037 efx_tx_qpio_disable(
1038 __in efx_txq_t *etp);
1040 extern __checkReturn efx_rc_t
1042 __in efx_txq_t *etp,
1043 __in_ecount(buf_length) uint8_t *buffer,
1044 __in size_t buf_length,
1045 __in size_t pio_buf_offset);
1047 extern __checkReturn efx_rc_t
1049 __in efx_txq_t *etp,
1050 __in size_t pkt_length,
1051 __in unsigned int completed,
1052 __inout unsigned int *addedp);
1054 extern __checkReturn efx_rc_t
1056 __in efx_txq_t *etp,
1057 __in_ecount(n) efx_desc_t *ed,
1058 __in unsigned int n,
1059 __in unsigned int completed,
1060 __inout unsigned int *addedp);
1063 efx_tx_qdesc_dma_create(
1064 __in efx_txq_t *etp,
1065 __in efsys_dma_addr_t addr,
1068 __out efx_desc_t *edp);
1071 efx_tx_qdesc_tso_create(
1072 __in efx_txq_t *etp,
1073 __in uint16_t ipv4_id,
1074 __in uint32_t tcp_seq,
1075 __in uint8_t tcp_flags,
1076 __out efx_desc_t *edp);
1078 /* Number of FATSOv2 option descriptors */
1079 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1081 /* Maximum number of DMA segments per TSO packet (not superframe) */
1082 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1085 efx_tx_qdesc_tso2_create(
1086 __in efx_txq_t *etp,
1087 __in uint16_t ipv4_id,
1088 __in uint32_t tcp_seq,
1089 __in uint16_t tcp_mss,
1090 __out_ecount(count) efx_desc_t *edp,
1094 efx_tx_qdesc_vlantci_create(
1095 __in efx_txq_t *etp,
1097 __out efx_desc_t *edp);
1101 __in efx_txq_t *etp);
1106 #if EFSYS_OPT_FILTER
1108 #define EFX_ETHER_TYPE_IPV4 0x0800
1109 #define EFX_ETHER_TYPE_IPV6 0x86DD
1111 #define EFX_IPPROTO_TCP 6
1112 #define EFX_IPPROTO_UDP 17
1114 /* Use RSS to spread across multiple queues */
1115 #define EFX_FILTER_FLAG_RX_RSS 0x01
1116 /* Enable RX scatter */
1117 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1119 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1120 * May only be set by the filter implementation for each type.
1121 * A removal request will restore the automatic filter in its place.
1123 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1124 /* Filter is for RX */
1125 #define EFX_FILTER_FLAG_RX 0x08
1126 /* Filter is for TX */
1127 #define EFX_FILTER_FLAG_TX 0x10
1129 typedef unsigned int efx_filter_flags_t;
1131 typedef enum efx_filter_match_flags_e {
1132 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1134 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1136 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1137 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1138 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1139 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1140 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1141 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1142 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1143 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1145 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1146 * I/G bit. Used for RX default
1147 * unicast and multicast/
1148 * broadcast filters. */
1149 } efx_filter_match_flags_t;
1151 typedef enum efx_filter_priority_s {
1152 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1153 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1154 * address list or hardware
1155 * requirements. This may only be used
1156 * by the filter implementation for
1158 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1159 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1160 * client (e.g. SR-IOV, HyperV VMQ etc.)
1162 } efx_filter_priority_t;
1165 * FIXME: All these fields are assumed to be in little-endian byte order.
1166 * It may be better for some to be big-endian. See bug42804.
1169 typedef struct efx_filter_spec_s {
1170 uint32_t efs_match_flags:12;
1171 uint32_t efs_priority:2;
1172 uint32_t efs_flags:6;
1173 uint32_t efs_dmaq_id:12;
1174 uint32_t efs_rss_context;
1175 uint16_t efs_outer_vid;
1176 uint16_t efs_inner_vid;
1177 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1178 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1179 uint16_t efs_ether_type;
1180 uint8_t efs_ip_proto;
1181 uint16_t efs_loc_port;
1182 uint16_t efs_rem_port;
1183 efx_oword_t efs_rem_host;
1184 efx_oword_t efs_loc_host;
1185 } efx_filter_spec_t;
1188 /* Default values for use in filter specifications */
1189 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1190 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1191 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1193 extern __checkReturn efx_rc_t
1195 __in efx_nic_t *enp);
1199 __in efx_nic_t *enp);
1201 extern __checkReturn efx_rc_t
1203 __in efx_nic_t *enp,
1204 __inout efx_filter_spec_t *spec);
1206 extern __checkReturn efx_rc_t
1208 __in efx_nic_t *enp,
1209 __inout efx_filter_spec_t *spec);
1211 extern __checkReturn efx_rc_t
1213 __in efx_nic_t *enp);
1215 extern __checkReturn efx_rc_t
1216 efx_filter_supported_filters(
1217 __in efx_nic_t *enp,
1218 __out uint32_t *list,
1219 __out size_t *length);
1222 efx_filter_spec_init_rx(
1223 __out efx_filter_spec_t *spec,
1224 __in efx_filter_priority_t priority,
1225 __in efx_filter_flags_t flags,
1226 __in efx_rxq_t *erp);
1229 efx_filter_spec_init_tx(
1230 __out efx_filter_spec_t *spec,
1231 __in efx_txq_t *etp);
1233 extern __checkReturn efx_rc_t
1234 efx_filter_spec_set_ipv4_local(
1235 __inout efx_filter_spec_t *spec,
1238 __in uint16_t port);
1240 extern __checkReturn efx_rc_t
1241 efx_filter_spec_set_ipv4_full(
1242 __inout efx_filter_spec_t *spec,
1244 __in uint32_t lhost,
1245 __in uint16_t lport,
1246 __in uint32_t rhost,
1247 __in uint16_t rport);
1249 extern __checkReturn efx_rc_t
1250 efx_filter_spec_set_eth_local(
1251 __inout efx_filter_spec_t *spec,
1253 __in const uint8_t *addr);
1255 extern __checkReturn efx_rc_t
1256 efx_filter_spec_set_uc_def(
1257 __inout efx_filter_spec_t *spec);
1259 extern __checkReturn efx_rc_t
1260 efx_filter_spec_set_mc_def(
1261 __inout efx_filter_spec_t *spec);
1263 #endif /* EFSYS_OPT_FILTER */
1267 extern __checkReturn uint32_t
1269 __in_ecount(count) uint32_t const *input,
1271 __in uint32_t init);
1273 extern __checkReturn uint32_t
1275 __in_ecount(length) uint8_t const *input,
1277 __in uint32_t init);
1285 #endif /* _SYS_EFX_H */