2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 extern __checkReturn efx_rc_t
152 efx_nic_register_test(
153 __in efx_nic_t *enp);
155 #endif /* EFSYS_OPT_DIAG */
159 __in efx_nic_t *enp);
163 __in efx_nic_t *enp);
167 __in efx_nic_t *enp);
169 #define EFX_PCIE_LINK_SPEED_GEN1 1
170 #define EFX_PCIE_LINK_SPEED_GEN2 2
171 #define EFX_PCIE_LINK_SPEED_GEN3 3
173 typedef enum efx_pcie_link_performance_e {
174 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
175 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
176 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
177 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
178 } efx_pcie_link_performance_t;
180 extern __checkReturn efx_rc_t
181 efx_nic_calculate_pcie_link_bandwidth(
182 __in uint32_t pcie_link_width,
183 __in uint32_t pcie_link_gen,
184 __out uint32_t *bandwidth_mbpsp);
186 extern __checkReturn efx_rc_t
187 efx_nic_check_pcie_link_speed(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out efx_pcie_link_performance_t *resultp);
195 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
196 /* Huntington and Medford require MCDIv2 commands */
197 #define WITH_MCDI_V2 1
200 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
202 typedef enum efx_mcdi_exception_e {
203 EFX_MCDI_EXCEPTION_MC_REBOOT,
204 EFX_MCDI_EXCEPTION_MC_BADASSERT,
205 } efx_mcdi_exception_t;
207 #if EFSYS_OPT_MCDI_LOGGING
208 typedef enum efx_log_msg_e {
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_get_timeout(
246 __in efx_mcdi_req_t *emrp,
247 __out uint32_t *usec_timeoutp);
250 efx_mcdi_request_start(
252 __in efx_mcdi_req_t *emrp,
253 __in boolean_t ev_cpl);
255 extern __checkReturn boolean_t
256 efx_mcdi_request_poll(
257 __in efx_nic_t *enp);
259 extern __checkReturn boolean_t
260 efx_mcdi_request_abort(
261 __in efx_nic_t *enp);
265 __in efx_nic_t *enp);
267 #endif /* EFSYS_OPT_MCDI */
271 #define EFX_NINTR_SIENA 1024
273 typedef enum efx_intr_type_e {
274 EFX_INTR_INVALID = 0,
280 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
282 extern __checkReturn efx_rc_t
285 __in efx_intr_type_t type,
286 __in efsys_mem_t *esmp);
290 __in efx_nic_t *enp);
294 __in efx_nic_t *enp);
297 efx_intr_disable_unlocked(
298 __in efx_nic_t *enp);
300 #define EFX_INTR_NEVQS 32
302 extern __checkReturn efx_rc_t
305 __in unsigned int level);
308 efx_intr_status_line(
310 __out boolean_t *fatalp,
311 __out uint32_t *maskp);
314 efx_intr_status_message(
316 __in unsigned int message,
317 __out boolean_t *fatalp);
321 __in efx_nic_t *enp);
325 __in efx_nic_t *enp);
329 typedef enum efx_link_mode_e {
330 EFX_LINK_UNKNOWN = 0,
343 #define EFX_MAC_ADDR_LEN 6
345 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
347 #define EFX_MAC_MULTICAST_LIST_MAX 256
349 #define EFX_MAC_SDU_MAX 9202
351 #define EFX_MAC_PDU_ADJUSTMENT \
355 + /* bug16011 */ 16) \
357 #define EFX_MAC_PDU(_sdu) \
358 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
361 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
362 * the SDU rounded up slightly.
364 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
366 #define EFX_MAC_PDU_MIN 60
367 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
369 extern __checkReturn efx_rc_t
374 extern __checkReturn efx_rc_t
379 extern __checkReturn efx_rc_t
384 extern __checkReturn efx_rc_t
387 __in boolean_t all_unicst,
388 __in boolean_t mulcst,
389 __in boolean_t all_mulcst,
390 __in boolean_t brdcst);
392 extern __checkReturn efx_rc_t
393 efx_mac_multicast_list_set(
395 __in_ecount(6*count) uint8_t const *addrs,
398 extern __checkReturn efx_rc_t
399 efx_mac_filter_default_rxq_set(
402 __in boolean_t using_rss);
405 efx_mac_filter_default_rxq_clear(
406 __in efx_nic_t *enp);
408 extern __checkReturn efx_rc_t
411 __in boolean_t enabled);
413 extern __checkReturn efx_rc_t
416 __out boolean_t *mac_upp);
418 #define EFX_FCNTL_RESPOND 0x00000001
419 #define EFX_FCNTL_GENERATE 0x00000002
421 extern __checkReturn efx_rc_t
424 __in unsigned int fcntl,
425 __in boolean_t autoneg);
430 __out unsigned int *fcntl_wantedp,
431 __out unsigned int *fcntl_linkp);
436 typedef enum efx_mon_type_e {
448 __in efx_nic_t *enp);
450 #endif /* EFSYS_OPT_NAMES */
452 extern __checkReturn efx_rc_t
454 __in efx_nic_t *enp);
458 __in efx_nic_t *enp);
462 extern __checkReturn efx_rc_t
464 __in efx_nic_t *enp);
466 extern __checkReturn efx_rc_t
468 __in efx_nic_t *enp);
470 extern __checkReturn efx_rc_t
473 __out_opt efx_link_mode_t *link_modep);
477 __in efx_nic_t *enp);
479 typedef enum efx_phy_cap_type_e {
480 EFX_PHY_CAP_INVALID = 0,
487 EFX_PHY_CAP_10000FDX,
491 EFX_PHY_CAP_40000FDX,
493 } efx_phy_cap_type_t;
496 #define EFX_PHY_CAP_CURRENT 0x00000000
497 #define EFX_PHY_CAP_DEFAULT 0x00000001
498 #define EFX_PHY_CAP_PERM 0x00000002
504 __out uint32_t *maskp);
506 extern __checkReturn efx_rc_t
514 __out uint32_t *maskp);
516 extern __checkReturn efx_rc_t
519 __out uint32_t *ouip);
521 typedef enum efx_phy_media_type_e {
522 EFX_PHY_MEDIA_INVALID = 0,
527 EFX_PHY_MEDIA_SFP_PLUS,
528 EFX_PHY_MEDIA_BASE_T,
529 EFX_PHY_MEDIA_QSFP_PLUS,
531 } efx_phy_media_type_t;
533 /* Get the type of medium currently used. If the board has ports for
534 * modules, a module is present, and we recognise the media type of
535 * the module, then this will be the media type of the module.
536 * Otherwise it will be the media type of the port.
539 efx_phy_media_type_get(
541 __out efx_phy_media_type_t *typep);
544 efx_phy_module_get_info(
546 __in uint8_t dev_addr,
549 __out_bcount(len) uint8_t *data);
554 typedef enum efx_bist_type_e {
555 EFX_BIST_TYPE_UNKNOWN,
556 EFX_BIST_TYPE_PHY_NORMAL,
557 EFX_BIST_TYPE_PHY_CABLE_SHORT,
558 EFX_BIST_TYPE_PHY_CABLE_LONG,
559 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
560 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
561 EFX_BIST_TYPE_REG, /* Test the register memories */
562 EFX_BIST_TYPE_NTYPES,
565 typedef enum efx_bist_result_e {
566 EFX_BIST_RESULT_UNKNOWN,
567 EFX_BIST_RESULT_RUNNING,
568 EFX_BIST_RESULT_PASSED,
569 EFX_BIST_RESULT_FAILED,
572 typedef enum efx_phy_cable_status_e {
573 EFX_PHY_CABLE_STATUS_OK,
574 EFX_PHY_CABLE_STATUS_INVALID,
575 EFX_PHY_CABLE_STATUS_OPEN,
576 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
577 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
578 EFX_PHY_CABLE_STATUS_BUSY,
579 } efx_phy_cable_status_t;
581 typedef enum efx_bist_value_e {
582 EFX_BIST_PHY_CABLE_LENGTH_A,
583 EFX_BIST_PHY_CABLE_LENGTH_B,
584 EFX_BIST_PHY_CABLE_LENGTH_C,
585 EFX_BIST_PHY_CABLE_LENGTH_D,
586 EFX_BIST_PHY_CABLE_STATUS_A,
587 EFX_BIST_PHY_CABLE_STATUS_B,
588 EFX_BIST_PHY_CABLE_STATUS_C,
589 EFX_BIST_PHY_CABLE_STATUS_D,
591 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
599 EFX_BIST_MEM_ECC_PARITY,
600 EFX_BIST_MEM_ECC_FATAL,
604 extern __checkReturn efx_rc_t
605 efx_bist_enable_offline(
606 __in efx_nic_t *enp);
608 extern __checkReturn efx_rc_t
611 __in efx_bist_type_t type);
613 extern __checkReturn efx_rc_t
616 __in efx_bist_type_t type,
617 __out efx_bist_result_t *resultp,
618 __out_opt uint32_t *value_maskp,
619 __out_ecount_opt(count) unsigned long *valuesp,
625 __in efx_bist_type_t type);
627 #endif /* EFSYS_OPT_BIST */
629 #define EFX_FEATURE_IPV6 0x00000001
630 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
631 #define EFX_FEATURE_LINK_EVENTS 0x00000004
632 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
633 #define EFX_FEATURE_MCDI 0x00000020
634 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
635 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
636 #define EFX_FEATURE_TURBO 0x00000100
637 #define EFX_FEATURE_MCDI_DMA 0x00000200
638 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
639 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
640 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
641 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
642 #define EFX_FEATURE_PACKED_STREAM 0x00004000
644 typedef struct efx_nic_cfg_s {
645 uint32_t enc_board_type;
646 uint32_t enc_phy_type;
648 char enc_phy_name[21];
650 char enc_phy_revision[21];
651 efx_mon_type_t enc_mon_type;
652 unsigned int enc_features;
653 uint8_t enc_mac_addr[6];
654 uint8_t enc_port; /* PHY port number */
655 uint32_t enc_intr_vec_base;
656 uint32_t enc_intr_limit;
657 uint32_t enc_evq_limit;
658 uint32_t enc_txq_limit;
659 uint32_t enc_rxq_limit;
660 uint32_t enc_txq_max_ndescs;
661 uint32_t enc_buftbl_limit;
662 uint32_t enc_piobuf_limit;
663 uint32_t enc_piobuf_size;
664 uint32_t enc_piobuf_min_alloc_size;
665 uint32_t enc_evq_timer_quantum_ns;
666 uint32_t enc_evq_timer_max_us;
667 uint32_t enc_clk_mult;
668 uint32_t enc_rx_prefix_size;
669 uint32_t enc_rx_buf_align_start;
670 uint32_t enc_rx_buf_align_end;
671 #if EFSYS_OPT_PHY_FLAGS
672 uint32_t enc_phy_flags_mask;
673 #endif /* EFSYS_OPT_PHY_FLAGS */
675 uint8_t enc_mcdi_mdio_channel;
676 #endif /* EFSYS_OPT_MCDI */
678 uint32_t enc_bist_mask;
679 #endif /* EFSYS_OPT_BIST */
680 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
683 uint32_t enc_privilege_mask;
684 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
685 boolean_t enc_bug26807_workaround;
686 boolean_t enc_bug35388_workaround;
687 boolean_t enc_bug41750_workaround;
688 boolean_t enc_bug61265_workaround;
689 boolean_t enc_rx_batching_enabled;
690 /* Maximum number of descriptors completed in an rx event. */
691 uint32_t enc_rx_batch_max;
692 /* Number of rx descriptors the hardware requires for a push. */
693 uint32_t enc_rx_push_align;
695 * Maximum number of bytes into the packet the TCP header can start for
696 * the hardware to apply TSO packet edits.
698 uint32_t enc_tx_tso_tcp_header_offset_limit;
699 boolean_t enc_fw_assisted_tso_enabled;
700 boolean_t enc_fw_assisted_tso_v2_enabled;
701 /* Number of TSO contexts on the NIC (FATSOv2) */
702 uint32_t enc_fw_assisted_tso_v2_n_contexts;
703 boolean_t enc_hw_tx_insert_vlan_enabled;
704 /* Number of PFs on the NIC */
705 uint32_t enc_hw_pf_count;
706 /* Datapath firmware vadapter/vport/vswitch support */
707 boolean_t enc_datapath_cap_evb;
708 boolean_t enc_rx_disable_scatter_supported;
709 boolean_t enc_allow_set_mac_with_installed_filters;
710 boolean_t enc_enhanced_set_mac_supported;
711 boolean_t enc_init_evq_v2_supported;
712 boolean_t enc_rx_packed_stream_supported;
713 boolean_t enc_rx_var_packed_stream_supported;
714 boolean_t enc_pm_and_rxdp_counters;
715 boolean_t enc_mac_stats_40g_tx_size_bins;
716 /* External port identifier */
717 uint8_t enc_external_port;
718 uint32_t enc_mcdi_max_payload_length;
719 /* VPD may be per-PF or global */
720 boolean_t enc_vpd_is_global;
721 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
722 uint32_t enc_required_pcie_bandwidth_mbps;
723 uint32_t enc_max_pcie_link_gen;
724 /* Firmware verifies integrity of NVRAM updates */
725 uint32_t enc_fw_verified_nvram_update_required;
728 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
729 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
731 #define EFX_PCI_FUNCTION(_encp) \
732 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
734 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
736 extern const efx_nic_cfg_t *
738 __in efx_nic_t *enp);
740 /* Driver resource limits (minimum required/maximum usable). */
741 typedef struct efx_drv_limits_s {
742 uint32_t edl_min_evq_count;
743 uint32_t edl_max_evq_count;
745 uint32_t edl_min_rxq_count;
746 uint32_t edl_max_rxq_count;
748 uint32_t edl_min_txq_count;
749 uint32_t edl_max_txq_count;
751 /* PIO blocks (sub-allocated from piobuf) */
752 uint32_t edl_min_pio_alloc_size;
753 uint32_t edl_max_pio_alloc_count;
756 extern __checkReturn efx_rc_t
757 efx_nic_set_drv_limits(
758 __inout efx_nic_t *enp,
759 __in efx_drv_limits_t *edlp);
761 typedef enum efx_nic_region_e {
762 EFX_REGION_VI, /* Memory BAR UC mapping */
763 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
766 extern __checkReturn efx_rc_t
767 efx_nic_get_bar_region(
769 __in efx_nic_region_t region,
770 __out uint32_t *offsetp,
771 __out size_t *sizep);
773 extern __checkReturn efx_rc_t
776 __out uint32_t *evq_countp,
777 __out uint32_t *rxq_countp,
778 __out uint32_t *txq_countp);
785 typedef enum efx_pattern_type_t {
786 EFX_PATTERN_BYTE_INCREMENT = 0,
787 EFX_PATTERN_ALL_THE_SAME,
788 EFX_PATTERN_BIT_ALTERNATE,
789 EFX_PATTERN_BYTE_ALTERNATE,
790 EFX_PATTERN_BYTE_CHANGING,
791 EFX_PATTERN_BIT_SWEEP,
793 } efx_pattern_type_t;
796 (*efx_sram_pattern_fn_t)(
798 __in boolean_t negate,
799 __out efx_qword_t *eqp);
801 extern __checkReturn efx_rc_t
804 __in efx_pattern_type_t type);
806 #endif /* EFSYS_OPT_DIAG */
808 extern __checkReturn efx_rc_t
809 efx_sram_buf_tbl_set(
812 __in efsys_mem_t *esmp,
816 efx_sram_buf_tbl_clear(
821 #define EFX_BUF_TBL_SIZE 0x20000
823 #define EFX_BUF_SIZE 4096
827 typedef struct efx_evq_s efx_evq_t;
831 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
832 typedef enum efx_ev_qstat_e {
839 EV_RX_BUF_OWNER_ID_ERR,
840 EV_RX_IPV4_HDR_CHKSUM_ERR,
841 EV_RX_TCP_UDP_CHKSUM_ERR,
845 EV_RX_MCAST_HASH_MATCH,
862 EV_DRIVER_SRM_UPD_DONE,
863 EV_DRIVER_TX_DESCQ_FLS_DONE,
864 EV_DRIVER_RX_DESCQ_FLS_DONE,
865 EV_DRIVER_RX_DESCQ_FLS_FAILED,
866 EV_DRIVER_RX_DSC_ERROR,
867 EV_DRIVER_TX_DSC_ERROR,
873 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
875 #endif /* EFSYS_OPT_QSTATS */
877 extern __checkReturn efx_rc_t
879 __in efx_nic_t *enp);
883 __in efx_nic_t *enp);
885 #define EFX_EVQ_MAXNEVS 32768
886 #define EFX_EVQ_MINNEVS 512
888 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
889 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
891 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
892 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
893 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
894 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
896 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
897 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
898 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
900 extern __checkReturn efx_rc_t
903 __in unsigned int index,
904 __in efsys_mem_t *esmp,
909 __deref_out efx_evq_t **eepp);
916 typedef __checkReturn boolean_t
917 (*efx_initialized_ev_t)(
920 #define EFX_PKT_UNICAST 0x0004
921 #define EFX_PKT_START 0x0008
923 #define EFX_PKT_VLAN_TAGGED 0x0010
924 #define EFX_CKSUM_TCPUDP 0x0020
925 #define EFX_CKSUM_IPV4 0x0040
926 #define EFX_PKT_CONT 0x0080
928 #define EFX_CHECK_VLAN 0x0100
929 #define EFX_PKT_TCP 0x0200
930 #define EFX_PKT_UDP 0x0400
931 #define EFX_PKT_IPV4 0x0800
933 #define EFX_PKT_IPV6 0x1000
934 #define EFX_PKT_PREFIX_LEN 0x2000
935 #define EFX_ADDR_MISMATCH 0x4000
936 #define EFX_DISCARD 0x8000
939 * The following flags are used only for packed stream
940 * mode. The values for the flags are reused to fit into 16 bit,
941 * since EFX_PKT_START and EFX_PKT_CONT are never used in
944 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
945 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
948 #define EFX_EV_RX_NLABELS 32
949 #define EFX_EV_TX_NLABELS 32
951 typedef __checkReturn boolean_t
957 __in uint16_t flags);
959 typedef __checkReturn boolean_t
965 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
966 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
967 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
968 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
969 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
970 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
971 #define EFX_EXCEPTION_RX_ERROR 0x00000007
972 #define EFX_EXCEPTION_TX_ERROR 0x00000008
973 #define EFX_EXCEPTION_EV_ERROR 0x00000009
975 typedef __checkReturn boolean_t
976 (*efx_exception_ev_t)(
981 typedef __checkReturn boolean_t
982 (*efx_rxq_flush_done_ev_t)(
984 __in uint32_t rxq_index);
986 typedef __checkReturn boolean_t
987 (*efx_rxq_flush_failed_ev_t)(
989 __in uint32_t rxq_index);
991 typedef __checkReturn boolean_t
992 (*efx_txq_flush_done_ev_t)(
994 __in uint32_t txq_index);
996 typedef __checkReturn boolean_t
997 (*efx_software_ev_t)(
999 __in uint16_t magic);
1001 typedef __checkReturn boolean_t
1004 __in uint32_t code);
1006 #define EFX_SRAM_CLEAR 0
1007 #define EFX_SRAM_UPDATE 1
1008 #define EFX_SRAM_ILLEGAL_CLEAR 2
1010 typedef __checkReturn boolean_t
1011 (*efx_wake_up_ev_t)(
1013 __in uint32_t label);
1015 typedef __checkReturn boolean_t
1018 __in uint32_t label);
1020 typedef __checkReturn boolean_t
1021 (*efx_link_change_ev_t)(
1023 __in efx_link_mode_t link_mode);
1025 typedef struct efx_ev_callbacks_s {
1026 efx_initialized_ev_t eec_initialized;
1029 efx_exception_ev_t eec_exception;
1030 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1031 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1032 efx_txq_flush_done_ev_t eec_txq_flush_done;
1033 efx_software_ev_t eec_software;
1034 efx_sram_ev_t eec_sram;
1035 efx_wake_up_ev_t eec_wake_up;
1036 efx_timer_ev_t eec_timer;
1037 efx_link_change_ev_t eec_link_change;
1038 } efx_ev_callbacks_t;
1040 extern __checkReturn boolean_t
1042 __in efx_evq_t *eep,
1043 __in unsigned int count);
1047 __in efx_evq_t *eep,
1048 __inout unsigned int *countp,
1049 __in const efx_ev_callbacks_t *eecp,
1050 __in_opt void *arg);
1052 extern __checkReturn efx_rc_t
1053 efx_ev_usecs_to_ticks(
1054 __in efx_nic_t *enp,
1055 __in unsigned int usecs,
1056 __out unsigned int *ticksp);
1058 extern __checkReturn efx_rc_t
1060 __in efx_evq_t *eep,
1061 __in unsigned int us);
1063 extern __checkReturn efx_rc_t
1065 __in efx_evq_t *eep,
1066 __in unsigned int count);
1068 #if EFSYS_OPT_QSTATS
1074 __in efx_nic_t *enp,
1075 __in unsigned int id);
1077 #endif /* EFSYS_OPT_NAMES */
1080 efx_ev_qstats_update(
1081 __in efx_evq_t *eep,
1082 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1084 #endif /* EFSYS_OPT_QSTATS */
1088 __in efx_evq_t *eep);
1092 extern __checkReturn efx_rc_t
1094 __inout efx_nic_t *enp);
1098 __in efx_nic_t *enp);
1100 extern __checkReturn efx_rc_t
1101 efx_pseudo_hdr_pkt_length_get(
1102 __in efx_rxq_t *erp,
1103 __in uint8_t *buffer,
1104 __out uint16_t *pkt_lengthp);
1106 #define EFX_RXQ_MAXNDESCS 4096
1107 #define EFX_RXQ_MINNDESCS 512
1109 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1110 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1111 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1112 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1114 typedef enum efx_rxq_type_e {
1115 EFX_RXQ_TYPE_DEFAULT,
1116 EFX_RXQ_TYPE_SCATTER,
1117 EFX_RXQ_TYPE_PACKED_STREAM_1M,
1118 EFX_RXQ_TYPE_PACKED_STREAM_512K,
1119 EFX_RXQ_TYPE_PACKED_STREAM_256K,
1120 EFX_RXQ_TYPE_PACKED_STREAM_128K,
1121 EFX_RXQ_TYPE_PACKED_STREAM_64K,
1125 extern __checkReturn efx_rc_t
1127 __in efx_nic_t *enp,
1128 __in unsigned int index,
1129 __in unsigned int label,
1130 __in efx_rxq_type_t type,
1131 __in efsys_mem_t *esmp,
1134 __in efx_evq_t *eep,
1135 __deref_out efx_rxq_t **erpp);
1137 typedef struct efx_buffer_s {
1138 efsys_dma_addr_t eb_addr;
1143 typedef struct efx_desc_s {
1149 __in efx_rxq_t *erp,
1150 __in_ecount(n) efsys_dma_addr_t *addrp,
1152 __in unsigned int n,
1153 __in unsigned int completed,
1154 __in unsigned int added);
1158 __in efx_rxq_t *erp,
1159 __in unsigned int added,
1160 __inout unsigned int *pushedp);
1162 extern __checkReturn efx_rc_t
1164 __in efx_rxq_t *erp);
1168 __in efx_rxq_t *erp);
1172 __in efx_rxq_t *erp);
1176 typedef struct efx_txq_s efx_txq_t;
1178 #if EFSYS_OPT_QSTATS
1180 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1181 typedef enum efx_tx_qstat_e {
1187 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1189 #endif /* EFSYS_OPT_QSTATS */
1191 extern __checkReturn efx_rc_t
1193 __in efx_nic_t *enp);
1197 __in efx_nic_t *enp);
1199 #define EFX_TXQ_MINNDESCS 512
1201 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1202 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1203 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1204 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1206 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1208 #define EFX_TXQ_CKSUM_IPV4 0x0001
1209 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1210 #define EFX_TXQ_FATSOV2 0x0004
1212 extern __checkReturn efx_rc_t
1214 __in efx_nic_t *enp,
1215 __in unsigned int index,
1216 __in unsigned int label,
1217 __in efsys_mem_t *esmp,
1220 __in uint16_t flags,
1221 __in efx_evq_t *eep,
1222 __deref_out efx_txq_t **etpp,
1223 __out unsigned int *addedp);
1225 extern __checkReturn efx_rc_t
1227 __in efx_txq_t *etp,
1228 __in_ecount(n) efx_buffer_t *eb,
1229 __in unsigned int n,
1230 __in unsigned int completed,
1231 __inout unsigned int *addedp);
1233 extern __checkReturn efx_rc_t
1235 __in efx_txq_t *etp,
1236 __in unsigned int ns);
1240 __in efx_txq_t *etp,
1241 __in unsigned int added,
1242 __in unsigned int pushed);
1244 extern __checkReturn efx_rc_t
1246 __in efx_txq_t *etp);
1250 __in efx_txq_t *etp);
1252 extern __checkReturn efx_rc_t
1254 __in efx_txq_t *etp);
1257 efx_tx_qpio_disable(
1258 __in efx_txq_t *etp);
1260 extern __checkReturn efx_rc_t
1262 __in efx_txq_t *etp,
1263 __in_ecount(buf_length) uint8_t *buffer,
1264 __in size_t buf_length,
1265 __in size_t pio_buf_offset);
1267 extern __checkReturn efx_rc_t
1269 __in efx_txq_t *etp,
1270 __in size_t pkt_length,
1271 __in unsigned int completed,
1272 __inout unsigned int *addedp);
1274 extern __checkReturn efx_rc_t
1276 __in efx_txq_t *etp,
1277 __in_ecount(n) efx_desc_t *ed,
1278 __in unsigned int n,
1279 __in unsigned int completed,
1280 __inout unsigned int *addedp);
1283 efx_tx_qdesc_dma_create(
1284 __in efx_txq_t *etp,
1285 __in efsys_dma_addr_t addr,
1288 __out efx_desc_t *edp);
1291 efx_tx_qdesc_tso_create(
1292 __in efx_txq_t *etp,
1293 __in uint16_t ipv4_id,
1294 __in uint32_t tcp_seq,
1295 __in uint8_t tcp_flags,
1296 __out efx_desc_t *edp);
1298 /* Number of FATSOv2 option descriptors */
1299 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1301 /* Maximum number of DMA segments per TSO packet (not superframe) */
1302 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1305 efx_tx_qdesc_tso2_create(
1306 __in efx_txq_t *etp,
1307 __in uint16_t ipv4_id,
1308 __in uint32_t tcp_seq,
1309 __in uint16_t tcp_mss,
1310 __out_ecount(count) efx_desc_t *edp,
1314 efx_tx_qdesc_vlantci_create(
1315 __in efx_txq_t *etp,
1317 __out efx_desc_t *edp);
1319 #if EFSYS_OPT_QSTATS
1325 __in efx_nic_t *etp,
1326 __in unsigned int id);
1328 #endif /* EFSYS_OPT_NAMES */
1331 efx_tx_qstats_update(
1332 __in efx_txq_t *etp,
1333 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1335 #endif /* EFSYS_OPT_QSTATS */
1339 __in efx_txq_t *etp);
1344 #if EFSYS_OPT_FILTER
1346 #define EFX_ETHER_TYPE_IPV4 0x0800
1347 #define EFX_ETHER_TYPE_IPV6 0x86DD
1349 #define EFX_IPPROTO_TCP 6
1350 #define EFX_IPPROTO_UDP 17
1352 /* Use RSS to spread across multiple queues */
1353 #define EFX_FILTER_FLAG_RX_RSS 0x01
1354 /* Enable RX scatter */
1355 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1357 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1358 * May only be set by the filter implementation for each type.
1359 * A removal request will restore the automatic filter in its place.
1361 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1362 /* Filter is for RX */
1363 #define EFX_FILTER_FLAG_RX 0x08
1364 /* Filter is for TX */
1365 #define EFX_FILTER_FLAG_TX 0x10
1367 typedef unsigned int efx_filter_flags_t;
1369 typedef enum efx_filter_match_flags_e {
1370 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1372 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1374 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1375 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1376 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1377 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1378 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1379 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1380 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1381 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1383 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1384 * I/G bit. Used for RX default
1385 * unicast and multicast/
1386 * broadcast filters. */
1387 } efx_filter_match_flags_t;
1389 typedef enum efx_filter_priority_s {
1390 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1391 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1392 * address list or hardware
1393 * requirements. This may only be used
1394 * by the filter implementation for
1396 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1397 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1398 * client (e.g. SR-IOV, HyperV VMQ etc.)
1400 } efx_filter_priority_t;
1403 * FIXME: All these fields are assumed to be in little-endian byte order.
1404 * It may be better for some to be big-endian. See bug42804.
1407 typedef struct efx_filter_spec_s {
1408 uint32_t efs_match_flags:12;
1409 uint32_t efs_priority:2;
1410 uint32_t efs_flags:6;
1411 uint32_t efs_dmaq_id:12;
1412 uint32_t efs_rss_context;
1413 uint16_t efs_outer_vid;
1414 uint16_t efs_inner_vid;
1415 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1416 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1417 uint16_t efs_ether_type;
1418 uint8_t efs_ip_proto;
1419 uint16_t efs_loc_port;
1420 uint16_t efs_rem_port;
1421 efx_oword_t efs_rem_host;
1422 efx_oword_t efs_loc_host;
1423 } efx_filter_spec_t;
1426 /* Default values for use in filter specifications */
1427 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1428 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1429 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1431 extern __checkReturn efx_rc_t
1433 __in efx_nic_t *enp);
1437 __in efx_nic_t *enp);
1439 extern __checkReturn efx_rc_t
1441 __in efx_nic_t *enp,
1442 __inout efx_filter_spec_t *spec);
1444 extern __checkReturn efx_rc_t
1446 __in efx_nic_t *enp,
1447 __inout efx_filter_spec_t *spec);
1449 extern __checkReturn efx_rc_t
1451 __in efx_nic_t *enp);
1453 extern __checkReturn efx_rc_t
1454 efx_filter_supported_filters(
1455 __in efx_nic_t *enp,
1456 __out uint32_t *list,
1457 __out size_t *length);
1460 efx_filter_spec_init_rx(
1461 __out efx_filter_spec_t *spec,
1462 __in efx_filter_priority_t priority,
1463 __in efx_filter_flags_t flags,
1464 __in efx_rxq_t *erp);
1467 efx_filter_spec_init_tx(
1468 __out efx_filter_spec_t *spec,
1469 __in efx_txq_t *etp);
1471 extern __checkReturn efx_rc_t
1472 efx_filter_spec_set_ipv4_local(
1473 __inout efx_filter_spec_t *spec,
1476 __in uint16_t port);
1478 extern __checkReturn efx_rc_t
1479 efx_filter_spec_set_ipv4_full(
1480 __inout efx_filter_spec_t *spec,
1482 __in uint32_t lhost,
1483 __in uint16_t lport,
1484 __in uint32_t rhost,
1485 __in uint16_t rport);
1487 extern __checkReturn efx_rc_t
1488 efx_filter_spec_set_eth_local(
1489 __inout efx_filter_spec_t *spec,
1491 __in const uint8_t *addr);
1493 extern __checkReturn efx_rc_t
1494 efx_filter_spec_set_uc_def(
1495 __inout efx_filter_spec_t *spec);
1497 extern __checkReturn efx_rc_t
1498 efx_filter_spec_set_mc_def(
1499 __inout efx_filter_spec_t *spec);
1501 #endif /* EFSYS_OPT_FILTER */
1505 extern __checkReturn uint32_t
1507 __in_ecount(count) uint32_t const *input,
1509 __in uint32_t init);
1511 extern __checkReturn uint32_t
1513 __in_ecount(length) uint8_t const *input,
1515 __in uint32_t init);
1523 #endif /* _SYS_EFX_H */