2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 extern __checkReturn efx_rc_t
152 efx_nic_register_test(
153 __in efx_nic_t *enp);
155 #endif /* EFSYS_OPT_DIAG */
159 __in efx_nic_t *enp);
163 __in efx_nic_t *enp);
167 __in efx_nic_t *enp);
169 #define EFX_PCIE_LINK_SPEED_GEN1 1
170 #define EFX_PCIE_LINK_SPEED_GEN2 2
171 #define EFX_PCIE_LINK_SPEED_GEN3 3
173 typedef enum efx_pcie_link_performance_e {
174 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
175 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
176 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
177 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
178 } efx_pcie_link_performance_t;
180 extern __checkReturn efx_rc_t
181 efx_nic_calculate_pcie_link_bandwidth(
182 __in uint32_t pcie_link_width,
183 __in uint32_t pcie_link_gen,
184 __out uint32_t *bandwidth_mbpsp);
186 extern __checkReturn efx_rc_t
187 efx_nic_check_pcie_link_speed(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out efx_pcie_link_performance_t *resultp);
195 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
196 /* Huntington and Medford require MCDIv2 commands */
197 #define WITH_MCDI_V2 1
200 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
202 typedef enum efx_mcdi_exception_e {
203 EFX_MCDI_EXCEPTION_MC_REBOOT,
204 EFX_MCDI_EXCEPTION_MC_BADASSERT,
205 } efx_mcdi_exception_t;
207 #if EFSYS_OPT_MCDI_LOGGING
208 typedef enum efx_log_msg_e {
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_get_timeout(
246 __in efx_mcdi_req_t *emrp,
247 __out uint32_t *usec_timeoutp);
250 efx_mcdi_request_start(
252 __in efx_mcdi_req_t *emrp,
253 __in boolean_t ev_cpl);
255 extern __checkReturn boolean_t
256 efx_mcdi_request_poll(
257 __in efx_nic_t *enp);
259 extern __checkReturn boolean_t
260 efx_mcdi_request_abort(
261 __in efx_nic_t *enp);
265 __in efx_nic_t *enp);
267 #endif /* EFSYS_OPT_MCDI */
271 #define EFX_NINTR_SIENA 1024
273 typedef enum efx_intr_type_e {
274 EFX_INTR_INVALID = 0,
280 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
282 extern __checkReturn efx_rc_t
285 __in efx_intr_type_t type,
286 __in efsys_mem_t *esmp);
290 __in efx_nic_t *enp);
294 __in efx_nic_t *enp);
297 efx_intr_disable_unlocked(
298 __in efx_nic_t *enp);
300 #define EFX_INTR_NEVQS 32
302 extern __checkReturn efx_rc_t
305 __in unsigned int level);
308 efx_intr_status_line(
310 __out boolean_t *fatalp,
311 __out uint32_t *maskp);
314 efx_intr_status_message(
316 __in unsigned int message,
317 __out boolean_t *fatalp);
321 __in efx_nic_t *enp);
325 __in efx_nic_t *enp);
329 #if EFSYS_OPT_MAC_STATS
331 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
332 typedef enum efx_mac_stat_e {
335 EFX_MAC_RX_UNICST_PKTS,
336 EFX_MAC_RX_MULTICST_PKTS,
337 EFX_MAC_RX_BRDCST_PKTS,
338 EFX_MAC_RX_PAUSE_PKTS,
339 EFX_MAC_RX_LE_64_PKTS,
340 EFX_MAC_RX_65_TO_127_PKTS,
341 EFX_MAC_RX_128_TO_255_PKTS,
342 EFX_MAC_RX_256_TO_511_PKTS,
343 EFX_MAC_RX_512_TO_1023_PKTS,
344 EFX_MAC_RX_1024_TO_15XX_PKTS,
345 EFX_MAC_RX_GE_15XX_PKTS,
347 EFX_MAC_RX_FCS_ERRORS,
348 EFX_MAC_RX_DROP_EVENTS,
349 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
350 EFX_MAC_RX_SYMBOL_ERRORS,
351 EFX_MAC_RX_ALIGN_ERRORS,
352 EFX_MAC_RX_INTERNAL_ERRORS,
353 EFX_MAC_RX_JABBER_PKTS,
354 EFX_MAC_RX_LANE0_CHAR_ERR,
355 EFX_MAC_RX_LANE1_CHAR_ERR,
356 EFX_MAC_RX_LANE2_CHAR_ERR,
357 EFX_MAC_RX_LANE3_CHAR_ERR,
358 EFX_MAC_RX_LANE0_DISP_ERR,
359 EFX_MAC_RX_LANE1_DISP_ERR,
360 EFX_MAC_RX_LANE2_DISP_ERR,
361 EFX_MAC_RX_LANE3_DISP_ERR,
362 EFX_MAC_RX_MATCH_FAULT,
363 EFX_MAC_RX_NODESC_DROP_CNT,
366 EFX_MAC_TX_UNICST_PKTS,
367 EFX_MAC_TX_MULTICST_PKTS,
368 EFX_MAC_TX_BRDCST_PKTS,
369 EFX_MAC_TX_PAUSE_PKTS,
370 EFX_MAC_TX_LE_64_PKTS,
371 EFX_MAC_TX_65_TO_127_PKTS,
372 EFX_MAC_TX_128_TO_255_PKTS,
373 EFX_MAC_TX_256_TO_511_PKTS,
374 EFX_MAC_TX_512_TO_1023_PKTS,
375 EFX_MAC_TX_1024_TO_15XX_PKTS,
376 EFX_MAC_TX_GE_15XX_PKTS,
378 EFX_MAC_TX_SGL_COL_PKTS,
379 EFX_MAC_TX_MULT_COL_PKTS,
380 EFX_MAC_TX_EX_COL_PKTS,
381 EFX_MAC_TX_LATE_COL_PKTS,
383 EFX_MAC_TX_EX_DEF_PKTS,
384 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
385 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
386 EFX_MAC_PM_TRUNC_VFIFO_FULL,
387 EFX_MAC_PM_DISCARD_VFIFO_FULL,
388 EFX_MAC_PM_TRUNC_QBB,
389 EFX_MAC_PM_DISCARD_QBB,
390 EFX_MAC_PM_DISCARD_MAPPING,
391 EFX_MAC_RXDP_Q_DISABLED_PKTS,
392 EFX_MAC_RXDP_DI_DROPPED_PKTS,
393 EFX_MAC_RXDP_STREAMING_PKTS,
394 EFX_MAC_RXDP_HLB_FETCH,
395 EFX_MAC_RXDP_HLB_WAIT,
396 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
397 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
398 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
399 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
400 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
401 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
402 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
403 EFX_MAC_VADAPTER_RX_BAD_BYTES,
404 EFX_MAC_VADAPTER_RX_OVERFLOW,
405 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
406 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
407 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
408 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
409 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
410 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
411 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
412 EFX_MAC_VADAPTER_TX_BAD_BYTES,
413 EFX_MAC_VADAPTER_TX_OVERFLOW,
417 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
419 #endif /* EFSYS_OPT_MAC_STATS */
421 typedef enum efx_link_mode_e {
422 EFX_LINK_UNKNOWN = 0,
435 #define EFX_MAC_ADDR_LEN 6
437 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
439 #define EFX_MAC_MULTICAST_LIST_MAX 256
441 #define EFX_MAC_SDU_MAX 9202
443 #define EFX_MAC_PDU_ADJUSTMENT \
447 + /* bug16011 */ 16) \
449 #define EFX_MAC_PDU(_sdu) \
450 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
453 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
454 * the SDU rounded up slightly.
456 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
458 #define EFX_MAC_PDU_MIN 60
459 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
461 extern __checkReturn efx_rc_t
466 extern __checkReturn efx_rc_t
471 extern __checkReturn efx_rc_t
476 extern __checkReturn efx_rc_t
479 __in boolean_t all_unicst,
480 __in boolean_t mulcst,
481 __in boolean_t all_mulcst,
482 __in boolean_t brdcst);
484 extern __checkReturn efx_rc_t
485 efx_mac_multicast_list_set(
487 __in_ecount(6*count) uint8_t const *addrs,
490 extern __checkReturn efx_rc_t
491 efx_mac_filter_default_rxq_set(
494 __in boolean_t using_rss);
497 efx_mac_filter_default_rxq_clear(
498 __in efx_nic_t *enp);
500 extern __checkReturn efx_rc_t
503 __in boolean_t enabled);
505 extern __checkReturn efx_rc_t
508 __out boolean_t *mac_upp);
510 #define EFX_FCNTL_RESPOND 0x00000001
511 #define EFX_FCNTL_GENERATE 0x00000002
513 extern __checkReturn efx_rc_t
516 __in unsigned int fcntl,
517 __in boolean_t autoneg);
522 __out unsigned int *fcntl_wantedp,
523 __out unsigned int *fcntl_linkp);
526 #if EFSYS_OPT_MAC_STATS
530 extern __checkReturn const char *
533 __in unsigned int id);
535 #endif /* EFSYS_OPT_NAMES */
537 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
539 #define EFX_MAC_STATS_MASK_NPAGES \
540 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
541 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
544 * Get mask of MAC statistics supported by the hardware.
546 * If mask_size is insufficient to return the mask, EINVAL error is
547 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
548 * (which is sizeof (uint32_t)) is sufficient.
550 extern __checkReturn efx_rc_t
551 efx_mac_stats_get_mask(
553 __out_bcount(mask_size) uint32_t *maskp,
554 __in size_t mask_size);
556 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
557 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
558 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
560 #define EFX_MAC_STATS_SIZE 0x400
563 * Upload mac statistics supported by the hardware into the given buffer.
565 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
568 * The hardware will only DMA statistics that it understands (of course).
569 * Drivers should not make any assumptions about which statistics are
570 * supported, especially when the statistics are generated by firmware.
572 * Thus, drivers should zero this buffer before use, so that not-understood
573 * statistics read back as zero.
575 extern __checkReturn efx_rc_t
576 efx_mac_stats_upload(
578 __in efsys_mem_t *esmp);
580 extern __checkReturn efx_rc_t
581 efx_mac_stats_periodic(
583 __in efsys_mem_t *esmp,
584 __in uint16_t period_ms,
585 __in boolean_t events);
587 extern __checkReturn efx_rc_t
588 efx_mac_stats_update(
590 __in efsys_mem_t *esmp,
591 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
592 __inout_opt uint32_t *generationp);
594 #endif /* EFSYS_OPT_MAC_STATS */
598 typedef enum efx_mon_type_e {
610 __in efx_nic_t *enp);
612 #endif /* EFSYS_OPT_NAMES */
614 extern __checkReturn efx_rc_t
616 __in efx_nic_t *enp);
620 __in efx_nic_t *enp);
624 extern __checkReturn efx_rc_t
626 __in efx_nic_t *enp);
628 #if EFSYS_OPT_PHY_LED_CONTROL
630 typedef enum efx_phy_led_mode_e {
631 EFX_PHY_LED_DEFAULT = 0,
636 } efx_phy_led_mode_t;
638 extern __checkReturn efx_rc_t
641 __in efx_phy_led_mode_t mode);
643 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
645 extern __checkReturn efx_rc_t
647 __in efx_nic_t *enp);
649 extern __checkReturn efx_rc_t
652 __out_opt efx_link_mode_t *link_modep);
656 __in efx_nic_t *enp);
658 typedef enum efx_phy_cap_type_e {
659 EFX_PHY_CAP_INVALID = 0,
666 EFX_PHY_CAP_10000FDX,
670 EFX_PHY_CAP_40000FDX,
672 } efx_phy_cap_type_t;
675 #define EFX_PHY_CAP_CURRENT 0x00000000
676 #define EFX_PHY_CAP_DEFAULT 0x00000001
677 #define EFX_PHY_CAP_PERM 0x00000002
683 __out uint32_t *maskp);
685 extern __checkReturn efx_rc_t
693 __out uint32_t *maskp);
695 extern __checkReturn efx_rc_t
698 __out uint32_t *ouip);
700 typedef enum efx_phy_media_type_e {
701 EFX_PHY_MEDIA_INVALID = 0,
706 EFX_PHY_MEDIA_SFP_PLUS,
707 EFX_PHY_MEDIA_BASE_T,
708 EFX_PHY_MEDIA_QSFP_PLUS,
710 } efx_phy_media_type_t;
712 /* Get the type of medium currently used. If the board has ports for
713 * modules, a module is present, and we recognise the media type of
714 * the module, then this will be the media type of the module.
715 * Otherwise it will be the media type of the port.
718 efx_phy_media_type_get(
720 __out efx_phy_media_type_t *typep);
723 efx_phy_module_get_info(
725 __in uint8_t dev_addr,
728 __out_bcount(len) uint8_t *data);
730 #if EFSYS_OPT_PHY_STATS
732 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
733 typedef enum efx_phy_stat_e {
735 EFX_PHY_STAT_PMA_PMD_LINK_UP,
736 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
737 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
738 EFX_PHY_STAT_PMA_PMD_REV_A,
739 EFX_PHY_STAT_PMA_PMD_REV_B,
740 EFX_PHY_STAT_PMA_PMD_REV_C,
741 EFX_PHY_STAT_PMA_PMD_REV_D,
742 EFX_PHY_STAT_PCS_LINK_UP,
743 EFX_PHY_STAT_PCS_RX_FAULT,
744 EFX_PHY_STAT_PCS_TX_FAULT,
745 EFX_PHY_STAT_PCS_BER,
746 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
747 EFX_PHY_STAT_PHY_XS_LINK_UP,
748 EFX_PHY_STAT_PHY_XS_RX_FAULT,
749 EFX_PHY_STAT_PHY_XS_TX_FAULT,
750 EFX_PHY_STAT_PHY_XS_ALIGN,
751 EFX_PHY_STAT_PHY_XS_SYNC_A,
752 EFX_PHY_STAT_PHY_XS_SYNC_B,
753 EFX_PHY_STAT_PHY_XS_SYNC_C,
754 EFX_PHY_STAT_PHY_XS_SYNC_D,
755 EFX_PHY_STAT_AN_LINK_UP,
756 EFX_PHY_STAT_AN_MASTER,
757 EFX_PHY_STAT_AN_LOCAL_RX_OK,
758 EFX_PHY_STAT_AN_REMOTE_RX_OK,
759 EFX_PHY_STAT_CL22EXT_LINK_UP,
764 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
765 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
766 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
767 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
768 EFX_PHY_STAT_AN_COMPLETE,
769 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
770 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
771 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
772 EFX_PHY_STAT_PCS_FW_VERSION_0,
773 EFX_PHY_STAT_PCS_FW_VERSION_1,
774 EFX_PHY_STAT_PCS_FW_VERSION_2,
775 EFX_PHY_STAT_PCS_FW_VERSION_3,
776 EFX_PHY_STAT_PCS_FW_BUILD_YY,
777 EFX_PHY_STAT_PCS_FW_BUILD_MM,
778 EFX_PHY_STAT_PCS_FW_BUILD_DD,
779 EFX_PHY_STAT_PCS_OP_MODE,
783 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
790 __in efx_phy_stat_t stat);
792 #endif /* EFSYS_OPT_NAMES */
794 #define EFX_PHY_STATS_SIZE 0x100
796 extern __checkReturn efx_rc_t
797 efx_phy_stats_update(
799 __in efsys_mem_t *esmp,
800 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
802 #endif /* EFSYS_OPT_PHY_STATS */
807 typedef enum efx_bist_type_e {
808 EFX_BIST_TYPE_UNKNOWN,
809 EFX_BIST_TYPE_PHY_NORMAL,
810 EFX_BIST_TYPE_PHY_CABLE_SHORT,
811 EFX_BIST_TYPE_PHY_CABLE_LONG,
812 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
813 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
814 EFX_BIST_TYPE_REG, /* Test the register memories */
815 EFX_BIST_TYPE_NTYPES,
818 typedef enum efx_bist_result_e {
819 EFX_BIST_RESULT_UNKNOWN,
820 EFX_BIST_RESULT_RUNNING,
821 EFX_BIST_RESULT_PASSED,
822 EFX_BIST_RESULT_FAILED,
825 typedef enum efx_phy_cable_status_e {
826 EFX_PHY_CABLE_STATUS_OK,
827 EFX_PHY_CABLE_STATUS_INVALID,
828 EFX_PHY_CABLE_STATUS_OPEN,
829 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
830 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
831 EFX_PHY_CABLE_STATUS_BUSY,
832 } efx_phy_cable_status_t;
834 typedef enum efx_bist_value_e {
835 EFX_BIST_PHY_CABLE_LENGTH_A,
836 EFX_BIST_PHY_CABLE_LENGTH_B,
837 EFX_BIST_PHY_CABLE_LENGTH_C,
838 EFX_BIST_PHY_CABLE_LENGTH_D,
839 EFX_BIST_PHY_CABLE_STATUS_A,
840 EFX_BIST_PHY_CABLE_STATUS_B,
841 EFX_BIST_PHY_CABLE_STATUS_C,
842 EFX_BIST_PHY_CABLE_STATUS_D,
844 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
852 EFX_BIST_MEM_ECC_PARITY,
853 EFX_BIST_MEM_ECC_FATAL,
857 extern __checkReturn efx_rc_t
858 efx_bist_enable_offline(
859 __in efx_nic_t *enp);
861 extern __checkReturn efx_rc_t
864 __in efx_bist_type_t type);
866 extern __checkReturn efx_rc_t
869 __in efx_bist_type_t type,
870 __out efx_bist_result_t *resultp,
871 __out_opt uint32_t *value_maskp,
872 __out_ecount_opt(count) unsigned long *valuesp,
878 __in efx_bist_type_t type);
880 #endif /* EFSYS_OPT_BIST */
882 #define EFX_FEATURE_IPV6 0x00000001
883 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
884 #define EFX_FEATURE_LINK_EVENTS 0x00000004
885 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
886 #define EFX_FEATURE_MCDI 0x00000020
887 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
888 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
889 #define EFX_FEATURE_TURBO 0x00000100
890 #define EFX_FEATURE_MCDI_DMA 0x00000200
891 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
892 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
893 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
894 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
895 #define EFX_FEATURE_PACKED_STREAM 0x00004000
897 typedef struct efx_nic_cfg_s {
898 uint32_t enc_board_type;
899 uint32_t enc_phy_type;
901 char enc_phy_name[21];
903 char enc_phy_revision[21];
904 efx_mon_type_t enc_mon_type;
905 unsigned int enc_features;
906 uint8_t enc_mac_addr[6];
907 uint8_t enc_port; /* PHY port number */
908 uint32_t enc_intr_vec_base;
909 uint32_t enc_intr_limit;
910 uint32_t enc_evq_limit;
911 uint32_t enc_txq_limit;
912 uint32_t enc_rxq_limit;
913 uint32_t enc_txq_max_ndescs;
914 uint32_t enc_buftbl_limit;
915 uint32_t enc_piobuf_limit;
916 uint32_t enc_piobuf_size;
917 uint32_t enc_piobuf_min_alloc_size;
918 uint32_t enc_evq_timer_quantum_ns;
919 uint32_t enc_evq_timer_max_us;
920 uint32_t enc_clk_mult;
921 uint32_t enc_rx_prefix_size;
922 uint32_t enc_rx_buf_align_start;
923 uint32_t enc_rx_buf_align_end;
924 #if EFSYS_OPT_PHY_FLAGS
925 uint32_t enc_phy_flags_mask;
926 #endif /* EFSYS_OPT_PHY_FLAGS */
927 #if EFSYS_OPT_PHY_LED_CONTROL
928 uint32_t enc_led_mask;
929 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
930 #if EFSYS_OPT_PHY_STATS
931 uint64_t enc_phy_stat_mask;
932 #endif /* EFSYS_OPT_PHY_STATS */
934 uint8_t enc_mcdi_mdio_channel;
935 #if EFSYS_OPT_PHY_STATS
936 uint32_t enc_mcdi_phy_stat_mask;
937 #endif /* EFSYS_OPT_PHY_STATS */
938 #endif /* EFSYS_OPT_MCDI */
940 uint32_t enc_bist_mask;
941 #endif /* EFSYS_OPT_BIST */
942 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
945 uint32_t enc_privilege_mask;
946 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
947 boolean_t enc_bug26807_workaround;
948 boolean_t enc_bug35388_workaround;
949 boolean_t enc_bug41750_workaround;
950 boolean_t enc_bug61265_workaround;
951 boolean_t enc_rx_batching_enabled;
952 /* Maximum number of descriptors completed in an rx event. */
953 uint32_t enc_rx_batch_max;
954 /* Number of rx descriptors the hardware requires for a push. */
955 uint32_t enc_rx_push_align;
957 * Maximum number of bytes into the packet the TCP header can start for
958 * the hardware to apply TSO packet edits.
960 uint32_t enc_tx_tso_tcp_header_offset_limit;
961 boolean_t enc_fw_assisted_tso_enabled;
962 boolean_t enc_fw_assisted_tso_v2_enabled;
963 /* Number of TSO contexts on the NIC (FATSOv2) */
964 uint32_t enc_fw_assisted_tso_v2_n_contexts;
965 boolean_t enc_hw_tx_insert_vlan_enabled;
966 /* Number of PFs on the NIC */
967 uint32_t enc_hw_pf_count;
968 /* Datapath firmware vadapter/vport/vswitch support */
969 boolean_t enc_datapath_cap_evb;
970 boolean_t enc_rx_disable_scatter_supported;
971 boolean_t enc_allow_set_mac_with_installed_filters;
972 boolean_t enc_enhanced_set_mac_supported;
973 boolean_t enc_init_evq_v2_supported;
974 boolean_t enc_rx_packed_stream_supported;
975 boolean_t enc_rx_var_packed_stream_supported;
976 boolean_t enc_pm_and_rxdp_counters;
977 boolean_t enc_mac_stats_40g_tx_size_bins;
978 /* External port identifier */
979 uint8_t enc_external_port;
980 uint32_t enc_mcdi_max_payload_length;
981 /* VPD may be per-PF or global */
982 boolean_t enc_vpd_is_global;
983 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
984 uint32_t enc_required_pcie_bandwidth_mbps;
985 uint32_t enc_max_pcie_link_gen;
986 /* Firmware verifies integrity of NVRAM updates */
987 uint32_t enc_fw_verified_nvram_update_required;
990 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
991 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
993 #define EFX_PCI_FUNCTION(_encp) \
994 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
996 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
998 extern const efx_nic_cfg_t *
1000 __in efx_nic_t *enp);
1002 /* Driver resource limits (minimum required/maximum usable). */
1003 typedef struct efx_drv_limits_s {
1004 uint32_t edl_min_evq_count;
1005 uint32_t edl_max_evq_count;
1007 uint32_t edl_min_rxq_count;
1008 uint32_t edl_max_rxq_count;
1010 uint32_t edl_min_txq_count;
1011 uint32_t edl_max_txq_count;
1013 /* PIO blocks (sub-allocated from piobuf) */
1014 uint32_t edl_min_pio_alloc_size;
1015 uint32_t edl_max_pio_alloc_count;
1018 extern __checkReturn efx_rc_t
1019 efx_nic_set_drv_limits(
1020 __inout efx_nic_t *enp,
1021 __in efx_drv_limits_t *edlp);
1023 typedef enum efx_nic_region_e {
1024 EFX_REGION_VI, /* Memory BAR UC mapping */
1025 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1028 extern __checkReturn efx_rc_t
1029 efx_nic_get_bar_region(
1030 __in efx_nic_t *enp,
1031 __in efx_nic_region_t region,
1032 __out uint32_t *offsetp,
1033 __out size_t *sizep);
1035 extern __checkReturn efx_rc_t
1036 efx_nic_get_vi_pool(
1037 __in efx_nic_t *enp,
1038 __out uint32_t *evq_countp,
1039 __out uint32_t *rxq_countp,
1040 __out uint32_t *txq_countp);
1047 typedef enum efx_pattern_type_t {
1048 EFX_PATTERN_BYTE_INCREMENT = 0,
1049 EFX_PATTERN_ALL_THE_SAME,
1050 EFX_PATTERN_BIT_ALTERNATE,
1051 EFX_PATTERN_BYTE_ALTERNATE,
1052 EFX_PATTERN_BYTE_CHANGING,
1053 EFX_PATTERN_BIT_SWEEP,
1055 } efx_pattern_type_t;
1058 (*efx_sram_pattern_fn_t)(
1060 __in boolean_t negate,
1061 __out efx_qword_t *eqp);
1063 extern __checkReturn efx_rc_t
1065 __in efx_nic_t *enp,
1066 __in efx_pattern_type_t type);
1068 #endif /* EFSYS_OPT_DIAG */
1070 extern __checkReturn efx_rc_t
1071 efx_sram_buf_tbl_set(
1072 __in efx_nic_t *enp,
1074 __in efsys_mem_t *esmp,
1078 efx_sram_buf_tbl_clear(
1079 __in efx_nic_t *enp,
1083 #define EFX_BUF_TBL_SIZE 0x20000
1085 #define EFX_BUF_SIZE 4096
1089 typedef struct efx_evq_s efx_evq_t;
1091 #if EFSYS_OPT_QSTATS
1093 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1094 typedef enum efx_ev_qstat_e {
1100 EV_RX_PAUSE_FRM_ERR,
1101 EV_RX_BUF_OWNER_ID_ERR,
1102 EV_RX_IPV4_HDR_CHKSUM_ERR,
1103 EV_RX_TCP_UDP_CHKSUM_ERR,
1107 EV_RX_MCAST_HASH_MATCH,
1124 EV_DRIVER_SRM_UPD_DONE,
1125 EV_DRIVER_TX_DESCQ_FLS_DONE,
1126 EV_DRIVER_RX_DESCQ_FLS_DONE,
1127 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1128 EV_DRIVER_RX_DSC_ERROR,
1129 EV_DRIVER_TX_DSC_ERROR,
1135 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1137 #endif /* EFSYS_OPT_QSTATS */
1139 extern __checkReturn efx_rc_t
1141 __in efx_nic_t *enp);
1145 __in efx_nic_t *enp);
1147 #define EFX_EVQ_MAXNEVS 32768
1148 #define EFX_EVQ_MINNEVS 512
1150 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1151 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1153 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1154 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1155 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1156 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1158 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1159 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1160 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1162 extern __checkReturn efx_rc_t
1164 __in efx_nic_t *enp,
1165 __in unsigned int index,
1166 __in efsys_mem_t *esmp,
1170 __in uint32_t flags,
1171 __deref_out efx_evq_t **eepp);
1175 __in efx_evq_t *eep,
1176 __in uint16_t data);
1178 typedef __checkReturn boolean_t
1179 (*efx_initialized_ev_t)(
1180 __in_opt void *arg);
1182 #define EFX_PKT_UNICAST 0x0004
1183 #define EFX_PKT_START 0x0008
1185 #define EFX_PKT_VLAN_TAGGED 0x0010
1186 #define EFX_CKSUM_TCPUDP 0x0020
1187 #define EFX_CKSUM_IPV4 0x0040
1188 #define EFX_PKT_CONT 0x0080
1190 #define EFX_CHECK_VLAN 0x0100
1191 #define EFX_PKT_TCP 0x0200
1192 #define EFX_PKT_UDP 0x0400
1193 #define EFX_PKT_IPV4 0x0800
1195 #define EFX_PKT_IPV6 0x1000
1196 #define EFX_PKT_PREFIX_LEN 0x2000
1197 #define EFX_ADDR_MISMATCH 0x4000
1198 #define EFX_DISCARD 0x8000
1201 * The following flags are used only for packed stream
1202 * mode. The values for the flags are reused to fit into 16 bit,
1203 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1204 * packed stream mode
1206 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1207 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1210 #define EFX_EV_RX_NLABELS 32
1211 #define EFX_EV_TX_NLABELS 32
1213 typedef __checkReturn boolean_t
1216 __in uint32_t label,
1219 __in uint16_t flags);
1221 typedef __checkReturn boolean_t
1224 __in uint32_t label,
1227 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1228 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1229 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1230 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1231 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1232 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1233 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1234 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1235 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1237 typedef __checkReturn boolean_t
1238 (*efx_exception_ev_t)(
1240 __in uint32_t label,
1241 __in uint32_t data);
1243 typedef __checkReturn boolean_t
1244 (*efx_rxq_flush_done_ev_t)(
1246 __in uint32_t rxq_index);
1248 typedef __checkReturn boolean_t
1249 (*efx_rxq_flush_failed_ev_t)(
1251 __in uint32_t rxq_index);
1253 typedef __checkReturn boolean_t
1254 (*efx_txq_flush_done_ev_t)(
1256 __in uint32_t txq_index);
1258 typedef __checkReturn boolean_t
1259 (*efx_software_ev_t)(
1261 __in uint16_t magic);
1263 typedef __checkReturn boolean_t
1266 __in uint32_t code);
1268 #define EFX_SRAM_CLEAR 0
1269 #define EFX_SRAM_UPDATE 1
1270 #define EFX_SRAM_ILLEGAL_CLEAR 2
1272 typedef __checkReturn boolean_t
1273 (*efx_wake_up_ev_t)(
1275 __in uint32_t label);
1277 typedef __checkReturn boolean_t
1280 __in uint32_t label);
1282 typedef __checkReturn boolean_t
1283 (*efx_link_change_ev_t)(
1285 __in efx_link_mode_t link_mode);
1287 #if EFSYS_OPT_MAC_STATS
1289 typedef __checkReturn boolean_t
1290 (*efx_mac_stats_ev_t)(
1292 __in uint32_t generation
1295 #endif /* EFSYS_OPT_MAC_STATS */
1297 typedef struct efx_ev_callbacks_s {
1298 efx_initialized_ev_t eec_initialized;
1301 efx_exception_ev_t eec_exception;
1302 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1303 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1304 efx_txq_flush_done_ev_t eec_txq_flush_done;
1305 efx_software_ev_t eec_software;
1306 efx_sram_ev_t eec_sram;
1307 efx_wake_up_ev_t eec_wake_up;
1308 efx_timer_ev_t eec_timer;
1309 efx_link_change_ev_t eec_link_change;
1310 #if EFSYS_OPT_MAC_STATS
1311 efx_mac_stats_ev_t eec_mac_stats;
1312 #endif /* EFSYS_OPT_MAC_STATS */
1313 } efx_ev_callbacks_t;
1315 extern __checkReturn boolean_t
1317 __in efx_evq_t *eep,
1318 __in unsigned int count);
1320 #if EFSYS_OPT_EV_PREFETCH
1324 __in efx_evq_t *eep,
1325 __in unsigned int count);
1327 #endif /* EFSYS_OPT_EV_PREFETCH */
1331 __in efx_evq_t *eep,
1332 __inout unsigned int *countp,
1333 __in const efx_ev_callbacks_t *eecp,
1334 __in_opt void *arg);
1336 extern __checkReturn efx_rc_t
1337 efx_ev_usecs_to_ticks(
1338 __in efx_nic_t *enp,
1339 __in unsigned int usecs,
1340 __out unsigned int *ticksp);
1342 extern __checkReturn efx_rc_t
1344 __in efx_evq_t *eep,
1345 __in unsigned int us);
1347 extern __checkReturn efx_rc_t
1349 __in efx_evq_t *eep,
1350 __in unsigned int count);
1352 #if EFSYS_OPT_QSTATS
1358 __in efx_nic_t *enp,
1359 __in unsigned int id);
1361 #endif /* EFSYS_OPT_NAMES */
1364 efx_ev_qstats_update(
1365 __in efx_evq_t *eep,
1366 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1368 #endif /* EFSYS_OPT_QSTATS */
1372 __in efx_evq_t *eep);
1376 extern __checkReturn efx_rc_t
1378 __inout efx_nic_t *enp);
1382 __in efx_nic_t *enp);
1384 extern __checkReturn efx_rc_t
1385 efx_pseudo_hdr_pkt_length_get(
1386 __in efx_rxq_t *erp,
1387 __in uint8_t *buffer,
1388 __out uint16_t *pkt_lengthp);
1390 #define EFX_RXQ_MAXNDESCS 4096
1391 #define EFX_RXQ_MINNDESCS 512
1393 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1394 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1395 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1396 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1398 typedef enum efx_rxq_type_e {
1399 EFX_RXQ_TYPE_DEFAULT,
1400 EFX_RXQ_TYPE_SCATTER,
1401 EFX_RXQ_TYPE_PACKED_STREAM_1M,
1402 EFX_RXQ_TYPE_PACKED_STREAM_512K,
1403 EFX_RXQ_TYPE_PACKED_STREAM_256K,
1404 EFX_RXQ_TYPE_PACKED_STREAM_128K,
1405 EFX_RXQ_TYPE_PACKED_STREAM_64K,
1409 extern __checkReturn efx_rc_t
1411 __in efx_nic_t *enp,
1412 __in unsigned int index,
1413 __in unsigned int label,
1414 __in efx_rxq_type_t type,
1415 __in efsys_mem_t *esmp,
1418 __in efx_evq_t *eep,
1419 __deref_out efx_rxq_t **erpp);
1421 typedef struct efx_buffer_s {
1422 efsys_dma_addr_t eb_addr;
1427 typedef struct efx_desc_s {
1433 __in efx_rxq_t *erp,
1434 __in_ecount(n) efsys_dma_addr_t *addrp,
1436 __in unsigned int n,
1437 __in unsigned int completed,
1438 __in unsigned int added);
1442 __in efx_rxq_t *erp,
1443 __in unsigned int added,
1444 __inout unsigned int *pushedp);
1446 extern __checkReturn efx_rc_t
1448 __in efx_rxq_t *erp);
1452 __in efx_rxq_t *erp);
1456 __in efx_rxq_t *erp);
1460 typedef struct efx_txq_s efx_txq_t;
1462 #if EFSYS_OPT_QSTATS
1464 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1465 typedef enum efx_tx_qstat_e {
1471 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1473 #endif /* EFSYS_OPT_QSTATS */
1475 extern __checkReturn efx_rc_t
1477 __in efx_nic_t *enp);
1481 __in efx_nic_t *enp);
1483 #define EFX_TXQ_MINNDESCS 512
1485 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1486 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1487 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1488 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1490 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1492 #define EFX_TXQ_CKSUM_IPV4 0x0001
1493 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1494 #define EFX_TXQ_FATSOV2 0x0004
1496 extern __checkReturn efx_rc_t
1498 __in efx_nic_t *enp,
1499 __in unsigned int index,
1500 __in unsigned int label,
1501 __in efsys_mem_t *esmp,
1504 __in uint16_t flags,
1505 __in efx_evq_t *eep,
1506 __deref_out efx_txq_t **etpp,
1507 __out unsigned int *addedp);
1509 extern __checkReturn efx_rc_t
1511 __in efx_txq_t *etp,
1512 __in_ecount(n) efx_buffer_t *eb,
1513 __in unsigned int n,
1514 __in unsigned int completed,
1515 __inout unsigned int *addedp);
1517 extern __checkReturn efx_rc_t
1519 __in efx_txq_t *etp,
1520 __in unsigned int ns);
1524 __in efx_txq_t *etp,
1525 __in unsigned int added,
1526 __in unsigned int pushed);
1528 extern __checkReturn efx_rc_t
1530 __in efx_txq_t *etp);
1534 __in efx_txq_t *etp);
1536 extern __checkReturn efx_rc_t
1538 __in efx_txq_t *etp);
1541 efx_tx_qpio_disable(
1542 __in efx_txq_t *etp);
1544 extern __checkReturn efx_rc_t
1546 __in efx_txq_t *etp,
1547 __in_ecount(buf_length) uint8_t *buffer,
1548 __in size_t buf_length,
1549 __in size_t pio_buf_offset);
1551 extern __checkReturn efx_rc_t
1553 __in efx_txq_t *etp,
1554 __in size_t pkt_length,
1555 __in unsigned int completed,
1556 __inout unsigned int *addedp);
1558 extern __checkReturn efx_rc_t
1560 __in efx_txq_t *etp,
1561 __in_ecount(n) efx_desc_t *ed,
1562 __in unsigned int n,
1563 __in unsigned int completed,
1564 __inout unsigned int *addedp);
1567 efx_tx_qdesc_dma_create(
1568 __in efx_txq_t *etp,
1569 __in efsys_dma_addr_t addr,
1572 __out efx_desc_t *edp);
1575 efx_tx_qdesc_tso_create(
1576 __in efx_txq_t *etp,
1577 __in uint16_t ipv4_id,
1578 __in uint32_t tcp_seq,
1579 __in uint8_t tcp_flags,
1580 __out efx_desc_t *edp);
1582 /* Number of FATSOv2 option descriptors */
1583 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1585 /* Maximum number of DMA segments per TSO packet (not superframe) */
1586 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1589 efx_tx_qdesc_tso2_create(
1590 __in efx_txq_t *etp,
1591 __in uint16_t ipv4_id,
1592 __in uint32_t tcp_seq,
1593 __in uint16_t tcp_mss,
1594 __out_ecount(count) efx_desc_t *edp,
1598 efx_tx_qdesc_vlantci_create(
1599 __in efx_txq_t *etp,
1601 __out efx_desc_t *edp);
1603 #if EFSYS_OPT_QSTATS
1609 __in efx_nic_t *etp,
1610 __in unsigned int id);
1612 #endif /* EFSYS_OPT_NAMES */
1615 efx_tx_qstats_update(
1616 __in efx_txq_t *etp,
1617 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1619 #endif /* EFSYS_OPT_QSTATS */
1623 __in efx_txq_t *etp);
1628 #if EFSYS_OPT_FILTER
1630 #define EFX_ETHER_TYPE_IPV4 0x0800
1631 #define EFX_ETHER_TYPE_IPV6 0x86DD
1633 #define EFX_IPPROTO_TCP 6
1634 #define EFX_IPPROTO_UDP 17
1636 /* Use RSS to spread across multiple queues */
1637 #define EFX_FILTER_FLAG_RX_RSS 0x01
1638 /* Enable RX scatter */
1639 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1641 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1642 * May only be set by the filter implementation for each type.
1643 * A removal request will restore the automatic filter in its place.
1645 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1646 /* Filter is for RX */
1647 #define EFX_FILTER_FLAG_RX 0x08
1648 /* Filter is for TX */
1649 #define EFX_FILTER_FLAG_TX 0x10
1651 typedef unsigned int efx_filter_flags_t;
1653 typedef enum efx_filter_match_flags_e {
1654 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1656 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1658 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1659 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1660 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1661 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1662 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1663 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1664 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1665 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1667 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1668 * I/G bit. Used for RX default
1669 * unicast and multicast/
1670 * broadcast filters. */
1671 } efx_filter_match_flags_t;
1673 typedef enum efx_filter_priority_s {
1674 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1675 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1676 * address list or hardware
1677 * requirements. This may only be used
1678 * by the filter implementation for
1680 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1681 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1682 * client (e.g. SR-IOV, HyperV VMQ etc.)
1684 } efx_filter_priority_t;
1687 * FIXME: All these fields are assumed to be in little-endian byte order.
1688 * It may be better for some to be big-endian. See bug42804.
1691 typedef struct efx_filter_spec_s {
1692 uint32_t efs_match_flags:12;
1693 uint32_t efs_priority:2;
1694 uint32_t efs_flags:6;
1695 uint32_t efs_dmaq_id:12;
1696 uint32_t efs_rss_context;
1697 uint16_t efs_outer_vid;
1698 uint16_t efs_inner_vid;
1699 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1700 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1701 uint16_t efs_ether_type;
1702 uint8_t efs_ip_proto;
1703 uint16_t efs_loc_port;
1704 uint16_t efs_rem_port;
1705 efx_oword_t efs_rem_host;
1706 efx_oword_t efs_loc_host;
1707 } efx_filter_spec_t;
1710 /* Default values for use in filter specifications */
1711 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1712 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1713 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1715 extern __checkReturn efx_rc_t
1717 __in efx_nic_t *enp);
1721 __in efx_nic_t *enp);
1723 extern __checkReturn efx_rc_t
1725 __in efx_nic_t *enp,
1726 __inout efx_filter_spec_t *spec);
1728 extern __checkReturn efx_rc_t
1730 __in efx_nic_t *enp,
1731 __inout efx_filter_spec_t *spec);
1733 extern __checkReturn efx_rc_t
1735 __in efx_nic_t *enp);
1737 extern __checkReturn efx_rc_t
1738 efx_filter_supported_filters(
1739 __in efx_nic_t *enp,
1740 __out uint32_t *list,
1741 __out size_t *length);
1744 efx_filter_spec_init_rx(
1745 __out efx_filter_spec_t *spec,
1746 __in efx_filter_priority_t priority,
1747 __in efx_filter_flags_t flags,
1748 __in efx_rxq_t *erp);
1751 efx_filter_spec_init_tx(
1752 __out efx_filter_spec_t *spec,
1753 __in efx_txq_t *etp);
1755 extern __checkReturn efx_rc_t
1756 efx_filter_spec_set_ipv4_local(
1757 __inout efx_filter_spec_t *spec,
1760 __in uint16_t port);
1762 extern __checkReturn efx_rc_t
1763 efx_filter_spec_set_ipv4_full(
1764 __inout efx_filter_spec_t *spec,
1766 __in uint32_t lhost,
1767 __in uint16_t lport,
1768 __in uint32_t rhost,
1769 __in uint16_t rport);
1771 extern __checkReturn efx_rc_t
1772 efx_filter_spec_set_eth_local(
1773 __inout efx_filter_spec_t *spec,
1775 __in const uint8_t *addr);
1777 extern __checkReturn efx_rc_t
1778 efx_filter_spec_set_uc_def(
1779 __inout efx_filter_spec_t *spec);
1781 extern __checkReturn efx_rc_t
1782 efx_filter_spec_set_mc_def(
1783 __inout efx_filter_spec_t *spec);
1785 #endif /* EFSYS_OPT_FILTER */
1789 extern __checkReturn uint32_t
1791 __in_ecount(count) uint32_t const *input,
1793 __in uint32_t init);
1795 extern __checkReturn uint32_t
1797 __in_ecount(length) uint8_t const *input,
1799 __in uint32_t init);
1807 #endif /* _SYS_EFX_H */