1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
133 typedef enum efx_fw_variant_e {
134 EFX_FW_VARIANT_FULL_FEATURED,
135 EFX_FW_VARIANT_LOW_LATENCY,
136 EFX_FW_VARIANT_PACKED_STREAM,
137 EFX_FW_VARIANT_HIGH_TX_RATE,
138 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
139 EFX_FW_VARIANT_RULES_ENGINE,
141 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
144 extern __checkReturn efx_rc_t
147 __in efx_fw_variant_t efv);
149 extern __checkReturn efx_rc_t
151 __in efx_nic_t *enp);
153 extern __checkReturn efx_rc_t
155 __in efx_nic_t *enp);
159 extern __checkReturn efx_rc_t
160 efx_nic_register_test(
161 __in efx_nic_t *enp);
163 #endif /* EFSYS_OPT_DIAG */
167 __in efx_nic_t *enp);
171 __in efx_nic_t *enp);
175 __in efx_nic_t *enp);
177 #define EFX_PCIE_LINK_SPEED_GEN1 1
178 #define EFX_PCIE_LINK_SPEED_GEN2 2
179 #define EFX_PCIE_LINK_SPEED_GEN3 3
181 typedef enum efx_pcie_link_performance_e {
182 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
183 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
184 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
185 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
186 } efx_pcie_link_performance_t;
188 extern __checkReturn efx_rc_t
189 efx_nic_calculate_pcie_link_bandwidth(
190 __in uint32_t pcie_link_width,
191 __in uint32_t pcie_link_gen,
192 __out uint32_t *bandwidth_mbpsp);
194 extern __checkReturn efx_rc_t
195 efx_nic_check_pcie_link_speed(
197 __in uint32_t pcie_link_width,
198 __in uint32_t pcie_link_gen,
199 __out efx_pcie_link_performance_t *resultp);
203 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
204 /* Huntington and Medford require MCDIv2 commands */
205 #define WITH_MCDI_V2 1
208 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
210 typedef enum efx_mcdi_exception_e {
211 EFX_MCDI_EXCEPTION_MC_REBOOT,
212 EFX_MCDI_EXCEPTION_MC_BADASSERT,
213 } efx_mcdi_exception_t;
215 #if EFSYS_OPT_MCDI_LOGGING
216 typedef enum efx_log_msg_e {
218 EFX_LOG_MCDI_REQUEST,
219 EFX_LOG_MCDI_RESPONSE,
221 #endif /* EFSYS_OPT_MCDI_LOGGING */
223 typedef struct efx_mcdi_transport_s {
225 efsys_mem_t *emt_dma_mem;
226 void (*emt_execute)(void *, efx_mcdi_req_t *);
227 void (*emt_ev_cpl)(void *);
228 void (*emt_exception)(void *, efx_mcdi_exception_t);
229 #if EFSYS_OPT_MCDI_LOGGING
230 void (*emt_logger)(void *, efx_log_msg_t,
231 void *, size_t, void *, size_t);
232 #endif /* EFSYS_OPT_MCDI_LOGGING */
233 #if EFSYS_OPT_MCDI_PROXY_AUTH
234 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
235 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
236 } efx_mcdi_transport_t;
238 extern __checkReturn efx_rc_t
241 __in const efx_mcdi_transport_t *mtp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
249 __in efx_nic_t *enp);
252 efx_mcdi_get_timeout(
254 __in efx_mcdi_req_t *emrp,
255 __out uint32_t *usec_timeoutp);
258 efx_mcdi_request_start(
260 __in efx_mcdi_req_t *emrp,
261 __in boolean_t ev_cpl);
263 extern __checkReturn boolean_t
264 efx_mcdi_request_poll(
265 __in efx_nic_t *enp);
267 extern __checkReturn boolean_t
268 efx_mcdi_request_abort(
269 __in efx_nic_t *enp);
273 __in efx_nic_t *enp);
275 #endif /* EFSYS_OPT_MCDI */
279 #define EFX_NINTR_SIENA 1024
281 typedef enum efx_intr_type_e {
282 EFX_INTR_INVALID = 0,
288 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
290 extern __checkReturn efx_rc_t
293 __in efx_intr_type_t type,
294 __in efsys_mem_t *esmp);
298 __in efx_nic_t *enp);
302 __in efx_nic_t *enp);
305 efx_intr_disable_unlocked(
306 __in efx_nic_t *enp);
308 #define EFX_INTR_NEVQS 32
310 extern __checkReturn efx_rc_t
313 __in unsigned int level);
316 efx_intr_status_line(
318 __out boolean_t *fatalp,
319 __out uint32_t *maskp);
322 efx_intr_status_message(
324 __in unsigned int message,
325 __out boolean_t *fatalp);
329 __in efx_nic_t *enp);
333 __in efx_nic_t *enp);
337 #if EFSYS_OPT_MAC_STATS
339 /* START MKCONFIG GENERATED EfxHeaderMacBlock 7d59c0d68431a5d1 */
340 typedef enum efx_mac_stat_e {
343 EFX_MAC_RX_UNICST_PKTS,
344 EFX_MAC_RX_MULTICST_PKTS,
345 EFX_MAC_RX_BRDCST_PKTS,
346 EFX_MAC_RX_PAUSE_PKTS,
347 EFX_MAC_RX_LE_64_PKTS,
348 EFX_MAC_RX_65_TO_127_PKTS,
349 EFX_MAC_RX_128_TO_255_PKTS,
350 EFX_MAC_RX_256_TO_511_PKTS,
351 EFX_MAC_RX_512_TO_1023_PKTS,
352 EFX_MAC_RX_1024_TO_15XX_PKTS,
353 EFX_MAC_RX_GE_15XX_PKTS,
355 EFX_MAC_RX_FCS_ERRORS,
356 EFX_MAC_RX_DROP_EVENTS,
357 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
358 EFX_MAC_RX_SYMBOL_ERRORS,
359 EFX_MAC_RX_ALIGN_ERRORS,
360 EFX_MAC_RX_INTERNAL_ERRORS,
361 EFX_MAC_RX_JABBER_PKTS,
362 EFX_MAC_RX_LANE0_CHAR_ERR,
363 EFX_MAC_RX_LANE1_CHAR_ERR,
364 EFX_MAC_RX_LANE2_CHAR_ERR,
365 EFX_MAC_RX_LANE3_CHAR_ERR,
366 EFX_MAC_RX_LANE0_DISP_ERR,
367 EFX_MAC_RX_LANE1_DISP_ERR,
368 EFX_MAC_RX_LANE2_DISP_ERR,
369 EFX_MAC_RX_LANE3_DISP_ERR,
370 EFX_MAC_RX_MATCH_FAULT,
371 EFX_MAC_RX_NODESC_DROP_CNT,
374 EFX_MAC_TX_UNICST_PKTS,
375 EFX_MAC_TX_MULTICST_PKTS,
376 EFX_MAC_TX_BRDCST_PKTS,
377 EFX_MAC_TX_PAUSE_PKTS,
378 EFX_MAC_TX_LE_64_PKTS,
379 EFX_MAC_TX_65_TO_127_PKTS,
380 EFX_MAC_TX_128_TO_255_PKTS,
381 EFX_MAC_TX_256_TO_511_PKTS,
382 EFX_MAC_TX_512_TO_1023_PKTS,
383 EFX_MAC_TX_1024_TO_15XX_PKTS,
384 EFX_MAC_TX_GE_15XX_PKTS,
386 EFX_MAC_TX_SGL_COL_PKTS,
387 EFX_MAC_TX_MULT_COL_PKTS,
388 EFX_MAC_TX_EX_COL_PKTS,
389 EFX_MAC_TX_LATE_COL_PKTS,
391 EFX_MAC_TX_EX_DEF_PKTS,
392 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
393 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
394 EFX_MAC_PM_TRUNC_VFIFO_FULL,
395 EFX_MAC_PM_DISCARD_VFIFO_FULL,
396 EFX_MAC_PM_TRUNC_QBB,
397 EFX_MAC_PM_DISCARD_QBB,
398 EFX_MAC_PM_DISCARD_MAPPING,
399 EFX_MAC_RXDP_Q_DISABLED_PKTS,
400 EFX_MAC_RXDP_DI_DROPPED_PKTS,
401 EFX_MAC_RXDP_STREAMING_PKTS,
402 EFX_MAC_RXDP_HLB_FETCH,
403 EFX_MAC_RXDP_HLB_WAIT,
404 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
405 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
406 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
407 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
408 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
409 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
410 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
411 EFX_MAC_VADAPTER_RX_BAD_BYTES,
412 EFX_MAC_VADAPTER_RX_OVERFLOW,
413 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
414 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
415 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
416 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
417 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
418 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
419 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
420 EFX_MAC_VADAPTER_TX_BAD_BYTES,
421 EFX_MAC_VADAPTER_TX_OVERFLOW,
422 EFX_MAC_FEC_UNCORRECTED_ERRORS,
423 EFX_MAC_FEC_CORRECTED_ERRORS,
424 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
425 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
426 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
427 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
428 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
429 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
430 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
431 EFX_MAC_CTPIO_OVERFLOW_FAIL,
432 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
433 EFX_MAC_CTPIO_TIMEOUT_FAIL,
434 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
435 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
436 EFX_MAC_CTPIO_INVALID_WR_FAIL,
437 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
438 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
439 EFX_MAC_CTPIO_RUNT_FALLBACK,
440 EFX_MAC_CTPIO_SUCCESS,
441 EFX_MAC_CTPIO_FALLBACK,
442 EFX_MAC_CTPIO_POISON,
447 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
449 #endif /* EFSYS_OPT_MAC_STATS */
451 typedef enum efx_link_mode_e {
452 EFX_LINK_UNKNOWN = 0,
468 #define EFX_MAC_ADDR_LEN 6
470 #define EFX_VNI_OR_VSID_LEN 3
472 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
474 #define EFX_MAC_MULTICAST_LIST_MAX 256
476 #define EFX_MAC_SDU_MAX 9202
478 #define EFX_MAC_PDU_ADJUSTMENT \
482 + /* bug16011 */ 16) \
484 #define EFX_MAC_PDU(_sdu) \
485 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
488 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
489 * the SDU rounded up slightly.
491 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
493 #define EFX_MAC_PDU_MIN 60
494 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
496 extern __checkReturn efx_rc_t
501 extern __checkReturn efx_rc_t
506 extern __checkReturn efx_rc_t
511 extern __checkReturn efx_rc_t
514 __in boolean_t all_unicst,
515 __in boolean_t mulcst,
516 __in boolean_t all_mulcst,
517 __in boolean_t brdcst);
519 extern __checkReturn efx_rc_t
520 efx_mac_multicast_list_set(
522 __in_ecount(6*count) uint8_t const *addrs,
525 extern __checkReturn efx_rc_t
526 efx_mac_filter_default_rxq_set(
529 __in boolean_t using_rss);
532 efx_mac_filter_default_rxq_clear(
533 __in efx_nic_t *enp);
535 extern __checkReturn efx_rc_t
538 __in boolean_t enabled);
540 extern __checkReturn efx_rc_t
543 __out boolean_t *mac_upp);
545 #define EFX_FCNTL_RESPOND 0x00000001
546 #define EFX_FCNTL_GENERATE 0x00000002
548 extern __checkReturn efx_rc_t
551 __in unsigned int fcntl,
552 __in boolean_t autoneg);
557 __out unsigned int *fcntl_wantedp,
558 __out unsigned int *fcntl_linkp);
561 #if EFSYS_OPT_MAC_STATS
565 extern __checkReturn const char *
568 __in unsigned int id);
570 #endif /* EFSYS_OPT_NAMES */
572 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
574 #define EFX_MAC_STATS_MASK_NPAGES \
575 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
576 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
579 * Get mask of MAC statistics supported by the hardware.
581 * If mask_size is insufficient to return the mask, EINVAL error is
582 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
583 * (which is sizeof (uint32_t)) is sufficient.
585 extern __checkReturn efx_rc_t
586 efx_mac_stats_get_mask(
588 __out_bcount(mask_size) uint32_t *maskp,
589 __in size_t mask_size);
591 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
592 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
593 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
596 extern __checkReturn efx_rc_t
598 __in efx_nic_t *enp);
601 * Upload mac statistics supported by the hardware into the given buffer.
603 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
604 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
606 * The hardware will only DMA statistics that it understands (of course).
607 * Drivers should not make any assumptions about which statistics are
608 * supported, especially when the statistics are generated by firmware.
610 * Thus, drivers should zero this buffer before use, so that not-understood
611 * statistics read back as zero.
613 extern __checkReturn efx_rc_t
614 efx_mac_stats_upload(
616 __in efsys_mem_t *esmp);
618 extern __checkReturn efx_rc_t
619 efx_mac_stats_periodic(
621 __in efsys_mem_t *esmp,
622 __in uint16_t period_ms,
623 __in boolean_t events);
625 extern __checkReturn efx_rc_t
626 efx_mac_stats_update(
628 __in efsys_mem_t *esmp,
629 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
630 __inout_opt uint32_t *generationp);
632 #endif /* EFSYS_OPT_MAC_STATS */
636 typedef enum efx_mon_type_e {
648 __in efx_nic_t *enp);
650 #endif /* EFSYS_OPT_NAMES */
652 extern __checkReturn efx_rc_t
654 __in efx_nic_t *enp);
656 #if EFSYS_OPT_MON_STATS
658 #define EFX_MON_STATS_PAGE_SIZE 0x100
659 #define EFX_MON_MASK_ELEMENT_SIZE 32
661 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
662 typedef enum efx_mon_stat_e {
669 EFX_MON_STAT_EXT_TEMP,
670 EFX_MON_STAT_INT_TEMP,
673 EFX_MON_STAT_INT_COOLING,
674 EFX_MON_STAT_EXT_COOLING,
682 EFX_MON_STAT_AOE_TEMP,
683 EFX_MON_STAT_PSU_AOE_TEMP,
684 EFX_MON_STAT_PSU_TEMP,
690 EFX_MON_STAT_VAOE_IN,
692 EFX_MON_STAT_IAOE_IN,
693 EFX_MON_STAT_NIC_POWER,
697 EFX_MON_STAT_0_9V_ADC,
698 EFX_MON_STAT_INT_TEMP2,
699 EFX_MON_STAT_VREG_TEMP,
700 EFX_MON_STAT_VREG_0_9V_TEMP,
701 EFX_MON_STAT_VREG_1_2V_TEMP,
702 EFX_MON_STAT_INT_VPTAT,
703 EFX_MON_STAT_INT_ADC_TEMP,
704 EFX_MON_STAT_EXT_VPTAT,
705 EFX_MON_STAT_EXT_ADC_TEMP,
706 EFX_MON_STAT_AMBIENT_TEMP,
707 EFX_MON_STAT_AIRFLOW,
708 EFX_MON_STAT_VDD08D_VSS08D_CSR,
709 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
710 EFX_MON_STAT_HOTPOINT_TEMP,
711 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
712 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
713 EFX_MON_STAT_MUM_VCC,
716 EFX_MON_STAT_0V9_A_TEMP,
719 EFX_MON_STAT_0V9_B_TEMP,
720 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
721 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
722 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
723 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
724 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
725 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
726 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
727 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
728 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
729 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
730 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
731 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
732 EFX_MON_STAT_SODIMM_VOUT,
733 EFX_MON_STAT_SODIMM_0_TEMP,
734 EFX_MON_STAT_SODIMM_1_TEMP,
735 EFX_MON_STAT_PHY0_VCC,
736 EFX_MON_STAT_PHY1_VCC,
737 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
738 EFX_MON_STAT_BOARD_FRONT_TEMP,
739 EFX_MON_STAT_BOARD_BACK_TEMP,
749 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
751 typedef enum efx_mon_stat_state_e {
752 EFX_MON_STAT_STATE_OK = 0,
753 EFX_MON_STAT_STATE_WARNING = 1,
754 EFX_MON_STAT_STATE_FATAL = 2,
755 EFX_MON_STAT_STATE_BROKEN = 3,
756 EFX_MON_STAT_STATE_NO_READING = 4,
757 } efx_mon_stat_state_t;
759 typedef struct efx_mon_stat_value_s {
762 } efx_mon_stat_value_t;
769 __in efx_mon_stat_t id);
771 #endif /* EFSYS_OPT_NAMES */
773 extern __checkReturn efx_rc_t
774 efx_mon_stats_update(
776 __in efsys_mem_t *esmp,
777 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
779 #endif /* EFSYS_OPT_MON_STATS */
783 __in efx_nic_t *enp);
787 extern __checkReturn efx_rc_t
789 __in efx_nic_t *enp);
791 #if EFSYS_OPT_PHY_LED_CONTROL
793 typedef enum efx_phy_led_mode_e {
794 EFX_PHY_LED_DEFAULT = 0,
799 } efx_phy_led_mode_t;
801 extern __checkReturn efx_rc_t
804 __in efx_phy_led_mode_t mode);
806 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
808 extern __checkReturn efx_rc_t
810 __in efx_nic_t *enp);
812 #if EFSYS_OPT_LOOPBACK
814 typedef enum efx_loopback_type_e {
815 EFX_LOOPBACK_OFF = 0,
816 EFX_LOOPBACK_DATA = 1,
817 EFX_LOOPBACK_GMAC = 2,
818 EFX_LOOPBACK_XGMII = 3,
819 EFX_LOOPBACK_XGXS = 4,
820 EFX_LOOPBACK_XAUI = 5,
821 EFX_LOOPBACK_GMII = 6,
822 EFX_LOOPBACK_SGMII = 7,
823 EFX_LOOPBACK_XGBR = 8,
824 EFX_LOOPBACK_XFI = 9,
825 EFX_LOOPBACK_XAUI_FAR = 10,
826 EFX_LOOPBACK_GMII_FAR = 11,
827 EFX_LOOPBACK_SGMII_FAR = 12,
828 EFX_LOOPBACK_XFI_FAR = 13,
829 EFX_LOOPBACK_GPHY = 14,
830 EFX_LOOPBACK_PHY_XS = 15,
831 EFX_LOOPBACK_PCS = 16,
832 EFX_LOOPBACK_PMA_PMD = 17,
833 EFX_LOOPBACK_XPORT = 18,
834 EFX_LOOPBACK_XGMII_WS = 19,
835 EFX_LOOPBACK_XAUI_WS = 20,
836 EFX_LOOPBACK_XAUI_WS_FAR = 21,
837 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
838 EFX_LOOPBACK_GMII_WS = 23,
839 EFX_LOOPBACK_XFI_WS = 24,
840 EFX_LOOPBACK_XFI_WS_FAR = 25,
841 EFX_LOOPBACK_PHYXS_WS = 26,
842 EFX_LOOPBACK_PMA_INT = 27,
843 EFX_LOOPBACK_SD_NEAR = 28,
844 EFX_LOOPBACK_SD_FAR = 29,
845 EFX_LOOPBACK_PMA_INT_WS = 30,
846 EFX_LOOPBACK_SD_FEP2_WS = 31,
847 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
848 EFX_LOOPBACK_SD_FEP_WS = 33,
849 EFX_LOOPBACK_SD_FES_WS = 34,
850 EFX_LOOPBACK_AOE_INT_NEAR = 35,
851 EFX_LOOPBACK_DATA_WS = 36,
852 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
854 } efx_loopback_type_t;
856 typedef enum efx_loopback_kind_e {
857 EFX_LOOPBACK_KIND_OFF = 0,
858 EFX_LOOPBACK_KIND_ALL,
859 EFX_LOOPBACK_KIND_MAC,
860 EFX_LOOPBACK_KIND_PHY,
862 } efx_loopback_kind_t;
866 __in efx_loopback_kind_t loopback_kind,
867 __out efx_qword_t *maskp);
869 extern __checkReturn efx_rc_t
870 efx_port_loopback_set(
872 __in efx_link_mode_t link_mode,
873 __in efx_loopback_type_t type);
877 extern __checkReturn const char *
878 efx_loopback_type_name(
880 __in efx_loopback_type_t type);
882 #endif /* EFSYS_OPT_NAMES */
884 #endif /* EFSYS_OPT_LOOPBACK */
886 extern __checkReturn efx_rc_t
889 __out_opt efx_link_mode_t *link_modep);
893 __in efx_nic_t *enp);
895 typedef enum efx_phy_cap_type_e {
896 EFX_PHY_CAP_INVALID = 0,
903 EFX_PHY_CAP_10000FDX,
907 EFX_PHY_CAP_40000FDX,
909 EFX_PHY_CAP_100000FDX,
910 EFX_PHY_CAP_25000FDX,
911 EFX_PHY_CAP_50000FDX,
912 EFX_PHY_CAP_BASER_FEC,
913 EFX_PHY_CAP_BASER_FEC_REQUESTED,
915 EFX_PHY_CAP_RS_FEC_REQUESTED,
916 EFX_PHY_CAP_25G_BASER_FEC,
917 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
919 } efx_phy_cap_type_t;
922 #define EFX_PHY_CAP_CURRENT 0x00000000
923 #define EFX_PHY_CAP_DEFAULT 0x00000001
924 #define EFX_PHY_CAP_PERM 0x00000002
930 __out uint32_t *maskp);
932 extern __checkReturn efx_rc_t
940 __out uint32_t *maskp);
942 extern __checkReturn efx_rc_t
945 __out uint32_t *ouip);
947 typedef enum efx_phy_media_type_e {
948 EFX_PHY_MEDIA_INVALID = 0,
953 EFX_PHY_MEDIA_SFP_PLUS,
954 EFX_PHY_MEDIA_BASE_T,
955 EFX_PHY_MEDIA_QSFP_PLUS,
957 } efx_phy_media_type_t;
960 * Get the type of medium currently used. If the board has ports for
961 * modules, a module is present, and we recognise the media type of
962 * the module, then this will be the media type of the module.
963 * Otherwise it will be the media type of the port.
966 efx_phy_media_type_get(
968 __out efx_phy_media_type_t *typep);
970 extern __checkReturn efx_rc_t
971 efx_phy_module_get_info(
973 __in uint8_t dev_addr,
976 __out_bcount(len) uint8_t *data);
978 #if EFSYS_OPT_PHY_STATS
980 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
981 typedef enum efx_phy_stat_e {
983 EFX_PHY_STAT_PMA_PMD_LINK_UP,
984 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
985 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
986 EFX_PHY_STAT_PMA_PMD_REV_A,
987 EFX_PHY_STAT_PMA_PMD_REV_B,
988 EFX_PHY_STAT_PMA_PMD_REV_C,
989 EFX_PHY_STAT_PMA_PMD_REV_D,
990 EFX_PHY_STAT_PCS_LINK_UP,
991 EFX_PHY_STAT_PCS_RX_FAULT,
992 EFX_PHY_STAT_PCS_TX_FAULT,
993 EFX_PHY_STAT_PCS_BER,
994 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
995 EFX_PHY_STAT_PHY_XS_LINK_UP,
996 EFX_PHY_STAT_PHY_XS_RX_FAULT,
997 EFX_PHY_STAT_PHY_XS_TX_FAULT,
998 EFX_PHY_STAT_PHY_XS_ALIGN,
999 EFX_PHY_STAT_PHY_XS_SYNC_A,
1000 EFX_PHY_STAT_PHY_XS_SYNC_B,
1001 EFX_PHY_STAT_PHY_XS_SYNC_C,
1002 EFX_PHY_STAT_PHY_XS_SYNC_D,
1003 EFX_PHY_STAT_AN_LINK_UP,
1004 EFX_PHY_STAT_AN_MASTER,
1005 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1006 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1007 EFX_PHY_STAT_CL22EXT_LINK_UP,
1012 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1013 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1014 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1015 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1016 EFX_PHY_STAT_AN_COMPLETE,
1017 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1018 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1019 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1020 EFX_PHY_STAT_PCS_FW_VERSION_0,
1021 EFX_PHY_STAT_PCS_FW_VERSION_1,
1022 EFX_PHY_STAT_PCS_FW_VERSION_2,
1023 EFX_PHY_STAT_PCS_FW_VERSION_3,
1024 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1025 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1026 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1027 EFX_PHY_STAT_PCS_OP_MODE,
1031 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1037 __in efx_nic_t *enp,
1038 __in efx_phy_stat_t stat);
1040 #endif /* EFSYS_OPT_NAMES */
1042 #define EFX_PHY_STATS_SIZE 0x100
1044 extern __checkReturn efx_rc_t
1045 efx_phy_stats_update(
1046 __in efx_nic_t *enp,
1047 __in efsys_mem_t *esmp,
1048 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1050 #endif /* EFSYS_OPT_PHY_STATS */
1055 typedef enum efx_bist_type_e {
1056 EFX_BIST_TYPE_UNKNOWN,
1057 EFX_BIST_TYPE_PHY_NORMAL,
1058 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1059 EFX_BIST_TYPE_PHY_CABLE_LONG,
1060 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1061 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1062 EFX_BIST_TYPE_REG, /* Test the register memories */
1063 EFX_BIST_TYPE_NTYPES,
1066 typedef enum efx_bist_result_e {
1067 EFX_BIST_RESULT_UNKNOWN,
1068 EFX_BIST_RESULT_RUNNING,
1069 EFX_BIST_RESULT_PASSED,
1070 EFX_BIST_RESULT_FAILED,
1071 } efx_bist_result_t;
1073 typedef enum efx_phy_cable_status_e {
1074 EFX_PHY_CABLE_STATUS_OK,
1075 EFX_PHY_CABLE_STATUS_INVALID,
1076 EFX_PHY_CABLE_STATUS_OPEN,
1077 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1078 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1079 EFX_PHY_CABLE_STATUS_BUSY,
1080 } efx_phy_cable_status_t;
1082 typedef enum efx_bist_value_e {
1083 EFX_BIST_PHY_CABLE_LENGTH_A,
1084 EFX_BIST_PHY_CABLE_LENGTH_B,
1085 EFX_BIST_PHY_CABLE_LENGTH_C,
1086 EFX_BIST_PHY_CABLE_LENGTH_D,
1087 EFX_BIST_PHY_CABLE_STATUS_A,
1088 EFX_BIST_PHY_CABLE_STATUS_B,
1089 EFX_BIST_PHY_CABLE_STATUS_C,
1090 EFX_BIST_PHY_CABLE_STATUS_D,
1091 EFX_BIST_FAULT_CODE,
1093 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1099 EFX_BIST_MEM_EXPECT,
1100 EFX_BIST_MEM_ACTUAL,
1102 EFX_BIST_MEM_ECC_PARITY,
1103 EFX_BIST_MEM_ECC_FATAL,
1107 extern __checkReturn efx_rc_t
1108 efx_bist_enable_offline(
1109 __in efx_nic_t *enp);
1111 extern __checkReturn efx_rc_t
1113 __in efx_nic_t *enp,
1114 __in efx_bist_type_t type);
1116 extern __checkReturn efx_rc_t
1118 __in efx_nic_t *enp,
1119 __in efx_bist_type_t type,
1120 __out efx_bist_result_t *resultp,
1121 __out_opt uint32_t *value_maskp,
1122 __out_ecount_opt(count) unsigned long *valuesp,
1127 __in efx_nic_t *enp,
1128 __in efx_bist_type_t type);
1130 #endif /* EFSYS_OPT_BIST */
1132 #define EFX_FEATURE_IPV6 0x00000001
1133 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1134 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1135 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1136 #define EFX_FEATURE_MCDI 0x00000020
1137 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1138 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1139 #define EFX_FEATURE_TURBO 0x00000100
1140 #define EFX_FEATURE_MCDI_DMA 0x00000200
1141 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1142 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1143 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1144 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1145 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1147 typedef enum efx_tunnel_protocol_e {
1148 EFX_TUNNEL_PROTOCOL_NONE = 0,
1149 EFX_TUNNEL_PROTOCOL_VXLAN,
1150 EFX_TUNNEL_PROTOCOL_GENEVE,
1151 EFX_TUNNEL_PROTOCOL_NVGRE,
1153 } efx_tunnel_protocol_t;
1155 typedef enum efx_vi_window_shift_e {
1156 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1157 EFX_VI_WINDOW_SHIFT_8K = 13,
1158 EFX_VI_WINDOW_SHIFT_16K = 14,
1159 EFX_VI_WINDOW_SHIFT_64K = 16,
1160 } efx_vi_window_shift_t;
1162 typedef struct efx_nic_cfg_s {
1163 uint32_t enc_board_type;
1164 uint32_t enc_phy_type;
1166 char enc_phy_name[21];
1168 char enc_phy_revision[21];
1169 efx_mon_type_t enc_mon_type;
1170 #if EFSYS_OPT_MON_STATS
1171 uint32_t enc_mon_stat_dma_buf_size;
1172 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1174 unsigned int enc_features;
1175 efx_vi_window_shift_t enc_vi_window_shift;
1176 uint8_t enc_mac_addr[6];
1177 uint8_t enc_port; /* PHY port number */
1178 uint32_t enc_intr_vec_base;
1179 uint32_t enc_intr_limit;
1180 uint32_t enc_evq_limit;
1181 uint32_t enc_txq_limit;
1182 uint32_t enc_rxq_limit;
1183 uint32_t enc_txq_max_ndescs;
1184 uint32_t enc_buftbl_limit;
1185 uint32_t enc_piobuf_limit;
1186 uint32_t enc_piobuf_size;
1187 uint32_t enc_piobuf_min_alloc_size;
1188 uint32_t enc_evq_timer_quantum_ns;
1189 uint32_t enc_evq_timer_max_us;
1190 uint32_t enc_clk_mult;
1191 uint32_t enc_rx_prefix_size;
1192 uint32_t enc_rx_buf_align_start;
1193 uint32_t enc_rx_buf_align_end;
1194 uint32_t enc_rx_scale_max_exclusive_contexts;
1195 #if EFSYS_OPT_LOOPBACK
1196 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1197 #endif /* EFSYS_OPT_LOOPBACK */
1198 #if EFSYS_OPT_PHY_FLAGS
1199 uint32_t enc_phy_flags_mask;
1200 #endif /* EFSYS_OPT_PHY_FLAGS */
1201 #if EFSYS_OPT_PHY_LED_CONTROL
1202 uint32_t enc_led_mask;
1203 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1204 #if EFSYS_OPT_PHY_STATS
1205 uint64_t enc_phy_stat_mask;
1206 #endif /* EFSYS_OPT_PHY_STATS */
1208 uint8_t enc_mcdi_mdio_channel;
1209 #if EFSYS_OPT_PHY_STATS
1210 uint32_t enc_mcdi_phy_stat_mask;
1211 #endif /* EFSYS_OPT_PHY_STATS */
1212 #if EFSYS_OPT_MON_STATS
1213 uint32_t *enc_mcdi_sensor_maskp;
1214 uint32_t enc_mcdi_sensor_mask_size;
1215 #endif /* EFSYS_OPT_MON_STATS */
1216 #endif /* EFSYS_OPT_MCDI */
1218 uint32_t enc_bist_mask;
1219 #endif /* EFSYS_OPT_BIST */
1220 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1223 uint32_t enc_privilege_mask;
1224 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1225 boolean_t enc_bug26807_workaround;
1226 boolean_t enc_bug35388_workaround;
1227 boolean_t enc_bug41750_workaround;
1228 boolean_t enc_bug61265_workaround;
1229 boolean_t enc_rx_batching_enabled;
1230 /* Maximum number of descriptors completed in an rx event. */
1231 uint32_t enc_rx_batch_max;
1232 /* Number of rx descriptors the hardware requires for a push. */
1233 uint32_t enc_rx_push_align;
1234 /* Maximum amount of data in DMA descriptor */
1235 uint32_t enc_tx_dma_desc_size_max;
1237 * Boundary which DMA descriptor data must not cross or 0 if no
1240 uint32_t enc_tx_dma_desc_boundary;
1242 * Maximum number of bytes into the packet the TCP header can start for
1243 * the hardware to apply TSO packet edits.
1245 uint32_t enc_tx_tso_tcp_header_offset_limit;
1246 boolean_t enc_fw_assisted_tso_enabled;
1247 boolean_t enc_fw_assisted_tso_v2_enabled;
1248 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1249 /* Number of TSO contexts on the NIC (FATSOv2) */
1250 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1251 boolean_t enc_hw_tx_insert_vlan_enabled;
1252 /* Number of PFs on the NIC */
1253 uint32_t enc_hw_pf_count;
1254 /* Datapath firmware vadapter/vport/vswitch support */
1255 boolean_t enc_datapath_cap_evb;
1256 boolean_t enc_rx_disable_scatter_supported;
1257 boolean_t enc_allow_set_mac_with_installed_filters;
1258 boolean_t enc_enhanced_set_mac_supported;
1259 boolean_t enc_init_evq_v2_supported;
1260 boolean_t enc_rx_packed_stream_supported;
1261 boolean_t enc_rx_var_packed_stream_supported;
1262 boolean_t enc_pm_and_rxdp_counters;
1263 boolean_t enc_mac_stats_40g_tx_size_bins;
1264 uint32_t enc_tunnel_encapsulations_supported;
1266 * NIC global maximum for unique UDP tunnel ports shared by all
1269 uint32_t enc_tunnel_config_udp_entries_max;
1270 /* External port identifier */
1271 uint8_t enc_external_port;
1272 uint32_t enc_mcdi_max_payload_length;
1273 /* VPD may be per-PF or global */
1274 boolean_t enc_vpd_is_global;
1275 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1276 uint32_t enc_required_pcie_bandwidth_mbps;
1277 uint32_t enc_max_pcie_link_gen;
1278 /* Firmware verifies integrity of NVRAM updates */
1279 uint32_t enc_nvram_update_verify_result_supported;
1280 /* Firmware support for extended MAC_STATS buffer */
1281 uint32_t enc_mac_stats_nstats;
1282 boolean_t enc_fec_counters;
1285 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1286 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1288 #define EFX_PCI_FUNCTION(_encp) \
1289 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1291 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1293 extern const efx_nic_cfg_t *
1295 __in efx_nic_t *enp);
1297 /* RxDPCPU firmware id values by which FW variant can be identified */
1298 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1299 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1300 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1301 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1302 #define EFX_RXDP_DPDK_FW_ID 0x6
1304 typedef struct efx_nic_fw_info_s {
1305 /* Basic FW version information */
1306 uint16_t enfi_mc_fw_version[4];
1308 * If datapath capabilities can be detected,
1309 * additional FW information is to be shown
1311 boolean_t enfi_dpcpu_fw_ids_valid;
1312 /* Rx and Tx datapath CPU FW IDs */
1313 uint16_t enfi_rx_dpcpu_fw_id;
1314 uint16_t enfi_tx_dpcpu_fw_id;
1315 } efx_nic_fw_info_t;
1317 extern __checkReturn efx_rc_t
1318 efx_nic_get_fw_version(
1319 __in efx_nic_t *enp,
1320 __out efx_nic_fw_info_t *enfip);
1322 /* Driver resource limits (minimum required/maximum usable). */
1323 typedef struct efx_drv_limits_s {
1324 uint32_t edl_min_evq_count;
1325 uint32_t edl_max_evq_count;
1327 uint32_t edl_min_rxq_count;
1328 uint32_t edl_max_rxq_count;
1330 uint32_t edl_min_txq_count;
1331 uint32_t edl_max_txq_count;
1333 /* PIO blocks (sub-allocated from piobuf) */
1334 uint32_t edl_min_pio_alloc_size;
1335 uint32_t edl_max_pio_alloc_count;
1338 extern __checkReturn efx_rc_t
1339 efx_nic_set_drv_limits(
1340 __inout efx_nic_t *enp,
1341 __in efx_drv_limits_t *edlp);
1343 typedef enum efx_nic_region_e {
1344 EFX_REGION_VI, /* Memory BAR UC mapping */
1345 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1348 extern __checkReturn efx_rc_t
1349 efx_nic_get_bar_region(
1350 __in efx_nic_t *enp,
1351 __in efx_nic_region_t region,
1352 __out uint32_t *offsetp,
1353 __out size_t *sizep);
1355 extern __checkReturn efx_rc_t
1356 efx_nic_get_vi_pool(
1357 __in efx_nic_t *enp,
1358 __out uint32_t *evq_countp,
1359 __out uint32_t *rxq_countp,
1360 __out uint32_t *txq_countp);
1365 typedef enum efx_vpd_tag_e {
1372 typedef uint16_t efx_vpd_keyword_t;
1374 typedef struct efx_vpd_value_s {
1375 efx_vpd_tag_t evv_tag;
1376 efx_vpd_keyword_t evv_keyword;
1378 uint8_t evv_value[0x100];
1382 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1384 extern __checkReturn efx_rc_t
1386 __in efx_nic_t *enp);
1388 extern __checkReturn efx_rc_t
1390 __in efx_nic_t *enp,
1391 __out size_t *sizep);
1393 extern __checkReturn efx_rc_t
1395 __in efx_nic_t *enp,
1396 __out_bcount(size) caddr_t data,
1399 extern __checkReturn efx_rc_t
1401 __in efx_nic_t *enp,
1402 __in_bcount(size) caddr_t data,
1405 extern __checkReturn efx_rc_t
1407 __in efx_nic_t *enp,
1408 __in_bcount(size) caddr_t data,
1411 extern __checkReturn efx_rc_t
1413 __in efx_nic_t *enp,
1414 __in_bcount(size) caddr_t data,
1416 __inout efx_vpd_value_t *evvp);
1418 extern __checkReturn efx_rc_t
1420 __in efx_nic_t *enp,
1421 __inout_bcount(size) caddr_t data,
1423 __in efx_vpd_value_t *evvp);
1425 extern __checkReturn efx_rc_t
1427 __in efx_nic_t *enp,
1428 __inout_bcount(size) caddr_t data,
1430 __out efx_vpd_value_t *evvp,
1431 __inout unsigned int *contp);
1433 extern __checkReturn efx_rc_t
1435 __in efx_nic_t *enp,
1436 __in_bcount(size) caddr_t data,
1441 __in efx_nic_t *enp);
1443 #endif /* EFSYS_OPT_VPD */
1449 typedef enum efx_nvram_type_e {
1450 EFX_NVRAM_INVALID = 0,
1452 EFX_NVRAM_BOOTROM_CFG,
1453 EFX_NVRAM_MC_FIRMWARE,
1454 EFX_NVRAM_MC_GOLDEN,
1460 EFX_NVRAM_FPGA_BACKUP,
1461 EFX_NVRAM_DYNAMIC_CFG,
1464 EFX_NVRAM_MUM_FIRMWARE,
1468 extern __checkReturn efx_rc_t
1470 __in efx_nic_t *enp);
1474 extern __checkReturn efx_rc_t
1476 __in efx_nic_t *enp);
1478 #endif /* EFSYS_OPT_DIAG */
1480 extern __checkReturn efx_rc_t
1482 __in efx_nic_t *enp,
1483 __in efx_nvram_type_t type,
1484 __out size_t *sizep);
1486 extern __checkReturn efx_rc_t
1488 __in efx_nic_t *enp,
1489 __in efx_nvram_type_t type,
1490 __out_opt size_t *pref_chunkp);
1492 extern __checkReturn efx_rc_t
1493 efx_nvram_rw_finish(
1494 __in efx_nic_t *enp,
1495 __in efx_nvram_type_t type,
1496 __out_opt uint32_t *verify_resultp);
1498 extern __checkReturn efx_rc_t
1499 efx_nvram_get_version(
1500 __in efx_nic_t *enp,
1501 __in efx_nvram_type_t type,
1502 __out uint32_t *subtypep,
1503 __out_ecount(4) uint16_t version[4]);
1505 extern __checkReturn efx_rc_t
1506 efx_nvram_read_chunk(
1507 __in efx_nic_t *enp,
1508 __in efx_nvram_type_t type,
1509 __in unsigned int offset,
1510 __out_bcount(size) caddr_t data,
1513 extern __checkReturn efx_rc_t
1514 efx_nvram_read_backup(
1515 __in efx_nic_t *enp,
1516 __in efx_nvram_type_t type,
1517 __in unsigned int offset,
1518 __out_bcount(size) caddr_t data,
1521 extern __checkReturn efx_rc_t
1522 efx_nvram_set_version(
1523 __in efx_nic_t *enp,
1524 __in efx_nvram_type_t type,
1525 __in_ecount(4) uint16_t version[4]);
1527 extern __checkReturn efx_rc_t
1529 __in efx_nic_t *enp,
1530 __in efx_nvram_type_t type,
1531 __in_bcount(partn_size) caddr_t partn_data,
1532 __in size_t partn_size);
1534 extern __checkReturn efx_rc_t
1536 __in efx_nic_t *enp,
1537 __in efx_nvram_type_t type);
1539 extern __checkReturn efx_rc_t
1540 efx_nvram_write_chunk(
1541 __in efx_nic_t *enp,
1542 __in efx_nvram_type_t type,
1543 __in unsigned int offset,
1544 __in_bcount(size) caddr_t data,
1549 __in efx_nic_t *enp);
1551 #endif /* EFSYS_OPT_NVRAM */
1553 #if EFSYS_OPT_BOOTCFG
1555 /* Report size and offset of bootcfg sector in NVRAM partition. */
1556 extern __checkReturn efx_rc_t
1557 efx_bootcfg_sector_info(
1558 __in efx_nic_t *enp,
1560 __out_opt uint32_t *sector_countp,
1561 __out size_t *offsetp,
1562 __out size_t *max_sizep);
1565 * Copy bootcfg sector data to a target buffer which may differ in size.
1566 * Optionally corrects format errors in source buffer.
1569 efx_bootcfg_copy_sector(
1570 __in efx_nic_t *enp,
1571 __inout_bcount(sector_length)
1573 __in size_t sector_length,
1574 __out_bcount(data_size) uint8_t *data,
1575 __in size_t data_size,
1576 __in boolean_t handle_format_errors);
1580 __in efx_nic_t *enp,
1581 __out_bcount(size) uint8_t *data,
1586 __in efx_nic_t *enp,
1587 __in_bcount(size) uint8_t *data,
1590 #endif /* EFSYS_OPT_BOOTCFG */
1592 #if EFSYS_OPT_IMAGE_LAYOUT
1594 #include "ef10_signed_image_layout.h"
1597 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1600 * The image header format is extensible. However, older drivers require an
1601 * exact match of image header version and header length when validating and
1602 * writing firmware images.
1604 * To avoid breaking backward compatibility, we use the upper bits of the
1605 * controller version fields to contain an extra version number used for
1606 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1607 * version). See bug39254 and SF-102785-PS for details.
1609 typedef struct efx_image_header_s {
1611 uint32_t eih_version;
1613 uint32_t eih_subtype;
1614 uint32_t eih_code_size;
1617 uint32_t eih_controller_version_min;
1619 uint16_t eih_controller_version_min_short;
1620 uint8_t eih_extra_version_a;
1621 uint8_t eih_extra_version_b;
1625 uint32_t eih_controller_version_max;
1627 uint16_t eih_controller_version_max_short;
1628 uint8_t eih_extra_version_c;
1629 uint8_t eih_extra_version_d;
1632 uint16_t eih_code_version_a;
1633 uint16_t eih_code_version_b;
1634 uint16_t eih_code_version_c;
1635 uint16_t eih_code_version_d;
1636 } efx_image_header_t;
1638 #define EFX_IMAGE_HEADER_SIZE (40)
1639 #define EFX_IMAGE_HEADER_VERSION (4)
1640 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1643 typedef struct efx_image_trailer_s {
1645 } efx_image_trailer_t;
1647 #define EFX_IMAGE_TRAILER_SIZE (4)
1649 typedef enum efx_image_format_e {
1650 EFX_IMAGE_FORMAT_NO_IMAGE,
1651 EFX_IMAGE_FORMAT_INVALID,
1652 EFX_IMAGE_FORMAT_UNSIGNED,
1653 EFX_IMAGE_FORMAT_SIGNED,
1654 } efx_image_format_t;
1656 typedef struct efx_image_info_s {
1657 efx_image_format_t eii_format;
1658 uint8_t * eii_imagep;
1659 size_t eii_image_size;
1660 efx_image_header_t * eii_headerp;
1663 extern __checkReturn efx_rc_t
1664 efx_check_reflash_image(
1666 __in uint32_t buffer_size,
1667 __out efx_image_info_t *infop);
1669 extern __checkReturn efx_rc_t
1670 efx_build_signed_image_write_buffer(
1671 __out uint8_t *bufferp,
1672 __in uint32_t buffer_size,
1673 __in efx_image_info_t *infop,
1674 __out efx_image_header_t **headerpp);
1676 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1680 typedef enum efx_pattern_type_t {
1681 EFX_PATTERN_BYTE_INCREMENT = 0,
1682 EFX_PATTERN_ALL_THE_SAME,
1683 EFX_PATTERN_BIT_ALTERNATE,
1684 EFX_PATTERN_BYTE_ALTERNATE,
1685 EFX_PATTERN_BYTE_CHANGING,
1686 EFX_PATTERN_BIT_SWEEP,
1688 } efx_pattern_type_t;
1691 (*efx_sram_pattern_fn_t)(
1693 __in boolean_t negate,
1694 __out efx_qword_t *eqp);
1696 extern __checkReturn efx_rc_t
1698 __in efx_nic_t *enp,
1699 __in efx_pattern_type_t type);
1701 #endif /* EFSYS_OPT_DIAG */
1703 extern __checkReturn efx_rc_t
1704 efx_sram_buf_tbl_set(
1705 __in efx_nic_t *enp,
1707 __in efsys_mem_t *esmp,
1711 efx_sram_buf_tbl_clear(
1712 __in efx_nic_t *enp,
1716 #define EFX_BUF_TBL_SIZE 0x20000
1718 #define EFX_BUF_SIZE 4096
1722 typedef struct efx_evq_s efx_evq_t;
1724 #if EFSYS_OPT_QSTATS
1726 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1727 typedef enum efx_ev_qstat_e {
1733 EV_RX_PAUSE_FRM_ERR,
1734 EV_RX_BUF_OWNER_ID_ERR,
1735 EV_RX_IPV4_HDR_CHKSUM_ERR,
1736 EV_RX_TCP_UDP_CHKSUM_ERR,
1740 EV_RX_MCAST_HASH_MATCH,
1757 EV_DRIVER_SRM_UPD_DONE,
1758 EV_DRIVER_TX_DESCQ_FLS_DONE,
1759 EV_DRIVER_RX_DESCQ_FLS_DONE,
1760 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1761 EV_DRIVER_RX_DSC_ERROR,
1762 EV_DRIVER_TX_DSC_ERROR,
1768 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1770 #endif /* EFSYS_OPT_QSTATS */
1772 extern __checkReturn efx_rc_t
1774 __in efx_nic_t *enp);
1778 __in efx_nic_t *enp);
1780 #define EFX_EVQ_MAXNEVS 32768
1781 #define EFX_EVQ_MINNEVS 512
1783 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1784 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1786 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1787 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1788 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1789 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1791 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1792 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1793 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1795 extern __checkReturn efx_rc_t
1797 __in efx_nic_t *enp,
1798 __in unsigned int index,
1799 __in efsys_mem_t *esmp,
1803 __in uint32_t flags,
1804 __deref_out efx_evq_t **eepp);
1808 __in efx_evq_t *eep,
1809 __in uint16_t data);
1811 typedef __checkReturn boolean_t
1812 (*efx_initialized_ev_t)(
1813 __in_opt void *arg);
1815 #define EFX_PKT_UNICAST 0x0004
1816 #define EFX_PKT_START 0x0008
1818 #define EFX_PKT_VLAN_TAGGED 0x0010
1819 #define EFX_CKSUM_TCPUDP 0x0020
1820 #define EFX_CKSUM_IPV4 0x0040
1821 #define EFX_PKT_CONT 0x0080
1823 #define EFX_CHECK_VLAN 0x0100
1824 #define EFX_PKT_TCP 0x0200
1825 #define EFX_PKT_UDP 0x0400
1826 #define EFX_PKT_IPV4 0x0800
1828 #define EFX_PKT_IPV6 0x1000
1829 #define EFX_PKT_PREFIX_LEN 0x2000
1830 #define EFX_ADDR_MISMATCH 0x4000
1831 #define EFX_DISCARD 0x8000
1834 * The following flags are used only for packed stream
1835 * mode. The values for the flags are reused to fit into 16 bit,
1836 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1837 * packed stream mode
1839 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1840 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1843 #define EFX_EV_RX_NLABELS 32
1844 #define EFX_EV_TX_NLABELS 32
1846 typedef __checkReturn boolean_t
1849 __in uint32_t label,
1852 __in uint16_t flags);
1854 #if EFSYS_OPT_RX_PACKED_STREAM
1857 * Packed stream mode is documented in SF-112241-TC.
1858 * The general idea is that, instead of putting each incoming
1859 * packet into a separate buffer which is specified in a RX
1860 * descriptor, a large buffer is provided to the hardware and
1861 * packets are put there in a continuous stream.
1862 * The main advantage of such an approach is that RX queue refilling
1863 * happens much less frequently.
1866 typedef __checkReturn boolean_t
1869 __in uint32_t label,
1871 __in uint32_t pkt_count,
1872 __in uint16_t flags);
1876 typedef __checkReturn boolean_t
1879 __in uint32_t label,
1882 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1883 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1884 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1885 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1886 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1887 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1888 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1889 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1890 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1892 typedef __checkReturn boolean_t
1893 (*efx_exception_ev_t)(
1895 __in uint32_t label,
1896 __in uint32_t data);
1898 typedef __checkReturn boolean_t
1899 (*efx_rxq_flush_done_ev_t)(
1901 __in uint32_t rxq_index);
1903 typedef __checkReturn boolean_t
1904 (*efx_rxq_flush_failed_ev_t)(
1906 __in uint32_t rxq_index);
1908 typedef __checkReturn boolean_t
1909 (*efx_txq_flush_done_ev_t)(
1911 __in uint32_t txq_index);
1913 typedef __checkReturn boolean_t
1914 (*efx_software_ev_t)(
1916 __in uint16_t magic);
1918 typedef __checkReturn boolean_t
1921 __in uint32_t code);
1923 #define EFX_SRAM_CLEAR 0
1924 #define EFX_SRAM_UPDATE 1
1925 #define EFX_SRAM_ILLEGAL_CLEAR 2
1927 typedef __checkReturn boolean_t
1928 (*efx_wake_up_ev_t)(
1930 __in uint32_t label);
1932 typedef __checkReturn boolean_t
1935 __in uint32_t label);
1937 typedef __checkReturn boolean_t
1938 (*efx_link_change_ev_t)(
1940 __in efx_link_mode_t link_mode);
1942 #if EFSYS_OPT_MON_STATS
1944 typedef __checkReturn boolean_t
1945 (*efx_monitor_ev_t)(
1947 __in efx_mon_stat_t id,
1948 __in efx_mon_stat_value_t value);
1950 #endif /* EFSYS_OPT_MON_STATS */
1952 #if EFSYS_OPT_MAC_STATS
1954 typedef __checkReturn boolean_t
1955 (*efx_mac_stats_ev_t)(
1957 __in uint32_t generation);
1959 #endif /* EFSYS_OPT_MAC_STATS */
1961 typedef struct efx_ev_callbacks_s {
1962 efx_initialized_ev_t eec_initialized;
1964 #if EFSYS_OPT_RX_PACKED_STREAM
1965 efx_rx_ps_ev_t eec_rx_ps;
1968 efx_exception_ev_t eec_exception;
1969 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1970 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1971 efx_txq_flush_done_ev_t eec_txq_flush_done;
1972 efx_software_ev_t eec_software;
1973 efx_sram_ev_t eec_sram;
1974 efx_wake_up_ev_t eec_wake_up;
1975 efx_timer_ev_t eec_timer;
1976 efx_link_change_ev_t eec_link_change;
1977 #if EFSYS_OPT_MON_STATS
1978 efx_monitor_ev_t eec_monitor;
1979 #endif /* EFSYS_OPT_MON_STATS */
1980 #if EFSYS_OPT_MAC_STATS
1981 efx_mac_stats_ev_t eec_mac_stats;
1982 #endif /* EFSYS_OPT_MAC_STATS */
1983 } efx_ev_callbacks_t;
1985 extern __checkReturn boolean_t
1987 __in efx_evq_t *eep,
1988 __in unsigned int count);
1990 #if EFSYS_OPT_EV_PREFETCH
1994 __in efx_evq_t *eep,
1995 __in unsigned int count);
1997 #endif /* EFSYS_OPT_EV_PREFETCH */
2001 __in efx_evq_t *eep,
2002 __inout unsigned int *countp,
2003 __in const efx_ev_callbacks_t *eecp,
2004 __in_opt void *arg);
2006 extern __checkReturn efx_rc_t
2007 efx_ev_usecs_to_ticks(
2008 __in efx_nic_t *enp,
2009 __in unsigned int usecs,
2010 __out unsigned int *ticksp);
2012 extern __checkReturn efx_rc_t
2014 __in efx_evq_t *eep,
2015 __in unsigned int us);
2017 extern __checkReturn efx_rc_t
2019 __in efx_evq_t *eep,
2020 __in unsigned int count);
2022 #if EFSYS_OPT_QSTATS
2028 __in efx_nic_t *enp,
2029 __in unsigned int id);
2031 #endif /* EFSYS_OPT_NAMES */
2034 efx_ev_qstats_update(
2035 __in efx_evq_t *eep,
2036 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2038 #endif /* EFSYS_OPT_QSTATS */
2042 __in efx_evq_t *eep);
2046 extern __checkReturn efx_rc_t
2048 __inout efx_nic_t *enp);
2052 __in efx_nic_t *enp);
2054 #if EFSYS_OPT_RX_SCATTER
2055 __checkReturn efx_rc_t
2056 efx_rx_scatter_enable(
2057 __in efx_nic_t *enp,
2058 __in unsigned int buf_size);
2059 #endif /* EFSYS_OPT_RX_SCATTER */
2061 /* Handle to represent use of the default RSS context. */
2062 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2064 #if EFSYS_OPT_RX_SCALE
2066 typedef enum efx_rx_hash_alg_e {
2067 EFX_RX_HASHALG_LFSR = 0,
2068 EFX_RX_HASHALG_TOEPLITZ
2069 } efx_rx_hash_alg_t;
2071 #define EFX_RX_HASH_IPV4 (1U << 0)
2072 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2073 #define EFX_RX_HASH_IPV6 (1U << 2)
2074 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2076 typedef unsigned int efx_rx_hash_type_t;
2078 typedef enum efx_rx_hash_support_e {
2079 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2080 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2081 } efx_rx_hash_support_t;
2083 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2084 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2085 #define EFX_MAXRSS 64 /* RX indirection entry range */
2086 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2088 typedef enum efx_rx_scale_context_type_e {
2089 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2090 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2091 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2092 } efx_rx_scale_context_type_t;
2094 extern __checkReturn efx_rc_t
2095 efx_rx_hash_default_support_get(
2096 __in efx_nic_t *enp,
2097 __out efx_rx_hash_support_t *supportp);
2100 extern __checkReturn efx_rc_t
2101 efx_rx_scale_default_support_get(
2102 __in efx_nic_t *enp,
2103 __out efx_rx_scale_context_type_t *typep);
2105 extern __checkReturn efx_rc_t
2106 efx_rx_scale_context_alloc(
2107 __in efx_nic_t *enp,
2108 __in efx_rx_scale_context_type_t type,
2109 __in uint32_t num_queues,
2110 __out uint32_t *rss_contextp);
2112 extern __checkReturn efx_rc_t
2113 efx_rx_scale_context_free(
2114 __in efx_nic_t *enp,
2115 __in uint32_t rss_context);
2117 extern __checkReturn efx_rc_t
2118 efx_rx_scale_mode_set(
2119 __in efx_nic_t *enp,
2120 __in uint32_t rss_context,
2121 __in efx_rx_hash_alg_t alg,
2122 __in efx_rx_hash_type_t type,
2123 __in boolean_t insert);
2125 extern __checkReturn efx_rc_t
2126 efx_rx_scale_tbl_set(
2127 __in efx_nic_t *enp,
2128 __in uint32_t rss_context,
2129 __in_ecount(n) unsigned int *table,
2132 extern __checkReturn efx_rc_t
2133 efx_rx_scale_key_set(
2134 __in efx_nic_t *enp,
2135 __in uint32_t rss_context,
2136 __in_ecount(n) uint8_t *key,
2139 extern __checkReturn uint32_t
2140 efx_pseudo_hdr_hash_get(
2141 __in efx_rxq_t *erp,
2142 __in efx_rx_hash_alg_t func,
2143 __in uint8_t *buffer);
2145 #endif /* EFSYS_OPT_RX_SCALE */
2147 extern __checkReturn efx_rc_t
2148 efx_pseudo_hdr_pkt_length_get(
2149 __in efx_rxq_t *erp,
2150 __in uint8_t *buffer,
2151 __out uint16_t *pkt_lengthp);
2153 #define EFX_RXQ_MAXNDESCS 4096
2154 #define EFX_RXQ_MINNDESCS 512
2156 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2157 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2158 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2159 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2161 typedef enum efx_rxq_type_e {
2162 EFX_RXQ_TYPE_DEFAULT,
2163 EFX_RXQ_TYPE_PACKED_STREAM,
2168 * Dummy flag to be used instead of 0 to make it clear that the argument
2169 * is receive queue flags.
2171 #define EFX_RXQ_FLAG_NONE 0x0
2172 #define EFX_RXQ_FLAG_SCATTER 0x1
2174 * If tunnels are supported and Rx event can provide information about
2175 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2176 * full-feature firmware variant running), outer classes are requested by
2177 * default. However, if the driver supports tunnels, the flag allows to
2178 * request inner classes which are required to be able to interpret inner
2179 * Rx checksum offload results.
2181 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2183 extern __checkReturn efx_rc_t
2185 __in efx_nic_t *enp,
2186 __in unsigned int index,
2187 __in unsigned int label,
2188 __in efx_rxq_type_t type,
2189 __in efsys_mem_t *esmp,
2192 __in unsigned int flags,
2193 __in efx_evq_t *eep,
2194 __deref_out efx_rxq_t **erpp);
2196 #if EFSYS_OPT_RX_PACKED_STREAM
2198 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2199 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2200 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2201 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2202 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2204 extern __checkReturn efx_rc_t
2205 efx_rx_qcreate_packed_stream(
2206 __in efx_nic_t *enp,
2207 __in unsigned int index,
2208 __in unsigned int label,
2209 __in uint32_t ps_buf_size,
2210 __in efsys_mem_t *esmp,
2212 __in efx_evq_t *eep,
2213 __deref_out efx_rxq_t **erpp);
2217 typedef struct efx_buffer_s {
2218 efsys_dma_addr_t eb_addr;
2223 typedef struct efx_desc_s {
2229 __in efx_rxq_t *erp,
2230 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2232 __in unsigned int ndescs,
2233 __in unsigned int completed,
2234 __in unsigned int added);
2238 __in efx_rxq_t *erp,
2239 __in unsigned int added,
2240 __inout unsigned int *pushedp);
2242 #if EFSYS_OPT_RX_PACKED_STREAM
2245 efx_rx_qpush_ps_credits(
2246 __in efx_rxq_t *erp);
2248 extern __checkReturn uint8_t *
2249 efx_rx_qps_packet_info(
2250 __in efx_rxq_t *erp,
2251 __in uint8_t *buffer,
2252 __in uint32_t buffer_length,
2253 __in uint32_t current_offset,
2254 __out uint16_t *lengthp,
2255 __out uint32_t *next_offsetp,
2256 __out uint32_t *timestamp);
2259 extern __checkReturn efx_rc_t
2261 __in efx_rxq_t *erp);
2265 __in efx_rxq_t *erp);
2269 __in efx_rxq_t *erp);
2273 typedef struct efx_txq_s efx_txq_t;
2275 #if EFSYS_OPT_QSTATS
2277 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2278 typedef enum efx_tx_qstat_e {
2284 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2286 #endif /* EFSYS_OPT_QSTATS */
2288 extern __checkReturn efx_rc_t
2290 __in efx_nic_t *enp);
2294 __in efx_nic_t *enp);
2296 #define EFX_TXQ_MINNDESCS 512
2298 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2299 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2300 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2302 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2304 #define EFX_TXQ_CKSUM_IPV4 0x0001
2305 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2306 #define EFX_TXQ_FATSOV2 0x0004
2307 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2308 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2310 extern __checkReturn efx_rc_t
2312 __in efx_nic_t *enp,
2313 __in unsigned int index,
2314 __in unsigned int label,
2315 __in efsys_mem_t *esmp,
2318 __in uint16_t flags,
2319 __in efx_evq_t *eep,
2320 __deref_out efx_txq_t **etpp,
2321 __out unsigned int *addedp);
2323 extern __checkReturn efx_rc_t
2325 __in efx_txq_t *etp,
2326 __in_ecount(ndescs) efx_buffer_t *eb,
2327 __in unsigned int ndescs,
2328 __in unsigned int completed,
2329 __inout unsigned int *addedp);
2331 extern __checkReturn efx_rc_t
2333 __in efx_txq_t *etp,
2334 __in unsigned int ns);
2338 __in efx_txq_t *etp,
2339 __in unsigned int added,
2340 __in unsigned int pushed);
2342 extern __checkReturn efx_rc_t
2344 __in efx_txq_t *etp);
2348 __in efx_txq_t *etp);
2350 extern __checkReturn efx_rc_t
2352 __in efx_txq_t *etp);
2355 efx_tx_qpio_disable(
2356 __in efx_txq_t *etp);
2358 extern __checkReturn efx_rc_t
2360 __in efx_txq_t *etp,
2361 __in_ecount(buf_length) uint8_t *buffer,
2362 __in size_t buf_length,
2363 __in size_t pio_buf_offset);
2365 extern __checkReturn efx_rc_t
2367 __in efx_txq_t *etp,
2368 __in size_t pkt_length,
2369 __in unsigned int completed,
2370 __inout unsigned int *addedp);
2372 extern __checkReturn efx_rc_t
2374 __in efx_txq_t *etp,
2375 __in_ecount(n) efx_desc_t *ed,
2376 __in unsigned int n,
2377 __in unsigned int completed,
2378 __inout unsigned int *addedp);
2381 efx_tx_qdesc_dma_create(
2382 __in efx_txq_t *etp,
2383 __in efsys_dma_addr_t addr,
2386 __out efx_desc_t *edp);
2389 efx_tx_qdesc_tso_create(
2390 __in efx_txq_t *etp,
2391 __in uint16_t ipv4_id,
2392 __in uint32_t tcp_seq,
2393 __in uint8_t tcp_flags,
2394 __out efx_desc_t *edp);
2396 /* Number of FATSOv2 option descriptors */
2397 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2399 /* Maximum number of DMA segments per TSO packet (not superframe) */
2400 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2403 efx_tx_qdesc_tso2_create(
2404 __in efx_txq_t *etp,
2405 __in uint16_t ipv4_id,
2406 __in uint16_t outer_ipv4_id,
2407 __in uint32_t tcp_seq,
2408 __in uint16_t tcp_mss,
2409 __out_ecount(count) efx_desc_t *edp,
2413 efx_tx_qdesc_vlantci_create(
2414 __in efx_txq_t *etp,
2416 __out efx_desc_t *edp);
2419 efx_tx_qdesc_checksum_create(
2420 __in efx_txq_t *etp,
2421 __in uint16_t flags,
2422 __out efx_desc_t *edp);
2424 #if EFSYS_OPT_QSTATS
2430 __in efx_nic_t *etp,
2431 __in unsigned int id);
2433 #endif /* EFSYS_OPT_NAMES */
2436 efx_tx_qstats_update(
2437 __in efx_txq_t *etp,
2438 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2440 #endif /* EFSYS_OPT_QSTATS */
2444 __in efx_txq_t *etp);
2449 #if EFSYS_OPT_FILTER
2451 #define EFX_ETHER_TYPE_IPV4 0x0800
2452 #define EFX_ETHER_TYPE_IPV6 0x86DD
2454 #define EFX_IPPROTO_TCP 6
2455 #define EFX_IPPROTO_UDP 17
2456 #define EFX_IPPROTO_GRE 47
2458 /* Use RSS to spread across multiple queues */
2459 #define EFX_FILTER_FLAG_RX_RSS 0x01
2460 /* Enable RX scatter */
2461 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2463 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2464 * May only be set by the filter implementation for each type.
2465 * A removal request will restore the automatic filter in its place.
2467 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2468 /* Filter is for RX */
2469 #define EFX_FILTER_FLAG_RX 0x08
2470 /* Filter is for TX */
2471 #define EFX_FILTER_FLAG_TX 0x10
2473 typedef uint8_t efx_filter_flags_t;
2476 * Flags which specify the fields to match on. The values are the same as in the
2477 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2480 /* Match by remote IP host address */
2481 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2482 /* Match by local IP host address */
2483 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2484 /* Match by remote MAC address */
2485 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2486 /* Match by remote TCP/UDP port */
2487 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2488 /* Match by remote TCP/UDP port */
2489 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2490 /* Match by local TCP/UDP port */
2491 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2492 /* Match by Ether-type */
2493 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2494 /* Match by inner VLAN ID */
2495 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2496 /* Match by outer VLAN ID */
2497 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2498 /* Match by IP transport protocol */
2499 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2500 /* Match by VNI or VSID */
2501 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2502 /* For encapsulated packets, match by inner frame local MAC address */
2503 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2504 /* For encapsulated packets, match all multicast inner frames */
2505 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2506 /* For encapsulated packets, match all unicast inner frames */
2507 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2509 * Match by encap type, this flag does not correspond to
2510 * the MCDI match flags and any unoccupied value may be used
2512 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2513 /* Match otherwise-unmatched multicast and broadcast packets */
2514 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2515 /* Match otherwise-unmatched unicast packets */
2516 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2518 typedef uint32_t efx_filter_match_flags_t;
2520 typedef enum efx_filter_priority_s {
2521 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2522 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2523 * address list or hardware
2524 * requirements. This may only be used
2525 * by the filter implementation for
2527 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2528 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2529 * client (e.g. SR-IOV, HyperV VMQ etc.)
2531 } efx_filter_priority_t;
2534 * FIXME: All these fields are assumed to be in little-endian byte order.
2535 * It may be better for some to be big-endian. See bug42804.
2538 typedef struct efx_filter_spec_s {
2539 efx_filter_match_flags_t efs_match_flags;
2540 uint8_t efs_priority;
2541 efx_filter_flags_t efs_flags;
2542 uint16_t efs_dmaq_id;
2543 uint32_t efs_rss_context;
2544 uint16_t efs_outer_vid;
2545 uint16_t efs_inner_vid;
2546 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2547 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2548 uint16_t efs_ether_type;
2549 uint8_t efs_ip_proto;
2550 efx_tunnel_protocol_t efs_encap_type;
2551 uint16_t efs_loc_port;
2552 uint16_t efs_rem_port;
2553 efx_oword_t efs_rem_host;
2554 efx_oword_t efs_loc_host;
2555 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2556 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2557 } efx_filter_spec_t;
2560 /* Default values for use in filter specifications */
2561 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2562 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2564 extern __checkReturn efx_rc_t
2566 __in efx_nic_t *enp);
2570 __in efx_nic_t *enp);
2572 extern __checkReturn efx_rc_t
2574 __in efx_nic_t *enp,
2575 __inout efx_filter_spec_t *spec);
2577 extern __checkReturn efx_rc_t
2579 __in efx_nic_t *enp,
2580 __inout efx_filter_spec_t *spec);
2582 extern __checkReturn efx_rc_t
2584 __in efx_nic_t *enp);
2586 extern __checkReturn efx_rc_t
2587 efx_filter_supported_filters(
2588 __in efx_nic_t *enp,
2589 __out_ecount(buffer_length) uint32_t *buffer,
2590 __in size_t buffer_length,
2591 __out size_t *list_lengthp);
2594 efx_filter_spec_init_rx(
2595 __out efx_filter_spec_t *spec,
2596 __in efx_filter_priority_t priority,
2597 __in efx_filter_flags_t flags,
2598 __in efx_rxq_t *erp);
2601 efx_filter_spec_init_tx(
2602 __out efx_filter_spec_t *spec,
2603 __in efx_txq_t *etp);
2605 extern __checkReturn efx_rc_t
2606 efx_filter_spec_set_ipv4_local(
2607 __inout efx_filter_spec_t *spec,
2610 __in uint16_t port);
2612 extern __checkReturn efx_rc_t
2613 efx_filter_spec_set_ipv4_full(
2614 __inout efx_filter_spec_t *spec,
2616 __in uint32_t lhost,
2617 __in uint16_t lport,
2618 __in uint32_t rhost,
2619 __in uint16_t rport);
2621 extern __checkReturn efx_rc_t
2622 efx_filter_spec_set_eth_local(
2623 __inout efx_filter_spec_t *spec,
2625 __in const uint8_t *addr);
2628 efx_filter_spec_set_ether_type(
2629 __inout efx_filter_spec_t *spec,
2630 __in uint16_t ether_type);
2632 extern __checkReturn efx_rc_t
2633 efx_filter_spec_set_uc_def(
2634 __inout efx_filter_spec_t *spec);
2636 extern __checkReturn efx_rc_t
2637 efx_filter_spec_set_mc_def(
2638 __inout efx_filter_spec_t *spec);
2640 typedef enum efx_filter_inner_frame_match_e {
2641 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2642 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2643 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2644 } efx_filter_inner_frame_match_t;
2646 extern __checkReturn efx_rc_t
2647 efx_filter_spec_set_encap_type(
2648 __inout efx_filter_spec_t *spec,
2649 __in efx_tunnel_protocol_t encap_type,
2650 __in efx_filter_inner_frame_match_t inner_frame_match);
2652 extern __checkReturn efx_rc_t
2653 efx_filter_spec_set_vxlan_full(
2654 __inout efx_filter_spec_t *spec,
2655 __in const uint8_t *vxlan_id,
2656 __in const uint8_t *inner_addr,
2657 __in const uint8_t *outer_addr);
2659 #if EFSYS_OPT_RX_SCALE
2660 extern __checkReturn efx_rc_t
2661 efx_filter_spec_set_rss_context(
2662 __inout efx_filter_spec_t *spec,
2663 __in uint32_t rss_context);
2665 #endif /* EFSYS_OPT_FILTER */
2669 extern __checkReturn uint32_t
2671 __in_ecount(count) uint32_t const *input,
2673 __in uint32_t init);
2675 extern __checkReturn uint32_t
2677 __in_ecount(length) uint8_t const *input,
2679 __in uint32_t init);
2681 #if EFSYS_OPT_LICENSING
2685 typedef struct efx_key_stats_s {
2687 uint32_t eks_invalid;
2688 uint32_t eks_blacklisted;
2689 uint32_t eks_unverifiable;
2690 uint32_t eks_wrong_node;
2691 uint32_t eks_licensed_apps_lo;
2692 uint32_t eks_licensed_apps_hi;
2693 uint32_t eks_licensed_features_lo;
2694 uint32_t eks_licensed_features_hi;
2697 extern __checkReturn efx_rc_t
2699 __in efx_nic_t *enp);
2703 __in efx_nic_t *enp);
2705 extern __checkReturn boolean_t
2706 efx_lic_check_support(
2707 __in efx_nic_t *enp);
2709 extern __checkReturn efx_rc_t
2710 efx_lic_update_licenses(
2711 __in efx_nic_t *enp);
2713 extern __checkReturn efx_rc_t
2714 efx_lic_get_key_stats(
2715 __in efx_nic_t *enp,
2716 __out efx_key_stats_t *ksp);
2718 extern __checkReturn efx_rc_t
2720 __in efx_nic_t *enp,
2721 __in uint64_t app_id,
2722 __out boolean_t *licensedp);
2724 extern __checkReturn efx_rc_t
2726 __in efx_nic_t *enp,
2727 __in size_t buffer_size,
2728 __out uint32_t *typep,
2729 __out size_t *lengthp,
2730 __out_opt uint8_t *bufferp);
2733 extern __checkReturn efx_rc_t
2735 __in efx_nic_t *enp,
2736 __in_bcount(buffer_size)
2738 __in size_t buffer_size,
2739 __out uint32_t *startp);
2741 extern __checkReturn efx_rc_t
2743 __in efx_nic_t *enp,
2744 __in_bcount(buffer_size)
2746 __in size_t buffer_size,
2747 __in uint32_t offset,
2748 __out uint32_t *endp);
2750 extern __checkReturn __success(return != B_FALSE) boolean_t
2752 __in efx_nic_t *enp,
2753 __in_bcount(buffer_size)
2755 __in size_t buffer_size,
2756 __in uint32_t offset,
2757 __out uint32_t *startp,
2758 __out uint32_t *lengthp);
2760 extern __checkReturn __success(return != B_FALSE) boolean_t
2761 efx_lic_validate_key(
2762 __in efx_nic_t *enp,
2763 __in_bcount(length) caddr_t keyp,
2764 __in uint32_t length);
2766 extern __checkReturn efx_rc_t
2768 __in efx_nic_t *enp,
2769 __in_bcount(buffer_size)
2771 __in size_t buffer_size,
2772 __in uint32_t offset,
2773 __in uint32_t length,
2774 __out_bcount_part(key_max_size, *lengthp)
2776 __in size_t key_max_size,
2777 __out uint32_t *lengthp);
2779 extern __checkReturn efx_rc_t
2781 __in efx_nic_t *enp,
2782 __in_bcount(buffer_size)
2784 __in size_t buffer_size,
2785 __in uint32_t offset,
2786 __in_bcount(length) caddr_t keyp,
2787 __in uint32_t length,
2788 __out uint32_t *lengthp);
2790 __checkReturn efx_rc_t
2792 __in efx_nic_t *enp,
2793 __in_bcount(buffer_size)
2795 __in size_t buffer_size,
2796 __in uint32_t offset,
2797 __in uint32_t length,
2799 __out uint32_t *deltap);
2801 extern __checkReturn efx_rc_t
2802 efx_lic_create_partition(
2803 __in efx_nic_t *enp,
2804 __in_bcount(buffer_size)
2806 __in size_t buffer_size);
2808 extern __checkReturn efx_rc_t
2809 efx_lic_finish_partition(
2810 __in efx_nic_t *enp,
2811 __in_bcount(buffer_size)
2813 __in size_t buffer_size);
2815 #endif /* EFSYS_OPT_LICENSING */
2819 #if EFSYS_OPT_TUNNEL
2821 extern __checkReturn efx_rc_t
2823 __in efx_nic_t *enp);
2827 __in efx_nic_t *enp);
2830 * For overlay network encapsulation using UDP, the firmware needs to know
2831 * the configured UDP port for the overlay so it can decode encapsulated
2833 * The UDP port/protocol list is global.
2836 extern __checkReturn efx_rc_t
2837 efx_tunnel_config_udp_add(
2838 __in efx_nic_t *enp,
2839 __in uint16_t port /* host/cpu-endian */,
2840 __in efx_tunnel_protocol_t protocol);
2842 extern __checkReturn efx_rc_t
2843 efx_tunnel_config_udp_remove(
2844 __in efx_nic_t *enp,
2845 __in uint16_t port /* host/cpu-endian */,
2846 __in efx_tunnel_protocol_t protocol);
2849 efx_tunnel_config_clear(
2850 __in efx_nic_t *enp);
2853 * Apply tunnel UDP ports configuration to hardware.
2855 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
2858 extern __checkReturn efx_rc_t
2859 efx_tunnel_reconfigure(
2860 __in efx_nic_t *enp);
2862 #endif /* EFSYS_OPT_TUNNEL */
2869 #endif /* _SYS_EFX_H */