1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
11 #include "efx_check.h"
12 #include "efx_phy_ids.h"
18 #define EFX_STATIC_ASSERT(_cond) \
19 ((void)sizeof (char[(_cond) ? 1 : -1]))
21 #define EFX_ARRAY_SIZE(_array) \
22 (sizeof (_array) / sizeof ((_array)[0]))
24 #define EFX_FIELD_OFFSET(_type, _field) \
25 ((size_t)&(((_type *)0)->_field))
27 /* The macro expands divider twice */
28 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 typedef __success(return == 0) int efx_rc_t;
37 typedef enum efx_family_e {
39 EFX_FAMILY_FALCON, /* Obsolete and not supported */
41 EFX_FAMILY_HUNTINGTON,
47 extern __checkReturn efx_rc_t
51 __out efx_family_t *efp,
52 __out unsigned int *membarp);
55 #define EFX_PCI_VENID_SFC 0x1924
57 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
59 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
60 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
61 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
63 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
64 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
65 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
67 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
68 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
70 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
71 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
72 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
74 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
75 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
76 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
79 #define EFX_MEM_BAR_SIENA 2
81 #define EFX_MEM_BAR_HUNTINGTON_PF 2
82 #define EFX_MEM_BAR_HUNTINGTON_VF 0
84 #define EFX_MEM_BAR_MEDFORD_PF 2
85 #define EFX_MEM_BAR_MEDFORD_VF 0
87 #define EFX_MEM_BAR_MEDFORD2 0
108 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
109 extern __checkReturn uint32_t
111 __in uint32_t crc_init,
112 __in_ecount(length) uint8_t const *input,
116 /* Type prototypes */
118 typedef struct efx_rxq_s efx_rxq_t;
122 typedef struct efx_nic_s efx_nic_t;
124 extern __checkReturn efx_rc_t
126 __in efx_family_t family,
127 __in efsys_identifier_t *esip,
128 __in efsys_bar_t *esbp,
129 __in efsys_lock_t *eslp,
130 __deref_out efx_nic_t **enpp);
132 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
133 typedef enum efx_fw_variant_e {
134 EFX_FW_VARIANT_FULL_FEATURED,
135 EFX_FW_VARIANT_LOW_LATENCY,
136 EFX_FW_VARIANT_PACKED_STREAM,
137 EFX_FW_VARIANT_HIGH_TX_RATE,
138 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
139 EFX_FW_VARIANT_RULES_ENGINE,
141 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
144 extern __checkReturn efx_rc_t
147 __in efx_fw_variant_t efv);
149 extern __checkReturn efx_rc_t
151 __in efx_nic_t *enp);
153 extern __checkReturn efx_rc_t
155 __in efx_nic_t *enp);
159 extern __checkReturn efx_rc_t
160 efx_nic_register_test(
161 __in efx_nic_t *enp);
163 #endif /* EFSYS_OPT_DIAG */
167 __in efx_nic_t *enp);
171 __in efx_nic_t *enp);
175 __in efx_nic_t *enp);
177 #define EFX_PCIE_LINK_SPEED_GEN1 1
178 #define EFX_PCIE_LINK_SPEED_GEN2 2
179 #define EFX_PCIE_LINK_SPEED_GEN3 3
181 typedef enum efx_pcie_link_performance_e {
182 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
183 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
184 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
185 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
186 } efx_pcie_link_performance_t;
188 extern __checkReturn efx_rc_t
189 efx_nic_calculate_pcie_link_bandwidth(
190 __in uint32_t pcie_link_width,
191 __in uint32_t pcie_link_gen,
192 __out uint32_t *bandwidth_mbpsp);
194 extern __checkReturn efx_rc_t
195 efx_nic_check_pcie_link_speed(
197 __in uint32_t pcie_link_width,
198 __in uint32_t pcie_link_gen,
199 __out efx_pcie_link_performance_t *resultp);
203 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
204 /* Huntington and Medford require MCDIv2 commands */
205 #define WITH_MCDI_V2 1
208 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
210 typedef enum efx_mcdi_exception_e {
211 EFX_MCDI_EXCEPTION_MC_REBOOT,
212 EFX_MCDI_EXCEPTION_MC_BADASSERT,
213 } efx_mcdi_exception_t;
215 #if EFSYS_OPT_MCDI_LOGGING
216 typedef enum efx_log_msg_e {
218 EFX_LOG_MCDI_REQUEST,
219 EFX_LOG_MCDI_RESPONSE,
221 #endif /* EFSYS_OPT_MCDI_LOGGING */
223 typedef struct efx_mcdi_transport_s {
225 efsys_mem_t *emt_dma_mem;
226 void (*emt_execute)(void *, efx_mcdi_req_t *);
227 void (*emt_ev_cpl)(void *);
228 void (*emt_exception)(void *, efx_mcdi_exception_t);
229 #if EFSYS_OPT_MCDI_LOGGING
230 void (*emt_logger)(void *, efx_log_msg_t,
231 void *, size_t, void *, size_t);
232 #endif /* EFSYS_OPT_MCDI_LOGGING */
233 #if EFSYS_OPT_MCDI_PROXY_AUTH
234 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
235 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
236 } efx_mcdi_transport_t;
238 extern __checkReturn efx_rc_t
241 __in const efx_mcdi_transport_t *mtp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
249 __in efx_nic_t *enp);
252 efx_mcdi_get_timeout(
254 __in efx_mcdi_req_t *emrp,
255 __out uint32_t *usec_timeoutp);
258 efx_mcdi_request_start(
260 __in efx_mcdi_req_t *emrp,
261 __in boolean_t ev_cpl);
263 extern __checkReturn boolean_t
264 efx_mcdi_request_poll(
265 __in efx_nic_t *enp);
267 extern __checkReturn boolean_t
268 efx_mcdi_request_abort(
269 __in efx_nic_t *enp);
273 __in efx_nic_t *enp);
275 #endif /* EFSYS_OPT_MCDI */
279 #define EFX_NINTR_SIENA 1024
281 typedef enum efx_intr_type_e {
282 EFX_INTR_INVALID = 0,
288 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
290 extern __checkReturn efx_rc_t
293 __in efx_intr_type_t type,
294 __in efsys_mem_t *esmp);
298 __in efx_nic_t *enp);
302 __in efx_nic_t *enp);
305 efx_intr_disable_unlocked(
306 __in efx_nic_t *enp);
308 #define EFX_INTR_NEVQS 32
310 extern __checkReturn efx_rc_t
313 __in unsigned int level);
316 efx_intr_status_line(
318 __out boolean_t *fatalp,
319 __out uint32_t *maskp);
322 efx_intr_status_message(
324 __in unsigned int message,
325 __out boolean_t *fatalp);
329 __in efx_nic_t *enp);
333 __in efx_nic_t *enp);
337 #if EFSYS_OPT_MAC_STATS
339 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
340 typedef enum efx_mac_stat_e {
343 EFX_MAC_RX_UNICST_PKTS,
344 EFX_MAC_RX_MULTICST_PKTS,
345 EFX_MAC_RX_BRDCST_PKTS,
346 EFX_MAC_RX_PAUSE_PKTS,
347 EFX_MAC_RX_LE_64_PKTS,
348 EFX_MAC_RX_65_TO_127_PKTS,
349 EFX_MAC_RX_128_TO_255_PKTS,
350 EFX_MAC_RX_256_TO_511_PKTS,
351 EFX_MAC_RX_512_TO_1023_PKTS,
352 EFX_MAC_RX_1024_TO_15XX_PKTS,
353 EFX_MAC_RX_GE_15XX_PKTS,
355 EFX_MAC_RX_FCS_ERRORS,
356 EFX_MAC_RX_DROP_EVENTS,
357 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
358 EFX_MAC_RX_SYMBOL_ERRORS,
359 EFX_MAC_RX_ALIGN_ERRORS,
360 EFX_MAC_RX_INTERNAL_ERRORS,
361 EFX_MAC_RX_JABBER_PKTS,
362 EFX_MAC_RX_LANE0_CHAR_ERR,
363 EFX_MAC_RX_LANE1_CHAR_ERR,
364 EFX_MAC_RX_LANE2_CHAR_ERR,
365 EFX_MAC_RX_LANE3_CHAR_ERR,
366 EFX_MAC_RX_LANE0_DISP_ERR,
367 EFX_MAC_RX_LANE1_DISP_ERR,
368 EFX_MAC_RX_LANE2_DISP_ERR,
369 EFX_MAC_RX_LANE3_DISP_ERR,
370 EFX_MAC_RX_MATCH_FAULT,
371 EFX_MAC_RX_NODESC_DROP_CNT,
374 EFX_MAC_TX_UNICST_PKTS,
375 EFX_MAC_TX_MULTICST_PKTS,
376 EFX_MAC_TX_BRDCST_PKTS,
377 EFX_MAC_TX_PAUSE_PKTS,
378 EFX_MAC_TX_LE_64_PKTS,
379 EFX_MAC_TX_65_TO_127_PKTS,
380 EFX_MAC_TX_128_TO_255_PKTS,
381 EFX_MAC_TX_256_TO_511_PKTS,
382 EFX_MAC_TX_512_TO_1023_PKTS,
383 EFX_MAC_TX_1024_TO_15XX_PKTS,
384 EFX_MAC_TX_GE_15XX_PKTS,
386 EFX_MAC_TX_SGL_COL_PKTS,
387 EFX_MAC_TX_MULT_COL_PKTS,
388 EFX_MAC_TX_EX_COL_PKTS,
389 EFX_MAC_TX_LATE_COL_PKTS,
391 EFX_MAC_TX_EX_DEF_PKTS,
392 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
393 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
394 EFX_MAC_PM_TRUNC_VFIFO_FULL,
395 EFX_MAC_PM_DISCARD_VFIFO_FULL,
396 EFX_MAC_PM_TRUNC_QBB,
397 EFX_MAC_PM_DISCARD_QBB,
398 EFX_MAC_PM_DISCARD_MAPPING,
399 EFX_MAC_RXDP_Q_DISABLED_PKTS,
400 EFX_MAC_RXDP_DI_DROPPED_PKTS,
401 EFX_MAC_RXDP_STREAMING_PKTS,
402 EFX_MAC_RXDP_HLB_FETCH,
403 EFX_MAC_RXDP_HLB_WAIT,
404 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
405 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
406 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
407 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
408 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
409 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
410 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
411 EFX_MAC_VADAPTER_RX_BAD_BYTES,
412 EFX_MAC_VADAPTER_RX_OVERFLOW,
413 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
414 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
415 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
416 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
417 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
418 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
419 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
420 EFX_MAC_VADAPTER_TX_BAD_BYTES,
421 EFX_MAC_VADAPTER_TX_OVERFLOW,
422 EFX_MAC_FEC_UNCORRECTED_ERRORS,
423 EFX_MAC_FEC_CORRECTED_ERRORS,
424 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
425 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
426 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
427 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
428 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
429 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
430 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
431 EFX_MAC_CTPIO_OVERFLOW_FAIL,
432 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
433 EFX_MAC_CTPIO_TIMEOUT_FAIL,
434 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
435 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
436 EFX_MAC_CTPIO_INVALID_WR_FAIL,
437 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
438 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
439 EFX_MAC_CTPIO_RUNT_FALLBACK,
440 EFX_MAC_CTPIO_SUCCESS,
441 EFX_MAC_CTPIO_FALLBACK,
442 EFX_MAC_CTPIO_POISON,
444 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
445 EFX_MAC_RXDP_HLB_IDLE,
446 EFX_MAC_RXDP_HLB_TIMEOUT,
450 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
452 #endif /* EFSYS_OPT_MAC_STATS */
454 typedef enum efx_link_mode_e {
455 EFX_LINK_UNKNOWN = 0,
471 #define EFX_MAC_ADDR_LEN 6
473 #define EFX_VNI_OR_VSID_LEN 3
475 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
477 #define EFX_MAC_MULTICAST_LIST_MAX 256
479 #define EFX_MAC_SDU_MAX 9202
481 #define EFX_MAC_PDU_ADJUSTMENT \
485 + /* bug16011 */ 16) \
487 #define EFX_MAC_PDU(_sdu) \
488 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
491 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
492 * the SDU rounded up slightly.
494 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
496 #define EFX_MAC_PDU_MIN 60
497 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
499 extern __checkReturn efx_rc_t
504 extern __checkReturn efx_rc_t
509 extern __checkReturn efx_rc_t
514 extern __checkReturn efx_rc_t
517 __in boolean_t all_unicst,
518 __in boolean_t mulcst,
519 __in boolean_t all_mulcst,
520 __in boolean_t brdcst);
522 extern __checkReturn efx_rc_t
523 efx_mac_multicast_list_set(
525 __in_ecount(6*count) uint8_t const *addrs,
528 extern __checkReturn efx_rc_t
529 efx_mac_filter_default_rxq_set(
532 __in boolean_t using_rss);
535 efx_mac_filter_default_rxq_clear(
536 __in efx_nic_t *enp);
538 extern __checkReturn efx_rc_t
541 __in boolean_t enabled);
543 extern __checkReturn efx_rc_t
546 __out boolean_t *mac_upp);
548 #define EFX_FCNTL_RESPOND 0x00000001
549 #define EFX_FCNTL_GENERATE 0x00000002
551 extern __checkReturn efx_rc_t
554 __in unsigned int fcntl,
555 __in boolean_t autoneg);
560 __out unsigned int *fcntl_wantedp,
561 __out unsigned int *fcntl_linkp);
564 #if EFSYS_OPT_MAC_STATS
568 extern __checkReturn const char *
571 __in unsigned int id);
573 #endif /* EFSYS_OPT_NAMES */
575 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
577 #define EFX_MAC_STATS_MASK_NPAGES \
578 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
579 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
582 * Get mask of MAC statistics supported by the hardware.
584 * If mask_size is insufficient to return the mask, EINVAL error is
585 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
586 * (which is sizeof (uint32_t)) is sufficient.
588 extern __checkReturn efx_rc_t
589 efx_mac_stats_get_mask(
591 __out_bcount(mask_size) uint32_t *maskp,
592 __in size_t mask_size);
594 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
595 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
596 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
599 extern __checkReturn efx_rc_t
601 __in efx_nic_t *enp);
604 * Upload mac statistics supported by the hardware into the given buffer.
606 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
607 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
609 * The hardware will only DMA statistics that it understands (of course).
610 * Drivers should not make any assumptions about which statistics are
611 * supported, especially when the statistics are generated by firmware.
613 * Thus, drivers should zero this buffer before use, so that not-understood
614 * statistics read back as zero.
616 extern __checkReturn efx_rc_t
617 efx_mac_stats_upload(
619 __in efsys_mem_t *esmp);
621 extern __checkReturn efx_rc_t
622 efx_mac_stats_periodic(
624 __in efsys_mem_t *esmp,
625 __in uint16_t period_ms,
626 __in boolean_t events);
628 extern __checkReturn efx_rc_t
629 efx_mac_stats_update(
631 __in efsys_mem_t *esmp,
632 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
633 __inout_opt uint32_t *generationp);
635 #endif /* EFSYS_OPT_MAC_STATS */
639 typedef enum efx_mon_type_e {
651 __in efx_nic_t *enp);
653 #endif /* EFSYS_OPT_NAMES */
655 extern __checkReturn efx_rc_t
657 __in efx_nic_t *enp);
659 #if EFSYS_OPT_MON_STATS
661 #define EFX_MON_STATS_PAGE_SIZE 0x100
662 #define EFX_MON_MASK_ELEMENT_SIZE 32
664 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 400fdb0517af1fca */
665 typedef enum efx_mon_stat_e {
672 EFX_MON_STAT_EXT_TEMP,
673 EFX_MON_STAT_INT_TEMP,
676 EFX_MON_STAT_INT_COOLING,
677 EFX_MON_STAT_EXT_COOLING,
685 EFX_MON_STAT_AOE_TEMP,
686 EFX_MON_STAT_PSU_AOE_TEMP,
687 EFX_MON_STAT_PSU_TEMP,
693 EFX_MON_STAT_VAOE_IN,
695 EFX_MON_STAT_IAOE_IN,
696 EFX_MON_STAT_NIC_POWER,
700 EFX_MON_STAT_0_9V_ADC,
701 EFX_MON_STAT_INT_TEMP2,
702 EFX_MON_STAT_VREG_TEMP,
703 EFX_MON_STAT_VREG_0_9V_TEMP,
704 EFX_MON_STAT_VREG_1_2V_TEMP,
705 EFX_MON_STAT_INT_VPTAT,
706 EFX_MON_STAT_INT_ADC_TEMP,
707 EFX_MON_STAT_EXT_VPTAT,
708 EFX_MON_STAT_EXT_ADC_TEMP,
709 EFX_MON_STAT_AMBIENT_TEMP,
710 EFX_MON_STAT_AIRFLOW,
711 EFX_MON_STAT_VDD08D_VSS08D_CSR,
712 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
713 EFX_MON_STAT_HOTPOINT_TEMP,
714 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
715 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
716 EFX_MON_STAT_MUM_VCC,
719 EFX_MON_STAT_0V9_A_TEMP,
722 EFX_MON_STAT_0V9_B_TEMP,
723 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
724 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
725 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
726 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
727 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
728 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
729 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
730 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
731 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
732 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
733 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
734 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
735 EFX_MON_STAT_SODIMM_VOUT,
736 EFX_MON_STAT_SODIMM_0_TEMP,
737 EFX_MON_STAT_SODIMM_1_TEMP,
738 EFX_MON_STAT_PHY0_VCC,
739 EFX_MON_STAT_PHY1_VCC,
740 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
741 EFX_MON_STAT_BOARD_FRONT_TEMP,
742 EFX_MON_STAT_BOARD_BACK_TEMP,
752 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
754 typedef enum efx_mon_stat_state_e {
755 EFX_MON_STAT_STATE_OK = 0,
756 EFX_MON_STAT_STATE_WARNING = 1,
757 EFX_MON_STAT_STATE_FATAL = 2,
758 EFX_MON_STAT_STATE_BROKEN = 3,
759 EFX_MON_STAT_STATE_NO_READING = 4,
760 } efx_mon_stat_state_t;
762 typedef struct efx_mon_stat_value_s {
765 } efx_mon_stat_value_t;
772 __in efx_mon_stat_t id);
774 #endif /* EFSYS_OPT_NAMES */
776 extern __checkReturn efx_rc_t
777 efx_mon_stats_update(
779 __in efsys_mem_t *esmp,
780 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
782 #endif /* EFSYS_OPT_MON_STATS */
786 __in efx_nic_t *enp);
790 extern __checkReturn efx_rc_t
792 __in efx_nic_t *enp);
794 #if EFSYS_OPT_PHY_LED_CONTROL
796 typedef enum efx_phy_led_mode_e {
797 EFX_PHY_LED_DEFAULT = 0,
802 } efx_phy_led_mode_t;
804 extern __checkReturn efx_rc_t
807 __in efx_phy_led_mode_t mode);
809 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
811 extern __checkReturn efx_rc_t
813 __in efx_nic_t *enp);
815 #if EFSYS_OPT_LOOPBACK
817 typedef enum efx_loopback_type_e {
818 EFX_LOOPBACK_OFF = 0,
819 EFX_LOOPBACK_DATA = 1,
820 EFX_LOOPBACK_GMAC = 2,
821 EFX_LOOPBACK_XGMII = 3,
822 EFX_LOOPBACK_XGXS = 4,
823 EFX_LOOPBACK_XAUI = 5,
824 EFX_LOOPBACK_GMII = 6,
825 EFX_LOOPBACK_SGMII = 7,
826 EFX_LOOPBACK_XGBR = 8,
827 EFX_LOOPBACK_XFI = 9,
828 EFX_LOOPBACK_XAUI_FAR = 10,
829 EFX_LOOPBACK_GMII_FAR = 11,
830 EFX_LOOPBACK_SGMII_FAR = 12,
831 EFX_LOOPBACK_XFI_FAR = 13,
832 EFX_LOOPBACK_GPHY = 14,
833 EFX_LOOPBACK_PHY_XS = 15,
834 EFX_LOOPBACK_PCS = 16,
835 EFX_LOOPBACK_PMA_PMD = 17,
836 EFX_LOOPBACK_XPORT = 18,
837 EFX_LOOPBACK_XGMII_WS = 19,
838 EFX_LOOPBACK_XAUI_WS = 20,
839 EFX_LOOPBACK_XAUI_WS_FAR = 21,
840 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
841 EFX_LOOPBACK_GMII_WS = 23,
842 EFX_LOOPBACK_XFI_WS = 24,
843 EFX_LOOPBACK_XFI_WS_FAR = 25,
844 EFX_LOOPBACK_PHYXS_WS = 26,
845 EFX_LOOPBACK_PMA_INT = 27,
846 EFX_LOOPBACK_SD_NEAR = 28,
847 EFX_LOOPBACK_SD_FAR = 29,
848 EFX_LOOPBACK_PMA_INT_WS = 30,
849 EFX_LOOPBACK_SD_FEP2_WS = 31,
850 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
851 EFX_LOOPBACK_SD_FEP_WS = 33,
852 EFX_LOOPBACK_SD_FES_WS = 34,
853 EFX_LOOPBACK_AOE_INT_NEAR = 35,
854 EFX_LOOPBACK_DATA_WS = 36,
855 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
857 } efx_loopback_type_t;
859 typedef enum efx_loopback_kind_e {
860 EFX_LOOPBACK_KIND_OFF = 0,
861 EFX_LOOPBACK_KIND_ALL,
862 EFX_LOOPBACK_KIND_MAC,
863 EFX_LOOPBACK_KIND_PHY,
865 } efx_loopback_kind_t;
869 __in efx_loopback_kind_t loopback_kind,
870 __out efx_qword_t *maskp);
872 extern __checkReturn efx_rc_t
873 efx_port_loopback_set(
875 __in efx_link_mode_t link_mode,
876 __in efx_loopback_type_t type);
880 extern __checkReturn const char *
881 efx_loopback_type_name(
883 __in efx_loopback_type_t type);
885 #endif /* EFSYS_OPT_NAMES */
887 #endif /* EFSYS_OPT_LOOPBACK */
889 extern __checkReturn efx_rc_t
892 __out_opt efx_link_mode_t *link_modep);
896 __in efx_nic_t *enp);
898 typedef enum efx_phy_cap_type_e {
899 EFX_PHY_CAP_INVALID = 0,
906 EFX_PHY_CAP_10000FDX,
910 EFX_PHY_CAP_40000FDX,
912 EFX_PHY_CAP_100000FDX,
913 EFX_PHY_CAP_25000FDX,
914 EFX_PHY_CAP_50000FDX,
915 EFX_PHY_CAP_BASER_FEC,
916 EFX_PHY_CAP_BASER_FEC_REQUESTED,
918 EFX_PHY_CAP_RS_FEC_REQUESTED,
919 EFX_PHY_CAP_25G_BASER_FEC,
920 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
922 } efx_phy_cap_type_t;
925 #define EFX_PHY_CAP_CURRENT 0x00000000
926 #define EFX_PHY_CAP_DEFAULT 0x00000001
927 #define EFX_PHY_CAP_PERM 0x00000002
933 __out uint32_t *maskp);
935 extern __checkReturn efx_rc_t
943 __out uint32_t *maskp);
945 extern __checkReturn efx_rc_t
948 __out uint32_t *ouip);
950 typedef enum efx_phy_media_type_e {
951 EFX_PHY_MEDIA_INVALID = 0,
956 EFX_PHY_MEDIA_SFP_PLUS,
957 EFX_PHY_MEDIA_BASE_T,
958 EFX_PHY_MEDIA_QSFP_PLUS,
960 } efx_phy_media_type_t;
963 * Get the type of medium currently used. If the board has ports for
964 * modules, a module is present, and we recognise the media type of
965 * the module, then this will be the media type of the module.
966 * Otherwise it will be the media type of the port.
969 efx_phy_media_type_get(
971 __out efx_phy_media_type_t *typep);
973 extern __checkReturn efx_rc_t
974 efx_phy_module_get_info(
976 __in uint8_t dev_addr,
979 __out_bcount(len) uint8_t *data);
981 #if EFSYS_OPT_PHY_STATS
983 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
984 typedef enum efx_phy_stat_e {
986 EFX_PHY_STAT_PMA_PMD_LINK_UP,
987 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
988 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
989 EFX_PHY_STAT_PMA_PMD_REV_A,
990 EFX_PHY_STAT_PMA_PMD_REV_B,
991 EFX_PHY_STAT_PMA_PMD_REV_C,
992 EFX_PHY_STAT_PMA_PMD_REV_D,
993 EFX_PHY_STAT_PCS_LINK_UP,
994 EFX_PHY_STAT_PCS_RX_FAULT,
995 EFX_PHY_STAT_PCS_TX_FAULT,
996 EFX_PHY_STAT_PCS_BER,
997 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
998 EFX_PHY_STAT_PHY_XS_LINK_UP,
999 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1000 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1001 EFX_PHY_STAT_PHY_XS_ALIGN,
1002 EFX_PHY_STAT_PHY_XS_SYNC_A,
1003 EFX_PHY_STAT_PHY_XS_SYNC_B,
1004 EFX_PHY_STAT_PHY_XS_SYNC_C,
1005 EFX_PHY_STAT_PHY_XS_SYNC_D,
1006 EFX_PHY_STAT_AN_LINK_UP,
1007 EFX_PHY_STAT_AN_MASTER,
1008 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1009 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1010 EFX_PHY_STAT_CL22EXT_LINK_UP,
1015 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1016 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1017 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1018 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1019 EFX_PHY_STAT_AN_COMPLETE,
1020 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1021 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1022 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1023 EFX_PHY_STAT_PCS_FW_VERSION_0,
1024 EFX_PHY_STAT_PCS_FW_VERSION_1,
1025 EFX_PHY_STAT_PCS_FW_VERSION_2,
1026 EFX_PHY_STAT_PCS_FW_VERSION_3,
1027 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1028 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1029 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1030 EFX_PHY_STAT_PCS_OP_MODE,
1034 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1040 __in efx_nic_t *enp,
1041 __in efx_phy_stat_t stat);
1043 #endif /* EFSYS_OPT_NAMES */
1045 #define EFX_PHY_STATS_SIZE 0x100
1047 extern __checkReturn efx_rc_t
1048 efx_phy_stats_update(
1049 __in efx_nic_t *enp,
1050 __in efsys_mem_t *esmp,
1051 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1053 #endif /* EFSYS_OPT_PHY_STATS */
1058 typedef enum efx_bist_type_e {
1059 EFX_BIST_TYPE_UNKNOWN,
1060 EFX_BIST_TYPE_PHY_NORMAL,
1061 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1062 EFX_BIST_TYPE_PHY_CABLE_LONG,
1063 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1064 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1065 EFX_BIST_TYPE_REG, /* Test the register memories */
1066 EFX_BIST_TYPE_NTYPES,
1069 typedef enum efx_bist_result_e {
1070 EFX_BIST_RESULT_UNKNOWN,
1071 EFX_BIST_RESULT_RUNNING,
1072 EFX_BIST_RESULT_PASSED,
1073 EFX_BIST_RESULT_FAILED,
1074 } efx_bist_result_t;
1076 typedef enum efx_phy_cable_status_e {
1077 EFX_PHY_CABLE_STATUS_OK,
1078 EFX_PHY_CABLE_STATUS_INVALID,
1079 EFX_PHY_CABLE_STATUS_OPEN,
1080 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1081 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1082 EFX_PHY_CABLE_STATUS_BUSY,
1083 } efx_phy_cable_status_t;
1085 typedef enum efx_bist_value_e {
1086 EFX_BIST_PHY_CABLE_LENGTH_A,
1087 EFX_BIST_PHY_CABLE_LENGTH_B,
1088 EFX_BIST_PHY_CABLE_LENGTH_C,
1089 EFX_BIST_PHY_CABLE_LENGTH_D,
1090 EFX_BIST_PHY_CABLE_STATUS_A,
1091 EFX_BIST_PHY_CABLE_STATUS_B,
1092 EFX_BIST_PHY_CABLE_STATUS_C,
1093 EFX_BIST_PHY_CABLE_STATUS_D,
1094 EFX_BIST_FAULT_CODE,
1096 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1102 EFX_BIST_MEM_EXPECT,
1103 EFX_BIST_MEM_ACTUAL,
1105 EFX_BIST_MEM_ECC_PARITY,
1106 EFX_BIST_MEM_ECC_FATAL,
1110 extern __checkReturn efx_rc_t
1111 efx_bist_enable_offline(
1112 __in efx_nic_t *enp);
1114 extern __checkReturn efx_rc_t
1116 __in efx_nic_t *enp,
1117 __in efx_bist_type_t type);
1119 extern __checkReturn efx_rc_t
1121 __in efx_nic_t *enp,
1122 __in efx_bist_type_t type,
1123 __out efx_bist_result_t *resultp,
1124 __out_opt uint32_t *value_maskp,
1125 __out_ecount_opt(count) unsigned long *valuesp,
1130 __in efx_nic_t *enp,
1131 __in efx_bist_type_t type);
1133 #endif /* EFSYS_OPT_BIST */
1135 #define EFX_FEATURE_IPV6 0x00000001
1136 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1137 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1138 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1139 #define EFX_FEATURE_MCDI 0x00000020
1140 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1141 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1142 #define EFX_FEATURE_TURBO 0x00000100
1143 #define EFX_FEATURE_MCDI_DMA 0x00000200
1144 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1145 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1146 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1147 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1148 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1150 typedef enum efx_tunnel_protocol_e {
1151 EFX_TUNNEL_PROTOCOL_NONE = 0,
1152 EFX_TUNNEL_PROTOCOL_VXLAN,
1153 EFX_TUNNEL_PROTOCOL_GENEVE,
1154 EFX_TUNNEL_PROTOCOL_NVGRE,
1156 } efx_tunnel_protocol_t;
1158 typedef enum efx_vi_window_shift_e {
1159 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1160 EFX_VI_WINDOW_SHIFT_8K = 13,
1161 EFX_VI_WINDOW_SHIFT_16K = 14,
1162 EFX_VI_WINDOW_SHIFT_64K = 16,
1163 } efx_vi_window_shift_t;
1165 typedef struct efx_nic_cfg_s {
1166 uint32_t enc_board_type;
1167 uint32_t enc_phy_type;
1169 char enc_phy_name[21];
1171 char enc_phy_revision[21];
1172 efx_mon_type_t enc_mon_type;
1173 #if EFSYS_OPT_MON_STATS
1174 uint32_t enc_mon_stat_dma_buf_size;
1175 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1177 unsigned int enc_features;
1178 efx_vi_window_shift_t enc_vi_window_shift;
1179 uint8_t enc_mac_addr[6];
1180 uint8_t enc_port; /* PHY port number */
1181 uint32_t enc_intr_vec_base;
1182 uint32_t enc_intr_limit;
1183 uint32_t enc_evq_limit;
1184 uint32_t enc_txq_limit;
1185 uint32_t enc_rxq_limit;
1186 uint32_t enc_txq_max_ndescs;
1187 uint32_t enc_buftbl_limit;
1188 uint32_t enc_piobuf_limit;
1189 uint32_t enc_piobuf_size;
1190 uint32_t enc_piobuf_min_alloc_size;
1191 uint32_t enc_evq_timer_quantum_ns;
1192 uint32_t enc_evq_timer_max_us;
1193 uint32_t enc_clk_mult;
1194 uint32_t enc_rx_prefix_size;
1195 uint32_t enc_rx_buf_align_start;
1196 uint32_t enc_rx_buf_align_end;
1197 uint32_t enc_rx_scale_max_exclusive_contexts;
1199 * Mask of supported hash algorithms.
1200 * Hash algorithm types are used as the bit indices.
1202 uint32_t enc_rx_scale_hash_alg_mask;
1204 * Indicates whether port numbers can be included to the
1205 * input data for hash computation.
1207 boolean_t enc_rx_scale_l4_hash_supported;
1208 boolean_t enc_rx_scale_additional_modes_supported;
1209 #if EFSYS_OPT_LOOPBACK
1210 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1211 #endif /* EFSYS_OPT_LOOPBACK */
1212 #if EFSYS_OPT_PHY_FLAGS
1213 uint32_t enc_phy_flags_mask;
1214 #endif /* EFSYS_OPT_PHY_FLAGS */
1215 #if EFSYS_OPT_PHY_LED_CONTROL
1216 uint32_t enc_led_mask;
1217 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1218 #if EFSYS_OPT_PHY_STATS
1219 uint64_t enc_phy_stat_mask;
1220 #endif /* EFSYS_OPT_PHY_STATS */
1222 uint8_t enc_mcdi_mdio_channel;
1223 #if EFSYS_OPT_PHY_STATS
1224 uint32_t enc_mcdi_phy_stat_mask;
1225 #endif /* EFSYS_OPT_PHY_STATS */
1226 #if EFSYS_OPT_MON_STATS
1227 uint32_t *enc_mcdi_sensor_maskp;
1228 uint32_t enc_mcdi_sensor_mask_size;
1229 #endif /* EFSYS_OPT_MON_STATS */
1230 #endif /* EFSYS_OPT_MCDI */
1232 uint32_t enc_bist_mask;
1233 #endif /* EFSYS_OPT_BIST */
1234 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1237 uint32_t enc_privilege_mask;
1238 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1239 boolean_t enc_bug26807_workaround;
1240 boolean_t enc_bug35388_workaround;
1241 boolean_t enc_bug41750_workaround;
1242 boolean_t enc_bug61265_workaround;
1243 boolean_t enc_rx_batching_enabled;
1244 /* Maximum number of descriptors completed in an rx event. */
1245 uint32_t enc_rx_batch_max;
1246 /* Number of rx descriptors the hardware requires for a push. */
1247 uint32_t enc_rx_push_align;
1248 /* Maximum amount of data in DMA descriptor */
1249 uint32_t enc_tx_dma_desc_size_max;
1251 * Boundary which DMA descriptor data must not cross or 0 if no
1254 uint32_t enc_tx_dma_desc_boundary;
1256 * Maximum number of bytes into the packet the TCP header can start for
1257 * the hardware to apply TSO packet edits.
1259 uint32_t enc_tx_tso_tcp_header_offset_limit;
1260 boolean_t enc_fw_assisted_tso_enabled;
1261 boolean_t enc_fw_assisted_tso_v2_enabled;
1262 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1263 /* Number of TSO contexts on the NIC (FATSOv2) */
1264 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1265 boolean_t enc_hw_tx_insert_vlan_enabled;
1266 /* Number of PFs on the NIC */
1267 uint32_t enc_hw_pf_count;
1268 /* Datapath firmware vadapter/vport/vswitch support */
1269 boolean_t enc_datapath_cap_evb;
1270 boolean_t enc_rx_disable_scatter_supported;
1271 boolean_t enc_allow_set_mac_with_installed_filters;
1272 boolean_t enc_enhanced_set_mac_supported;
1273 boolean_t enc_init_evq_v2_supported;
1274 boolean_t enc_rx_packed_stream_supported;
1275 boolean_t enc_rx_var_packed_stream_supported;
1276 boolean_t enc_rx_es_super_buffer_supported;
1277 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1278 boolean_t enc_pm_and_rxdp_counters;
1279 boolean_t enc_mac_stats_40g_tx_size_bins;
1280 uint32_t enc_tunnel_encapsulations_supported;
1282 * NIC global maximum for unique UDP tunnel ports shared by all
1285 uint32_t enc_tunnel_config_udp_entries_max;
1286 /* External port identifier */
1287 uint8_t enc_external_port;
1288 uint32_t enc_mcdi_max_payload_length;
1289 /* VPD may be per-PF or global */
1290 boolean_t enc_vpd_is_global;
1291 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1292 uint32_t enc_required_pcie_bandwidth_mbps;
1293 uint32_t enc_max_pcie_link_gen;
1294 /* Firmware verifies integrity of NVRAM updates */
1295 uint32_t enc_nvram_update_verify_result_supported;
1296 /* Firmware support for extended MAC_STATS buffer */
1297 uint32_t enc_mac_stats_nstats;
1298 boolean_t enc_fec_counters;
1299 boolean_t enc_hlb_counters;
1300 /* Firmware support for "FLAG" and "MARK" filter actions */
1301 boolean_t enc_filter_action_flag_supported;
1302 boolean_t enc_filter_action_mark_supported;
1303 uint32_t enc_filter_action_mark_max;
1306 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1307 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1309 #define EFX_PCI_FUNCTION(_encp) \
1310 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1312 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1314 extern const efx_nic_cfg_t *
1316 __in efx_nic_t *enp);
1318 /* RxDPCPU firmware id values by which FW variant can be identified */
1319 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1320 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1321 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1322 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1323 #define EFX_RXDP_DPDK_FW_ID 0x6
1325 typedef struct efx_nic_fw_info_s {
1326 /* Basic FW version information */
1327 uint16_t enfi_mc_fw_version[4];
1329 * If datapath capabilities can be detected,
1330 * additional FW information is to be shown
1332 boolean_t enfi_dpcpu_fw_ids_valid;
1333 /* Rx and Tx datapath CPU FW IDs */
1334 uint16_t enfi_rx_dpcpu_fw_id;
1335 uint16_t enfi_tx_dpcpu_fw_id;
1336 } efx_nic_fw_info_t;
1338 extern __checkReturn efx_rc_t
1339 efx_nic_get_fw_version(
1340 __in efx_nic_t *enp,
1341 __out efx_nic_fw_info_t *enfip);
1343 /* Driver resource limits (minimum required/maximum usable). */
1344 typedef struct efx_drv_limits_s {
1345 uint32_t edl_min_evq_count;
1346 uint32_t edl_max_evq_count;
1348 uint32_t edl_min_rxq_count;
1349 uint32_t edl_max_rxq_count;
1351 uint32_t edl_min_txq_count;
1352 uint32_t edl_max_txq_count;
1354 /* PIO blocks (sub-allocated from piobuf) */
1355 uint32_t edl_min_pio_alloc_size;
1356 uint32_t edl_max_pio_alloc_count;
1359 extern __checkReturn efx_rc_t
1360 efx_nic_set_drv_limits(
1361 __inout efx_nic_t *enp,
1362 __in efx_drv_limits_t *edlp);
1364 typedef enum efx_nic_region_e {
1365 EFX_REGION_VI, /* Memory BAR UC mapping */
1366 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1369 extern __checkReturn efx_rc_t
1370 efx_nic_get_bar_region(
1371 __in efx_nic_t *enp,
1372 __in efx_nic_region_t region,
1373 __out uint32_t *offsetp,
1374 __out size_t *sizep);
1376 extern __checkReturn efx_rc_t
1377 efx_nic_get_vi_pool(
1378 __in efx_nic_t *enp,
1379 __out uint32_t *evq_countp,
1380 __out uint32_t *rxq_countp,
1381 __out uint32_t *txq_countp);
1386 typedef enum efx_vpd_tag_e {
1393 typedef uint16_t efx_vpd_keyword_t;
1395 typedef struct efx_vpd_value_s {
1396 efx_vpd_tag_t evv_tag;
1397 efx_vpd_keyword_t evv_keyword;
1399 uint8_t evv_value[0x100];
1403 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1405 extern __checkReturn efx_rc_t
1407 __in efx_nic_t *enp);
1409 extern __checkReturn efx_rc_t
1411 __in efx_nic_t *enp,
1412 __out size_t *sizep);
1414 extern __checkReturn efx_rc_t
1416 __in efx_nic_t *enp,
1417 __out_bcount(size) caddr_t data,
1420 extern __checkReturn efx_rc_t
1422 __in efx_nic_t *enp,
1423 __in_bcount(size) caddr_t data,
1426 extern __checkReturn efx_rc_t
1428 __in efx_nic_t *enp,
1429 __in_bcount(size) caddr_t data,
1432 extern __checkReturn efx_rc_t
1434 __in efx_nic_t *enp,
1435 __in_bcount(size) caddr_t data,
1437 __inout efx_vpd_value_t *evvp);
1439 extern __checkReturn efx_rc_t
1441 __in efx_nic_t *enp,
1442 __inout_bcount(size) caddr_t data,
1444 __in efx_vpd_value_t *evvp);
1446 extern __checkReturn efx_rc_t
1448 __in efx_nic_t *enp,
1449 __inout_bcount(size) caddr_t data,
1451 __out efx_vpd_value_t *evvp,
1452 __inout unsigned int *contp);
1454 extern __checkReturn efx_rc_t
1456 __in efx_nic_t *enp,
1457 __in_bcount(size) caddr_t data,
1462 __in efx_nic_t *enp);
1464 #endif /* EFSYS_OPT_VPD */
1470 typedef enum efx_nvram_type_e {
1471 EFX_NVRAM_INVALID = 0,
1473 EFX_NVRAM_BOOTROM_CFG,
1474 EFX_NVRAM_MC_FIRMWARE,
1475 EFX_NVRAM_MC_GOLDEN,
1481 EFX_NVRAM_FPGA_BACKUP,
1482 EFX_NVRAM_DYNAMIC_CFG,
1485 EFX_NVRAM_MUM_FIRMWARE,
1486 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1487 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1491 extern __checkReturn efx_rc_t
1493 __in efx_nic_t *enp);
1497 extern __checkReturn efx_rc_t
1499 __in efx_nic_t *enp);
1501 #endif /* EFSYS_OPT_DIAG */
1503 extern __checkReturn efx_rc_t
1505 __in efx_nic_t *enp,
1506 __in efx_nvram_type_t type,
1507 __out size_t *sizep);
1509 extern __checkReturn efx_rc_t
1511 __in efx_nic_t *enp,
1512 __in efx_nvram_type_t type,
1513 __out_opt size_t *pref_chunkp);
1515 extern __checkReturn efx_rc_t
1516 efx_nvram_rw_finish(
1517 __in efx_nic_t *enp,
1518 __in efx_nvram_type_t type,
1519 __out_opt uint32_t *verify_resultp);
1521 extern __checkReturn efx_rc_t
1522 efx_nvram_get_version(
1523 __in efx_nic_t *enp,
1524 __in efx_nvram_type_t type,
1525 __out uint32_t *subtypep,
1526 __out_ecount(4) uint16_t version[4]);
1528 extern __checkReturn efx_rc_t
1529 efx_nvram_read_chunk(
1530 __in efx_nic_t *enp,
1531 __in efx_nvram_type_t type,
1532 __in unsigned int offset,
1533 __out_bcount(size) caddr_t data,
1536 extern __checkReturn efx_rc_t
1537 efx_nvram_read_backup(
1538 __in efx_nic_t *enp,
1539 __in efx_nvram_type_t type,
1540 __in unsigned int offset,
1541 __out_bcount(size) caddr_t data,
1544 extern __checkReturn efx_rc_t
1545 efx_nvram_set_version(
1546 __in efx_nic_t *enp,
1547 __in efx_nvram_type_t type,
1548 __in_ecount(4) uint16_t version[4]);
1550 extern __checkReturn efx_rc_t
1552 __in efx_nic_t *enp,
1553 __in efx_nvram_type_t type,
1554 __in_bcount(partn_size) caddr_t partn_data,
1555 __in size_t partn_size);
1557 extern __checkReturn efx_rc_t
1559 __in efx_nic_t *enp,
1560 __in efx_nvram_type_t type);
1562 extern __checkReturn efx_rc_t
1563 efx_nvram_write_chunk(
1564 __in efx_nic_t *enp,
1565 __in efx_nvram_type_t type,
1566 __in unsigned int offset,
1567 __in_bcount(size) caddr_t data,
1572 __in efx_nic_t *enp);
1574 #endif /* EFSYS_OPT_NVRAM */
1576 #if EFSYS_OPT_BOOTCFG
1578 /* Report size and offset of bootcfg sector in NVRAM partition. */
1579 extern __checkReturn efx_rc_t
1580 efx_bootcfg_sector_info(
1581 __in efx_nic_t *enp,
1583 __out_opt uint32_t *sector_countp,
1584 __out size_t *offsetp,
1585 __out size_t *max_sizep);
1588 * Copy bootcfg sector data to a target buffer which may differ in size.
1589 * Optionally corrects format errors in source buffer.
1592 efx_bootcfg_copy_sector(
1593 __in efx_nic_t *enp,
1594 __inout_bcount(sector_length)
1596 __in size_t sector_length,
1597 __out_bcount(data_size) uint8_t *data,
1598 __in size_t data_size,
1599 __in boolean_t handle_format_errors);
1603 __in efx_nic_t *enp,
1604 __out_bcount(size) uint8_t *data,
1609 __in efx_nic_t *enp,
1610 __in_bcount(size) uint8_t *data,
1613 #endif /* EFSYS_OPT_BOOTCFG */
1615 #if EFSYS_OPT_IMAGE_LAYOUT
1617 #include "ef10_signed_image_layout.h"
1620 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1623 * The image header format is extensible. However, older drivers require an
1624 * exact match of image header version and header length when validating and
1625 * writing firmware images.
1627 * To avoid breaking backward compatibility, we use the upper bits of the
1628 * controller version fields to contain an extra version number used for
1629 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1630 * version). See bug39254 and SF-102785-PS for details.
1632 typedef struct efx_image_header_s {
1634 uint32_t eih_version;
1636 uint32_t eih_subtype;
1637 uint32_t eih_code_size;
1640 uint32_t eih_controller_version_min;
1642 uint16_t eih_controller_version_min_short;
1643 uint8_t eih_extra_version_a;
1644 uint8_t eih_extra_version_b;
1648 uint32_t eih_controller_version_max;
1650 uint16_t eih_controller_version_max_short;
1651 uint8_t eih_extra_version_c;
1652 uint8_t eih_extra_version_d;
1655 uint16_t eih_code_version_a;
1656 uint16_t eih_code_version_b;
1657 uint16_t eih_code_version_c;
1658 uint16_t eih_code_version_d;
1659 } efx_image_header_t;
1661 #define EFX_IMAGE_HEADER_SIZE (40)
1662 #define EFX_IMAGE_HEADER_VERSION (4)
1663 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1666 typedef struct efx_image_trailer_s {
1668 } efx_image_trailer_t;
1670 #define EFX_IMAGE_TRAILER_SIZE (4)
1672 typedef enum efx_image_format_e {
1673 EFX_IMAGE_FORMAT_NO_IMAGE,
1674 EFX_IMAGE_FORMAT_INVALID,
1675 EFX_IMAGE_FORMAT_UNSIGNED,
1676 EFX_IMAGE_FORMAT_SIGNED,
1677 } efx_image_format_t;
1679 typedef struct efx_image_info_s {
1680 efx_image_format_t eii_format;
1681 uint8_t * eii_imagep;
1682 size_t eii_image_size;
1683 efx_image_header_t * eii_headerp;
1686 extern __checkReturn efx_rc_t
1687 efx_check_reflash_image(
1689 __in uint32_t buffer_size,
1690 __out efx_image_info_t *infop);
1692 extern __checkReturn efx_rc_t
1693 efx_build_signed_image_write_buffer(
1694 __out_bcount(buffer_size)
1696 __in uint32_t buffer_size,
1697 __in efx_image_info_t *infop,
1698 __out efx_image_header_t **headerpp);
1700 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1704 typedef enum efx_pattern_type_t {
1705 EFX_PATTERN_BYTE_INCREMENT = 0,
1706 EFX_PATTERN_ALL_THE_SAME,
1707 EFX_PATTERN_BIT_ALTERNATE,
1708 EFX_PATTERN_BYTE_ALTERNATE,
1709 EFX_PATTERN_BYTE_CHANGING,
1710 EFX_PATTERN_BIT_SWEEP,
1712 } efx_pattern_type_t;
1715 (*efx_sram_pattern_fn_t)(
1717 __in boolean_t negate,
1718 __out efx_qword_t *eqp);
1720 extern __checkReturn efx_rc_t
1722 __in efx_nic_t *enp,
1723 __in efx_pattern_type_t type);
1725 #endif /* EFSYS_OPT_DIAG */
1727 extern __checkReturn efx_rc_t
1728 efx_sram_buf_tbl_set(
1729 __in efx_nic_t *enp,
1731 __in efsys_mem_t *esmp,
1735 efx_sram_buf_tbl_clear(
1736 __in efx_nic_t *enp,
1740 #define EFX_BUF_TBL_SIZE 0x20000
1742 #define EFX_BUF_SIZE 4096
1746 typedef struct efx_evq_s efx_evq_t;
1748 #if EFSYS_OPT_QSTATS
1750 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1751 typedef enum efx_ev_qstat_e {
1757 EV_RX_PAUSE_FRM_ERR,
1758 EV_RX_BUF_OWNER_ID_ERR,
1759 EV_RX_IPV4_HDR_CHKSUM_ERR,
1760 EV_RX_TCP_UDP_CHKSUM_ERR,
1764 EV_RX_MCAST_HASH_MATCH,
1781 EV_DRIVER_SRM_UPD_DONE,
1782 EV_DRIVER_TX_DESCQ_FLS_DONE,
1783 EV_DRIVER_RX_DESCQ_FLS_DONE,
1784 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1785 EV_DRIVER_RX_DSC_ERROR,
1786 EV_DRIVER_TX_DSC_ERROR,
1792 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1794 #endif /* EFSYS_OPT_QSTATS */
1796 extern __checkReturn efx_rc_t
1798 __in efx_nic_t *enp);
1802 __in efx_nic_t *enp);
1804 #define EFX_EVQ_MAXNEVS 32768
1805 #define EFX_EVQ_MINNEVS 512
1807 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1808 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1810 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1811 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1812 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1813 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1815 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1816 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1817 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1819 extern __checkReturn efx_rc_t
1821 __in efx_nic_t *enp,
1822 __in unsigned int index,
1823 __in efsys_mem_t *esmp,
1827 __in uint32_t flags,
1828 __deref_out efx_evq_t **eepp);
1832 __in efx_evq_t *eep,
1833 __in uint16_t data);
1835 typedef __checkReturn boolean_t
1836 (*efx_initialized_ev_t)(
1837 __in_opt void *arg);
1839 #define EFX_PKT_UNICAST 0x0004
1840 #define EFX_PKT_START 0x0008
1842 #define EFX_PKT_VLAN_TAGGED 0x0010
1843 #define EFX_CKSUM_TCPUDP 0x0020
1844 #define EFX_CKSUM_IPV4 0x0040
1845 #define EFX_PKT_CONT 0x0080
1847 #define EFX_CHECK_VLAN 0x0100
1848 #define EFX_PKT_TCP 0x0200
1849 #define EFX_PKT_UDP 0x0400
1850 #define EFX_PKT_IPV4 0x0800
1852 #define EFX_PKT_IPV6 0x1000
1853 #define EFX_PKT_PREFIX_LEN 0x2000
1854 #define EFX_ADDR_MISMATCH 0x4000
1855 #define EFX_DISCARD 0x8000
1858 * The following flags are used only for packed stream
1859 * mode. The values for the flags are reused to fit into 16 bit,
1860 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1861 * packed stream mode
1863 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1864 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1867 #define EFX_EV_RX_NLABELS 32
1868 #define EFX_EV_TX_NLABELS 32
1870 typedef __checkReturn boolean_t
1873 __in uint32_t label,
1876 __in uint16_t flags);
1878 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1881 * Packed stream mode is documented in SF-112241-TC.
1882 * The general idea is that, instead of putting each incoming
1883 * packet into a separate buffer which is specified in a RX
1884 * descriptor, a large buffer is provided to the hardware and
1885 * packets are put there in a continuous stream.
1886 * The main advantage of such an approach is that RX queue refilling
1887 * happens much less frequently.
1889 * Equal stride packed stream mode is documented in SF-119419-TC.
1890 * The general idea is to utilize advantages of the packed stream,
1891 * but avoid indirection in packets representation.
1892 * The main advantage of such an approach is that RX queue refilling
1893 * happens much less frequently and packets buffers are independent
1894 * from upper layers point of view.
1897 typedef __checkReturn boolean_t
1900 __in uint32_t label,
1902 __in uint32_t pkt_count,
1903 __in uint16_t flags);
1907 typedef __checkReturn boolean_t
1910 __in uint32_t label,
1913 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1914 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1915 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1916 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1917 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1918 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1919 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1920 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1921 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1923 typedef __checkReturn boolean_t
1924 (*efx_exception_ev_t)(
1926 __in uint32_t label,
1927 __in uint32_t data);
1929 typedef __checkReturn boolean_t
1930 (*efx_rxq_flush_done_ev_t)(
1932 __in uint32_t rxq_index);
1934 typedef __checkReturn boolean_t
1935 (*efx_rxq_flush_failed_ev_t)(
1937 __in uint32_t rxq_index);
1939 typedef __checkReturn boolean_t
1940 (*efx_txq_flush_done_ev_t)(
1942 __in uint32_t txq_index);
1944 typedef __checkReturn boolean_t
1945 (*efx_software_ev_t)(
1947 __in uint16_t magic);
1949 typedef __checkReturn boolean_t
1952 __in uint32_t code);
1954 #define EFX_SRAM_CLEAR 0
1955 #define EFX_SRAM_UPDATE 1
1956 #define EFX_SRAM_ILLEGAL_CLEAR 2
1958 typedef __checkReturn boolean_t
1959 (*efx_wake_up_ev_t)(
1961 __in uint32_t label);
1963 typedef __checkReturn boolean_t
1966 __in uint32_t label);
1968 typedef __checkReturn boolean_t
1969 (*efx_link_change_ev_t)(
1971 __in efx_link_mode_t link_mode);
1973 #if EFSYS_OPT_MON_STATS
1975 typedef __checkReturn boolean_t
1976 (*efx_monitor_ev_t)(
1978 __in efx_mon_stat_t id,
1979 __in efx_mon_stat_value_t value);
1981 #endif /* EFSYS_OPT_MON_STATS */
1983 #if EFSYS_OPT_MAC_STATS
1985 typedef __checkReturn boolean_t
1986 (*efx_mac_stats_ev_t)(
1988 __in uint32_t generation);
1990 #endif /* EFSYS_OPT_MAC_STATS */
1992 typedef struct efx_ev_callbacks_s {
1993 efx_initialized_ev_t eec_initialized;
1995 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1996 efx_rx_ps_ev_t eec_rx_ps;
1999 efx_exception_ev_t eec_exception;
2000 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2001 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2002 efx_txq_flush_done_ev_t eec_txq_flush_done;
2003 efx_software_ev_t eec_software;
2004 efx_sram_ev_t eec_sram;
2005 efx_wake_up_ev_t eec_wake_up;
2006 efx_timer_ev_t eec_timer;
2007 efx_link_change_ev_t eec_link_change;
2008 #if EFSYS_OPT_MON_STATS
2009 efx_monitor_ev_t eec_monitor;
2010 #endif /* EFSYS_OPT_MON_STATS */
2011 #if EFSYS_OPT_MAC_STATS
2012 efx_mac_stats_ev_t eec_mac_stats;
2013 #endif /* EFSYS_OPT_MAC_STATS */
2014 } efx_ev_callbacks_t;
2016 extern __checkReturn boolean_t
2018 __in efx_evq_t *eep,
2019 __in unsigned int count);
2021 #if EFSYS_OPT_EV_PREFETCH
2025 __in efx_evq_t *eep,
2026 __in unsigned int count);
2028 #endif /* EFSYS_OPT_EV_PREFETCH */
2032 __in efx_evq_t *eep,
2033 __inout unsigned int *countp,
2034 __in const efx_ev_callbacks_t *eecp,
2035 __in_opt void *arg);
2037 extern __checkReturn efx_rc_t
2038 efx_ev_usecs_to_ticks(
2039 __in efx_nic_t *enp,
2040 __in unsigned int usecs,
2041 __out unsigned int *ticksp);
2043 extern __checkReturn efx_rc_t
2045 __in efx_evq_t *eep,
2046 __in unsigned int us);
2048 extern __checkReturn efx_rc_t
2050 __in efx_evq_t *eep,
2051 __in unsigned int count);
2053 #if EFSYS_OPT_QSTATS
2059 __in efx_nic_t *enp,
2060 __in unsigned int id);
2062 #endif /* EFSYS_OPT_NAMES */
2065 efx_ev_qstats_update(
2066 __in efx_evq_t *eep,
2067 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2069 #endif /* EFSYS_OPT_QSTATS */
2073 __in efx_evq_t *eep);
2077 extern __checkReturn efx_rc_t
2079 __inout efx_nic_t *enp);
2083 __in efx_nic_t *enp);
2085 #if EFSYS_OPT_RX_SCATTER
2086 __checkReturn efx_rc_t
2087 efx_rx_scatter_enable(
2088 __in efx_nic_t *enp,
2089 __in unsigned int buf_size);
2090 #endif /* EFSYS_OPT_RX_SCATTER */
2092 /* Handle to represent use of the default RSS context. */
2093 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2095 #if EFSYS_OPT_RX_SCALE
2097 typedef enum efx_rx_hash_alg_e {
2098 EFX_RX_HASHALG_LFSR = 0,
2099 EFX_RX_HASHALG_TOEPLITZ,
2100 EFX_RX_HASHALG_PACKED_STREAM,
2102 } efx_rx_hash_alg_t;
2105 * Legacy hash type flags.
2107 * They represent standard tuples for distinct traffic classes.
2109 #define EFX_RX_HASH_IPV4 (1U << 0)
2110 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2111 #define EFX_RX_HASH_IPV6 (1U << 2)
2112 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2114 #define EFX_RX_HASH_LEGACY_MASK \
2115 (EFX_RX_HASH_IPV4 | \
2116 EFX_RX_HASH_TCPIPV4 | \
2117 EFX_RX_HASH_IPV6 | \
2118 EFX_RX_HASH_TCPIPV6)
2121 * The type of the argument used by efx_rx_scale_mode_set() to
2122 * provide a means for the client drivers to configure hashing.
2124 * A properly constructed value can either be:
2125 * - a combination of legacy flags
2126 * - a combination of EFX_RX_HASH() flags
2128 typedef unsigned int efx_rx_hash_type_t;
2130 typedef enum efx_rx_hash_support_e {
2131 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2132 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2133 } efx_rx_hash_support_t;
2135 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2136 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2137 #define EFX_MAXRSS 64 /* RX indirection entry range */
2138 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2140 typedef enum efx_rx_scale_context_type_e {
2141 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2142 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2143 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2144 } efx_rx_scale_context_type_t;
2147 * Traffic classes eligible for hash computation.
2149 * Select packet headers used in computing the receive hash.
2150 * This uses the same encoding as the RSS_MODES field of
2151 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2153 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2154 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2155 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2156 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2157 #define EFX_RX_CLASS_IPV4_LBN 16
2158 #define EFX_RX_CLASS_IPV4_WIDTH 4
2159 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2160 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2161 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2162 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2163 #define EFX_RX_CLASS_IPV6_LBN 28
2164 #define EFX_RX_CLASS_IPV6_WIDTH 4
2166 #define EFX_RX_NCLASSES 6
2169 * Ancillary flags used to construct generic hash tuples.
2170 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2172 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2173 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2174 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2175 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2178 * Generic hash tuples.
2180 * They express combinations of packet fields
2181 * which can contribute to the hash value for
2182 * a particular traffic class.
2184 #define EFX_RX_CLASS_HASH_DISABLE 0
2186 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2187 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2189 #define EFX_RX_CLASS_HASH_2TUPLE \
2190 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2191 EFX_RX_CLASS_HASH_DST_ADDR)
2193 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2194 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2195 EFX_RX_CLASS_HASH_SRC_PORT)
2197 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2198 (EFX_RX_CLASS_HASH_DST_ADDR | \
2199 EFX_RX_CLASS_HASH_DST_PORT)
2201 #define EFX_RX_CLASS_HASH_4TUPLE \
2202 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2203 EFX_RX_CLASS_HASH_DST_ADDR | \
2204 EFX_RX_CLASS_HASH_SRC_PORT | \
2205 EFX_RX_CLASS_HASH_DST_PORT)
2207 #define EFX_RX_CLASS_HASH_NTUPLES 7
2210 * Hash flag constructor.
2212 * Resulting flags encode hash tuples for specific traffic classes.
2213 * The client drivers are encouraged to use these flags to form
2214 * a hash type value.
2216 #define EFX_RX_HASH(_class, _tuple) \
2217 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2218 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2221 * The maximum number of EFX_RX_HASH() flags.
2223 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2225 extern __checkReturn efx_rc_t
2226 efx_rx_scale_hash_flags_get(
2227 __in efx_nic_t *enp,
2228 __in efx_rx_hash_alg_t hash_alg,
2229 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
2230 __out unsigned int *nflagsp);
2232 extern __checkReturn efx_rc_t
2233 efx_rx_hash_default_support_get(
2234 __in efx_nic_t *enp,
2235 __out efx_rx_hash_support_t *supportp);
2238 extern __checkReturn efx_rc_t
2239 efx_rx_scale_default_support_get(
2240 __in efx_nic_t *enp,
2241 __out efx_rx_scale_context_type_t *typep);
2243 extern __checkReturn efx_rc_t
2244 efx_rx_scale_context_alloc(
2245 __in efx_nic_t *enp,
2246 __in efx_rx_scale_context_type_t type,
2247 __in uint32_t num_queues,
2248 __out uint32_t *rss_contextp);
2250 extern __checkReturn efx_rc_t
2251 efx_rx_scale_context_free(
2252 __in efx_nic_t *enp,
2253 __in uint32_t rss_context);
2255 extern __checkReturn efx_rc_t
2256 efx_rx_scale_mode_set(
2257 __in efx_nic_t *enp,
2258 __in uint32_t rss_context,
2259 __in efx_rx_hash_alg_t alg,
2260 __in efx_rx_hash_type_t type,
2261 __in boolean_t insert);
2263 extern __checkReturn efx_rc_t
2264 efx_rx_scale_tbl_set(
2265 __in efx_nic_t *enp,
2266 __in uint32_t rss_context,
2267 __in_ecount(n) unsigned int *table,
2270 extern __checkReturn efx_rc_t
2271 efx_rx_scale_key_set(
2272 __in efx_nic_t *enp,
2273 __in uint32_t rss_context,
2274 __in_ecount(n) uint8_t *key,
2277 extern __checkReturn uint32_t
2278 efx_pseudo_hdr_hash_get(
2279 __in efx_rxq_t *erp,
2280 __in efx_rx_hash_alg_t func,
2281 __in uint8_t *buffer);
2283 #endif /* EFSYS_OPT_RX_SCALE */
2285 extern __checkReturn efx_rc_t
2286 efx_pseudo_hdr_pkt_length_get(
2287 __in efx_rxq_t *erp,
2288 __in uint8_t *buffer,
2289 __out uint16_t *pkt_lengthp);
2291 #define EFX_RXQ_MAXNDESCS 4096
2292 #define EFX_RXQ_MINNDESCS 512
2294 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2295 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2296 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2297 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2299 typedef enum efx_rxq_type_e {
2300 EFX_RXQ_TYPE_DEFAULT,
2301 EFX_RXQ_TYPE_PACKED_STREAM,
2302 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2307 * Dummy flag to be used instead of 0 to make it clear that the argument
2308 * is receive queue flags.
2310 #define EFX_RXQ_FLAG_NONE 0x0
2311 #define EFX_RXQ_FLAG_SCATTER 0x1
2313 * If tunnels are supported and Rx event can provide information about
2314 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2315 * full-feature firmware variant running), outer classes are requested by
2316 * default. However, if the driver supports tunnels, the flag allows to
2317 * request inner classes which are required to be able to interpret inner
2318 * Rx checksum offload results.
2320 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2322 extern __checkReturn efx_rc_t
2324 __in efx_nic_t *enp,
2325 __in unsigned int index,
2326 __in unsigned int label,
2327 __in efx_rxq_type_t type,
2328 __in efsys_mem_t *esmp,
2331 __in unsigned int flags,
2332 __in efx_evq_t *eep,
2333 __deref_out efx_rxq_t **erpp);
2335 #if EFSYS_OPT_RX_PACKED_STREAM
2337 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2338 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2339 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2340 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2341 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2343 extern __checkReturn efx_rc_t
2344 efx_rx_qcreate_packed_stream(
2345 __in efx_nic_t *enp,
2346 __in unsigned int index,
2347 __in unsigned int label,
2348 __in uint32_t ps_buf_size,
2349 __in efsys_mem_t *esmp,
2351 __in efx_evq_t *eep,
2352 __deref_out efx_rxq_t **erpp);
2356 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2358 /* Maximum head-of-line block timeout in nanoseconds */
2359 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2361 extern __checkReturn efx_rc_t
2362 efx_rx_qcreate_es_super_buffer(
2363 __in efx_nic_t *enp,
2364 __in unsigned int index,
2365 __in unsigned int label,
2366 __in uint32_t n_bufs_per_desc,
2367 __in uint32_t max_dma_len,
2368 __in uint32_t buf_stride,
2369 __in uint32_t hol_block_timeout,
2370 __in efsys_mem_t *esmp,
2372 __in unsigned int flags,
2373 __in efx_evq_t *eep,
2374 __deref_out efx_rxq_t **erpp);
2378 typedef struct efx_buffer_s {
2379 efsys_dma_addr_t eb_addr;
2384 typedef struct efx_desc_s {
2390 __in efx_rxq_t *erp,
2391 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2393 __in unsigned int ndescs,
2394 __in unsigned int completed,
2395 __in unsigned int added);
2399 __in efx_rxq_t *erp,
2400 __in unsigned int added,
2401 __inout unsigned int *pushedp);
2403 #if EFSYS_OPT_RX_PACKED_STREAM
2406 efx_rx_qpush_ps_credits(
2407 __in efx_rxq_t *erp);
2409 extern __checkReturn uint8_t *
2410 efx_rx_qps_packet_info(
2411 __in efx_rxq_t *erp,
2412 __in uint8_t *buffer,
2413 __in uint32_t buffer_length,
2414 __in uint32_t current_offset,
2415 __out uint16_t *lengthp,
2416 __out uint32_t *next_offsetp,
2417 __out uint32_t *timestamp);
2420 extern __checkReturn efx_rc_t
2422 __in efx_rxq_t *erp);
2426 __in efx_rxq_t *erp);
2430 __in efx_rxq_t *erp);
2434 typedef struct efx_txq_s efx_txq_t;
2436 #if EFSYS_OPT_QSTATS
2438 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2439 typedef enum efx_tx_qstat_e {
2445 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2447 #endif /* EFSYS_OPT_QSTATS */
2449 extern __checkReturn efx_rc_t
2451 __in efx_nic_t *enp);
2455 __in efx_nic_t *enp);
2457 #define EFX_TXQ_MINNDESCS 512
2459 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2460 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2461 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2463 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2465 #define EFX_TXQ_CKSUM_IPV4 0x0001
2466 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2467 #define EFX_TXQ_FATSOV2 0x0004
2468 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2469 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2471 extern __checkReturn efx_rc_t
2473 __in efx_nic_t *enp,
2474 __in unsigned int index,
2475 __in unsigned int label,
2476 __in efsys_mem_t *esmp,
2479 __in uint16_t flags,
2480 __in efx_evq_t *eep,
2481 __deref_out efx_txq_t **etpp,
2482 __out unsigned int *addedp);
2484 extern __checkReturn efx_rc_t
2486 __in efx_txq_t *etp,
2487 __in_ecount(ndescs) efx_buffer_t *eb,
2488 __in unsigned int ndescs,
2489 __in unsigned int completed,
2490 __inout unsigned int *addedp);
2492 extern __checkReturn efx_rc_t
2494 __in efx_txq_t *etp,
2495 __in unsigned int ns);
2499 __in efx_txq_t *etp,
2500 __in unsigned int added,
2501 __in unsigned int pushed);
2503 extern __checkReturn efx_rc_t
2505 __in efx_txq_t *etp);
2509 __in efx_txq_t *etp);
2511 extern __checkReturn efx_rc_t
2513 __in efx_txq_t *etp);
2516 efx_tx_qpio_disable(
2517 __in efx_txq_t *etp);
2519 extern __checkReturn efx_rc_t
2521 __in efx_txq_t *etp,
2522 __in_ecount(buf_length) uint8_t *buffer,
2523 __in size_t buf_length,
2524 __in size_t pio_buf_offset);
2526 extern __checkReturn efx_rc_t
2528 __in efx_txq_t *etp,
2529 __in size_t pkt_length,
2530 __in unsigned int completed,
2531 __inout unsigned int *addedp);
2533 extern __checkReturn efx_rc_t
2535 __in efx_txq_t *etp,
2536 __in_ecount(n) efx_desc_t *ed,
2537 __in unsigned int n,
2538 __in unsigned int completed,
2539 __inout unsigned int *addedp);
2542 efx_tx_qdesc_dma_create(
2543 __in efx_txq_t *etp,
2544 __in efsys_dma_addr_t addr,
2547 __out efx_desc_t *edp);
2550 efx_tx_qdesc_tso_create(
2551 __in efx_txq_t *etp,
2552 __in uint16_t ipv4_id,
2553 __in uint32_t tcp_seq,
2554 __in uint8_t tcp_flags,
2555 __out efx_desc_t *edp);
2557 /* Number of FATSOv2 option descriptors */
2558 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2560 /* Maximum number of DMA segments per TSO packet (not superframe) */
2561 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2564 efx_tx_qdesc_tso2_create(
2565 __in efx_txq_t *etp,
2566 __in uint16_t ipv4_id,
2567 __in uint16_t outer_ipv4_id,
2568 __in uint32_t tcp_seq,
2569 __in uint16_t tcp_mss,
2570 __out_ecount(count) efx_desc_t *edp,
2574 efx_tx_qdesc_vlantci_create(
2575 __in efx_txq_t *etp,
2577 __out efx_desc_t *edp);
2580 efx_tx_qdesc_checksum_create(
2581 __in efx_txq_t *etp,
2582 __in uint16_t flags,
2583 __out efx_desc_t *edp);
2585 #if EFSYS_OPT_QSTATS
2591 __in efx_nic_t *etp,
2592 __in unsigned int id);
2594 #endif /* EFSYS_OPT_NAMES */
2597 efx_tx_qstats_update(
2598 __in efx_txq_t *etp,
2599 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2601 #endif /* EFSYS_OPT_QSTATS */
2605 __in efx_txq_t *etp);
2610 #if EFSYS_OPT_FILTER
2612 #define EFX_ETHER_TYPE_IPV4 0x0800
2613 #define EFX_ETHER_TYPE_IPV6 0x86DD
2615 #define EFX_IPPROTO_TCP 6
2616 #define EFX_IPPROTO_UDP 17
2617 #define EFX_IPPROTO_GRE 47
2619 /* Use RSS to spread across multiple queues */
2620 #define EFX_FILTER_FLAG_RX_RSS 0x01
2621 /* Enable RX scatter */
2622 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2624 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2625 * May only be set by the filter implementation for each type.
2626 * A removal request will restore the automatic filter in its place.
2628 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2629 /* Filter is for RX */
2630 #define EFX_FILTER_FLAG_RX 0x08
2631 /* Filter is for TX */
2632 #define EFX_FILTER_FLAG_TX 0x10
2633 /* Set match flag on the received packet */
2634 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2635 /* Set match mark on the received packet */
2636 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2638 typedef uint8_t efx_filter_flags_t;
2641 * Flags which specify the fields to match on. The values are the same as in the
2642 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2645 /* Match by remote IP host address */
2646 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2647 /* Match by local IP host address */
2648 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2649 /* Match by remote MAC address */
2650 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2651 /* Match by remote TCP/UDP port */
2652 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2653 /* Match by remote TCP/UDP port */
2654 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2655 /* Match by local TCP/UDP port */
2656 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2657 /* Match by Ether-type */
2658 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2659 /* Match by inner VLAN ID */
2660 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2661 /* Match by outer VLAN ID */
2662 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2663 /* Match by IP transport protocol */
2664 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2665 /* Match by VNI or VSID */
2666 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2667 /* For encapsulated packets, match by inner frame local MAC address */
2668 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2669 /* For encapsulated packets, match all multicast inner frames */
2670 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2671 /* For encapsulated packets, match all unicast inner frames */
2672 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2674 * Match by encap type, this flag does not correspond to
2675 * the MCDI match flags and any unoccupied value may be used
2677 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2678 /* Match otherwise-unmatched multicast and broadcast packets */
2679 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2680 /* Match otherwise-unmatched unicast packets */
2681 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2683 typedef uint32_t efx_filter_match_flags_t;
2685 typedef enum efx_filter_priority_s {
2686 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2687 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2688 * address list or hardware
2689 * requirements. This may only be used
2690 * by the filter implementation for
2692 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2693 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2694 * client (e.g. SR-IOV, HyperV VMQ etc.)
2696 } efx_filter_priority_t;
2699 * FIXME: All these fields are assumed to be in little-endian byte order.
2700 * It may be better for some to be big-endian. See bug42804.
2703 typedef struct efx_filter_spec_s {
2704 efx_filter_match_flags_t efs_match_flags;
2705 uint8_t efs_priority;
2706 efx_filter_flags_t efs_flags;
2707 uint16_t efs_dmaq_id;
2708 uint32_t efs_rss_context;
2709 uint16_t efs_outer_vid;
2710 uint16_t efs_inner_vid;
2711 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2712 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2713 uint16_t efs_ether_type;
2714 uint8_t efs_ip_proto;
2715 efx_tunnel_protocol_t efs_encap_type;
2716 uint16_t efs_loc_port;
2717 uint16_t efs_rem_port;
2718 efx_oword_t efs_rem_host;
2719 efx_oword_t efs_loc_host;
2720 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2721 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2723 } efx_filter_spec_t;
2726 /* Default values for use in filter specifications */
2727 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2728 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2730 extern __checkReturn efx_rc_t
2732 __in efx_nic_t *enp);
2736 __in efx_nic_t *enp);
2738 extern __checkReturn efx_rc_t
2740 __in efx_nic_t *enp,
2741 __inout efx_filter_spec_t *spec);
2743 extern __checkReturn efx_rc_t
2745 __in efx_nic_t *enp,
2746 __inout efx_filter_spec_t *spec);
2748 extern __checkReturn efx_rc_t
2750 __in efx_nic_t *enp);
2752 extern __checkReturn efx_rc_t
2753 efx_filter_supported_filters(
2754 __in efx_nic_t *enp,
2755 __out_ecount(buffer_length) uint32_t *buffer,
2756 __in size_t buffer_length,
2757 __out size_t *list_lengthp);
2760 efx_filter_spec_init_rx(
2761 __out efx_filter_spec_t *spec,
2762 __in efx_filter_priority_t priority,
2763 __in efx_filter_flags_t flags,
2764 __in efx_rxq_t *erp);
2767 efx_filter_spec_init_tx(
2768 __out efx_filter_spec_t *spec,
2769 __in efx_txq_t *etp);
2771 extern __checkReturn efx_rc_t
2772 efx_filter_spec_set_ipv4_local(
2773 __inout efx_filter_spec_t *spec,
2776 __in uint16_t port);
2778 extern __checkReturn efx_rc_t
2779 efx_filter_spec_set_ipv4_full(
2780 __inout efx_filter_spec_t *spec,
2782 __in uint32_t lhost,
2783 __in uint16_t lport,
2784 __in uint32_t rhost,
2785 __in uint16_t rport);
2787 extern __checkReturn efx_rc_t
2788 efx_filter_spec_set_eth_local(
2789 __inout efx_filter_spec_t *spec,
2791 __in const uint8_t *addr);
2794 efx_filter_spec_set_ether_type(
2795 __inout efx_filter_spec_t *spec,
2796 __in uint16_t ether_type);
2798 extern __checkReturn efx_rc_t
2799 efx_filter_spec_set_uc_def(
2800 __inout efx_filter_spec_t *spec);
2802 extern __checkReturn efx_rc_t
2803 efx_filter_spec_set_mc_def(
2804 __inout efx_filter_spec_t *spec);
2806 typedef enum efx_filter_inner_frame_match_e {
2807 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2808 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2809 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2810 } efx_filter_inner_frame_match_t;
2812 extern __checkReturn efx_rc_t
2813 efx_filter_spec_set_encap_type(
2814 __inout efx_filter_spec_t *spec,
2815 __in efx_tunnel_protocol_t encap_type,
2816 __in efx_filter_inner_frame_match_t inner_frame_match);
2818 extern __checkReturn efx_rc_t
2819 efx_filter_spec_set_vxlan_full(
2820 __inout efx_filter_spec_t *spec,
2821 __in const uint8_t *vxlan_id,
2822 __in const uint8_t *inner_addr,
2823 __in const uint8_t *outer_addr);
2825 #if EFSYS_OPT_RX_SCALE
2826 extern __checkReturn efx_rc_t
2827 efx_filter_spec_set_rss_context(
2828 __inout efx_filter_spec_t *spec,
2829 __in uint32_t rss_context);
2831 #endif /* EFSYS_OPT_FILTER */
2835 extern __checkReturn uint32_t
2837 __in_ecount(count) uint32_t const *input,
2839 __in uint32_t init);
2841 extern __checkReturn uint32_t
2843 __in_ecount(length) uint8_t const *input,
2845 __in uint32_t init);
2847 #if EFSYS_OPT_LICENSING
2851 typedef struct efx_key_stats_s {
2853 uint32_t eks_invalid;
2854 uint32_t eks_blacklisted;
2855 uint32_t eks_unverifiable;
2856 uint32_t eks_wrong_node;
2857 uint32_t eks_licensed_apps_lo;
2858 uint32_t eks_licensed_apps_hi;
2859 uint32_t eks_licensed_features_lo;
2860 uint32_t eks_licensed_features_hi;
2863 extern __checkReturn efx_rc_t
2865 __in efx_nic_t *enp);
2869 __in efx_nic_t *enp);
2871 extern __checkReturn boolean_t
2872 efx_lic_check_support(
2873 __in efx_nic_t *enp);
2875 extern __checkReturn efx_rc_t
2876 efx_lic_update_licenses(
2877 __in efx_nic_t *enp);
2879 extern __checkReturn efx_rc_t
2880 efx_lic_get_key_stats(
2881 __in efx_nic_t *enp,
2882 __out efx_key_stats_t *ksp);
2884 extern __checkReturn efx_rc_t
2886 __in efx_nic_t *enp,
2887 __in uint64_t app_id,
2888 __out boolean_t *licensedp);
2890 extern __checkReturn efx_rc_t
2892 __in efx_nic_t *enp,
2893 __in size_t buffer_size,
2894 __out uint32_t *typep,
2895 __out size_t *lengthp,
2896 __out_opt uint8_t *bufferp);
2899 extern __checkReturn efx_rc_t
2901 __in efx_nic_t *enp,
2902 __in_bcount(buffer_size)
2904 __in size_t buffer_size,
2905 __out uint32_t *startp);
2907 extern __checkReturn efx_rc_t
2909 __in efx_nic_t *enp,
2910 __in_bcount(buffer_size)
2912 __in size_t buffer_size,
2913 __in uint32_t offset,
2914 __out uint32_t *endp);
2916 extern __checkReturn __success(return != B_FALSE) boolean_t
2918 __in efx_nic_t *enp,
2919 __in_bcount(buffer_size)
2921 __in size_t buffer_size,
2922 __in uint32_t offset,
2923 __out uint32_t *startp,
2924 __out uint32_t *lengthp);
2926 extern __checkReturn __success(return != B_FALSE) boolean_t
2927 efx_lic_validate_key(
2928 __in efx_nic_t *enp,
2929 __in_bcount(length) caddr_t keyp,
2930 __in uint32_t length);
2932 extern __checkReturn efx_rc_t
2934 __in efx_nic_t *enp,
2935 __in_bcount(buffer_size)
2937 __in size_t buffer_size,
2938 __in uint32_t offset,
2939 __in uint32_t length,
2940 __out_bcount_part(key_max_size, *lengthp)
2942 __in size_t key_max_size,
2943 __out uint32_t *lengthp);
2945 extern __checkReturn efx_rc_t
2947 __in efx_nic_t *enp,
2948 __in_bcount(buffer_size)
2950 __in size_t buffer_size,
2951 __in uint32_t offset,
2952 __in_bcount(length) caddr_t keyp,
2953 __in uint32_t length,
2954 __out uint32_t *lengthp);
2956 __checkReturn efx_rc_t
2958 __in efx_nic_t *enp,
2959 __in_bcount(buffer_size)
2961 __in size_t buffer_size,
2962 __in uint32_t offset,
2963 __in uint32_t length,
2965 __out uint32_t *deltap);
2967 extern __checkReturn efx_rc_t
2968 efx_lic_create_partition(
2969 __in efx_nic_t *enp,
2970 __in_bcount(buffer_size)
2972 __in size_t buffer_size);
2974 extern __checkReturn efx_rc_t
2975 efx_lic_finish_partition(
2976 __in efx_nic_t *enp,
2977 __in_bcount(buffer_size)
2979 __in size_t buffer_size);
2981 #endif /* EFSYS_OPT_LICENSING */
2985 #if EFSYS_OPT_TUNNEL
2987 extern __checkReturn efx_rc_t
2989 __in efx_nic_t *enp);
2993 __in efx_nic_t *enp);
2996 * For overlay network encapsulation using UDP, the firmware needs to know
2997 * the configured UDP port for the overlay so it can decode encapsulated
2999 * The UDP port/protocol list is global.
3002 extern __checkReturn efx_rc_t
3003 efx_tunnel_config_udp_add(
3004 __in efx_nic_t *enp,
3005 __in uint16_t port /* host/cpu-endian */,
3006 __in efx_tunnel_protocol_t protocol);
3008 extern __checkReturn efx_rc_t
3009 efx_tunnel_config_udp_remove(
3010 __in efx_nic_t *enp,
3011 __in uint16_t port /* host/cpu-endian */,
3012 __in efx_tunnel_protocol_t protocol);
3015 efx_tunnel_config_clear(
3016 __in efx_nic_t *enp);
3019 * Apply tunnel UDP ports configuration to hardware.
3021 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3024 extern __checkReturn efx_rc_t
3025 efx_tunnel_reconfigure(
3026 __in efx_nic_t *enp);
3028 #endif /* EFSYS_OPT_TUNNEL */
3030 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3033 * Firmware subvariant choice options.
3035 * It may be switched to no Tx checksum if attached drivers are either
3036 * preboot or firmware subvariant aware and no VIS are allocated.
3037 * If may be always switched to default explicitly using set request or
3038 * implicitly if unaware driver is attaching. If switching is done when
3039 * a driver is attached, it gets MC_REBOOT event and should recreate its
3042 * See SF-119419-TC DPDK Firmware Driver Interface and
3043 * SF-109306-TC EF10 for Driver Writers for details.
3045 typedef enum efx_nic_fw_subvariant_e {
3046 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3047 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3048 EFX_NIC_FW_SUBVARIANT_NTYPES
3049 } efx_nic_fw_subvariant_t;
3051 extern __checkReturn efx_rc_t
3052 efx_nic_get_fw_subvariant(
3053 __in efx_nic_t *enp,
3054 __out efx_nic_fw_subvariant_t *subvariantp);
3056 extern __checkReturn efx_rc_t
3057 efx_nic_set_fw_subvariant(
3058 __in efx_nic_t *enp,
3059 __in efx_nic_fw_subvariant_t subvariant);
3061 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3067 #endif /* _SYS_EFX_H */