2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 extern __checkReturn efx_rc_t
152 efx_nic_register_test(
153 __in efx_nic_t *enp);
155 #endif /* EFSYS_OPT_DIAG */
159 __in efx_nic_t *enp);
163 __in efx_nic_t *enp);
167 __in efx_nic_t *enp);
169 #define EFX_PCIE_LINK_SPEED_GEN1 1
170 #define EFX_PCIE_LINK_SPEED_GEN2 2
171 #define EFX_PCIE_LINK_SPEED_GEN3 3
173 typedef enum efx_pcie_link_performance_e {
174 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
175 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
176 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
177 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
178 } efx_pcie_link_performance_t;
180 extern __checkReturn efx_rc_t
181 efx_nic_calculate_pcie_link_bandwidth(
182 __in uint32_t pcie_link_width,
183 __in uint32_t pcie_link_gen,
184 __out uint32_t *bandwidth_mbpsp);
186 extern __checkReturn efx_rc_t
187 efx_nic_check_pcie_link_speed(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out efx_pcie_link_performance_t *resultp);
195 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
196 /* Huntington and Medford require MCDIv2 commands */
197 #define WITH_MCDI_V2 1
200 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
202 typedef enum efx_mcdi_exception_e {
203 EFX_MCDI_EXCEPTION_MC_REBOOT,
204 EFX_MCDI_EXCEPTION_MC_BADASSERT,
205 } efx_mcdi_exception_t;
207 #if EFSYS_OPT_MCDI_LOGGING
208 typedef enum efx_log_msg_e {
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_get_timeout(
246 __in efx_mcdi_req_t *emrp,
247 __out uint32_t *usec_timeoutp);
250 efx_mcdi_request_start(
252 __in efx_mcdi_req_t *emrp,
253 __in boolean_t ev_cpl);
255 extern __checkReturn boolean_t
256 efx_mcdi_request_poll(
257 __in efx_nic_t *enp);
259 extern __checkReturn boolean_t
260 efx_mcdi_request_abort(
261 __in efx_nic_t *enp);
265 __in efx_nic_t *enp);
267 #endif /* EFSYS_OPT_MCDI */
271 #define EFX_NINTR_SIENA 1024
273 typedef enum efx_intr_type_e {
274 EFX_INTR_INVALID = 0,
280 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
282 extern __checkReturn efx_rc_t
285 __in efx_intr_type_t type,
286 __in efsys_mem_t *esmp);
290 __in efx_nic_t *enp);
294 __in efx_nic_t *enp);
297 efx_intr_disable_unlocked(
298 __in efx_nic_t *enp);
300 #define EFX_INTR_NEVQS 32
302 extern __checkReturn efx_rc_t
305 __in unsigned int level);
308 efx_intr_status_line(
310 __out boolean_t *fatalp,
311 __out uint32_t *maskp);
314 efx_intr_status_message(
316 __in unsigned int message,
317 __out boolean_t *fatalp);
321 __in efx_nic_t *enp);
325 __in efx_nic_t *enp);
329 typedef enum efx_link_mode_e {
330 EFX_LINK_UNKNOWN = 0,
343 #define EFX_MAC_ADDR_LEN 6
345 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
347 #define EFX_MAC_MULTICAST_LIST_MAX 256
349 #define EFX_MAC_SDU_MAX 9202
351 #define EFX_MAC_PDU_ADJUSTMENT \
355 + /* bug16011 */ 16) \
357 #define EFX_MAC_PDU(_sdu) \
358 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
361 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
362 * the SDU rounded up slightly.
364 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
366 #define EFX_MAC_PDU_MIN 60
367 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
369 extern __checkReturn efx_rc_t
374 extern __checkReturn efx_rc_t
379 extern __checkReturn efx_rc_t
384 extern __checkReturn efx_rc_t
387 __in boolean_t all_unicst,
388 __in boolean_t mulcst,
389 __in boolean_t all_mulcst,
390 __in boolean_t brdcst);
392 extern __checkReturn efx_rc_t
393 efx_mac_multicast_list_set(
395 __in_ecount(6*count) uint8_t const *addrs,
398 extern __checkReturn efx_rc_t
399 efx_mac_filter_default_rxq_set(
402 __in boolean_t using_rss);
405 efx_mac_filter_default_rxq_clear(
406 __in efx_nic_t *enp);
408 extern __checkReturn efx_rc_t
411 __in boolean_t enabled);
413 extern __checkReturn efx_rc_t
416 __out boolean_t *mac_upp);
418 #define EFX_FCNTL_RESPOND 0x00000001
419 #define EFX_FCNTL_GENERATE 0x00000002
421 extern __checkReturn efx_rc_t
424 __in unsigned int fcntl,
425 __in boolean_t autoneg);
430 __out unsigned int *fcntl_wantedp,
431 __out unsigned int *fcntl_linkp);
436 typedef enum efx_mon_type_e {
448 __in efx_nic_t *enp);
450 #endif /* EFSYS_OPT_NAMES */
452 extern __checkReturn efx_rc_t
454 __in efx_nic_t *enp);
458 __in efx_nic_t *enp);
462 extern __checkReturn efx_rc_t
464 __in efx_nic_t *enp);
466 #if EFSYS_OPT_PHY_LED_CONTROL
468 typedef enum efx_phy_led_mode_e {
469 EFX_PHY_LED_DEFAULT = 0,
474 } efx_phy_led_mode_t;
476 extern __checkReturn efx_rc_t
479 __in efx_phy_led_mode_t mode);
481 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
483 extern __checkReturn efx_rc_t
485 __in efx_nic_t *enp);
487 extern __checkReturn efx_rc_t
490 __out_opt efx_link_mode_t *link_modep);
494 __in efx_nic_t *enp);
496 typedef enum efx_phy_cap_type_e {
497 EFX_PHY_CAP_INVALID = 0,
504 EFX_PHY_CAP_10000FDX,
508 EFX_PHY_CAP_40000FDX,
510 } efx_phy_cap_type_t;
513 #define EFX_PHY_CAP_CURRENT 0x00000000
514 #define EFX_PHY_CAP_DEFAULT 0x00000001
515 #define EFX_PHY_CAP_PERM 0x00000002
521 __out uint32_t *maskp);
523 extern __checkReturn efx_rc_t
531 __out uint32_t *maskp);
533 extern __checkReturn efx_rc_t
536 __out uint32_t *ouip);
538 typedef enum efx_phy_media_type_e {
539 EFX_PHY_MEDIA_INVALID = 0,
544 EFX_PHY_MEDIA_SFP_PLUS,
545 EFX_PHY_MEDIA_BASE_T,
546 EFX_PHY_MEDIA_QSFP_PLUS,
548 } efx_phy_media_type_t;
550 /* Get the type of medium currently used. If the board has ports for
551 * modules, a module is present, and we recognise the media type of
552 * the module, then this will be the media type of the module.
553 * Otherwise it will be the media type of the port.
556 efx_phy_media_type_get(
558 __out efx_phy_media_type_t *typep);
561 efx_phy_module_get_info(
563 __in uint8_t dev_addr,
566 __out_bcount(len) uint8_t *data);
568 #if EFSYS_OPT_PHY_STATS
570 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
571 typedef enum efx_phy_stat_e {
573 EFX_PHY_STAT_PMA_PMD_LINK_UP,
574 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
575 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
576 EFX_PHY_STAT_PMA_PMD_REV_A,
577 EFX_PHY_STAT_PMA_PMD_REV_B,
578 EFX_PHY_STAT_PMA_PMD_REV_C,
579 EFX_PHY_STAT_PMA_PMD_REV_D,
580 EFX_PHY_STAT_PCS_LINK_UP,
581 EFX_PHY_STAT_PCS_RX_FAULT,
582 EFX_PHY_STAT_PCS_TX_FAULT,
583 EFX_PHY_STAT_PCS_BER,
584 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
585 EFX_PHY_STAT_PHY_XS_LINK_UP,
586 EFX_PHY_STAT_PHY_XS_RX_FAULT,
587 EFX_PHY_STAT_PHY_XS_TX_FAULT,
588 EFX_PHY_STAT_PHY_XS_ALIGN,
589 EFX_PHY_STAT_PHY_XS_SYNC_A,
590 EFX_PHY_STAT_PHY_XS_SYNC_B,
591 EFX_PHY_STAT_PHY_XS_SYNC_C,
592 EFX_PHY_STAT_PHY_XS_SYNC_D,
593 EFX_PHY_STAT_AN_LINK_UP,
594 EFX_PHY_STAT_AN_MASTER,
595 EFX_PHY_STAT_AN_LOCAL_RX_OK,
596 EFX_PHY_STAT_AN_REMOTE_RX_OK,
597 EFX_PHY_STAT_CL22EXT_LINK_UP,
602 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
603 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
604 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
605 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
606 EFX_PHY_STAT_AN_COMPLETE,
607 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
608 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
609 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
610 EFX_PHY_STAT_PCS_FW_VERSION_0,
611 EFX_PHY_STAT_PCS_FW_VERSION_1,
612 EFX_PHY_STAT_PCS_FW_VERSION_2,
613 EFX_PHY_STAT_PCS_FW_VERSION_3,
614 EFX_PHY_STAT_PCS_FW_BUILD_YY,
615 EFX_PHY_STAT_PCS_FW_BUILD_MM,
616 EFX_PHY_STAT_PCS_FW_BUILD_DD,
617 EFX_PHY_STAT_PCS_OP_MODE,
621 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
628 __in efx_phy_stat_t stat);
630 #endif /* EFSYS_OPT_NAMES */
632 #define EFX_PHY_STATS_SIZE 0x100
634 extern __checkReturn efx_rc_t
635 efx_phy_stats_update(
637 __in efsys_mem_t *esmp,
638 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
640 #endif /* EFSYS_OPT_PHY_STATS */
645 typedef enum efx_bist_type_e {
646 EFX_BIST_TYPE_UNKNOWN,
647 EFX_BIST_TYPE_PHY_NORMAL,
648 EFX_BIST_TYPE_PHY_CABLE_SHORT,
649 EFX_BIST_TYPE_PHY_CABLE_LONG,
650 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
651 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
652 EFX_BIST_TYPE_REG, /* Test the register memories */
653 EFX_BIST_TYPE_NTYPES,
656 typedef enum efx_bist_result_e {
657 EFX_BIST_RESULT_UNKNOWN,
658 EFX_BIST_RESULT_RUNNING,
659 EFX_BIST_RESULT_PASSED,
660 EFX_BIST_RESULT_FAILED,
663 typedef enum efx_phy_cable_status_e {
664 EFX_PHY_CABLE_STATUS_OK,
665 EFX_PHY_CABLE_STATUS_INVALID,
666 EFX_PHY_CABLE_STATUS_OPEN,
667 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
668 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
669 EFX_PHY_CABLE_STATUS_BUSY,
670 } efx_phy_cable_status_t;
672 typedef enum efx_bist_value_e {
673 EFX_BIST_PHY_CABLE_LENGTH_A,
674 EFX_BIST_PHY_CABLE_LENGTH_B,
675 EFX_BIST_PHY_CABLE_LENGTH_C,
676 EFX_BIST_PHY_CABLE_LENGTH_D,
677 EFX_BIST_PHY_CABLE_STATUS_A,
678 EFX_BIST_PHY_CABLE_STATUS_B,
679 EFX_BIST_PHY_CABLE_STATUS_C,
680 EFX_BIST_PHY_CABLE_STATUS_D,
682 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
690 EFX_BIST_MEM_ECC_PARITY,
691 EFX_BIST_MEM_ECC_FATAL,
695 extern __checkReturn efx_rc_t
696 efx_bist_enable_offline(
697 __in efx_nic_t *enp);
699 extern __checkReturn efx_rc_t
702 __in efx_bist_type_t type);
704 extern __checkReturn efx_rc_t
707 __in efx_bist_type_t type,
708 __out efx_bist_result_t *resultp,
709 __out_opt uint32_t *value_maskp,
710 __out_ecount_opt(count) unsigned long *valuesp,
716 __in efx_bist_type_t type);
718 #endif /* EFSYS_OPT_BIST */
720 #define EFX_FEATURE_IPV6 0x00000001
721 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
722 #define EFX_FEATURE_LINK_EVENTS 0x00000004
723 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
724 #define EFX_FEATURE_MCDI 0x00000020
725 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
726 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
727 #define EFX_FEATURE_TURBO 0x00000100
728 #define EFX_FEATURE_MCDI_DMA 0x00000200
729 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
730 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
731 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
732 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
733 #define EFX_FEATURE_PACKED_STREAM 0x00004000
735 typedef struct efx_nic_cfg_s {
736 uint32_t enc_board_type;
737 uint32_t enc_phy_type;
739 char enc_phy_name[21];
741 char enc_phy_revision[21];
742 efx_mon_type_t enc_mon_type;
743 unsigned int enc_features;
744 uint8_t enc_mac_addr[6];
745 uint8_t enc_port; /* PHY port number */
746 uint32_t enc_intr_vec_base;
747 uint32_t enc_intr_limit;
748 uint32_t enc_evq_limit;
749 uint32_t enc_txq_limit;
750 uint32_t enc_rxq_limit;
751 uint32_t enc_txq_max_ndescs;
752 uint32_t enc_buftbl_limit;
753 uint32_t enc_piobuf_limit;
754 uint32_t enc_piobuf_size;
755 uint32_t enc_piobuf_min_alloc_size;
756 uint32_t enc_evq_timer_quantum_ns;
757 uint32_t enc_evq_timer_max_us;
758 uint32_t enc_clk_mult;
759 uint32_t enc_rx_prefix_size;
760 uint32_t enc_rx_buf_align_start;
761 uint32_t enc_rx_buf_align_end;
762 #if EFSYS_OPT_PHY_FLAGS
763 uint32_t enc_phy_flags_mask;
764 #endif /* EFSYS_OPT_PHY_FLAGS */
765 #if EFSYS_OPT_PHY_LED_CONTROL
766 uint32_t enc_led_mask;
767 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
768 #if EFSYS_OPT_PHY_STATS
769 uint64_t enc_phy_stat_mask;
770 #endif /* EFSYS_OPT_PHY_STATS */
772 uint8_t enc_mcdi_mdio_channel;
773 #if EFSYS_OPT_PHY_STATS
774 uint32_t enc_mcdi_phy_stat_mask;
775 #endif /* EFSYS_OPT_PHY_STATS */
776 #endif /* EFSYS_OPT_MCDI */
778 uint32_t enc_bist_mask;
779 #endif /* EFSYS_OPT_BIST */
780 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
783 uint32_t enc_privilege_mask;
784 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
785 boolean_t enc_bug26807_workaround;
786 boolean_t enc_bug35388_workaround;
787 boolean_t enc_bug41750_workaround;
788 boolean_t enc_bug61265_workaround;
789 boolean_t enc_rx_batching_enabled;
790 /* Maximum number of descriptors completed in an rx event. */
791 uint32_t enc_rx_batch_max;
792 /* Number of rx descriptors the hardware requires for a push. */
793 uint32_t enc_rx_push_align;
795 * Maximum number of bytes into the packet the TCP header can start for
796 * the hardware to apply TSO packet edits.
798 uint32_t enc_tx_tso_tcp_header_offset_limit;
799 boolean_t enc_fw_assisted_tso_enabled;
800 boolean_t enc_fw_assisted_tso_v2_enabled;
801 /* Number of TSO contexts on the NIC (FATSOv2) */
802 uint32_t enc_fw_assisted_tso_v2_n_contexts;
803 boolean_t enc_hw_tx_insert_vlan_enabled;
804 /* Number of PFs on the NIC */
805 uint32_t enc_hw_pf_count;
806 /* Datapath firmware vadapter/vport/vswitch support */
807 boolean_t enc_datapath_cap_evb;
808 boolean_t enc_rx_disable_scatter_supported;
809 boolean_t enc_allow_set_mac_with_installed_filters;
810 boolean_t enc_enhanced_set_mac_supported;
811 boolean_t enc_init_evq_v2_supported;
812 boolean_t enc_rx_packed_stream_supported;
813 boolean_t enc_rx_var_packed_stream_supported;
814 boolean_t enc_pm_and_rxdp_counters;
815 boolean_t enc_mac_stats_40g_tx_size_bins;
816 /* External port identifier */
817 uint8_t enc_external_port;
818 uint32_t enc_mcdi_max_payload_length;
819 /* VPD may be per-PF or global */
820 boolean_t enc_vpd_is_global;
821 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
822 uint32_t enc_required_pcie_bandwidth_mbps;
823 uint32_t enc_max_pcie_link_gen;
824 /* Firmware verifies integrity of NVRAM updates */
825 uint32_t enc_fw_verified_nvram_update_required;
828 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
829 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
831 #define EFX_PCI_FUNCTION(_encp) \
832 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
834 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
836 extern const efx_nic_cfg_t *
838 __in efx_nic_t *enp);
840 /* Driver resource limits (minimum required/maximum usable). */
841 typedef struct efx_drv_limits_s {
842 uint32_t edl_min_evq_count;
843 uint32_t edl_max_evq_count;
845 uint32_t edl_min_rxq_count;
846 uint32_t edl_max_rxq_count;
848 uint32_t edl_min_txq_count;
849 uint32_t edl_max_txq_count;
851 /* PIO blocks (sub-allocated from piobuf) */
852 uint32_t edl_min_pio_alloc_size;
853 uint32_t edl_max_pio_alloc_count;
856 extern __checkReturn efx_rc_t
857 efx_nic_set_drv_limits(
858 __inout efx_nic_t *enp,
859 __in efx_drv_limits_t *edlp);
861 typedef enum efx_nic_region_e {
862 EFX_REGION_VI, /* Memory BAR UC mapping */
863 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
866 extern __checkReturn efx_rc_t
867 efx_nic_get_bar_region(
869 __in efx_nic_region_t region,
870 __out uint32_t *offsetp,
871 __out size_t *sizep);
873 extern __checkReturn efx_rc_t
876 __out uint32_t *evq_countp,
877 __out uint32_t *rxq_countp,
878 __out uint32_t *txq_countp);
885 typedef enum efx_pattern_type_t {
886 EFX_PATTERN_BYTE_INCREMENT = 0,
887 EFX_PATTERN_ALL_THE_SAME,
888 EFX_PATTERN_BIT_ALTERNATE,
889 EFX_PATTERN_BYTE_ALTERNATE,
890 EFX_PATTERN_BYTE_CHANGING,
891 EFX_PATTERN_BIT_SWEEP,
893 } efx_pattern_type_t;
896 (*efx_sram_pattern_fn_t)(
898 __in boolean_t negate,
899 __out efx_qword_t *eqp);
901 extern __checkReturn efx_rc_t
904 __in efx_pattern_type_t type);
906 #endif /* EFSYS_OPT_DIAG */
908 extern __checkReturn efx_rc_t
909 efx_sram_buf_tbl_set(
912 __in efsys_mem_t *esmp,
916 efx_sram_buf_tbl_clear(
921 #define EFX_BUF_TBL_SIZE 0x20000
923 #define EFX_BUF_SIZE 4096
927 typedef struct efx_evq_s efx_evq_t;
931 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
932 typedef enum efx_ev_qstat_e {
939 EV_RX_BUF_OWNER_ID_ERR,
940 EV_RX_IPV4_HDR_CHKSUM_ERR,
941 EV_RX_TCP_UDP_CHKSUM_ERR,
945 EV_RX_MCAST_HASH_MATCH,
962 EV_DRIVER_SRM_UPD_DONE,
963 EV_DRIVER_TX_DESCQ_FLS_DONE,
964 EV_DRIVER_RX_DESCQ_FLS_DONE,
965 EV_DRIVER_RX_DESCQ_FLS_FAILED,
966 EV_DRIVER_RX_DSC_ERROR,
967 EV_DRIVER_TX_DSC_ERROR,
973 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
975 #endif /* EFSYS_OPT_QSTATS */
977 extern __checkReturn efx_rc_t
979 __in efx_nic_t *enp);
983 __in efx_nic_t *enp);
985 #define EFX_EVQ_MAXNEVS 32768
986 #define EFX_EVQ_MINNEVS 512
988 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
989 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
991 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
992 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
993 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
994 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
996 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
997 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
998 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1000 extern __checkReturn efx_rc_t
1002 __in efx_nic_t *enp,
1003 __in unsigned int index,
1004 __in efsys_mem_t *esmp,
1008 __in uint32_t flags,
1009 __deref_out efx_evq_t **eepp);
1013 __in efx_evq_t *eep,
1014 __in uint16_t data);
1016 typedef __checkReturn boolean_t
1017 (*efx_initialized_ev_t)(
1018 __in_opt void *arg);
1020 #define EFX_PKT_UNICAST 0x0004
1021 #define EFX_PKT_START 0x0008
1023 #define EFX_PKT_VLAN_TAGGED 0x0010
1024 #define EFX_CKSUM_TCPUDP 0x0020
1025 #define EFX_CKSUM_IPV4 0x0040
1026 #define EFX_PKT_CONT 0x0080
1028 #define EFX_CHECK_VLAN 0x0100
1029 #define EFX_PKT_TCP 0x0200
1030 #define EFX_PKT_UDP 0x0400
1031 #define EFX_PKT_IPV4 0x0800
1033 #define EFX_PKT_IPV6 0x1000
1034 #define EFX_PKT_PREFIX_LEN 0x2000
1035 #define EFX_ADDR_MISMATCH 0x4000
1036 #define EFX_DISCARD 0x8000
1039 * The following flags are used only for packed stream
1040 * mode. The values for the flags are reused to fit into 16 bit,
1041 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1042 * packed stream mode
1044 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1045 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1048 #define EFX_EV_RX_NLABELS 32
1049 #define EFX_EV_TX_NLABELS 32
1051 typedef __checkReturn boolean_t
1054 __in uint32_t label,
1057 __in uint16_t flags);
1059 typedef __checkReturn boolean_t
1062 __in uint32_t label,
1065 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1066 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1067 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1068 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1069 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1070 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1071 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1072 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1073 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1075 typedef __checkReturn boolean_t
1076 (*efx_exception_ev_t)(
1078 __in uint32_t label,
1079 __in uint32_t data);
1081 typedef __checkReturn boolean_t
1082 (*efx_rxq_flush_done_ev_t)(
1084 __in uint32_t rxq_index);
1086 typedef __checkReturn boolean_t
1087 (*efx_rxq_flush_failed_ev_t)(
1089 __in uint32_t rxq_index);
1091 typedef __checkReturn boolean_t
1092 (*efx_txq_flush_done_ev_t)(
1094 __in uint32_t txq_index);
1096 typedef __checkReturn boolean_t
1097 (*efx_software_ev_t)(
1099 __in uint16_t magic);
1101 typedef __checkReturn boolean_t
1104 __in uint32_t code);
1106 #define EFX_SRAM_CLEAR 0
1107 #define EFX_SRAM_UPDATE 1
1108 #define EFX_SRAM_ILLEGAL_CLEAR 2
1110 typedef __checkReturn boolean_t
1111 (*efx_wake_up_ev_t)(
1113 __in uint32_t label);
1115 typedef __checkReturn boolean_t
1118 __in uint32_t label);
1120 typedef __checkReturn boolean_t
1121 (*efx_link_change_ev_t)(
1123 __in efx_link_mode_t link_mode);
1125 typedef struct efx_ev_callbacks_s {
1126 efx_initialized_ev_t eec_initialized;
1129 efx_exception_ev_t eec_exception;
1130 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1131 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1132 efx_txq_flush_done_ev_t eec_txq_flush_done;
1133 efx_software_ev_t eec_software;
1134 efx_sram_ev_t eec_sram;
1135 efx_wake_up_ev_t eec_wake_up;
1136 efx_timer_ev_t eec_timer;
1137 efx_link_change_ev_t eec_link_change;
1138 } efx_ev_callbacks_t;
1140 extern __checkReturn boolean_t
1142 __in efx_evq_t *eep,
1143 __in unsigned int count);
1147 __in efx_evq_t *eep,
1148 __inout unsigned int *countp,
1149 __in const efx_ev_callbacks_t *eecp,
1150 __in_opt void *arg);
1152 extern __checkReturn efx_rc_t
1153 efx_ev_usecs_to_ticks(
1154 __in efx_nic_t *enp,
1155 __in unsigned int usecs,
1156 __out unsigned int *ticksp);
1158 extern __checkReturn efx_rc_t
1160 __in efx_evq_t *eep,
1161 __in unsigned int us);
1163 extern __checkReturn efx_rc_t
1165 __in efx_evq_t *eep,
1166 __in unsigned int count);
1168 #if EFSYS_OPT_QSTATS
1174 __in efx_nic_t *enp,
1175 __in unsigned int id);
1177 #endif /* EFSYS_OPT_NAMES */
1180 efx_ev_qstats_update(
1181 __in efx_evq_t *eep,
1182 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1184 #endif /* EFSYS_OPT_QSTATS */
1188 __in efx_evq_t *eep);
1192 extern __checkReturn efx_rc_t
1194 __inout efx_nic_t *enp);
1198 __in efx_nic_t *enp);
1200 extern __checkReturn efx_rc_t
1201 efx_pseudo_hdr_pkt_length_get(
1202 __in efx_rxq_t *erp,
1203 __in uint8_t *buffer,
1204 __out uint16_t *pkt_lengthp);
1206 #define EFX_RXQ_MAXNDESCS 4096
1207 #define EFX_RXQ_MINNDESCS 512
1209 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1210 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1211 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1212 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1214 typedef enum efx_rxq_type_e {
1215 EFX_RXQ_TYPE_DEFAULT,
1216 EFX_RXQ_TYPE_SCATTER,
1217 EFX_RXQ_TYPE_PACKED_STREAM_1M,
1218 EFX_RXQ_TYPE_PACKED_STREAM_512K,
1219 EFX_RXQ_TYPE_PACKED_STREAM_256K,
1220 EFX_RXQ_TYPE_PACKED_STREAM_128K,
1221 EFX_RXQ_TYPE_PACKED_STREAM_64K,
1225 extern __checkReturn efx_rc_t
1227 __in efx_nic_t *enp,
1228 __in unsigned int index,
1229 __in unsigned int label,
1230 __in efx_rxq_type_t type,
1231 __in efsys_mem_t *esmp,
1234 __in efx_evq_t *eep,
1235 __deref_out efx_rxq_t **erpp);
1237 typedef struct efx_buffer_s {
1238 efsys_dma_addr_t eb_addr;
1243 typedef struct efx_desc_s {
1249 __in efx_rxq_t *erp,
1250 __in_ecount(n) efsys_dma_addr_t *addrp,
1252 __in unsigned int n,
1253 __in unsigned int completed,
1254 __in unsigned int added);
1258 __in efx_rxq_t *erp,
1259 __in unsigned int added,
1260 __inout unsigned int *pushedp);
1262 extern __checkReturn efx_rc_t
1264 __in efx_rxq_t *erp);
1268 __in efx_rxq_t *erp);
1272 __in efx_rxq_t *erp);
1276 typedef struct efx_txq_s efx_txq_t;
1278 #if EFSYS_OPT_QSTATS
1280 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1281 typedef enum efx_tx_qstat_e {
1287 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1289 #endif /* EFSYS_OPT_QSTATS */
1291 extern __checkReturn efx_rc_t
1293 __in efx_nic_t *enp);
1297 __in efx_nic_t *enp);
1299 #define EFX_TXQ_MINNDESCS 512
1301 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1302 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1303 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1304 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1306 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1308 #define EFX_TXQ_CKSUM_IPV4 0x0001
1309 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1310 #define EFX_TXQ_FATSOV2 0x0004
1312 extern __checkReturn efx_rc_t
1314 __in efx_nic_t *enp,
1315 __in unsigned int index,
1316 __in unsigned int label,
1317 __in efsys_mem_t *esmp,
1320 __in uint16_t flags,
1321 __in efx_evq_t *eep,
1322 __deref_out efx_txq_t **etpp,
1323 __out unsigned int *addedp);
1325 extern __checkReturn efx_rc_t
1327 __in efx_txq_t *etp,
1328 __in_ecount(n) efx_buffer_t *eb,
1329 __in unsigned int n,
1330 __in unsigned int completed,
1331 __inout unsigned int *addedp);
1333 extern __checkReturn efx_rc_t
1335 __in efx_txq_t *etp,
1336 __in unsigned int ns);
1340 __in efx_txq_t *etp,
1341 __in unsigned int added,
1342 __in unsigned int pushed);
1344 extern __checkReturn efx_rc_t
1346 __in efx_txq_t *etp);
1350 __in efx_txq_t *etp);
1352 extern __checkReturn efx_rc_t
1354 __in efx_txq_t *etp);
1357 efx_tx_qpio_disable(
1358 __in efx_txq_t *etp);
1360 extern __checkReturn efx_rc_t
1362 __in efx_txq_t *etp,
1363 __in_ecount(buf_length) uint8_t *buffer,
1364 __in size_t buf_length,
1365 __in size_t pio_buf_offset);
1367 extern __checkReturn efx_rc_t
1369 __in efx_txq_t *etp,
1370 __in size_t pkt_length,
1371 __in unsigned int completed,
1372 __inout unsigned int *addedp);
1374 extern __checkReturn efx_rc_t
1376 __in efx_txq_t *etp,
1377 __in_ecount(n) efx_desc_t *ed,
1378 __in unsigned int n,
1379 __in unsigned int completed,
1380 __inout unsigned int *addedp);
1383 efx_tx_qdesc_dma_create(
1384 __in efx_txq_t *etp,
1385 __in efsys_dma_addr_t addr,
1388 __out efx_desc_t *edp);
1391 efx_tx_qdesc_tso_create(
1392 __in efx_txq_t *etp,
1393 __in uint16_t ipv4_id,
1394 __in uint32_t tcp_seq,
1395 __in uint8_t tcp_flags,
1396 __out efx_desc_t *edp);
1398 /* Number of FATSOv2 option descriptors */
1399 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1401 /* Maximum number of DMA segments per TSO packet (not superframe) */
1402 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1405 efx_tx_qdesc_tso2_create(
1406 __in efx_txq_t *etp,
1407 __in uint16_t ipv4_id,
1408 __in uint32_t tcp_seq,
1409 __in uint16_t tcp_mss,
1410 __out_ecount(count) efx_desc_t *edp,
1414 efx_tx_qdesc_vlantci_create(
1415 __in efx_txq_t *etp,
1417 __out efx_desc_t *edp);
1419 #if EFSYS_OPT_QSTATS
1425 __in efx_nic_t *etp,
1426 __in unsigned int id);
1428 #endif /* EFSYS_OPT_NAMES */
1431 efx_tx_qstats_update(
1432 __in efx_txq_t *etp,
1433 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1435 #endif /* EFSYS_OPT_QSTATS */
1439 __in efx_txq_t *etp);
1444 #if EFSYS_OPT_FILTER
1446 #define EFX_ETHER_TYPE_IPV4 0x0800
1447 #define EFX_ETHER_TYPE_IPV6 0x86DD
1449 #define EFX_IPPROTO_TCP 6
1450 #define EFX_IPPROTO_UDP 17
1452 /* Use RSS to spread across multiple queues */
1453 #define EFX_FILTER_FLAG_RX_RSS 0x01
1454 /* Enable RX scatter */
1455 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1457 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1458 * May only be set by the filter implementation for each type.
1459 * A removal request will restore the automatic filter in its place.
1461 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1462 /* Filter is for RX */
1463 #define EFX_FILTER_FLAG_RX 0x08
1464 /* Filter is for TX */
1465 #define EFX_FILTER_FLAG_TX 0x10
1467 typedef unsigned int efx_filter_flags_t;
1469 typedef enum efx_filter_match_flags_e {
1470 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1472 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1474 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1475 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1476 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1477 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1478 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1479 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1480 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1481 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1483 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1484 * I/G bit. Used for RX default
1485 * unicast and multicast/
1486 * broadcast filters. */
1487 } efx_filter_match_flags_t;
1489 typedef enum efx_filter_priority_s {
1490 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1491 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1492 * address list or hardware
1493 * requirements. This may only be used
1494 * by the filter implementation for
1496 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1497 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1498 * client (e.g. SR-IOV, HyperV VMQ etc.)
1500 } efx_filter_priority_t;
1503 * FIXME: All these fields are assumed to be in little-endian byte order.
1504 * It may be better for some to be big-endian. See bug42804.
1507 typedef struct efx_filter_spec_s {
1508 uint32_t efs_match_flags:12;
1509 uint32_t efs_priority:2;
1510 uint32_t efs_flags:6;
1511 uint32_t efs_dmaq_id:12;
1512 uint32_t efs_rss_context;
1513 uint16_t efs_outer_vid;
1514 uint16_t efs_inner_vid;
1515 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1516 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1517 uint16_t efs_ether_type;
1518 uint8_t efs_ip_proto;
1519 uint16_t efs_loc_port;
1520 uint16_t efs_rem_port;
1521 efx_oword_t efs_rem_host;
1522 efx_oword_t efs_loc_host;
1523 } efx_filter_spec_t;
1526 /* Default values for use in filter specifications */
1527 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1528 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1529 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1531 extern __checkReturn efx_rc_t
1533 __in efx_nic_t *enp);
1537 __in efx_nic_t *enp);
1539 extern __checkReturn efx_rc_t
1541 __in efx_nic_t *enp,
1542 __inout efx_filter_spec_t *spec);
1544 extern __checkReturn efx_rc_t
1546 __in efx_nic_t *enp,
1547 __inout efx_filter_spec_t *spec);
1549 extern __checkReturn efx_rc_t
1551 __in efx_nic_t *enp);
1553 extern __checkReturn efx_rc_t
1554 efx_filter_supported_filters(
1555 __in efx_nic_t *enp,
1556 __out uint32_t *list,
1557 __out size_t *length);
1560 efx_filter_spec_init_rx(
1561 __out efx_filter_spec_t *spec,
1562 __in efx_filter_priority_t priority,
1563 __in efx_filter_flags_t flags,
1564 __in efx_rxq_t *erp);
1567 efx_filter_spec_init_tx(
1568 __out efx_filter_spec_t *spec,
1569 __in efx_txq_t *etp);
1571 extern __checkReturn efx_rc_t
1572 efx_filter_spec_set_ipv4_local(
1573 __inout efx_filter_spec_t *spec,
1576 __in uint16_t port);
1578 extern __checkReturn efx_rc_t
1579 efx_filter_spec_set_ipv4_full(
1580 __inout efx_filter_spec_t *spec,
1582 __in uint32_t lhost,
1583 __in uint16_t lport,
1584 __in uint32_t rhost,
1585 __in uint16_t rport);
1587 extern __checkReturn efx_rc_t
1588 efx_filter_spec_set_eth_local(
1589 __inout efx_filter_spec_t *spec,
1591 __in const uint8_t *addr);
1593 extern __checkReturn efx_rc_t
1594 efx_filter_spec_set_uc_def(
1595 __inout efx_filter_spec_t *spec);
1597 extern __checkReturn efx_rc_t
1598 efx_filter_spec_set_mc_def(
1599 __inout efx_filter_spec_t *spec);
1601 #endif /* EFSYS_OPT_FILTER */
1605 extern __checkReturn uint32_t
1607 __in_ecount(count) uint32_t const *input,
1609 __in uint32_t init);
1611 extern __checkReturn uint32_t
1613 __in_ecount(length) uint8_t const *input,
1615 __in uint32_t init);
1623 #endif /* _SYS_EFX_H */