2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 extern __checkReturn efx_rc_t
152 efx_nic_register_test(
153 __in efx_nic_t *enp);
155 #endif /* EFSYS_OPT_DIAG */
159 __in efx_nic_t *enp);
163 __in efx_nic_t *enp);
167 __in efx_nic_t *enp);
169 #define EFX_PCIE_LINK_SPEED_GEN1 1
170 #define EFX_PCIE_LINK_SPEED_GEN2 2
171 #define EFX_PCIE_LINK_SPEED_GEN3 3
173 typedef enum efx_pcie_link_performance_e {
174 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
175 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
176 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
177 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
178 } efx_pcie_link_performance_t;
180 extern __checkReturn efx_rc_t
181 efx_nic_calculate_pcie_link_bandwidth(
182 __in uint32_t pcie_link_width,
183 __in uint32_t pcie_link_gen,
184 __out uint32_t *bandwidth_mbpsp);
186 extern __checkReturn efx_rc_t
187 efx_nic_check_pcie_link_speed(
189 __in uint32_t pcie_link_width,
190 __in uint32_t pcie_link_gen,
191 __out efx_pcie_link_performance_t *resultp);
195 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
196 /* Huntington and Medford require MCDIv2 commands */
197 #define WITH_MCDI_V2 1
200 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
202 typedef enum efx_mcdi_exception_e {
203 EFX_MCDI_EXCEPTION_MC_REBOOT,
204 EFX_MCDI_EXCEPTION_MC_BADASSERT,
205 } efx_mcdi_exception_t;
207 #if EFSYS_OPT_MCDI_LOGGING
208 typedef enum efx_log_msg_e {
210 EFX_LOG_MCDI_REQUEST,
211 EFX_LOG_MCDI_RESPONSE,
213 #endif /* EFSYS_OPT_MCDI_LOGGING */
215 typedef struct efx_mcdi_transport_s {
217 efsys_mem_t *emt_dma_mem;
218 void (*emt_execute)(void *, efx_mcdi_req_t *);
219 void (*emt_ev_cpl)(void *);
220 void (*emt_exception)(void *, efx_mcdi_exception_t);
221 #if EFSYS_OPT_MCDI_LOGGING
222 void (*emt_logger)(void *, efx_log_msg_t,
223 void *, size_t, void *, size_t);
224 #endif /* EFSYS_OPT_MCDI_LOGGING */
225 #if EFSYS_OPT_MCDI_PROXY_AUTH
226 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228 } efx_mcdi_transport_t;
230 extern __checkReturn efx_rc_t
233 __in const efx_mcdi_transport_t *mtp);
235 extern __checkReturn efx_rc_t
237 __in efx_nic_t *enp);
241 __in efx_nic_t *enp);
244 efx_mcdi_get_timeout(
246 __in efx_mcdi_req_t *emrp,
247 __out uint32_t *usec_timeoutp);
250 efx_mcdi_request_start(
252 __in efx_mcdi_req_t *emrp,
253 __in boolean_t ev_cpl);
255 extern __checkReturn boolean_t
256 efx_mcdi_request_poll(
257 __in efx_nic_t *enp);
259 extern __checkReturn boolean_t
260 efx_mcdi_request_abort(
261 __in efx_nic_t *enp);
265 __in efx_nic_t *enp);
267 #endif /* EFSYS_OPT_MCDI */
271 #define EFX_NINTR_SIENA 1024
273 typedef enum efx_intr_type_e {
274 EFX_INTR_INVALID = 0,
280 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
282 extern __checkReturn efx_rc_t
285 __in efx_intr_type_t type,
286 __in efsys_mem_t *esmp);
290 __in efx_nic_t *enp);
294 __in efx_nic_t *enp);
297 efx_intr_disable_unlocked(
298 __in efx_nic_t *enp);
300 #define EFX_INTR_NEVQS 32
302 extern __checkReturn efx_rc_t
305 __in unsigned int level);
308 efx_intr_status_line(
310 __out boolean_t *fatalp,
311 __out uint32_t *maskp);
314 efx_intr_status_message(
316 __in unsigned int message,
317 __out boolean_t *fatalp);
321 __in efx_nic_t *enp);
325 __in efx_nic_t *enp);
329 #if EFSYS_OPT_MAC_STATS
331 /* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
332 typedef enum efx_mac_stat_e {
335 EFX_MAC_RX_UNICST_PKTS,
336 EFX_MAC_RX_MULTICST_PKTS,
337 EFX_MAC_RX_BRDCST_PKTS,
338 EFX_MAC_RX_PAUSE_PKTS,
339 EFX_MAC_RX_LE_64_PKTS,
340 EFX_MAC_RX_65_TO_127_PKTS,
341 EFX_MAC_RX_128_TO_255_PKTS,
342 EFX_MAC_RX_256_TO_511_PKTS,
343 EFX_MAC_RX_512_TO_1023_PKTS,
344 EFX_MAC_RX_1024_TO_15XX_PKTS,
345 EFX_MAC_RX_GE_15XX_PKTS,
347 EFX_MAC_RX_FCS_ERRORS,
348 EFX_MAC_RX_DROP_EVENTS,
349 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
350 EFX_MAC_RX_SYMBOL_ERRORS,
351 EFX_MAC_RX_ALIGN_ERRORS,
352 EFX_MAC_RX_INTERNAL_ERRORS,
353 EFX_MAC_RX_JABBER_PKTS,
354 EFX_MAC_RX_LANE0_CHAR_ERR,
355 EFX_MAC_RX_LANE1_CHAR_ERR,
356 EFX_MAC_RX_LANE2_CHAR_ERR,
357 EFX_MAC_RX_LANE3_CHAR_ERR,
358 EFX_MAC_RX_LANE0_DISP_ERR,
359 EFX_MAC_RX_LANE1_DISP_ERR,
360 EFX_MAC_RX_LANE2_DISP_ERR,
361 EFX_MAC_RX_LANE3_DISP_ERR,
362 EFX_MAC_RX_MATCH_FAULT,
363 EFX_MAC_RX_NODESC_DROP_CNT,
366 EFX_MAC_TX_UNICST_PKTS,
367 EFX_MAC_TX_MULTICST_PKTS,
368 EFX_MAC_TX_BRDCST_PKTS,
369 EFX_MAC_TX_PAUSE_PKTS,
370 EFX_MAC_TX_LE_64_PKTS,
371 EFX_MAC_TX_65_TO_127_PKTS,
372 EFX_MAC_TX_128_TO_255_PKTS,
373 EFX_MAC_TX_256_TO_511_PKTS,
374 EFX_MAC_TX_512_TO_1023_PKTS,
375 EFX_MAC_TX_1024_TO_15XX_PKTS,
376 EFX_MAC_TX_GE_15XX_PKTS,
378 EFX_MAC_TX_SGL_COL_PKTS,
379 EFX_MAC_TX_MULT_COL_PKTS,
380 EFX_MAC_TX_EX_COL_PKTS,
381 EFX_MAC_TX_LATE_COL_PKTS,
383 EFX_MAC_TX_EX_DEF_PKTS,
384 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
385 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
386 EFX_MAC_PM_TRUNC_VFIFO_FULL,
387 EFX_MAC_PM_DISCARD_VFIFO_FULL,
388 EFX_MAC_PM_TRUNC_QBB,
389 EFX_MAC_PM_DISCARD_QBB,
390 EFX_MAC_PM_DISCARD_MAPPING,
391 EFX_MAC_RXDP_Q_DISABLED_PKTS,
392 EFX_MAC_RXDP_DI_DROPPED_PKTS,
393 EFX_MAC_RXDP_STREAMING_PKTS,
394 EFX_MAC_RXDP_HLB_FETCH,
395 EFX_MAC_RXDP_HLB_WAIT,
396 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
397 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
398 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
399 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
400 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
401 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
402 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
403 EFX_MAC_VADAPTER_RX_BAD_BYTES,
404 EFX_MAC_VADAPTER_RX_OVERFLOW,
405 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
406 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
407 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
408 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
409 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
410 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
411 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
412 EFX_MAC_VADAPTER_TX_BAD_BYTES,
413 EFX_MAC_VADAPTER_TX_OVERFLOW,
417 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
419 #endif /* EFSYS_OPT_MAC_STATS */
421 typedef enum efx_link_mode_e {
422 EFX_LINK_UNKNOWN = 0,
435 #define EFX_MAC_ADDR_LEN 6
437 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
439 #define EFX_MAC_MULTICAST_LIST_MAX 256
441 #define EFX_MAC_SDU_MAX 9202
443 #define EFX_MAC_PDU_ADJUSTMENT \
447 + /* bug16011 */ 16) \
449 #define EFX_MAC_PDU(_sdu) \
450 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
453 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
454 * the SDU rounded up slightly.
456 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
458 #define EFX_MAC_PDU_MIN 60
459 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
461 extern __checkReturn efx_rc_t
466 extern __checkReturn efx_rc_t
471 extern __checkReturn efx_rc_t
476 extern __checkReturn efx_rc_t
479 __in boolean_t all_unicst,
480 __in boolean_t mulcst,
481 __in boolean_t all_mulcst,
482 __in boolean_t brdcst);
484 extern __checkReturn efx_rc_t
485 efx_mac_multicast_list_set(
487 __in_ecount(6*count) uint8_t const *addrs,
490 extern __checkReturn efx_rc_t
491 efx_mac_filter_default_rxq_set(
494 __in boolean_t using_rss);
497 efx_mac_filter_default_rxq_clear(
498 __in efx_nic_t *enp);
500 extern __checkReturn efx_rc_t
503 __in boolean_t enabled);
505 extern __checkReturn efx_rc_t
508 __out boolean_t *mac_upp);
510 #define EFX_FCNTL_RESPOND 0x00000001
511 #define EFX_FCNTL_GENERATE 0x00000002
513 extern __checkReturn efx_rc_t
516 __in unsigned int fcntl,
517 __in boolean_t autoneg);
522 __out unsigned int *fcntl_wantedp,
523 __out unsigned int *fcntl_linkp);
526 #if EFSYS_OPT_MAC_STATS
530 extern __checkReturn const char *
533 __in unsigned int id);
535 #endif /* EFSYS_OPT_NAMES */
537 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
539 #define EFX_MAC_STATS_MASK_NPAGES \
540 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
541 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
544 * Get mask of MAC statistics supported by the hardware.
546 * If mask_size is insufficient to return the mask, EINVAL error is
547 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
548 * (which is sizeof (uint32_t)) is sufficient.
550 extern __checkReturn efx_rc_t
551 efx_mac_stats_get_mask(
553 __out_bcount(mask_size) uint32_t *maskp,
554 __in size_t mask_size);
556 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
557 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
558 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
560 #define EFX_MAC_STATS_SIZE 0x400
563 * Upload mac statistics supported by the hardware into the given buffer.
565 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
568 * The hardware will only DMA statistics that it understands (of course).
569 * Drivers should not make any assumptions about which statistics are
570 * supported, especially when the statistics are generated by firmware.
572 * Thus, drivers should zero this buffer before use, so that not-understood
573 * statistics read back as zero.
575 extern __checkReturn efx_rc_t
576 efx_mac_stats_upload(
578 __in efsys_mem_t *esmp);
580 extern __checkReturn efx_rc_t
581 efx_mac_stats_periodic(
583 __in efsys_mem_t *esmp,
584 __in uint16_t period_ms,
585 __in boolean_t events);
587 extern __checkReturn efx_rc_t
588 efx_mac_stats_update(
590 __in efsys_mem_t *esmp,
591 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
592 __inout_opt uint32_t *generationp);
594 #endif /* EFSYS_OPT_MAC_STATS */
598 typedef enum efx_mon_type_e {
610 __in efx_nic_t *enp);
612 #endif /* EFSYS_OPT_NAMES */
614 extern __checkReturn efx_rc_t
616 __in efx_nic_t *enp);
618 #if EFSYS_OPT_MON_STATS
620 #define EFX_MON_STATS_PAGE_SIZE 0x100
621 #define EFX_MON_MASK_ELEMENT_SIZE 32
623 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
624 typedef enum efx_mon_stat_e {
631 EFX_MON_STAT_EXT_TEMP,
632 EFX_MON_STAT_INT_TEMP,
635 EFX_MON_STAT_INT_COOLING,
636 EFX_MON_STAT_EXT_COOLING,
644 EFX_MON_STAT_AOE_TEMP,
645 EFX_MON_STAT_PSU_AOE_TEMP,
646 EFX_MON_STAT_PSU_TEMP,
652 EFX_MON_STAT_VAOE_IN,
654 EFX_MON_STAT_IAOE_IN,
655 EFX_MON_STAT_NIC_POWER,
659 EFX_MON_STAT_0_9V_ADC,
660 EFX_MON_STAT_INT_TEMP2,
661 EFX_MON_STAT_VREG_TEMP,
662 EFX_MON_STAT_VREG_0_9V_TEMP,
663 EFX_MON_STAT_VREG_1_2V_TEMP,
664 EFX_MON_STAT_INT_VPTAT,
665 EFX_MON_STAT_INT_ADC_TEMP,
666 EFX_MON_STAT_EXT_VPTAT,
667 EFX_MON_STAT_EXT_ADC_TEMP,
668 EFX_MON_STAT_AMBIENT_TEMP,
669 EFX_MON_STAT_AIRFLOW,
670 EFX_MON_STAT_VDD08D_VSS08D_CSR,
671 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
672 EFX_MON_STAT_HOTPOINT_TEMP,
673 EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
674 EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
675 EFX_MON_STAT_MUM_VCC,
678 EFX_MON_STAT_0V9_A_TEMP,
681 EFX_MON_STAT_0V9_B_TEMP,
682 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
683 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
684 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
685 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
686 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
687 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
688 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
689 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
690 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
691 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
692 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
693 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
694 EFX_MON_STAT_SODIMM_VOUT,
695 EFX_MON_STAT_SODIMM_0_TEMP,
696 EFX_MON_STAT_SODIMM_1_TEMP,
697 EFX_MON_STAT_PHY0_VCC,
698 EFX_MON_STAT_PHY1_VCC,
699 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
700 EFX_MON_STAT_BOARD_FRONT_TEMP,
701 EFX_MON_STAT_BOARD_BACK_TEMP,
705 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
707 typedef enum efx_mon_stat_state_e {
708 EFX_MON_STAT_STATE_OK = 0,
709 EFX_MON_STAT_STATE_WARNING = 1,
710 EFX_MON_STAT_STATE_FATAL = 2,
711 EFX_MON_STAT_STATE_BROKEN = 3,
712 EFX_MON_STAT_STATE_NO_READING = 4,
713 } efx_mon_stat_state_t;
715 typedef struct efx_mon_stat_value_s {
718 } efx_mon_stat_value_t;
725 __in efx_mon_stat_t id);
727 #endif /* EFSYS_OPT_NAMES */
729 extern __checkReturn efx_rc_t
730 efx_mon_stats_update(
732 __in efsys_mem_t *esmp,
733 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
735 #endif /* EFSYS_OPT_MON_STATS */
739 __in efx_nic_t *enp);
743 extern __checkReturn efx_rc_t
745 __in efx_nic_t *enp);
747 #if EFSYS_OPT_PHY_LED_CONTROL
749 typedef enum efx_phy_led_mode_e {
750 EFX_PHY_LED_DEFAULT = 0,
755 } efx_phy_led_mode_t;
757 extern __checkReturn efx_rc_t
760 __in efx_phy_led_mode_t mode);
762 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
764 extern __checkReturn efx_rc_t
766 __in efx_nic_t *enp);
768 #if EFSYS_OPT_LOOPBACK
770 typedef enum efx_loopback_type_e {
771 EFX_LOOPBACK_OFF = 0,
772 EFX_LOOPBACK_DATA = 1,
773 EFX_LOOPBACK_GMAC = 2,
774 EFX_LOOPBACK_XGMII = 3,
775 EFX_LOOPBACK_XGXS = 4,
776 EFX_LOOPBACK_XAUI = 5,
777 EFX_LOOPBACK_GMII = 6,
778 EFX_LOOPBACK_SGMII = 7,
779 EFX_LOOPBACK_XGBR = 8,
780 EFX_LOOPBACK_XFI = 9,
781 EFX_LOOPBACK_XAUI_FAR = 10,
782 EFX_LOOPBACK_GMII_FAR = 11,
783 EFX_LOOPBACK_SGMII_FAR = 12,
784 EFX_LOOPBACK_XFI_FAR = 13,
785 EFX_LOOPBACK_GPHY = 14,
786 EFX_LOOPBACK_PHY_XS = 15,
787 EFX_LOOPBACK_PCS = 16,
788 EFX_LOOPBACK_PMA_PMD = 17,
789 EFX_LOOPBACK_XPORT = 18,
790 EFX_LOOPBACK_XGMII_WS = 19,
791 EFX_LOOPBACK_XAUI_WS = 20,
792 EFX_LOOPBACK_XAUI_WS_FAR = 21,
793 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
794 EFX_LOOPBACK_GMII_WS = 23,
795 EFX_LOOPBACK_XFI_WS = 24,
796 EFX_LOOPBACK_XFI_WS_FAR = 25,
797 EFX_LOOPBACK_PHYXS_WS = 26,
798 EFX_LOOPBACK_PMA_INT = 27,
799 EFX_LOOPBACK_SD_NEAR = 28,
800 EFX_LOOPBACK_SD_FAR = 29,
801 EFX_LOOPBACK_PMA_INT_WS = 30,
802 EFX_LOOPBACK_SD_FEP2_WS = 31,
803 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
804 EFX_LOOPBACK_SD_FEP_WS = 33,
805 EFX_LOOPBACK_SD_FES_WS = 34,
807 } efx_loopback_type_t;
809 typedef enum efx_loopback_kind_e {
810 EFX_LOOPBACK_KIND_OFF = 0,
811 EFX_LOOPBACK_KIND_ALL,
812 EFX_LOOPBACK_KIND_MAC,
813 EFX_LOOPBACK_KIND_PHY,
815 } efx_loopback_kind_t;
819 __in efx_loopback_kind_t loopback_kind,
820 __out efx_qword_t *maskp);
822 extern __checkReturn efx_rc_t
823 efx_port_loopback_set(
825 __in efx_link_mode_t link_mode,
826 __in efx_loopback_type_t type);
830 extern __checkReturn const char *
831 efx_loopback_type_name(
833 __in efx_loopback_type_t type);
835 #endif /* EFSYS_OPT_NAMES */
837 #endif /* EFSYS_OPT_LOOPBACK */
839 extern __checkReturn efx_rc_t
842 __out_opt efx_link_mode_t *link_modep);
846 __in efx_nic_t *enp);
848 typedef enum efx_phy_cap_type_e {
849 EFX_PHY_CAP_INVALID = 0,
856 EFX_PHY_CAP_10000FDX,
860 EFX_PHY_CAP_40000FDX,
862 } efx_phy_cap_type_t;
865 #define EFX_PHY_CAP_CURRENT 0x00000000
866 #define EFX_PHY_CAP_DEFAULT 0x00000001
867 #define EFX_PHY_CAP_PERM 0x00000002
873 __out uint32_t *maskp);
875 extern __checkReturn efx_rc_t
883 __out uint32_t *maskp);
885 extern __checkReturn efx_rc_t
888 __out uint32_t *ouip);
890 typedef enum efx_phy_media_type_e {
891 EFX_PHY_MEDIA_INVALID = 0,
896 EFX_PHY_MEDIA_SFP_PLUS,
897 EFX_PHY_MEDIA_BASE_T,
898 EFX_PHY_MEDIA_QSFP_PLUS,
900 } efx_phy_media_type_t;
902 /* Get the type of medium currently used. If the board has ports for
903 * modules, a module is present, and we recognise the media type of
904 * the module, then this will be the media type of the module.
905 * Otherwise it will be the media type of the port.
908 efx_phy_media_type_get(
910 __out efx_phy_media_type_t *typep);
913 efx_phy_module_get_info(
915 __in uint8_t dev_addr,
918 __out_bcount(len) uint8_t *data);
920 #if EFSYS_OPT_PHY_STATS
922 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
923 typedef enum efx_phy_stat_e {
925 EFX_PHY_STAT_PMA_PMD_LINK_UP,
926 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
927 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
928 EFX_PHY_STAT_PMA_PMD_REV_A,
929 EFX_PHY_STAT_PMA_PMD_REV_B,
930 EFX_PHY_STAT_PMA_PMD_REV_C,
931 EFX_PHY_STAT_PMA_PMD_REV_D,
932 EFX_PHY_STAT_PCS_LINK_UP,
933 EFX_PHY_STAT_PCS_RX_FAULT,
934 EFX_PHY_STAT_PCS_TX_FAULT,
935 EFX_PHY_STAT_PCS_BER,
936 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
937 EFX_PHY_STAT_PHY_XS_LINK_UP,
938 EFX_PHY_STAT_PHY_XS_RX_FAULT,
939 EFX_PHY_STAT_PHY_XS_TX_FAULT,
940 EFX_PHY_STAT_PHY_XS_ALIGN,
941 EFX_PHY_STAT_PHY_XS_SYNC_A,
942 EFX_PHY_STAT_PHY_XS_SYNC_B,
943 EFX_PHY_STAT_PHY_XS_SYNC_C,
944 EFX_PHY_STAT_PHY_XS_SYNC_D,
945 EFX_PHY_STAT_AN_LINK_UP,
946 EFX_PHY_STAT_AN_MASTER,
947 EFX_PHY_STAT_AN_LOCAL_RX_OK,
948 EFX_PHY_STAT_AN_REMOTE_RX_OK,
949 EFX_PHY_STAT_CL22EXT_LINK_UP,
954 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
955 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
956 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
957 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
958 EFX_PHY_STAT_AN_COMPLETE,
959 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
960 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
961 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
962 EFX_PHY_STAT_PCS_FW_VERSION_0,
963 EFX_PHY_STAT_PCS_FW_VERSION_1,
964 EFX_PHY_STAT_PCS_FW_VERSION_2,
965 EFX_PHY_STAT_PCS_FW_VERSION_3,
966 EFX_PHY_STAT_PCS_FW_BUILD_YY,
967 EFX_PHY_STAT_PCS_FW_BUILD_MM,
968 EFX_PHY_STAT_PCS_FW_BUILD_DD,
969 EFX_PHY_STAT_PCS_OP_MODE,
973 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
980 __in efx_phy_stat_t stat);
982 #endif /* EFSYS_OPT_NAMES */
984 #define EFX_PHY_STATS_SIZE 0x100
986 extern __checkReturn efx_rc_t
987 efx_phy_stats_update(
989 __in efsys_mem_t *esmp,
990 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
992 #endif /* EFSYS_OPT_PHY_STATS */
997 typedef enum efx_bist_type_e {
998 EFX_BIST_TYPE_UNKNOWN,
999 EFX_BIST_TYPE_PHY_NORMAL,
1000 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1001 EFX_BIST_TYPE_PHY_CABLE_LONG,
1002 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1003 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus*/
1004 EFX_BIST_TYPE_REG, /* Test the register memories */
1005 EFX_BIST_TYPE_NTYPES,
1008 typedef enum efx_bist_result_e {
1009 EFX_BIST_RESULT_UNKNOWN,
1010 EFX_BIST_RESULT_RUNNING,
1011 EFX_BIST_RESULT_PASSED,
1012 EFX_BIST_RESULT_FAILED,
1013 } efx_bist_result_t;
1015 typedef enum efx_phy_cable_status_e {
1016 EFX_PHY_CABLE_STATUS_OK,
1017 EFX_PHY_CABLE_STATUS_INVALID,
1018 EFX_PHY_CABLE_STATUS_OPEN,
1019 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1020 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1021 EFX_PHY_CABLE_STATUS_BUSY,
1022 } efx_phy_cable_status_t;
1024 typedef enum efx_bist_value_e {
1025 EFX_BIST_PHY_CABLE_LENGTH_A,
1026 EFX_BIST_PHY_CABLE_LENGTH_B,
1027 EFX_BIST_PHY_CABLE_LENGTH_C,
1028 EFX_BIST_PHY_CABLE_LENGTH_D,
1029 EFX_BIST_PHY_CABLE_STATUS_A,
1030 EFX_BIST_PHY_CABLE_STATUS_B,
1031 EFX_BIST_PHY_CABLE_STATUS_C,
1032 EFX_BIST_PHY_CABLE_STATUS_D,
1033 EFX_BIST_FAULT_CODE,
1034 /* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1039 EFX_BIST_MEM_EXPECT,
1040 EFX_BIST_MEM_ACTUAL,
1042 EFX_BIST_MEM_ECC_PARITY,
1043 EFX_BIST_MEM_ECC_FATAL,
1047 extern __checkReturn efx_rc_t
1048 efx_bist_enable_offline(
1049 __in efx_nic_t *enp);
1051 extern __checkReturn efx_rc_t
1053 __in efx_nic_t *enp,
1054 __in efx_bist_type_t type);
1056 extern __checkReturn efx_rc_t
1058 __in efx_nic_t *enp,
1059 __in efx_bist_type_t type,
1060 __out efx_bist_result_t *resultp,
1061 __out_opt uint32_t *value_maskp,
1062 __out_ecount_opt(count) unsigned long *valuesp,
1067 __in efx_nic_t *enp,
1068 __in efx_bist_type_t type);
1070 #endif /* EFSYS_OPT_BIST */
1072 #define EFX_FEATURE_IPV6 0x00000001
1073 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1074 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1075 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1076 #define EFX_FEATURE_MCDI 0x00000020
1077 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1078 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1079 #define EFX_FEATURE_TURBO 0x00000100
1080 #define EFX_FEATURE_MCDI_DMA 0x00000200
1081 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1082 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1083 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1084 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1085 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1087 typedef struct efx_nic_cfg_s {
1088 uint32_t enc_board_type;
1089 uint32_t enc_phy_type;
1091 char enc_phy_name[21];
1093 char enc_phy_revision[21];
1094 efx_mon_type_t enc_mon_type;
1095 #if EFSYS_OPT_MON_STATS
1096 uint32_t enc_mon_stat_dma_buf_size;
1097 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1099 unsigned int enc_features;
1100 uint8_t enc_mac_addr[6];
1101 uint8_t enc_port; /* PHY port number */
1102 uint32_t enc_intr_vec_base;
1103 uint32_t enc_intr_limit;
1104 uint32_t enc_evq_limit;
1105 uint32_t enc_txq_limit;
1106 uint32_t enc_rxq_limit;
1107 uint32_t enc_txq_max_ndescs;
1108 uint32_t enc_buftbl_limit;
1109 uint32_t enc_piobuf_limit;
1110 uint32_t enc_piobuf_size;
1111 uint32_t enc_piobuf_min_alloc_size;
1112 uint32_t enc_evq_timer_quantum_ns;
1113 uint32_t enc_evq_timer_max_us;
1114 uint32_t enc_clk_mult;
1115 uint32_t enc_rx_prefix_size;
1116 uint32_t enc_rx_buf_align_start;
1117 uint32_t enc_rx_buf_align_end;
1118 #if EFSYS_OPT_LOOPBACK
1119 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1120 #endif /* EFSYS_OPT_LOOPBACK */
1121 #if EFSYS_OPT_PHY_FLAGS
1122 uint32_t enc_phy_flags_mask;
1123 #endif /* EFSYS_OPT_PHY_FLAGS */
1124 #if EFSYS_OPT_PHY_LED_CONTROL
1125 uint32_t enc_led_mask;
1126 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1127 #if EFSYS_OPT_PHY_STATS
1128 uint64_t enc_phy_stat_mask;
1129 #endif /* EFSYS_OPT_PHY_STATS */
1131 uint8_t enc_mcdi_mdio_channel;
1132 #if EFSYS_OPT_PHY_STATS
1133 uint32_t enc_mcdi_phy_stat_mask;
1134 #endif /* EFSYS_OPT_PHY_STATS */
1135 #if EFSYS_OPT_MON_STATS
1136 uint32_t *enc_mcdi_sensor_maskp;
1137 uint32_t enc_mcdi_sensor_mask_size;
1138 #endif /* EFSYS_OPT_MON_STATS */
1139 #endif /* EFSYS_OPT_MCDI */
1141 uint32_t enc_bist_mask;
1142 #endif /* EFSYS_OPT_BIST */
1143 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1146 uint32_t enc_privilege_mask;
1147 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1148 boolean_t enc_bug26807_workaround;
1149 boolean_t enc_bug35388_workaround;
1150 boolean_t enc_bug41750_workaround;
1151 boolean_t enc_bug61265_workaround;
1152 boolean_t enc_rx_batching_enabled;
1153 /* Maximum number of descriptors completed in an rx event. */
1154 uint32_t enc_rx_batch_max;
1155 /* Number of rx descriptors the hardware requires for a push. */
1156 uint32_t enc_rx_push_align;
1158 * Maximum number of bytes into the packet the TCP header can start for
1159 * the hardware to apply TSO packet edits.
1161 uint32_t enc_tx_tso_tcp_header_offset_limit;
1162 boolean_t enc_fw_assisted_tso_enabled;
1163 boolean_t enc_fw_assisted_tso_v2_enabled;
1164 /* Number of TSO contexts on the NIC (FATSOv2) */
1165 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1166 boolean_t enc_hw_tx_insert_vlan_enabled;
1167 /* Number of PFs on the NIC */
1168 uint32_t enc_hw_pf_count;
1169 /* Datapath firmware vadapter/vport/vswitch support */
1170 boolean_t enc_datapath_cap_evb;
1171 boolean_t enc_rx_disable_scatter_supported;
1172 boolean_t enc_allow_set_mac_with_installed_filters;
1173 boolean_t enc_enhanced_set_mac_supported;
1174 boolean_t enc_init_evq_v2_supported;
1175 boolean_t enc_rx_packed_stream_supported;
1176 boolean_t enc_rx_var_packed_stream_supported;
1177 boolean_t enc_pm_and_rxdp_counters;
1178 boolean_t enc_mac_stats_40g_tx_size_bins;
1179 /* External port identifier */
1180 uint8_t enc_external_port;
1181 uint32_t enc_mcdi_max_payload_length;
1182 /* VPD may be per-PF or global */
1183 boolean_t enc_vpd_is_global;
1184 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1185 uint32_t enc_required_pcie_bandwidth_mbps;
1186 uint32_t enc_max_pcie_link_gen;
1187 /* Firmware verifies integrity of NVRAM updates */
1188 uint32_t enc_fw_verified_nvram_update_required;
1191 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1192 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1194 #define EFX_PCI_FUNCTION(_encp) \
1195 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1197 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1199 extern const efx_nic_cfg_t *
1201 __in efx_nic_t *enp);
1203 /* Driver resource limits (minimum required/maximum usable). */
1204 typedef struct efx_drv_limits_s {
1205 uint32_t edl_min_evq_count;
1206 uint32_t edl_max_evq_count;
1208 uint32_t edl_min_rxq_count;
1209 uint32_t edl_max_rxq_count;
1211 uint32_t edl_min_txq_count;
1212 uint32_t edl_max_txq_count;
1214 /* PIO blocks (sub-allocated from piobuf) */
1215 uint32_t edl_min_pio_alloc_size;
1216 uint32_t edl_max_pio_alloc_count;
1219 extern __checkReturn efx_rc_t
1220 efx_nic_set_drv_limits(
1221 __inout efx_nic_t *enp,
1222 __in efx_drv_limits_t *edlp);
1224 typedef enum efx_nic_region_e {
1225 EFX_REGION_VI, /* Memory BAR UC mapping */
1226 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1229 extern __checkReturn efx_rc_t
1230 efx_nic_get_bar_region(
1231 __in efx_nic_t *enp,
1232 __in efx_nic_region_t region,
1233 __out uint32_t *offsetp,
1234 __out size_t *sizep);
1236 extern __checkReturn efx_rc_t
1237 efx_nic_get_vi_pool(
1238 __in efx_nic_t *enp,
1239 __out uint32_t *evq_countp,
1240 __out uint32_t *rxq_countp,
1241 __out uint32_t *txq_countp);
1248 typedef enum efx_pattern_type_t {
1249 EFX_PATTERN_BYTE_INCREMENT = 0,
1250 EFX_PATTERN_ALL_THE_SAME,
1251 EFX_PATTERN_BIT_ALTERNATE,
1252 EFX_PATTERN_BYTE_ALTERNATE,
1253 EFX_PATTERN_BYTE_CHANGING,
1254 EFX_PATTERN_BIT_SWEEP,
1256 } efx_pattern_type_t;
1259 (*efx_sram_pattern_fn_t)(
1261 __in boolean_t negate,
1262 __out efx_qword_t *eqp);
1264 extern __checkReturn efx_rc_t
1266 __in efx_nic_t *enp,
1267 __in efx_pattern_type_t type);
1269 #endif /* EFSYS_OPT_DIAG */
1271 extern __checkReturn efx_rc_t
1272 efx_sram_buf_tbl_set(
1273 __in efx_nic_t *enp,
1275 __in efsys_mem_t *esmp,
1279 efx_sram_buf_tbl_clear(
1280 __in efx_nic_t *enp,
1284 #define EFX_BUF_TBL_SIZE 0x20000
1286 #define EFX_BUF_SIZE 4096
1290 typedef struct efx_evq_s efx_evq_t;
1292 #if EFSYS_OPT_QSTATS
1294 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1295 typedef enum efx_ev_qstat_e {
1301 EV_RX_PAUSE_FRM_ERR,
1302 EV_RX_BUF_OWNER_ID_ERR,
1303 EV_RX_IPV4_HDR_CHKSUM_ERR,
1304 EV_RX_TCP_UDP_CHKSUM_ERR,
1308 EV_RX_MCAST_HASH_MATCH,
1325 EV_DRIVER_SRM_UPD_DONE,
1326 EV_DRIVER_TX_DESCQ_FLS_DONE,
1327 EV_DRIVER_RX_DESCQ_FLS_DONE,
1328 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1329 EV_DRIVER_RX_DSC_ERROR,
1330 EV_DRIVER_TX_DSC_ERROR,
1336 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1338 #endif /* EFSYS_OPT_QSTATS */
1340 extern __checkReturn efx_rc_t
1342 __in efx_nic_t *enp);
1346 __in efx_nic_t *enp);
1348 #define EFX_EVQ_MAXNEVS 32768
1349 #define EFX_EVQ_MINNEVS 512
1351 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1352 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1354 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1355 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1356 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1357 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1359 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1360 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1361 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1363 extern __checkReturn efx_rc_t
1365 __in efx_nic_t *enp,
1366 __in unsigned int index,
1367 __in efsys_mem_t *esmp,
1371 __in uint32_t flags,
1372 __deref_out efx_evq_t **eepp);
1376 __in efx_evq_t *eep,
1377 __in uint16_t data);
1379 typedef __checkReturn boolean_t
1380 (*efx_initialized_ev_t)(
1381 __in_opt void *arg);
1383 #define EFX_PKT_UNICAST 0x0004
1384 #define EFX_PKT_START 0x0008
1386 #define EFX_PKT_VLAN_TAGGED 0x0010
1387 #define EFX_CKSUM_TCPUDP 0x0020
1388 #define EFX_CKSUM_IPV4 0x0040
1389 #define EFX_PKT_CONT 0x0080
1391 #define EFX_CHECK_VLAN 0x0100
1392 #define EFX_PKT_TCP 0x0200
1393 #define EFX_PKT_UDP 0x0400
1394 #define EFX_PKT_IPV4 0x0800
1396 #define EFX_PKT_IPV6 0x1000
1397 #define EFX_PKT_PREFIX_LEN 0x2000
1398 #define EFX_ADDR_MISMATCH 0x4000
1399 #define EFX_DISCARD 0x8000
1402 * The following flags are used only for packed stream
1403 * mode. The values for the flags are reused to fit into 16 bit,
1404 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1405 * packed stream mode
1407 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1408 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1411 #define EFX_EV_RX_NLABELS 32
1412 #define EFX_EV_TX_NLABELS 32
1414 typedef __checkReturn boolean_t
1417 __in uint32_t label,
1420 __in uint16_t flags);
1422 #if EFSYS_OPT_RX_PACKED_STREAM
1425 * Packed stream mode is documented in SF-112241-TC.
1426 * The general idea is that, instead of putting each incoming
1427 * packet into a separate buffer which is specified in a RX
1428 * descriptor, a large buffer is provided to the hardware and
1429 * packets are put there in a continuous stream.
1430 * The main advantage of such an approach is that RX queue refilling
1431 * happens much less frequently.
1434 typedef __checkReturn boolean_t
1437 __in uint32_t label,
1439 __in uint32_t pkt_count,
1440 __in uint16_t flags);
1444 typedef __checkReturn boolean_t
1447 __in uint32_t label,
1450 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1451 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1452 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1453 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1454 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1455 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1456 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1457 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1458 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1460 typedef __checkReturn boolean_t
1461 (*efx_exception_ev_t)(
1463 __in uint32_t label,
1464 __in uint32_t data);
1466 typedef __checkReturn boolean_t
1467 (*efx_rxq_flush_done_ev_t)(
1469 __in uint32_t rxq_index);
1471 typedef __checkReturn boolean_t
1472 (*efx_rxq_flush_failed_ev_t)(
1474 __in uint32_t rxq_index);
1476 typedef __checkReturn boolean_t
1477 (*efx_txq_flush_done_ev_t)(
1479 __in uint32_t txq_index);
1481 typedef __checkReturn boolean_t
1482 (*efx_software_ev_t)(
1484 __in uint16_t magic);
1486 typedef __checkReturn boolean_t
1489 __in uint32_t code);
1491 #define EFX_SRAM_CLEAR 0
1492 #define EFX_SRAM_UPDATE 1
1493 #define EFX_SRAM_ILLEGAL_CLEAR 2
1495 typedef __checkReturn boolean_t
1496 (*efx_wake_up_ev_t)(
1498 __in uint32_t label);
1500 typedef __checkReturn boolean_t
1503 __in uint32_t label);
1505 typedef __checkReturn boolean_t
1506 (*efx_link_change_ev_t)(
1508 __in efx_link_mode_t link_mode);
1510 #if EFSYS_OPT_MON_STATS
1512 typedef __checkReturn boolean_t
1513 (*efx_monitor_ev_t)(
1515 __in efx_mon_stat_t id,
1516 __in efx_mon_stat_value_t value);
1518 #endif /* EFSYS_OPT_MON_STATS */
1520 #if EFSYS_OPT_MAC_STATS
1522 typedef __checkReturn boolean_t
1523 (*efx_mac_stats_ev_t)(
1525 __in uint32_t generation
1528 #endif /* EFSYS_OPT_MAC_STATS */
1530 typedef struct efx_ev_callbacks_s {
1531 efx_initialized_ev_t eec_initialized;
1533 #if EFSYS_OPT_RX_PACKED_STREAM
1534 efx_rx_ps_ev_t eec_rx_ps;
1537 efx_exception_ev_t eec_exception;
1538 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1539 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1540 efx_txq_flush_done_ev_t eec_txq_flush_done;
1541 efx_software_ev_t eec_software;
1542 efx_sram_ev_t eec_sram;
1543 efx_wake_up_ev_t eec_wake_up;
1544 efx_timer_ev_t eec_timer;
1545 efx_link_change_ev_t eec_link_change;
1546 #if EFSYS_OPT_MON_STATS
1547 efx_monitor_ev_t eec_monitor;
1548 #endif /* EFSYS_OPT_MON_STATS */
1549 #if EFSYS_OPT_MAC_STATS
1550 efx_mac_stats_ev_t eec_mac_stats;
1551 #endif /* EFSYS_OPT_MAC_STATS */
1552 } efx_ev_callbacks_t;
1554 extern __checkReturn boolean_t
1556 __in efx_evq_t *eep,
1557 __in unsigned int count);
1559 #if EFSYS_OPT_EV_PREFETCH
1563 __in efx_evq_t *eep,
1564 __in unsigned int count);
1566 #endif /* EFSYS_OPT_EV_PREFETCH */
1570 __in efx_evq_t *eep,
1571 __inout unsigned int *countp,
1572 __in const efx_ev_callbacks_t *eecp,
1573 __in_opt void *arg);
1575 extern __checkReturn efx_rc_t
1576 efx_ev_usecs_to_ticks(
1577 __in efx_nic_t *enp,
1578 __in unsigned int usecs,
1579 __out unsigned int *ticksp);
1581 extern __checkReturn efx_rc_t
1583 __in efx_evq_t *eep,
1584 __in unsigned int us);
1586 extern __checkReturn efx_rc_t
1588 __in efx_evq_t *eep,
1589 __in unsigned int count);
1591 #if EFSYS_OPT_QSTATS
1597 __in efx_nic_t *enp,
1598 __in unsigned int id);
1600 #endif /* EFSYS_OPT_NAMES */
1603 efx_ev_qstats_update(
1604 __in efx_evq_t *eep,
1605 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1607 #endif /* EFSYS_OPT_QSTATS */
1611 __in efx_evq_t *eep);
1615 extern __checkReturn efx_rc_t
1617 __inout efx_nic_t *enp);
1621 __in efx_nic_t *enp);
1623 #if EFSYS_OPT_RX_SCATTER
1624 __checkReturn efx_rc_t
1625 efx_rx_scatter_enable(
1626 __in efx_nic_t *enp,
1627 __in unsigned int buf_size);
1628 #endif /* EFSYS_OPT_RX_SCATTER */
1630 #if EFSYS_OPT_RX_SCALE
1632 typedef enum efx_rx_hash_alg_e {
1633 EFX_RX_HASHALG_LFSR = 0,
1634 EFX_RX_HASHALG_TOEPLITZ
1635 } efx_rx_hash_alg_t;
1637 typedef enum efx_rx_hash_type_e {
1638 EFX_RX_HASH_IPV4 = 0,
1639 EFX_RX_HASH_TCPIPV4,
1641 EFX_RX_HASH_TCPIPV6,
1642 } efx_rx_hash_type_t;
1644 typedef enum efx_rx_hash_support_e {
1645 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
1646 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
1647 } efx_rx_hash_support_t;
1649 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1650 #define EFX_MAXRSS 64 /* RX indirection entry range */
1651 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1653 typedef enum efx_rx_scale_support_e {
1654 EFX_RX_SCALE_UNAVAILABLE = 0, /* Not supported */
1655 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
1656 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
1657 } efx_rx_scale_support_t;
1659 extern __checkReturn efx_rc_t
1660 efx_rx_hash_support_get(
1661 __in efx_nic_t *enp,
1662 __out efx_rx_hash_support_t *supportp);
1665 extern __checkReturn efx_rc_t
1666 efx_rx_scale_support_get(
1667 __in efx_nic_t *enp,
1668 __out efx_rx_scale_support_t *supportp);
1670 extern __checkReturn efx_rc_t
1671 efx_rx_scale_mode_set(
1672 __in efx_nic_t *enp,
1673 __in efx_rx_hash_alg_t alg,
1674 __in efx_rx_hash_type_t type,
1675 __in boolean_t insert);
1677 extern __checkReturn efx_rc_t
1678 efx_rx_scale_tbl_set(
1679 __in efx_nic_t *enp,
1680 __in_ecount(n) unsigned int *table,
1683 extern __checkReturn efx_rc_t
1684 efx_rx_scale_key_set(
1685 __in efx_nic_t *enp,
1686 __in_ecount(n) uint8_t *key,
1689 extern __checkReturn uint32_t
1690 efx_pseudo_hdr_hash_get(
1691 __in efx_rxq_t *erp,
1692 __in efx_rx_hash_alg_t func,
1693 __in uint8_t *buffer);
1695 #endif /* EFSYS_OPT_RX_SCALE */
1697 extern __checkReturn efx_rc_t
1698 efx_pseudo_hdr_pkt_length_get(
1699 __in efx_rxq_t *erp,
1700 __in uint8_t *buffer,
1701 __out uint16_t *pkt_lengthp);
1703 #define EFX_RXQ_MAXNDESCS 4096
1704 #define EFX_RXQ_MINNDESCS 512
1706 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1707 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1708 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1709 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1711 typedef enum efx_rxq_type_e {
1712 EFX_RXQ_TYPE_DEFAULT,
1713 EFX_RXQ_TYPE_SCATTER,
1714 EFX_RXQ_TYPE_PACKED_STREAM_1M,
1715 EFX_RXQ_TYPE_PACKED_STREAM_512K,
1716 EFX_RXQ_TYPE_PACKED_STREAM_256K,
1717 EFX_RXQ_TYPE_PACKED_STREAM_128K,
1718 EFX_RXQ_TYPE_PACKED_STREAM_64K,
1722 extern __checkReturn efx_rc_t
1724 __in efx_nic_t *enp,
1725 __in unsigned int index,
1726 __in unsigned int label,
1727 __in efx_rxq_type_t type,
1728 __in efsys_mem_t *esmp,
1731 __in efx_evq_t *eep,
1732 __deref_out efx_rxq_t **erpp);
1734 typedef struct efx_buffer_s {
1735 efsys_dma_addr_t eb_addr;
1740 typedef struct efx_desc_s {
1746 __in efx_rxq_t *erp,
1747 __in_ecount(n) efsys_dma_addr_t *addrp,
1749 __in unsigned int n,
1750 __in unsigned int completed,
1751 __in unsigned int added);
1755 __in efx_rxq_t *erp,
1756 __in unsigned int added,
1757 __inout unsigned int *pushedp);
1759 #if EFSYS_OPT_RX_PACKED_STREAM
1762 * Fake length for RXQ descriptors in packed stream mode
1763 * to make hardware happy
1765 #define EFX_RXQ_PACKED_STREAM_FAKE_BUF_SIZE 32
1768 efx_rx_qps_update_credits(
1769 __in efx_rxq_t *erp);
1771 extern __checkReturn uint8_t *
1772 efx_rx_qps_packet_info(
1773 __in efx_rxq_t *erp,
1774 __in uint8_t *buffer,
1775 __in uint32_t buffer_length,
1776 __in uint32_t current_offset,
1777 __out uint16_t *lengthp,
1778 __out uint32_t *next_offsetp,
1779 __out uint32_t *timestamp);
1782 extern __checkReturn efx_rc_t
1784 __in efx_rxq_t *erp);
1788 __in efx_rxq_t *erp);
1792 __in efx_rxq_t *erp);
1796 typedef struct efx_txq_s efx_txq_t;
1798 #if EFSYS_OPT_QSTATS
1800 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1801 typedef enum efx_tx_qstat_e {
1807 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1809 #endif /* EFSYS_OPT_QSTATS */
1811 extern __checkReturn efx_rc_t
1813 __in efx_nic_t *enp);
1817 __in efx_nic_t *enp);
1819 #define EFX_TXQ_MINNDESCS 512
1821 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1822 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1823 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1824 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1826 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1828 #define EFX_TXQ_CKSUM_IPV4 0x0001
1829 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1830 #define EFX_TXQ_FATSOV2 0x0004
1832 extern __checkReturn efx_rc_t
1834 __in efx_nic_t *enp,
1835 __in unsigned int index,
1836 __in unsigned int label,
1837 __in efsys_mem_t *esmp,
1840 __in uint16_t flags,
1841 __in efx_evq_t *eep,
1842 __deref_out efx_txq_t **etpp,
1843 __out unsigned int *addedp);
1845 extern __checkReturn efx_rc_t
1847 __in efx_txq_t *etp,
1848 __in_ecount(n) efx_buffer_t *eb,
1849 __in unsigned int n,
1850 __in unsigned int completed,
1851 __inout unsigned int *addedp);
1853 extern __checkReturn efx_rc_t
1855 __in efx_txq_t *etp,
1856 __in unsigned int ns);
1860 __in efx_txq_t *etp,
1861 __in unsigned int added,
1862 __in unsigned int pushed);
1864 extern __checkReturn efx_rc_t
1866 __in efx_txq_t *etp);
1870 __in efx_txq_t *etp);
1872 extern __checkReturn efx_rc_t
1874 __in efx_txq_t *etp);
1877 efx_tx_qpio_disable(
1878 __in efx_txq_t *etp);
1880 extern __checkReturn efx_rc_t
1882 __in efx_txq_t *etp,
1883 __in_ecount(buf_length) uint8_t *buffer,
1884 __in size_t buf_length,
1885 __in size_t pio_buf_offset);
1887 extern __checkReturn efx_rc_t
1889 __in efx_txq_t *etp,
1890 __in size_t pkt_length,
1891 __in unsigned int completed,
1892 __inout unsigned int *addedp);
1894 extern __checkReturn efx_rc_t
1896 __in efx_txq_t *etp,
1897 __in_ecount(n) efx_desc_t *ed,
1898 __in unsigned int n,
1899 __in unsigned int completed,
1900 __inout unsigned int *addedp);
1903 efx_tx_qdesc_dma_create(
1904 __in efx_txq_t *etp,
1905 __in efsys_dma_addr_t addr,
1908 __out efx_desc_t *edp);
1911 efx_tx_qdesc_tso_create(
1912 __in efx_txq_t *etp,
1913 __in uint16_t ipv4_id,
1914 __in uint32_t tcp_seq,
1915 __in uint8_t tcp_flags,
1916 __out efx_desc_t *edp);
1918 /* Number of FATSOv2 option descriptors */
1919 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1921 /* Maximum number of DMA segments per TSO packet (not superframe) */
1922 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1925 efx_tx_qdesc_tso2_create(
1926 __in efx_txq_t *etp,
1927 __in uint16_t ipv4_id,
1928 __in uint32_t tcp_seq,
1929 __in uint16_t tcp_mss,
1930 __out_ecount(count) efx_desc_t *edp,
1934 efx_tx_qdesc_vlantci_create(
1935 __in efx_txq_t *etp,
1937 __out efx_desc_t *edp);
1939 #if EFSYS_OPT_QSTATS
1945 __in efx_nic_t *etp,
1946 __in unsigned int id);
1948 #endif /* EFSYS_OPT_NAMES */
1951 efx_tx_qstats_update(
1952 __in efx_txq_t *etp,
1953 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1955 #endif /* EFSYS_OPT_QSTATS */
1959 __in efx_txq_t *etp);
1964 #if EFSYS_OPT_FILTER
1966 #define EFX_ETHER_TYPE_IPV4 0x0800
1967 #define EFX_ETHER_TYPE_IPV6 0x86DD
1969 #define EFX_IPPROTO_TCP 6
1970 #define EFX_IPPROTO_UDP 17
1972 /* Use RSS to spread across multiple queues */
1973 #define EFX_FILTER_FLAG_RX_RSS 0x01
1974 /* Enable RX scatter */
1975 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1977 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1978 * May only be set by the filter implementation for each type.
1979 * A removal request will restore the automatic filter in its place.
1981 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1982 /* Filter is for RX */
1983 #define EFX_FILTER_FLAG_RX 0x08
1984 /* Filter is for TX */
1985 #define EFX_FILTER_FLAG_TX 0x10
1987 typedef unsigned int efx_filter_flags_t;
1989 typedef enum efx_filter_match_flags_e {
1990 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1992 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1994 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1995 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1996 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1997 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1998 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1999 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
2000 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
2001 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
2003 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
2004 * I/G bit. Used for RX default
2005 * unicast and multicast/
2006 * broadcast filters. */
2007 } efx_filter_match_flags_t;
2009 typedef enum efx_filter_priority_s {
2010 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2011 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2012 * address list or hardware
2013 * requirements. This may only be used
2014 * by the filter implementation for
2016 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2017 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2018 * client (e.g. SR-IOV, HyperV VMQ etc.)
2020 } efx_filter_priority_t;
2023 * FIXME: All these fields are assumed to be in little-endian byte order.
2024 * It may be better for some to be big-endian. See bug42804.
2027 typedef struct efx_filter_spec_s {
2028 uint32_t efs_match_flags:12;
2029 uint32_t efs_priority:2;
2030 uint32_t efs_flags:6;
2031 uint32_t efs_dmaq_id:12;
2032 uint32_t efs_rss_context;
2033 uint16_t efs_outer_vid;
2034 uint16_t efs_inner_vid;
2035 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2036 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2037 uint16_t efs_ether_type;
2038 uint8_t efs_ip_proto;
2039 uint16_t efs_loc_port;
2040 uint16_t efs_rem_port;
2041 efx_oword_t efs_rem_host;
2042 efx_oword_t efs_loc_host;
2043 } efx_filter_spec_t;
2046 /* Default values for use in filter specifications */
2047 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
2048 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2049 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2051 extern __checkReturn efx_rc_t
2053 __in efx_nic_t *enp);
2057 __in efx_nic_t *enp);
2059 extern __checkReturn efx_rc_t
2061 __in efx_nic_t *enp,
2062 __inout efx_filter_spec_t *spec);
2064 extern __checkReturn efx_rc_t
2066 __in efx_nic_t *enp,
2067 __inout efx_filter_spec_t *spec);
2069 extern __checkReturn efx_rc_t
2071 __in efx_nic_t *enp);
2073 extern __checkReturn efx_rc_t
2074 efx_filter_supported_filters(
2075 __in efx_nic_t *enp,
2076 __out uint32_t *list,
2077 __out size_t *length);
2080 efx_filter_spec_init_rx(
2081 __out efx_filter_spec_t *spec,
2082 __in efx_filter_priority_t priority,
2083 __in efx_filter_flags_t flags,
2084 __in efx_rxq_t *erp);
2087 efx_filter_spec_init_tx(
2088 __out efx_filter_spec_t *spec,
2089 __in efx_txq_t *etp);
2091 extern __checkReturn efx_rc_t
2092 efx_filter_spec_set_ipv4_local(
2093 __inout efx_filter_spec_t *spec,
2096 __in uint16_t port);
2098 extern __checkReturn efx_rc_t
2099 efx_filter_spec_set_ipv4_full(
2100 __inout efx_filter_spec_t *spec,
2102 __in uint32_t lhost,
2103 __in uint16_t lport,
2104 __in uint32_t rhost,
2105 __in uint16_t rport);
2107 extern __checkReturn efx_rc_t
2108 efx_filter_spec_set_eth_local(
2109 __inout efx_filter_spec_t *spec,
2111 __in const uint8_t *addr);
2113 extern __checkReturn efx_rc_t
2114 efx_filter_spec_set_uc_def(
2115 __inout efx_filter_spec_t *spec);
2117 extern __checkReturn efx_rc_t
2118 efx_filter_spec_set_mc_def(
2119 __inout efx_filter_spec_t *spec);
2121 #endif /* EFSYS_OPT_FILTER */
2125 extern __checkReturn uint32_t
2127 __in_ecount(count) uint32_t const *input,
2129 __in uint32_t init);
2131 extern __checkReturn uint32_t
2133 __in_ecount(length) uint8_t const *input,
2135 __in uint32_t init);
2143 #endif /* _SYS_EFX_H */