1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2006-2018 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_check.h"
13 #include "efx_phy_ids.h"
19 #define EFX_STATIC_ASSERT(_cond) \
20 ((void)sizeof (char[(_cond) ? 1 : -1]))
22 #define EFX_ARRAY_SIZE(_array) \
23 (sizeof (_array) / sizeof ((_array)[0]))
25 #define EFX_FIELD_OFFSET(_type, _field) \
26 ((size_t)&(((_type *)0)->_field))
28 /* The macro expands divider twice */
29 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
33 typedef __success(return == 0) int efx_rc_t;
38 typedef enum efx_family_e {
40 EFX_FAMILY_FALCON, /* Obsolete and not supported */
42 EFX_FAMILY_HUNTINGTON,
48 extern __checkReturn efx_rc_t
52 __out efx_family_t *efp,
53 __out unsigned int *membarp);
56 #define EFX_PCI_VENID_SFC 0x1924
58 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
60 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
61 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
62 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
64 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
65 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
66 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
68 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
69 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
71 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
72 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
73 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
75 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
76 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
77 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
80 #define EFX_MEM_BAR_SIENA 2
82 #define EFX_MEM_BAR_HUNTINGTON_PF 2
83 #define EFX_MEM_BAR_HUNTINGTON_VF 0
85 #define EFX_MEM_BAR_MEDFORD_PF 2
86 #define EFX_MEM_BAR_MEDFORD_VF 0
88 #define EFX_MEM_BAR_MEDFORD2 0
109 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
110 extern __checkReturn uint32_t
112 __in uint32_t crc_init,
113 __in_ecount(length) uint8_t const *input,
117 /* Type prototypes */
119 typedef struct efx_rxq_s efx_rxq_t;
123 typedef struct efx_nic_s efx_nic_t;
125 extern __checkReturn efx_rc_t
127 __in efx_family_t family,
128 __in efsys_identifier_t *esip,
129 __in efsys_bar_t *esbp,
130 __in efsys_lock_t *eslp,
131 __deref_out efx_nic_t **enpp);
133 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
134 typedef enum efx_fw_variant_e {
135 EFX_FW_VARIANT_FULL_FEATURED,
136 EFX_FW_VARIANT_LOW_LATENCY,
137 EFX_FW_VARIANT_PACKED_STREAM,
138 EFX_FW_VARIANT_HIGH_TX_RATE,
139 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
140 EFX_FW_VARIANT_RULES_ENGINE,
142 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
145 extern __checkReturn efx_rc_t
148 __in efx_fw_variant_t efv);
150 extern __checkReturn efx_rc_t
152 __in efx_nic_t *enp);
154 extern __checkReturn efx_rc_t
156 __in efx_nic_t *enp);
160 extern __checkReturn efx_rc_t
161 efx_nic_register_test(
162 __in efx_nic_t *enp);
164 #endif /* EFSYS_OPT_DIAG */
168 __in efx_nic_t *enp);
172 __in efx_nic_t *enp);
176 __in efx_nic_t *enp);
178 #define EFX_PCIE_LINK_SPEED_GEN1 1
179 #define EFX_PCIE_LINK_SPEED_GEN2 2
180 #define EFX_PCIE_LINK_SPEED_GEN3 3
182 typedef enum efx_pcie_link_performance_e {
183 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
184 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
185 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
186 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
187 } efx_pcie_link_performance_t;
189 extern __checkReturn efx_rc_t
190 efx_nic_calculate_pcie_link_bandwidth(
191 __in uint32_t pcie_link_width,
192 __in uint32_t pcie_link_gen,
193 __out uint32_t *bandwidth_mbpsp);
195 extern __checkReturn efx_rc_t
196 efx_nic_check_pcie_link_speed(
198 __in uint32_t pcie_link_width,
199 __in uint32_t pcie_link_gen,
200 __out efx_pcie_link_performance_t *resultp);
204 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
205 /* Huntington and Medford require MCDIv2 commands */
206 #define WITH_MCDI_V2 1
209 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
211 typedef enum efx_mcdi_exception_e {
212 EFX_MCDI_EXCEPTION_MC_REBOOT,
213 EFX_MCDI_EXCEPTION_MC_BADASSERT,
214 } efx_mcdi_exception_t;
216 #if EFSYS_OPT_MCDI_LOGGING
217 typedef enum efx_log_msg_e {
219 EFX_LOG_MCDI_REQUEST,
220 EFX_LOG_MCDI_RESPONSE,
222 #endif /* EFSYS_OPT_MCDI_LOGGING */
224 typedef struct efx_mcdi_transport_s {
226 efsys_mem_t *emt_dma_mem;
227 void (*emt_execute)(void *, efx_mcdi_req_t *);
228 void (*emt_ev_cpl)(void *);
229 void (*emt_exception)(void *, efx_mcdi_exception_t);
230 #if EFSYS_OPT_MCDI_LOGGING
231 void (*emt_logger)(void *, efx_log_msg_t,
232 void *, size_t, void *, size_t);
233 #endif /* EFSYS_OPT_MCDI_LOGGING */
234 #if EFSYS_OPT_MCDI_PROXY_AUTH
235 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
236 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
237 } efx_mcdi_transport_t;
239 extern __checkReturn efx_rc_t
242 __in const efx_mcdi_transport_t *mtp);
244 extern __checkReturn efx_rc_t
246 __in efx_nic_t *enp);
250 __in efx_nic_t *enp);
253 efx_mcdi_get_timeout(
255 __in efx_mcdi_req_t *emrp,
256 __out uint32_t *usec_timeoutp);
259 efx_mcdi_request_start(
261 __in efx_mcdi_req_t *emrp,
262 __in boolean_t ev_cpl);
264 extern __checkReturn boolean_t
265 efx_mcdi_request_poll(
266 __in efx_nic_t *enp);
268 extern __checkReturn boolean_t
269 efx_mcdi_request_abort(
270 __in efx_nic_t *enp);
274 __in efx_nic_t *enp);
276 #endif /* EFSYS_OPT_MCDI */
280 #define EFX_NINTR_SIENA 1024
282 typedef enum efx_intr_type_e {
283 EFX_INTR_INVALID = 0,
289 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
291 extern __checkReturn efx_rc_t
294 __in efx_intr_type_t type,
295 __in efsys_mem_t *esmp);
299 __in efx_nic_t *enp);
303 __in efx_nic_t *enp);
306 efx_intr_disable_unlocked(
307 __in efx_nic_t *enp);
309 #define EFX_INTR_NEVQS 32
311 extern __checkReturn efx_rc_t
314 __in unsigned int level);
317 efx_intr_status_line(
319 __out boolean_t *fatalp,
320 __out uint32_t *maskp);
323 efx_intr_status_message(
325 __in unsigned int message,
326 __out boolean_t *fatalp);
330 __in efx_nic_t *enp);
334 __in efx_nic_t *enp);
338 #if EFSYS_OPT_MAC_STATS
340 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
341 typedef enum efx_mac_stat_e {
344 EFX_MAC_RX_UNICST_PKTS,
345 EFX_MAC_RX_MULTICST_PKTS,
346 EFX_MAC_RX_BRDCST_PKTS,
347 EFX_MAC_RX_PAUSE_PKTS,
348 EFX_MAC_RX_LE_64_PKTS,
349 EFX_MAC_RX_65_TO_127_PKTS,
350 EFX_MAC_RX_128_TO_255_PKTS,
351 EFX_MAC_RX_256_TO_511_PKTS,
352 EFX_MAC_RX_512_TO_1023_PKTS,
353 EFX_MAC_RX_1024_TO_15XX_PKTS,
354 EFX_MAC_RX_GE_15XX_PKTS,
356 EFX_MAC_RX_FCS_ERRORS,
357 EFX_MAC_RX_DROP_EVENTS,
358 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
359 EFX_MAC_RX_SYMBOL_ERRORS,
360 EFX_MAC_RX_ALIGN_ERRORS,
361 EFX_MAC_RX_INTERNAL_ERRORS,
362 EFX_MAC_RX_JABBER_PKTS,
363 EFX_MAC_RX_LANE0_CHAR_ERR,
364 EFX_MAC_RX_LANE1_CHAR_ERR,
365 EFX_MAC_RX_LANE2_CHAR_ERR,
366 EFX_MAC_RX_LANE3_CHAR_ERR,
367 EFX_MAC_RX_LANE0_DISP_ERR,
368 EFX_MAC_RX_LANE1_DISP_ERR,
369 EFX_MAC_RX_LANE2_DISP_ERR,
370 EFX_MAC_RX_LANE3_DISP_ERR,
371 EFX_MAC_RX_MATCH_FAULT,
372 EFX_MAC_RX_NODESC_DROP_CNT,
375 EFX_MAC_TX_UNICST_PKTS,
376 EFX_MAC_TX_MULTICST_PKTS,
377 EFX_MAC_TX_BRDCST_PKTS,
378 EFX_MAC_TX_PAUSE_PKTS,
379 EFX_MAC_TX_LE_64_PKTS,
380 EFX_MAC_TX_65_TO_127_PKTS,
381 EFX_MAC_TX_128_TO_255_PKTS,
382 EFX_MAC_TX_256_TO_511_PKTS,
383 EFX_MAC_TX_512_TO_1023_PKTS,
384 EFX_MAC_TX_1024_TO_15XX_PKTS,
385 EFX_MAC_TX_GE_15XX_PKTS,
387 EFX_MAC_TX_SGL_COL_PKTS,
388 EFX_MAC_TX_MULT_COL_PKTS,
389 EFX_MAC_TX_EX_COL_PKTS,
390 EFX_MAC_TX_LATE_COL_PKTS,
392 EFX_MAC_TX_EX_DEF_PKTS,
393 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
394 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
395 EFX_MAC_PM_TRUNC_VFIFO_FULL,
396 EFX_MAC_PM_DISCARD_VFIFO_FULL,
397 EFX_MAC_PM_TRUNC_QBB,
398 EFX_MAC_PM_DISCARD_QBB,
399 EFX_MAC_PM_DISCARD_MAPPING,
400 EFX_MAC_RXDP_Q_DISABLED_PKTS,
401 EFX_MAC_RXDP_DI_DROPPED_PKTS,
402 EFX_MAC_RXDP_STREAMING_PKTS,
403 EFX_MAC_RXDP_HLB_FETCH,
404 EFX_MAC_RXDP_HLB_WAIT,
405 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
406 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
407 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
408 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
409 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
410 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
411 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
412 EFX_MAC_VADAPTER_RX_BAD_BYTES,
413 EFX_MAC_VADAPTER_RX_OVERFLOW,
414 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
415 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
416 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
417 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
418 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
419 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
420 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
421 EFX_MAC_VADAPTER_TX_BAD_BYTES,
422 EFX_MAC_VADAPTER_TX_OVERFLOW,
423 EFX_MAC_FEC_UNCORRECTED_ERRORS,
424 EFX_MAC_FEC_CORRECTED_ERRORS,
425 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
426 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
427 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
428 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
429 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
430 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
431 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
432 EFX_MAC_CTPIO_OVERFLOW_FAIL,
433 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
434 EFX_MAC_CTPIO_TIMEOUT_FAIL,
435 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
436 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
437 EFX_MAC_CTPIO_INVALID_WR_FAIL,
438 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
439 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
440 EFX_MAC_CTPIO_RUNT_FALLBACK,
441 EFX_MAC_CTPIO_SUCCESS,
442 EFX_MAC_CTPIO_FALLBACK,
443 EFX_MAC_CTPIO_POISON,
445 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
446 EFX_MAC_RXDP_HLB_IDLE,
447 EFX_MAC_RXDP_HLB_TIMEOUT,
451 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
453 #endif /* EFSYS_OPT_MAC_STATS */
455 typedef enum efx_link_mode_e {
456 EFX_LINK_UNKNOWN = 0,
472 #define EFX_MAC_ADDR_LEN 6
474 #define EFX_VNI_OR_VSID_LEN 3
476 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
478 #define EFX_MAC_MULTICAST_LIST_MAX 256
480 #define EFX_MAC_SDU_MAX 9202
482 #define EFX_MAC_PDU_ADJUSTMENT \
486 + /* bug16011 */ 16) \
488 #define EFX_MAC_PDU(_sdu) \
489 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
492 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
493 * the SDU rounded up slightly.
495 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
497 #define EFX_MAC_PDU_MIN 60
498 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
500 extern __checkReturn efx_rc_t
505 extern __checkReturn efx_rc_t
510 extern __checkReturn efx_rc_t
515 extern __checkReturn efx_rc_t
518 __in boolean_t all_unicst,
519 __in boolean_t mulcst,
520 __in boolean_t all_mulcst,
521 __in boolean_t brdcst);
523 extern __checkReturn efx_rc_t
524 efx_mac_multicast_list_set(
526 __in_ecount(6*count) uint8_t const *addrs,
529 extern __checkReturn efx_rc_t
530 efx_mac_filter_default_rxq_set(
533 __in boolean_t using_rss);
536 efx_mac_filter_default_rxq_clear(
537 __in efx_nic_t *enp);
539 extern __checkReturn efx_rc_t
542 __in boolean_t enabled);
544 extern __checkReturn efx_rc_t
547 __out boolean_t *mac_upp);
549 #define EFX_FCNTL_RESPOND 0x00000001
550 #define EFX_FCNTL_GENERATE 0x00000002
552 extern __checkReturn efx_rc_t
555 __in unsigned int fcntl,
556 __in boolean_t autoneg);
561 __out unsigned int *fcntl_wantedp,
562 __out unsigned int *fcntl_linkp);
565 #if EFSYS_OPT_MAC_STATS
569 extern __checkReturn const char *
572 __in unsigned int id);
574 #endif /* EFSYS_OPT_NAMES */
576 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
578 #define EFX_MAC_STATS_MASK_NPAGES \
579 (P2ROUNDUP(EFX_MAC_NSTATS, EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
580 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
583 * Get mask of MAC statistics supported by the hardware.
585 * If mask_size is insufficient to return the mask, EINVAL error is
586 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
587 * (which is sizeof (uint32_t)) is sufficient.
589 extern __checkReturn efx_rc_t
590 efx_mac_stats_get_mask(
592 __out_bcount(mask_size) uint32_t *maskp,
593 __in size_t mask_size);
595 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
596 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
597 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
600 extern __checkReturn efx_rc_t
602 __in efx_nic_t *enp);
605 * Upload mac statistics supported by the hardware into the given buffer.
607 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
608 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
610 * The hardware will only DMA statistics that it understands (of course).
611 * Drivers should not make any assumptions about which statistics are
612 * supported, especially when the statistics are generated by firmware.
614 * Thus, drivers should zero this buffer before use, so that not-understood
615 * statistics read back as zero.
617 extern __checkReturn efx_rc_t
618 efx_mac_stats_upload(
620 __in efsys_mem_t *esmp);
622 extern __checkReturn efx_rc_t
623 efx_mac_stats_periodic(
625 __in efsys_mem_t *esmp,
626 __in uint16_t period_ms,
627 __in boolean_t events);
629 extern __checkReturn efx_rc_t
630 efx_mac_stats_update(
632 __in efsys_mem_t *esmp,
633 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
634 __inout_opt uint32_t *generationp);
636 #endif /* EFSYS_OPT_MAC_STATS */
640 typedef enum efx_mon_type_e {
652 __in efx_nic_t *enp);
654 #endif /* EFSYS_OPT_NAMES */
656 extern __checkReturn efx_rc_t
658 __in efx_nic_t *enp);
660 #if EFSYS_OPT_MON_STATS
662 #define EFX_MON_STATS_PAGE_SIZE 0x100
663 #define EFX_MON_MASK_ELEMENT_SIZE 32
665 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
666 typedef enum efx_mon_stat_e {
667 EFX_MON_STAT_CONTROLLER_TEMP,
668 EFX_MON_STAT_PHY_COMMON_TEMP,
669 EFX_MON_STAT_CONTROLLER_COOLING,
670 EFX_MON_STAT_PHY0_TEMP,
671 EFX_MON_STAT_PHY0_COOLING,
672 EFX_MON_STAT_PHY1_TEMP,
673 EFX_MON_STAT_PHY1_COOLING,
679 EFX_MON_STAT_IN_12V0,
680 EFX_MON_STAT_IN_1V2A,
681 EFX_MON_STAT_IN_VREF,
682 EFX_MON_STAT_OUT_VAOE,
683 EFX_MON_STAT_AOE_TEMP,
684 EFX_MON_STAT_PSU_AOE_TEMP,
685 EFX_MON_STAT_PSU_TEMP,
691 EFX_MON_STAT_IN_VAOE,
692 EFX_MON_STAT_OUT_IAOE,
693 EFX_MON_STAT_IN_IAOE,
694 EFX_MON_STAT_NIC_POWER,
696 EFX_MON_STAT_IN_I0V9,
697 EFX_MON_STAT_IN_I1V2,
698 EFX_MON_STAT_IN_0V9_ADC,
699 EFX_MON_STAT_CONTROLLER_2_TEMP,
700 EFX_MON_STAT_VREG_INTERNAL_TEMP,
701 EFX_MON_STAT_VREG_0V9_TEMP,
702 EFX_MON_STAT_VREG_1V2_TEMP,
703 EFX_MON_STAT_CONTROLLER_VPTAT,
704 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
705 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
706 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
707 EFX_MON_STAT_AMBIENT_TEMP,
708 EFX_MON_STAT_AIRFLOW,
709 EFX_MON_STAT_VDD08D_VSS08D_CSR,
710 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
711 EFX_MON_STAT_HOTPOINT_TEMP,
712 EFX_MON_STAT_PHY_POWER_PORT0,
713 EFX_MON_STAT_PHY_POWER_PORT1,
714 EFX_MON_STAT_MUM_VCC,
715 EFX_MON_STAT_IN_0V9_A,
716 EFX_MON_STAT_IN_I0V9_A,
717 EFX_MON_STAT_VREG_0V9_A_TEMP,
718 EFX_MON_STAT_IN_0V9_B,
719 EFX_MON_STAT_IN_I0V9_B,
720 EFX_MON_STAT_VREG_0V9_B_TEMP,
721 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
722 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
723 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
724 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
725 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
726 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
727 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
728 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
729 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
730 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
731 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
732 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
733 EFX_MON_STAT_SODIMM_VOUT,
734 EFX_MON_STAT_SODIMM_0_TEMP,
735 EFX_MON_STAT_SODIMM_1_TEMP,
736 EFX_MON_STAT_PHY0_VCC,
737 EFX_MON_STAT_PHY1_VCC,
738 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
739 EFX_MON_STAT_BOARD_FRONT_TEMP,
740 EFX_MON_STAT_BOARD_BACK_TEMP,
741 EFX_MON_STAT_IN_I1V8,
742 EFX_MON_STAT_IN_I2V5,
743 EFX_MON_STAT_IN_I3V3,
744 EFX_MON_STAT_IN_I12V0,
746 EFX_MON_STAT_IN_I1V3,
750 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
752 typedef enum efx_mon_stat_state_e {
753 EFX_MON_STAT_STATE_OK = 0,
754 EFX_MON_STAT_STATE_WARNING = 1,
755 EFX_MON_STAT_STATE_FATAL = 2,
756 EFX_MON_STAT_STATE_BROKEN = 3,
757 EFX_MON_STAT_STATE_NO_READING = 4,
758 } efx_mon_stat_state_t;
760 typedef enum efx_mon_stat_unit_e {
761 EFX_MON_STAT_UNIT_UNKNOWN = 0,
762 EFX_MON_STAT_UNIT_BOOL,
763 EFX_MON_STAT_UNIT_TEMP_C,
764 EFX_MON_STAT_UNIT_VOLTAGE_MV,
765 EFX_MON_STAT_UNIT_CURRENT_MA,
766 EFX_MON_STAT_UNIT_POWER_W,
767 EFX_MON_STAT_UNIT_RPM,
769 } efx_mon_stat_unit_t;
771 typedef struct efx_mon_stat_value_s {
773 efx_mon_stat_state_t emsv_state;
774 efx_mon_stat_unit_t emsv_unit;
775 } efx_mon_stat_value_t;
777 typedef struct efx_mon_limit_value_s {
778 uint16_t emlv_warning_min;
779 uint16_t emlv_warning_max;
780 uint16_t emlv_fatal_min;
781 uint16_t emlv_fatal_max;
782 } efx_mon_stat_limits_t;
784 typedef enum efx_mon_stat_portmask_e {
785 EFX_MON_STAT_PORTMAP_NONE = 0,
786 EFX_MON_STAT_PORTMAP_PORT0 = 1,
787 EFX_MON_STAT_PORTMAP_PORT1 = 2,
788 EFX_MON_STAT_PORTMAP_PORT2 = 3,
789 EFX_MON_STAT_PORTMAP_PORT3 = 4,
790 EFX_MON_STAT_PORTMAP_ALL = (-1),
791 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
792 } efx_mon_stat_portmask_t;
799 __in efx_mon_stat_t id);
802 efx_mon_stat_description(
804 __in efx_mon_stat_t id);
806 #endif /* EFSYS_OPT_NAMES */
808 extern __checkReturn boolean_t
809 efx_mon_mcdi_to_efx_stat(
811 __out efx_mon_stat_t *statp);
813 extern __checkReturn boolean_t
814 efx_mon_get_stat_unit(
815 __in efx_mon_stat_t stat,
816 __out efx_mon_stat_unit_t *unitp);
818 extern __checkReturn boolean_t
819 efx_mon_get_stat_portmap(
820 __in efx_mon_stat_t stat,
821 __out efx_mon_stat_portmask_t *maskp);
823 extern __checkReturn efx_rc_t
824 efx_mon_stats_update(
826 __in efsys_mem_t *esmp,
827 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
829 extern __checkReturn efx_rc_t
830 efx_mon_limits_update(
832 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
834 #endif /* EFSYS_OPT_MON_STATS */
838 __in efx_nic_t *enp);
842 extern __checkReturn efx_rc_t
844 __in efx_nic_t *enp);
846 #if EFSYS_OPT_PHY_LED_CONTROL
848 typedef enum efx_phy_led_mode_e {
849 EFX_PHY_LED_DEFAULT = 0,
854 } efx_phy_led_mode_t;
856 extern __checkReturn efx_rc_t
859 __in efx_phy_led_mode_t mode);
861 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
863 extern __checkReturn efx_rc_t
865 __in efx_nic_t *enp);
867 #if EFSYS_OPT_LOOPBACK
869 typedef enum efx_loopback_type_e {
870 EFX_LOOPBACK_OFF = 0,
871 EFX_LOOPBACK_DATA = 1,
872 EFX_LOOPBACK_GMAC = 2,
873 EFX_LOOPBACK_XGMII = 3,
874 EFX_LOOPBACK_XGXS = 4,
875 EFX_LOOPBACK_XAUI = 5,
876 EFX_LOOPBACK_GMII = 6,
877 EFX_LOOPBACK_SGMII = 7,
878 EFX_LOOPBACK_XGBR = 8,
879 EFX_LOOPBACK_XFI = 9,
880 EFX_LOOPBACK_XAUI_FAR = 10,
881 EFX_LOOPBACK_GMII_FAR = 11,
882 EFX_LOOPBACK_SGMII_FAR = 12,
883 EFX_LOOPBACK_XFI_FAR = 13,
884 EFX_LOOPBACK_GPHY = 14,
885 EFX_LOOPBACK_PHY_XS = 15,
886 EFX_LOOPBACK_PCS = 16,
887 EFX_LOOPBACK_PMA_PMD = 17,
888 EFX_LOOPBACK_XPORT = 18,
889 EFX_LOOPBACK_XGMII_WS = 19,
890 EFX_LOOPBACK_XAUI_WS = 20,
891 EFX_LOOPBACK_XAUI_WS_FAR = 21,
892 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
893 EFX_LOOPBACK_GMII_WS = 23,
894 EFX_LOOPBACK_XFI_WS = 24,
895 EFX_LOOPBACK_XFI_WS_FAR = 25,
896 EFX_LOOPBACK_PHYXS_WS = 26,
897 EFX_LOOPBACK_PMA_INT = 27,
898 EFX_LOOPBACK_SD_NEAR = 28,
899 EFX_LOOPBACK_SD_FAR = 29,
900 EFX_LOOPBACK_PMA_INT_WS = 30,
901 EFX_LOOPBACK_SD_FEP2_WS = 31,
902 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
903 EFX_LOOPBACK_SD_FEP_WS = 33,
904 EFX_LOOPBACK_SD_FES_WS = 34,
905 EFX_LOOPBACK_AOE_INT_NEAR = 35,
906 EFX_LOOPBACK_DATA_WS = 36,
907 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
909 } efx_loopback_type_t;
911 typedef enum efx_loopback_kind_e {
912 EFX_LOOPBACK_KIND_OFF = 0,
913 EFX_LOOPBACK_KIND_ALL,
914 EFX_LOOPBACK_KIND_MAC,
915 EFX_LOOPBACK_KIND_PHY,
917 } efx_loopback_kind_t;
921 __in efx_loopback_kind_t loopback_kind,
922 __out efx_qword_t *maskp);
924 extern __checkReturn efx_rc_t
925 efx_port_loopback_set(
927 __in efx_link_mode_t link_mode,
928 __in efx_loopback_type_t type);
932 extern __checkReturn const char *
933 efx_loopback_type_name(
935 __in efx_loopback_type_t type);
937 #endif /* EFSYS_OPT_NAMES */
939 #endif /* EFSYS_OPT_LOOPBACK */
941 extern __checkReturn efx_rc_t
944 __out_opt efx_link_mode_t *link_modep);
948 __in efx_nic_t *enp);
950 typedef enum efx_phy_cap_type_e {
951 EFX_PHY_CAP_INVALID = 0,
958 EFX_PHY_CAP_10000FDX,
962 EFX_PHY_CAP_40000FDX,
964 EFX_PHY_CAP_100000FDX,
965 EFX_PHY_CAP_25000FDX,
966 EFX_PHY_CAP_50000FDX,
967 EFX_PHY_CAP_BASER_FEC,
968 EFX_PHY_CAP_BASER_FEC_REQUESTED,
970 EFX_PHY_CAP_RS_FEC_REQUESTED,
971 EFX_PHY_CAP_25G_BASER_FEC,
972 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
974 } efx_phy_cap_type_t;
977 #define EFX_PHY_CAP_CURRENT 0x00000000
978 #define EFX_PHY_CAP_DEFAULT 0x00000001
979 #define EFX_PHY_CAP_PERM 0x00000002
985 __out uint32_t *maskp);
987 extern __checkReturn efx_rc_t
995 __out uint32_t *maskp);
997 extern __checkReturn efx_rc_t
1000 __out uint32_t *ouip);
1002 typedef enum efx_phy_media_type_e {
1003 EFX_PHY_MEDIA_INVALID = 0,
1008 EFX_PHY_MEDIA_SFP_PLUS,
1009 EFX_PHY_MEDIA_BASE_T,
1010 EFX_PHY_MEDIA_QSFP_PLUS,
1011 EFX_PHY_MEDIA_NTYPES
1012 } efx_phy_media_type_t;
1015 * Get the type of medium currently used. If the board has ports for
1016 * modules, a module is present, and we recognise the media type of
1017 * the module, then this will be the media type of the module.
1018 * Otherwise it will be the media type of the port.
1021 efx_phy_media_type_get(
1022 __in efx_nic_t *enp,
1023 __out efx_phy_media_type_t *typep);
1025 extern __checkReturn efx_rc_t
1026 efx_phy_module_get_info(
1027 __in efx_nic_t *enp,
1028 __in uint8_t dev_addr,
1029 __in uint8_t offset,
1031 __out_bcount(len) uint8_t *data);
1033 #if EFSYS_OPT_PHY_STATS
1035 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1036 typedef enum efx_phy_stat_e {
1038 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1039 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1040 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1041 EFX_PHY_STAT_PMA_PMD_REV_A,
1042 EFX_PHY_STAT_PMA_PMD_REV_B,
1043 EFX_PHY_STAT_PMA_PMD_REV_C,
1044 EFX_PHY_STAT_PMA_PMD_REV_D,
1045 EFX_PHY_STAT_PCS_LINK_UP,
1046 EFX_PHY_STAT_PCS_RX_FAULT,
1047 EFX_PHY_STAT_PCS_TX_FAULT,
1048 EFX_PHY_STAT_PCS_BER,
1049 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1050 EFX_PHY_STAT_PHY_XS_LINK_UP,
1051 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1052 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1053 EFX_PHY_STAT_PHY_XS_ALIGN,
1054 EFX_PHY_STAT_PHY_XS_SYNC_A,
1055 EFX_PHY_STAT_PHY_XS_SYNC_B,
1056 EFX_PHY_STAT_PHY_XS_SYNC_C,
1057 EFX_PHY_STAT_PHY_XS_SYNC_D,
1058 EFX_PHY_STAT_AN_LINK_UP,
1059 EFX_PHY_STAT_AN_MASTER,
1060 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1061 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1062 EFX_PHY_STAT_CL22EXT_LINK_UP,
1067 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1068 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1069 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1070 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1071 EFX_PHY_STAT_AN_COMPLETE,
1072 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1073 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1074 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1075 EFX_PHY_STAT_PCS_FW_VERSION_0,
1076 EFX_PHY_STAT_PCS_FW_VERSION_1,
1077 EFX_PHY_STAT_PCS_FW_VERSION_2,
1078 EFX_PHY_STAT_PCS_FW_VERSION_3,
1079 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1080 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1081 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1082 EFX_PHY_STAT_PCS_OP_MODE,
1086 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1092 __in efx_nic_t *enp,
1093 __in efx_phy_stat_t stat);
1095 #endif /* EFSYS_OPT_NAMES */
1097 #define EFX_PHY_STATS_SIZE 0x100
1099 extern __checkReturn efx_rc_t
1100 efx_phy_stats_update(
1101 __in efx_nic_t *enp,
1102 __in efsys_mem_t *esmp,
1103 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1105 #endif /* EFSYS_OPT_PHY_STATS */
1110 typedef enum efx_bist_type_e {
1111 EFX_BIST_TYPE_UNKNOWN,
1112 EFX_BIST_TYPE_PHY_NORMAL,
1113 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1114 EFX_BIST_TYPE_PHY_CABLE_LONG,
1115 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1116 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1117 EFX_BIST_TYPE_REG, /* Test the register memories */
1118 EFX_BIST_TYPE_NTYPES,
1121 typedef enum efx_bist_result_e {
1122 EFX_BIST_RESULT_UNKNOWN,
1123 EFX_BIST_RESULT_RUNNING,
1124 EFX_BIST_RESULT_PASSED,
1125 EFX_BIST_RESULT_FAILED,
1126 } efx_bist_result_t;
1128 typedef enum efx_phy_cable_status_e {
1129 EFX_PHY_CABLE_STATUS_OK,
1130 EFX_PHY_CABLE_STATUS_INVALID,
1131 EFX_PHY_CABLE_STATUS_OPEN,
1132 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1133 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1134 EFX_PHY_CABLE_STATUS_BUSY,
1135 } efx_phy_cable_status_t;
1137 typedef enum efx_bist_value_e {
1138 EFX_BIST_PHY_CABLE_LENGTH_A,
1139 EFX_BIST_PHY_CABLE_LENGTH_B,
1140 EFX_BIST_PHY_CABLE_LENGTH_C,
1141 EFX_BIST_PHY_CABLE_LENGTH_D,
1142 EFX_BIST_PHY_CABLE_STATUS_A,
1143 EFX_BIST_PHY_CABLE_STATUS_B,
1144 EFX_BIST_PHY_CABLE_STATUS_C,
1145 EFX_BIST_PHY_CABLE_STATUS_D,
1146 EFX_BIST_FAULT_CODE,
1148 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1154 EFX_BIST_MEM_EXPECT,
1155 EFX_BIST_MEM_ACTUAL,
1157 EFX_BIST_MEM_ECC_PARITY,
1158 EFX_BIST_MEM_ECC_FATAL,
1162 extern __checkReturn efx_rc_t
1163 efx_bist_enable_offline(
1164 __in efx_nic_t *enp);
1166 extern __checkReturn efx_rc_t
1168 __in efx_nic_t *enp,
1169 __in efx_bist_type_t type);
1171 extern __checkReturn efx_rc_t
1173 __in efx_nic_t *enp,
1174 __in efx_bist_type_t type,
1175 __out efx_bist_result_t *resultp,
1176 __out_opt uint32_t *value_maskp,
1177 __out_ecount_opt(count) unsigned long *valuesp,
1182 __in efx_nic_t *enp,
1183 __in efx_bist_type_t type);
1185 #endif /* EFSYS_OPT_BIST */
1187 #define EFX_FEATURE_IPV6 0x00000001
1188 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1189 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1190 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1191 #define EFX_FEATURE_MCDI 0x00000020
1192 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1193 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1194 #define EFX_FEATURE_TURBO 0x00000100
1195 #define EFX_FEATURE_MCDI_DMA 0x00000200
1196 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1197 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1198 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1199 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1200 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1202 typedef enum efx_tunnel_protocol_e {
1203 EFX_TUNNEL_PROTOCOL_NONE = 0,
1204 EFX_TUNNEL_PROTOCOL_VXLAN,
1205 EFX_TUNNEL_PROTOCOL_GENEVE,
1206 EFX_TUNNEL_PROTOCOL_NVGRE,
1208 } efx_tunnel_protocol_t;
1210 typedef enum efx_vi_window_shift_e {
1211 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1212 EFX_VI_WINDOW_SHIFT_8K = 13,
1213 EFX_VI_WINDOW_SHIFT_16K = 14,
1214 EFX_VI_WINDOW_SHIFT_64K = 16,
1215 } efx_vi_window_shift_t;
1217 typedef struct efx_nic_cfg_s {
1218 uint32_t enc_board_type;
1219 uint32_t enc_phy_type;
1221 char enc_phy_name[21];
1223 char enc_phy_revision[21];
1224 efx_mon_type_t enc_mon_type;
1225 #if EFSYS_OPT_MON_STATS
1226 uint32_t enc_mon_stat_dma_buf_size;
1227 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1229 unsigned int enc_features;
1230 efx_vi_window_shift_t enc_vi_window_shift;
1231 uint8_t enc_mac_addr[6];
1232 uint8_t enc_port; /* PHY port number */
1233 uint32_t enc_intr_vec_base;
1234 uint32_t enc_intr_limit;
1235 uint32_t enc_evq_limit;
1236 uint32_t enc_txq_limit;
1237 uint32_t enc_rxq_limit;
1238 uint32_t enc_txq_max_ndescs;
1239 uint32_t enc_buftbl_limit;
1240 uint32_t enc_piobuf_limit;
1241 uint32_t enc_piobuf_size;
1242 uint32_t enc_piobuf_min_alloc_size;
1243 uint32_t enc_evq_timer_quantum_ns;
1244 uint32_t enc_evq_timer_max_us;
1245 uint32_t enc_clk_mult;
1246 uint32_t enc_rx_prefix_size;
1247 uint32_t enc_rx_buf_align_start;
1248 uint32_t enc_rx_buf_align_end;
1249 uint32_t enc_rx_scale_max_exclusive_contexts;
1251 * Mask of supported hash algorithms.
1252 * Hash algorithm types are used as the bit indices.
1254 uint32_t enc_rx_scale_hash_alg_mask;
1256 * Indicates whether port numbers can be included to the
1257 * input data for hash computation.
1259 boolean_t enc_rx_scale_l4_hash_supported;
1260 boolean_t enc_rx_scale_additional_modes_supported;
1261 #if EFSYS_OPT_LOOPBACK
1262 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1263 #endif /* EFSYS_OPT_LOOPBACK */
1264 #if EFSYS_OPT_PHY_FLAGS
1265 uint32_t enc_phy_flags_mask;
1266 #endif /* EFSYS_OPT_PHY_FLAGS */
1267 #if EFSYS_OPT_PHY_LED_CONTROL
1268 uint32_t enc_led_mask;
1269 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1270 #if EFSYS_OPT_PHY_STATS
1271 uint64_t enc_phy_stat_mask;
1272 #endif /* EFSYS_OPT_PHY_STATS */
1274 uint8_t enc_mcdi_mdio_channel;
1275 #if EFSYS_OPT_PHY_STATS
1276 uint32_t enc_mcdi_phy_stat_mask;
1277 #endif /* EFSYS_OPT_PHY_STATS */
1278 #if EFSYS_OPT_MON_STATS
1279 uint32_t *enc_mcdi_sensor_maskp;
1280 uint32_t enc_mcdi_sensor_mask_size;
1281 #endif /* EFSYS_OPT_MON_STATS */
1282 #endif /* EFSYS_OPT_MCDI */
1284 uint32_t enc_bist_mask;
1285 #endif /* EFSYS_OPT_BIST */
1286 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
1289 uint32_t enc_privilege_mask;
1290 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
1291 boolean_t enc_bug26807_workaround;
1292 boolean_t enc_bug35388_workaround;
1293 boolean_t enc_bug41750_workaround;
1294 boolean_t enc_bug61265_workaround;
1295 boolean_t enc_rx_batching_enabled;
1296 /* Maximum number of descriptors completed in an rx event. */
1297 uint32_t enc_rx_batch_max;
1298 /* Number of rx descriptors the hardware requires for a push. */
1299 uint32_t enc_rx_push_align;
1300 /* Maximum amount of data in DMA descriptor */
1301 uint32_t enc_tx_dma_desc_size_max;
1303 * Boundary which DMA descriptor data must not cross or 0 if no
1306 uint32_t enc_tx_dma_desc_boundary;
1308 * Maximum number of bytes into the packet the TCP header can start for
1309 * the hardware to apply TSO packet edits.
1311 uint32_t enc_tx_tso_tcp_header_offset_limit;
1312 boolean_t enc_fw_assisted_tso_enabled;
1313 boolean_t enc_fw_assisted_tso_v2_enabled;
1314 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1315 /* Number of TSO contexts on the NIC (FATSOv2) */
1316 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1317 boolean_t enc_hw_tx_insert_vlan_enabled;
1318 /* Number of PFs on the NIC */
1319 uint32_t enc_hw_pf_count;
1320 /* Datapath firmware vadapter/vport/vswitch support */
1321 boolean_t enc_datapath_cap_evb;
1322 boolean_t enc_rx_disable_scatter_supported;
1323 boolean_t enc_allow_set_mac_with_installed_filters;
1324 boolean_t enc_enhanced_set_mac_supported;
1325 boolean_t enc_init_evq_v2_supported;
1326 boolean_t enc_rx_packed_stream_supported;
1327 boolean_t enc_rx_var_packed_stream_supported;
1328 boolean_t enc_rx_es_super_buffer_supported;
1329 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1330 boolean_t enc_pm_and_rxdp_counters;
1331 boolean_t enc_mac_stats_40g_tx_size_bins;
1332 uint32_t enc_tunnel_encapsulations_supported;
1334 * NIC global maximum for unique UDP tunnel ports shared by all
1337 uint32_t enc_tunnel_config_udp_entries_max;
1338 /* External port identifier */
1339 uint8_t enc_external_port;
1340 uint32_t enc_mcdi_max_payload_length;
1341 /* VPD may be per-PF or global */
1342 boolean_t enc_vpd_is_global;
1343 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1344 uint32_t enc_required_pcie_bandwidth_mbps;
1345 uint32_t enc_max_pcie_link_gen;
1346 /* Firmware verifies integrity of NVRAM updates */
1347 uint32_t enc_nvram_update_verify_result_supported;
1348 /* Firmware support for extended MAC_STATS buffer */
1349 uint32_t enc_mac_stats_nstats;
1350 boolean_t enc_fec_counters;
1351 boolean_t enc_hlb_counters;
1352 /* Firmware support for "FLAG" and "MARK" filter actions */
1353 boolean_t enc_filter_action_flag_supported;
1354 boolean_t enc_filter_action_mark_supported;
1355 uint32_t enc_filter_action_mark_max;
1358 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1359 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1361 #define EFX_PCI_FUNCTION(_encp) \
1362 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1364 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1366 extern const efx_nic_cfg_t *
1368 __in efx_nic_t *enp);
1370 /* RxDPCPU firmware id values by which FW variant can be identified */
1371 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1372 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1373 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1374 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1375 #define EFX_RXDP_DPDK_FW_ID 0x6
1377 typedef struct efx_nic_fw_info_s {
1378 /* Basic FW version information */
1379 uint16_t enfi_mc_fw_version[4];
1381 * If datapath capabilities can be detected,
1382 * additional FW information is to be shown
1384 boolean_t enfi_dpcpu_fw_ids_valid;
1385 /* Rx and Tx datapath CPU FW IDs */
1386 uint16_t enfi_rx_dpcpu_fw_id;
1387 uint16_t enfi_tx_dpcpu_fw_id;
1388 } efx_nic_fw_info_t;
1390 extern __checkReturn efx_rc_t
1391 efx_nic_get_fw_version(
1392 __in efx_nic_t *enp,
1393 __out efx_nic_fw_info_t *enfip);
1395 /* Driver resource limits (minimum required/maximum usable). */
1396 typedef struct efx_drv_limits_s {
1397 uint32_t edl_min_evq_count;
1398 uint32_t edl_max_evq_count;
1400 uint32_t edl_min_rxq_count;
1401 uint32_t edl_max_rxq_count;
1403 uint32_t edl_min_txq_count;
1404 uint32_t edl_max_txq_count;
1406 /* PIO blocks (sub-allocated from piobuf) */
1407 uint32_t edl_min_pio_alloc_size;
1408 uint32_t edl_max_pio_alloc_count;
1411 extern __checkReturn efx_rc_t
1412 efx_nic_set_drv_limits(
1413 __inout efx_nic_t *enp,
1414 __in efx_drv_limits_t *edlp);
1416 typedef enum efx_nic_region_e {
1417 EFX_REGION_VI, /* Memory BAR UC mapping */
1418 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1421 extern __checkReturn efx_rc_t
1422 efx_nic_get_bar_region(
1423 __in efx_nic_t *enp,
1424 __in efx_nic_region_t region,
1425 __out uint32_t *offsetp,
1426 __out size_t *sizep);
1428 extern __checkReturn efx_rc_t
1429 efx_nic_get_vi_pool(
1430 __in efx_nic_t *enp,
1431 __out uint32_t *evq_countp,
1432 __out uint32_t *rxq_countp,
1433 __out uint32_t *txq_countp);
1438 typedef enum efx_vpd_tag_e {
1445 typedef uint16_t efx_vpd_keyword_t;
1447 typedef struct efx_vpd_value_s {
1448 efx_vpd_tag_t evv_tag;
1449 efx_vpd_keyword_t evv_keyword;
1451 uint8_t evv_value[0x100];
1455 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1457 extern __checkReturn efx_rc_t
1459 __in efx_nic_t *enp);
1461 extern __checkReturn efx_rc_t
1463 __in efx_nic_t *enp,
1464 __out size_t *sizep);
1466 extern __checkReturn efx_rc_t
1468 __in efx_nic_t *enp,
1469 __out_bcount(size) caddr_t data,
1472 extern __checkReturn efx_rc_t
1474 __in efx_nic_t *enp,
1475 __in_bcount(size) caddr_t data,
1478 extern __checkReturn efx_rc_t
1480 __in efx_nic_t *enp,
1481 __in_bcount(size) caddr_t data,
1484 extern __checkReturn efx_rc_t
1486 __in efx_nic_t *enp,
1487 __in_bcount(size) caddr_t data,
1489 __inout efx_vpd_value_t *evvp);
1491 extern __checkReturn efx_rc_t
1493 __in efx_nic_t *enp,
1494 __inout_bcount(size) caddr_t data,
1496 __in efx_vpd_value_t *evvp);
1498 extern __checkReturn efx_rc_t
1500 __in efx_nic_t *enp,
1501 __inout_bcount(size) caddr_t data,
1503 __out efx_vpd_value_t *evvp,
1504 __inout unsigned int *contp);
1506 extern __checkReturn efx_rc_t
1508 __in efx_nic_t *enp,
1509 __in_bcount(size) caddr_t data,
1514 __in efx_nic_t *enp);
1516 #endif /* EFSYS_OPT_VPD */
1522 typedef enum efx_nvram_type_e {
1523 EFX_NVRAM_INVALID = 0,
1525 EFX_NVRAM_BOOTROM_CFG,
1526 EFX_NVRAM_MC_FIRMWARE,
1527 EFX_NVRAM_MC_GOLDEN,
1533 EFX_NVRAM_FPGA_BACKUP,
1534 EFX_NVRAM_DYNAMIC_CFG,
1537 EFX_NVRAM_MUM_FIRMWARE,
1538 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1539 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1543 extern __checkReturn efx_rc_t
1545 __in efx_nic_t *enp);
1549 extern __checkReturn efx_rc_t
1551 __in efx_nic_t *enp);
1553 #endif /* EFSYS_OPT_DIAG */
1555 extern __checkReturn efx_rc_t
1557 __in efx_nic_t *enp,
1558 __in efx_nvram_type_t type,
1559 __out size_t *sizep);
1561 extern __checkReturn efx_rc_t
1563 __in efx_nic_t *enp,
1564 __in efx_nvram_type_t type,
1565 __out_opt size_t *pref_chunkp);
1567 extern __checkReturn efx_rc_t
1568 efx_nvram_rw_finish(
1569 __in efx_nic_t *enp,
1570 __in efx_nvram_type_t type,
1571 __out_opt uint32_t *verify_resultp);
1573 extern __checkReturn efx_rc_t
1574 efx_nvram_get_version(
1575 __in efx_nic_t *enp,
1576 __in efx_nvram_type_t type,
1577 __out uint32_t *subtypep,
1578 __out_ecount(4) uint16_t version[4]);
1580 extern __checkReturn efx_rc_t
1581 efx_nvram_read_chunk(
1582 __in efx_nic_t *enp,
1583 __in efx_nvram_type_t type,
1584 __in unsigned int offset,
1585 __out_bcount(size) caddr_t data,
1588 extern __checkReturn efx_rc_t
1589 efx_nvram_read_backup(
1590 __in efx_nic_t *enp,
1591 __in efx_nvram_type_t type,
1592 __in unsigned int offset,
1593 __out_bcount(size) caddr_t data,
1596 extern __checkReturn efx_rc_t
1597 efx_nvram_set_version(
1598 __in efx_nic_t *enp,
1599 __in efx_nvram_type_t type,
1600 __in_ecount(4) uint16_t version[4]);
1602 extern __checkReturn efx_rc_t
1604 __in efx_nic_t *enp,
1605 __in efx_nvram_type_t type,
1606 __in_bcount(partn_size) caddr_t partn_data,
1607 __in size_t partn_size);
1609 extern __checkReturn efx_rc_t
1611 __in efx_nic_t *enp,
1612 __in efx_nvram_type_t type);
1614 extern __checkReturn efx_rc_t
1615 efx_nvram_write_chunk(
1616 __in efx_nic_t *enp,
1617 __in efx_nvram_type_t type,
1618 __in unsigned int offset,
1619 __in_bcount(size) caddr_t data,
1624 __in efx_nic_t *enp);
1626 #endif /* EFSYS_OPT_NVRAM */
1628 #if EFSYS_OPT_BOOTCFG
1630 /* Report size and offset of bootcfg sector in NVRAM partition. */
1631 extern __checkReturn efx_rc_t
1632 efx_bootcfg_sector_info(
1633 __in efx_nic_t *enp,
1635 __out_opt uint32_t *sector_countp,
1636 __out size_t *offsetp,
1637 __out size_t *max_sizep);
1640 * Copy bootcfg sector data to a target buffer which may differ in size.
1641 * Optionally corrects format errors in source buffer.
1644 efx_bootcfg_copy_sector(
1645 __in efx_nic_t *enp,
1646 __inout_bcount(sector_length)
1648 __in size_t sector_length,
1649 __out_bcount(data_size) uint8_t *data,
1650 __in size_t data_size,
1651 __in boolean_t handle_format_errors);
1655 __in efx_nic_t *enp,
1656 __out_bcount(size) uint8_t *data,
1661 __in efx_nic_t *enp,
1662 __in_bcount(size) uint8_t *data,
1665 #endif /* EFSYS_OPT_BOOTCFG */
1667 #if EFSYS_OPT_IMAGE_LAYOUT
1669 #include "ef10_signed_image_layout.h"
1672 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
1675 * The image header format is extensible. However, older drivers require an
1676 * exact match of image header version and header length when validating and
1677 * writing firmware images.
1679 * To avoid breaking backward compatibility, we use the upper bits of the
1680 * controller version fields to contain an extra version number used for
1681 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
1682 * version). See bug39254 and SF-102785-PS for details.
1684 typedef struct efx_image_header_s {
1686 uint32_t eih_version;
1688 uint32_t eih_subtype;
1689 uint32_t eih_code_size;
1692 uint32_t eih_controller_version_min;
1694 uint16_t eih_controller_version_min_short;
1695 uint8_t eih_extra_version_a;
1696 uint8_t eih_extra_version_b;
1700 uint32_t eih_controller_version_max;
1702 uint16_t eih_controller_version_max_short;
1703 uint8_t eih_extra_version_c;
1704 uint8_t eih_extra_version_d;
1707 uint16_t eih_code_version_a;
1708 uint16_t eih_code_version_b;
1709 uint16_t eih_code_version_c;
1710 uint16_t eih_code_version_d;
1711 } efx_image_header_t;
1713 #define EFX_IMAGE_HEADER_SIZE (40)
1714 #define EFX_IMAGE_HEADER_VERSION (4)
1715 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
1718 typedef struct efx_image_trailer_s {
1720 } efx_image_trailer_t;
1722 #define EFX_IMAGE_TRAILER_SIZE (4)
1724 typedef enum efx_image_format_e {
1725 EFX_IMAGE_FORMAT_NO_IMAGE,
1726 EFX_IMAGE_FORMAT_INVALID,
1727 EFX_IMAGE_FORMAT_UNSIGNED,
1728 EFX_IMAGE_FORMAT_SIGNED,
1729 } efx_image_format_t;
1731 typedef struct efx_image_info_s {
1732 efx_image_format_t eii_format;
1733 uint8_t * eii_imagep;
1734 size_t eii_image_size;
1735 efx_image_header_t * eii_headerp;
1738 extern __checkReturn efx_rc_t
1739 efx_check_reflash_image(
1741 __in uint32_t buffer_size,
1742 __out efx_image_info_t *infop);
1744 extern __checkReturn efx_rc_t
1745 efx_build_signed_image_write_buffer(
1746 __out_bcount(buffer_size)
1748 __in uint32_t buffer_size,
1749 __in efx_image_info_t *infop,
1750 __out efx_image_header_t **headerpp);
1752 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
1756 typedef enum efx_pattern_type_t {
1757 EFX_PATTERN_BYTE_INCREMENT = 0,
1758 EFX_PATTERN_ALL_THE_SAME,
1759 EFX_PATTERN_BIT_ALTERNATE,
1760 EFX_PATTERN_BYTE_ALTERNATE,
1761 EFX_PATTERN_BYTE_CHANGING,
1762 EFX_PATTERN_BIT_SWEEP,
1764 } efx_pattern_type_t;
1767 (*efx_sram_pattern_fn_t)(
1769 __in boolean_t negate,
1770 __out efx_qword_t *eqp);
1772 extern __checkReturn efx_rc_t
1774 __in efx_nic_t *enp,
1775 __in efx_pattern_type_t type);
1777 #endif /* EFSYS_OPT_DIAG */
1779 extern __checkReturn efx_rc_t
1780 efx_sram_buf_tbl_set(
1781 __in efx_nic_t *enp,
1783 __in efsys_mem_t *esmp,
1787 efx_sram_buf_tbl_clear(
1788 __in efx_nic_t *enp,
1792 #define EFX_BUF_TBL_SIZE 0x20000
1794 #define EFX_BUF_SIZE 4096
1798 typedef struct efx_evq_s efx_evq_t;
1800 #if EFSYS_OPT_QSTATS
1802 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1803 typedef enum efx_ev_qstat_e {
1809 EV_RX_PAUSE_FRM_ERR,
1810 EV_RX_BUF_OWNER_ID_ERR,
1811 EV_RX_IPV4_HDR_CHKSUM_ERR,
1812 EV_RX_TCP_UDP_CHKSUM_ERR,
1816 EV_RX_MCAST_HASH_MATCH,
1833 EV_DRIVER_SRM_UPD_DONE,
1834 EV_DRIVER_TX_DESCQ_FLS_DONE,
1835 EV_DRIVER_RX_DESCQ_FLS_DONE,
1836 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1837 EV_DRIVER_RX_DSC_ERROR,
1838 EV_DRIVER_TX_DSC_ERROR,
1844 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1846 #endif /* EFSYS_OPT_QSTATS */
1848 extern __checkReturn efx_rc_t
1850 __in efx_nic_t *enp);
1854 __in efx_nic_t *enp);
1856 #define EFX_EVQ_MAXNEVS 32768
1857 #define EFX_EVQ_MINNEVS 512
1859 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1860 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1862 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
1863 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
1864 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
1865 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
1867 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
1868 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
1869 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
1871 extern __checkReturn efx_rc_t
1873 __in efx_nic_t *enp,
1874 __in unsigned int index,
1875 __in efsys_mem_t *esmp,
1879 __in uint32_t flags,
1880 __deref_out efx_evq_t **eepp);
1884 __in efx_evq_t *eep,
1885 __in uint16_t data);
1887 typedef __checkReturn boolean_t
1888 (*efx_initialized_ev_t)(
1889 __in_opt void *arg);
1891 #define EFX_PKT_UNICAST 0x0004
1892 #define EFX_PKT_START 0x0008
1894 #define EFX_PKT_VLAN_TAGGED 0x0010
1895 #define EFX_CKSUM_TCPUDP 0x0020
1896 #define EFX_CKSUM_IPV4 0x0040
1897 #define EFX_PKT_CONT 0x0080
1899 #define EFX_CHECK_VLAN 0x0100
1900 #define EFX_PKT_TCP 0x0200
1901 #define EFX_PKT_UDP 0x0400
1902 #define EFX_PKT_IPV4 0x0800
1904 #define EFX_PKT_IPV6 0x1000
1905 #define EFX_PKT_PREFIX_LEN 0x2000
1906 #define EFX_ADDR_MISMATCH 0x4000
1907 #define EFX_DISCARD 0x8000
1910 * The following flags are used only for packed stream
1911 * mode. The values for the flags are reused to fit into 16 bit,
1912 * since EFX_PKT_START and EFX_PKT_CONT are never used in
1913 * packed stream mode
1915 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
1916 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
1919 #define EFX_EV_RX_NLABELS 32
1920 #define EFX_EV_TX_NLABELS 32
1922 typedef __checkReturn boolean_t
1925 __in uint32_t label,
1928 __in uint16_t flags);
1930 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
1933 * Packed stream mode is documented in SF-112241-TC.
1934 * The general idea is that, instead of putting each incoming
1935 * packet into a separate buffer which is specified in a RX
1936 * descriptor, a large buffer is provided to the hardware and
1937 * packets are put there in a continuous stream.
1938 * The main advantage of such an approach is that RX queue refilling
1939 * happens much less frequently.
1941 * Equal stride packed stream mode is documented in SF-119419-TC.
1942 * The general idea is to utilize advantages of the packed stream,
1943 * but avoid indirection in packets representation.
1944 * The main advantage of such an approach is that RX queue refilling
1945 * happens much less frequently and packets buffers are independent
1946 * from upper layers point of view.
1949 typedef __checkReturn boolean_t
1952 __in uint32_t label,
1954 __in uint32_t pkt_count,
1955 __in uint16_t flags);
1959 typedef __checkReturn boolean_t
1962 __in uint32_t label,
1965 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1966 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1967 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1968 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1969 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1970 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1971 #define EFX_EXCEPTION_RX_ERROR 0x00000007
1972 #define EFX_EXCEPTION_TX_ERROR 0x00000008
1973 #define EFX_EXCEPTION_EV_ERROR 0x00000009
1975 typedef __checkReturn boolean_t
1976 (*efx_exception_ev_t)(
1978 __in uint32_t label,
1979 __in uint32_t data);
1981 typedef __checkReturn boolean_t
1982 (*efx_rxq_flush_done_ev_t)(
1984 __in uint32_t rxq_index);
1986 typedef __checkReturn boolean_t
1987 (*efx_rxq_flush_failed_ev_t)(
1989 __in uint32_t rxq_index);
1991 typedef __checkReturn boolean_t
1992 (*efx_txq_flush_done_ev_t)(
1994 __in uint32_t txq_index);
1996 typedef __checkReturn boolean_t
1997 (*efx_software_ev_t)(
1999 __in uint16_t magic);
2001 typedef __checkReturn boolean_t
2004 __in uint32_t code);
2006 #define EFX_SRAM_CLEAR 0
2007 #define EFX_SRAM_UPDATE 1
2008 #define EFX_SRAM_ILLEGAL_CLEAR 2
2010 typedef __checkReturn boolean_t
2011 (*efx_wake_up_ev_t)(
2013 __in uint32_t label);
2015 typedef __checkReturn boolean_t
2018 __in uint32_t label);
2020 typedef __checkReturn boolean_t
2021 (*efx_link_change_ev_t)(
2023 __in efx_link_mode_t link_mode);
2025 #if EFSYS_OPT_MON_STATS
2027 typedef __checkReturn boolean_t
2028 (*efx_monitor_ev_t)(
2030 __in efx_mon_stat_t id,
2031 __in efx_mon_stat_value_t value);
2033 #endif /* EFSYS_OPT_MON_STATS */
2035 #if EFSYS_OPT_MAC_STATS
2037 typedef __checkReturn boolean_t
2038 (*efx_mac_stats_ev_t)(
2040 __in uint32_t generation);
2042 #endif /* EFSYS_OPT_MAC_STATS */
2044 typedef struct efx_ev_callbacks_s {
2045 efx_initialized_ev_t eec_initialized;
2047 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2048 efx_rx_ps_ev_t eec_rx_ps;
2051 efx_exception_ev_t eec_exception;
2052 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2053 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2054 efx_txq_flush_done_ev_t eec_txq_flush_done;
2055 efx_software_ev_t eec_software;
2056 efx_sram_ev_t eec_sram;
2057 efx_wake_up_ev_t eec_wake_up;
2058 efx_timer_ev_t eec_timer;
2059 efx_link_change_ev_t eec_link_change;
2060 #if EFSYS_OPT_MON_STATS
2061 efx_monitor_ev_t eec_monitor;
2062 #endif /* EFSYS_OPT_MON_STATS */
2063 #if EFSYS_OPT_MAC_STATS
2064 efx_mac_stats_ev_t eec_mac_stats;
2065 #endif /* EFSYS_OPT_MAC_STATS */
2066 } efx_ev_callbacks_t;
2068 extern __checkReturn boolean_t
2070 __in efx_evq_t *eep,
2071 __in unsigned int count);
2073 #if EFSYS_OPT_EV_PREFETCH
2077 __in efx_evq_t *eep,
2078 __in unsigned int count);
2080 #endif /* EFSYS_OPT_EV_PREFETCH */
2084 __in efx_evq_t *eep,
2085 __inout unsigned int *countp,
2086 __in const efx_ev_callbacks_t *eecp,
2087 __in_opt void *arg);
2089 extern __checkReturn efx_rc_t
2090 efx_ev_usecs_to_ticks(
2091 __in efx_nic_t *enp,
2092 __in unsigned int usecs,
2093 __out unsigned int *ticksp);
2095 extern __checkReturn efx_rc_t
2097 __in efx_evq_t *eep,
2098 __in unsigned int us);
2100 extern __checkReturn efx_rc_t
2102 __in efx_evq_t *eep,
2103 __in unsigned int count);
2105 #if EFSYS_OPT_QSTATS
2111 __in efx_nic_t *enp,
2112 __in unsigned int id);
2114 #endif /* EFSYS_OPT_NAMES */
2117 efx_ev_qstats_update(
2118 __in efx_evq_t *eep,
2119 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2121 #endif /* EFSYS_OPT_QSTATS */
2125 __in efx_evq_t *eep);
2129 extern __checkReturn efx_rc_t
2131 __inout efx_nic_t *enp);
2135 __in efx_nic_t *enp);
2137 #if EFSYS_OPT_RX_SCATTER
2138 __checkReturn efx_rc_t
2139 efx_rx_scatter_enable(
2140 __in efx_nic_t *enp,
2141 __in unsigned int buf_size);
2142 #endif /* EFSYS_OPT_RX_SCATTER */
2144 /* Handle to represent use of the default RSS context. */
2145 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2147 #if EFSYS_OPT_RX_SCALE
2149 typedef enum efx_rx_hash_alg_e {
2150 EFX_RX_HASHALG_LFSR = 0,
2151 EFX_RX_HASHALG_TOEPLITZ,
2152 EFX_RX_HASHALG_PACKED_STREAM,
2154 } efx_rx_hash_alg_t;
2157 * Legacy hash type flags.
2159 * They represent standard tuples for distinct traffic classes.
2161 #define EFX_RX_HASH_IPV4 (1U << 0)
2162 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2163 #define EFX_RX_HASH_IPV6 (1U << 2)
2164 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2166 #define EFX_RX_HASH_LEGACY_MASK \
2167 (EFX_RX_HASH_IPV4 | \
2168 EFX_RX_HASH_TCPIPV4 | \
2169 EFX_RX_HASH_IPV6 | \
2170 EFX_RX_HASH_TCPIPV6)
2173 * The type of the argument used by efx_rx_scale_mode_set() to
2174 * provide a means for the client drivers to configure hashing.
2176 * A properly constructed value can either be:
2177 * - a combination of legacy flags
2178 * - a combination of EFX_RX_HASH() flags
2180 typedef unsigned int efx_rx_hash_type_t;
2182 typedef enum efx_rx_hash_support_e {
2183 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2184 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2185 } efx_rx_hash_support_t;
2187 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2188 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2189 #define EFX_MAXRSS 64 /* RX indirection entry range */
2190 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2192 typedef enum efx_rx_scale_context_type_e {
2193 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2194 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2195 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2196 } efx_rx_scale_context_type_t;
2199 * Traffic classes eligible for hash computation.
2201 * Select packet headers used in computing the receive hash.
2202 * This uses the same encoding as the RSS_MODES field of
2203 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2205 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2206 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2207 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2208 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2209 #define EFX_RX_CLASS_IPV4_LBN 16
2210 #define EFX_RX_CLASS_IPV4_WIDTH 4
2211 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2212 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2213 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2214 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2215 #define EFX_RX_CLASS_IPV6_LBN 28
2216 #define EFX_RX_CLASS_IPV6_WIDTH 4
2218 #define EFX_RX_NCLASSES 6
2221 * Ancillary flags used to construct generic hash tuples.
2222 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2224 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2225 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2226 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2227 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2230 * Generic hash tuples.
2232 * They express combinations of packet fields
2233 * which can contribute to the hash value for
2234 * a particular traffic class.
2236 #define EFX_RX_CLASS_HASH_DISABLE 0
2238 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2239 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2241 #define EFX_RX_CLASS_HASH_2TUPLE \
2242 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2243 EFX_RX_CLASS_HASH_DST_ADDR)
2245 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2246 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2247 EFX_RX_CLASS_HASH_SRC_PORT)
2249 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2250 (EFX_RX_CLASS_HASH_DST_ADDR | \
2251 EFX_RX_CLASS_HASH_DST_PORT)
2253 #define EFX_RX_CLASS_HASH_4TUPLE \
2254 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2255 EFX_RX_CLASS_HASH_DST_ADDR | \
2256 EFX_RX_CLASS_HASH_SRC_PORT | \
2257 EFX_RX_CLASS_HASH_DST_PORT)
2259 #define EFX_RX_CLASS_HASH_NTUPLES 7
2262 * Hash flag constructor.
2264 * Resulting flags encode hash tuples for specific traffic classes.
2265 * The client drivers are encouraged to use these flags to form
2266 * a hash type value.
2268 #define EFX_RX_HASH(_class, _tuple) \
2269 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2270 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2273 * The maximum number of EFX_RX_HASH() flags.
2275 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2277 extern __checkReturn efx_rc_t
2278 efx_rx_scale_hash_flags_get(
2279 __in efx_nic_t *enp,
2280 __in efx_rx_hash_alg_t hash_alg,
2281 __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flags,
2282 __out unsigned int *nflagsp);
2284 extern __checkReturn efx_rc_t
2285 efx_rx_hash_default_support_get(
2286 __in efx_nic_t *enp,
2287 __out efx_rx_hash_support_t *supportp);
2290 extern __checkReturn efx_rc_t
2291 efx_rx_scale_default_support_get(
2292 __in efx_nic_t *enp,
2293 __out efx_rx_scale_context_type_t *typep);
2295 extern __checkReturn efx_rc_t
2296 efx_rx_scale_context_alloc(
2297 __in efx_nic_t *enp,
2298 __in efx_rx_scale_context_type_t type,
2299 __in uint32_t num_queues,
2300 __out uint32_t *rss_contextp);
2302 extern __checkReturn efx_rc_t
2303 efx_rx_scale_context_free(
2304 __in efx_nic_t *enp,
2305 __in uint32_t rss_context);
2307 extern __checkReturn efx_rc_t
2308 efx_rx_scale_mode_set(
2309 __in efx_nic_t *enp,
2310 __in uint32_t rss_context,
2311 __in efx_rx_hash_alg_t alg,
2312 __in efx_rx_hash_type_t type,
2313 __in boolean_t insert);
2315 extern __checkReturn efx_rc_t
2316 efx_rx_scale_tbl_set(
2317 __in efx_nic_t *enp,
2318 __in uint32_t rss_context,
2319 __in_ecount(n) unsigned int *table,
2322 extern __checkReturn efx_rc_t
2323 efx_rx_scale_key_set(
2324 __in efx_nic_t *enp,
2325 __in uint32_t rss_context,
2326 __in_ecount(n) uint8_t *key,
2329 extern __checkReturn uint32_t
2330 efx_pseudo_hdr_hash_get(
2331 __in efx_rxq_t *erp,
2332 __in efx_rx_hash_alg_t func,
2333 __in uint8_t *buffer);
2335 #endif /* EFSYS_OPT_RX_SCALE */
2337 extern __checkReturn efx_rc_t
2338 efx_pseudo_hdr_pkt_length_get(
2339 __in efx_rxq_t *erp,
2340 __in uint8_t *buffer,
2341 __out uint16_t *pkt_lengthp);
2343 #define EFX_RXQ_MAXNDESCS 4096
2344 #define EFX_RXQ_MINNDESCS 512
2346 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2347 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2348 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2349 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
2351 typedef enum efx_rxq_type_e {
2352 EFX_RXQ_TYPE_DEFAULT,
2353 EFX_RXQ_TYPE_PACKED_STREAM,
2354 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2359 * Dummy flag to be used instead of 0 to make it clear that the argument
2360 * is receive queue flags.
2362 #define EFX_RXQ_FLAG_NONE 0x0
2363 #define EFX_RXQ_FLAG_SCATTER 0x1
2365 * If tunnels are supported and Rx event can provide information about
2366 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2367 * full-feature firmware variant running), outer classes are requested by
2368 * default. However, if the driver supports tunnels, the flag allows to
2369 * request inner classes which are required to be able to interpret inner
2370 * Rx checksum offload results.
2372 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2374 extern __checkReturn efx_rc_t
2376 __in efx_nic_t *enp,
2377 __in unsigned int index,
2378 __in unsigned int label,
2379 __in efx_rxq_type_t type,
2380 __in efsys_mem_t *esmp,
2383 __in unsigned int flags,
2384 __in efx_evq_t *eep,
2385 __deref_out efx_rxq_t **erpp);
2387 #if EFSYS_OPT_RX_PACKED_STREAM
2389 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2390 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2391 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2392 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2393 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2395 extern __checkReturn efx_rc_t
2396 efx_rx_qcreate_packed_stream(
2397 __in efx_nic_t *enp,
2398 __in unsigned int index,
2399 __in unsigned int label,
2400 __in uint32_t ps_buf_size,
2401 __in efsys_mem_t *esmp,
2403 __in efx_evq_t *eep,
2404 __deref_out efx_rxq_t **erpp);
2408 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2410 /* Maximum head-of-line block timeout in nanoseconds */
2411 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2413 extern __checkReturn efx_rc_t
2414 efx_rx_qcreate_es_super_buffer(
2415 __in efx_nic_t *enp,
2416 __in unsigned int index,
2417 __in unsigned int label,
2418 __in uint32_t n_bufs_per_desc,
2419 __in uint32_t max_dma_len,
2420 __in uint32_t buf_stride,
2421 __in uint32_t hol_block_timeout,
2422 __in efsys_mem_t *esmp,
2424 __in unsigned int flags,
2425 __in efx_evq_t *eep,
2426 __deref_out efx_rxq_t **erpp);
2430 typedef struct efx_buffer_s {
2431 efsys_dma_addr_t eb_addr;
2436 typedef struct efx_desc_s {
2442 __in efx_rxq_t *erp,
2443 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
2445 __in unsigned int ndescs,
2446 __in unsigned int completed,
2447 __in unsigned int added);
2451 __in efx_rxq_t *erp,
2452 __in unsigned int added,
2453 __inout unsigned int *pushedp);
2455 #if EFSYS_OPT_RX_PACKED_STREAM
2458 efx_rx_qpush_ps_credits(
2459 __in efx_rxq_t *erp);
2461 extern __checkReturn uint8_t *
2462 efx_rx_qps_packet_info(
2463 __in efx_rxq_t *erp,
2464 __in uint8_t *buffer,
2465 __in uint32_t buffer_length,
2466 __in uint32_t current_offset,
2467 __out uint16_t *lengthp,
2468 __out uint32_t *next_offsetp,
2469 __out uint32_t *timestamp);
2472 extern __checkReturn efx_rc_t
2474 __in efx_rxq_t *erp);
2478 __in efx_rxq_t *erp);
2482 __in efx_rxq_t *erp);
2486 typedef struct efx_txq_s efx_txq_t;
2488 #if EFSYS_OPT_QSTATS
2490 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
2491 typedef enum efx_tx_qstat_e {
2497 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
2499 #endif /* EFSYS_OPT_QSTATS */
2501 extern __checkReturn efx_rc_t
2503 __in efx_nic_t *enp);
2507 __in efx_nic_t *enp);
2509 #define EFX_TXQ_MINNDESCS 512
2511 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
2512 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2513 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2515 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2517 #define EFX_TXQ_CKSUM_IPV4 0x0001
2518 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
2519 #define EFX_TXQ_FATSOV2 0x0004
2520 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
2521 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
2523 extern __checkReturn efx_rc_t
2525 __in efx_nic_t *enp,
2526 __in unsigned int index,
2527 __in unsigned int label,
2528 __in efsys_mem_t *esmp,
2531 __in uint16_t flags,
2532 __in efx_evq_t *eep,
2533 __deref_out efx_txq_t **etpp,
2534 __out unsigned int *addedp);
2536 extern __checkReturn efx_rc_t
2538 __in efx_txq_t *etp,
2539 __in_ecount(ndescs) efx_buffer_t *eb,
2540 __in unsigned int ndescs,
2541 __in unsigned int completed,
2542 __inout unsigned int *addedp);
2544 extern __checkReturn efx_rc_t
2546 __in efx_txq_t *etp,
2547 __in unsigned int ns);
2551 __in efx_txq_t *etp,
2552 __in unsigned int added,
2553 __in unsigned int pushed);
2555 extern __checkReturn efx_rc_t
2557 __in efx_txq_t *etp);
2561 __in efx_txq_t *etp);
2563 extern __checkReturn efx_rc_t
2565 __in efx_txq_t *etp);
2568 efx_tx_qpio_disable(
2569 __in efx_txq_t *etp);
2571 extern __checkReturn efx_rc_t
2573 __in efx_txq_t *etp,
2574 __in_ecount(buf_length) uint8_t *buffer,
2575 __in size_t buf_length,
2576 __in size_t pio_buf_offset);
2578 extern __checkReturn efx_rc_t
2580 __in efx_txq_t *etp,
2581 __in size_t pkt_length,
2582 __in unsigned int completed,
2583 __inout unsigned int *addedp);
2585 extern __checkReturn efx_rc_t
2587 __in efx_txq_t *etp,
2588 __in_ecount(n) efx_desc_t *ed,
2589 __in unsigned int n,
2590 __in unsigned int completed,
2591 __inout unsigned int *addedp);
2594 efx_tx_qdesc_dma_create(
2595 __in efx_txq_t *etp,
2596 __in efsys_dma_addr_t addr,
2599 __out efx_desc_t *edp);
2602 efx_tx_qdesc_tso_create(
2603 __in efx_txq_t *etp,
2604 __in uint16_t ipv4_id,
2605 __in uint32_t tcp_seq,
2606 __in uint8_t tcp_flags,
2607 __out efx_desc_t *edp);
2609 /* Number of FATSOv2 option descriptors */
2610 #define EFX_TX_FATSOV2_OPT_NDESCS 2
2612 /* Maximum number of DMA segments per TSO packet (not superframe) */
2613 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
2616 efx_tx_qdesc_tso2_create(
2617 __in efx_txq_t *etp,
2618 __in uint16_t ipv4_id,
2619 __in uint16_t outer_ipv4_id,
2620 __in uint32_t tcp_seq,
2621 __in uint16_t tcp_mss,
2622 __out_ecount(count) efx_desc_t *edp,
2626 efx_tx_qdesc_vlantci_create(
2627 __in efx_txq_t *etp,
2629 __out efx_desc_t *edp);
2632 efx_tx_qdesc_checksum_create(
2633 __in efx_txq_t *etp,
2634 __in uint16_t flags,
2635 __out efx_desc_t *edp);
2637 #if EFSYS_OPT_QSTATS
2643 __in efx_nic_t *etp,
2644 __in unsigned int id);
2646 #endif /* EFSYS_OPT_NAMES */
2649 efx_tx_qstats_update(
2650 __in efx_txq_t *etp,
2651 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
2653 #endif /* EFSYS_OPT_QSTATS */
2657 __in efx_txq_t *etp);
2662 #if EFSYS_OPT_FILTER
2664 #define EFX_ETHER_TYPE_IPV4 0x0800
2665 #define EFX_ETHER_TYPE_IPV6 0x86DD
2667 #define EFX_IPPROTO_TCP 6
2668 #define EFX_IPPROTO_UDP 17
2669 #define EFX_IPPROTO_GRE 47
2671 /* Use RSS to spread across multiple queues */
2672 #define EFX_FILTER_FLAG_RX_RSS 0x01
2673 /* Enable RX scatter */
2674 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
2676 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2677 * May only be set by the filter implementation for each type.
2678 * A removal request will restore the automatic filter in its place.
2680 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
2681 /* Filter is for RX */
2682 #define EFX_FILTER_FLAG_RX 0x08
2683 /* Filter is for TX */
2684 #define EFX_FILTER_FLAG_TX 0x10
2685 /* Set match flag on the received packet */
2686 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
2687 /* Set match mark on the received packet */
2688 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
2690 typedef uint8_t efx_filter_flags_t;
2693 * Flags which specify the fields to match on. The values are the same as in the
2694 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2697 /* Match by remote IP host address */
2698 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
2699 /* Match by local IP host address */
2700 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
2701 /* Match by remote MAC address */
2702 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
2703 /* Match by remote TCP/UDP port */
2704 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
2705 /* Match by remote TCP/UDP port */
2706 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
2707 /* Match by local TCP/UDP port */
2708 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
2709 /* Match by Ether-type */
2710 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
2711 /* Match by inner VLAN ID */
2712 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
2713 /* Match by outer VLAN ID */
2714 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
2715 /* Match by IP transport protocol */
2716 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
2717 /* Match by VNI or VSID */
2718 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
2719 /* For encapsulated packets, match by inner frame local MAC address */
2720 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
2721 /* For encapsulated packets, match all multicast inner frames */
2722 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
2723 /* For encapsulated packets, match all unicast inner frames */
2724 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
2726 * Match by encap type, this flag does not correspond to
2727 * the MCDI match flags and any unoccupied value may be used
2729 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
2730 /* Match otherwise-unmatched multicast and broadcast packets */
2731 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
2732 /* Match otherwise-unmatched unicast packets */
2733 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
2735 typedef uint32_t efx_filter_match_flags_t;
2737 typedef enum efx_filter_priority_s {
2738 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
2739 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
2740 * address list or hardware
2741 * requirements. This may only be used
2742 * by the filter implementation for
2744 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
2745 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
2746 * client (e.g. SR-IOV, HyperV VMQ etc.)
2748 } efx_filter_priority_t;
2751 * FIXME: All these fields are assumed to be in little-endian byte order.
2752 * It may be better for some to be big-endian. See bug42804.
2755 typedef struct efx_filter_spec_s {
2756 efx_filter_match_flags_t efs_match_flags;
2757 uint8_t efs_priority;
2758 efx_filter_flags_t efs_flags;
2759 uint16_t efs_dmaq_id;
2760 uint32_t efs_rss_context;
2761 uint16_t efs_outer_vid;
2762 uint16_t efs_inner_vid;
2763 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
2764 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
2765 uint16_t efs_ether_type;
2766 uint8_t efs_ip_proto;
2767 efx_tunnel_protocol_t efs_encap_type;
2768 uint16_t efs_loc_port;
2769 uint16_t efs_rem_port;
2770 efx_oword_t efs_rem_host;
2771 efx_oword_t efs_loc_host;
2772 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
2773 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
2775 } efx_filter_spec_t;
2778 /* Default values for use in filter specifications */
2779 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
2780 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
2782 extern __checkReturn efx_rc_t
2784 __in efx_nic_t *enp);
2788 __in efx_nic_t *enp);
2790 extern __checkReturn efx_rc_t
2792 __in efx_nic_t *enp,
2793 __inout efx_filter_spec_t *spec);
2795 extern __checkReturn efx_rc_t
2797 __in efx_nic_t *enp,
2798 __inout efx_filter_spec_t *spec);
2800 extern __checkReturn efx_rc_t
2802 __in efx_nic_t *enp);
2804 extern __checkReturn efx_rc_t
2805 efx_filter_supported_filters(
2806 __in efx_nic_t *enp,
2807 __out_ecount(buffer_length) uint32_t *buffer,
2808 __in size_t buffer_length,
2809 __out size_t *list_lengthp);
2812 efx_filter_spec_init_rx(
2813 __out efx_filter_spec_t *spec,
2814 __in efx_filter_priority_t priority,
2815 __in efx_filter_flags_t flags,
2816 __in efx_rxq_t *erp);
2819 efx_filter_spec_init_tx(
2820 __out efx_filter_spec_t *spec,
2821 __in efx_txq_t *etp);
2823 extern __checkReturn efx_rc_t
2824 efx_filter_spec_set_ipv4_local(
2825 __inout efx_filter_spec_t *spec,
2828 __in uint16_t port);
2830 extern __checkReturn efx_rc_t
2831 efx_filter_spec_set_ipv4_full(
2832 __inout efx_filter_spec_t *spec,
2834 __in uint32_t lhost,
2835 __in uint16_t lport,
2836 __in uint32_t rhost,
2837 __in uint16_t rport);
2839 extern __checkReturn efx_rc_t
2840 efx_filter_spec_set_eth_local(
2841 __inout efx_filter_spec_t *spec,
2843 __in const uint8_t *addr);
2846 efx_filter_spec_set_ether_type(
2847 __inout efx_filter_spec_t *spec,
2848 __in uint16_t ether_type);
2850 extern __checkReturn efx_rc_t
2851 efx_filter_spec_set_uc_def(
2852 __inout efx_filter_spec_t *spec);
2854 extern __checkReturn efx_rc_t
2855 efx_filter_spec_set_mc_def(
2856 __inout efx_filter_spec_t *spec);
2858 typedef enum efx_filter_inner_frame_match_e {
2859 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2860 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2861 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2862 } efx_filter_inner_frame_match_t;
2864 extern __checkReturn efx_rc_t
2865 efx_filter_spec_set_encap_type(
2866 __inout efx_filter_spec_t *spec,
2867 __in efx_tunnel_protocol_t encap_type,
2868 __in efx_filter_inner_frame_match_t inner_frame_match);
2870 extern __checkReturn efx_rc_t
2871 efx_filter_spec_set_vxlan_full(
2872 __inout efx_filter_spec_t *spec,
2873 __in const uint8_t *vxlan_id,
2874 __in const uint8_t *inner_addr,
2875 __in const uint8_t *outer_addr);
2877 #if EFSYS_OPT_RX_SCALE
2878 extern __checkReturn efx_rc_t
2879 efx_filter_spec_set_rss_context(
2880 __inout efx_filter_spec_t *spec,
2881 __in uint32_t rss_context);
2883 #endif /* EFSYS_OPT_FILTER */
2887 extern __checkReturn uint32_t
2889 __in_ecount(count) uint32_t const *input,
2891 __in uint32_t init);
2893 extern __checkReturn uint32_t
2895 __in_ecount(length) uint8_t const *input,
2897 __in uint32_t init);
2899 #if EFSYS_OPT_LICENSING
2903 typedef struct efx_key_stats_s {
2905 uint32_t eks_invalid;
2906 uint32_t eks_blacklisted;
2907 uint32_t eks_unverifiable;
2908 uint32_t eks_wrong_node;
2909 uint32_t eks_licensed_apps_lo;
2910 uint32_t eks_licensed_apps_hi;
2911 uint32_t eks_licensed_features_lo;
2912 uint32_t eks_licensed_features_hi;
2915 extern __checkReturn efx_rc_t
2917 __in efx_nic_t *enp);
2921 __in efx_nic_t *enp);
2923 extern __checkReturn boolean_t
2924 efx_lic_check_support(
2925 __in efx_nic_t *enp);
2927 extern __checkReturn efx_rc_t
2928 efx_lic_update_licenses(
2929 __in efx_nic_t *enp);
2931 extern __checkReturn efx_rc_t
2932 efx_lic_get_key_stats(
2933 __in efx_nic_t *enp,
2934 __out efx_key_stats_t *ksp);
2936 extern __checkReturn efx_rc_t
2938 __in efx_nic_t *enp,
2939 __in uint64_t app_id,
2940 __out boolean_t *licensedp);
2942 extern __checkReturn efx_rc_t
2944 __in efx_nic_t *enp,
2945 __in size_t buffer_size,
2946 __out uint32_t *typep,
2947 __out size_t *lengthp,
2948 __out_opt uint8_t *bufferp);
2951 extern __checkReturn efx_rc_t
2953 __in efx_nic_t *enp,
2954 __in_bcount(buffer_size)
2956 __in size_t buffer_size,
2957 __out uint32_t *startp);
2959 extern __checkReturn efx_rc_t
2961 __in efx_nic_t *enp,
2962 __in_bcount(buffer_size)
2964 __in size_t buffer_size,
2965 __in uint32_t offset,
2966 __out uint32_t *endp);
2968 extern __checkReturn __success(return != B_FALSE) boolean_t
2970 __in efx_nic_t *enp,
2971 __in_bcount(buffer_size)
2973 __in size_t buffer_size,
2974 __in uint32_t offset,
2975 __out uint32_t *startp,
2976 __out uint32_t *lengthp);
2978 extern __checkReturn __success(return != B_FALSE) boolean_t
2979 efx_lic_validate_key(
2980 __in efx_nic_t *enp,
2981 __in_bcount(length) caddr_t keyp,
2982 __in uint32_t length);
2984 extern __checkReturn efx_rc_t
2986 __in efx_nic_t *enp,
2987 __in_bcount(buffer_size)
2989 __in size_t buffer_size,
2990 __in uint32_t offset,
2991 __in uint32_t length,
2992 __out_bcount_part(key_max_size, *lengthp)
2994 __in size_t key_max_size,
2995 __out uint32_t *lengthp);
2997 extern __checkReturn efx_rc_t
2999 __in efx_nic_t *enp,
3000 __in_bcount(buffer_size)
3002 __in size_t buffer_size,
3003 __in uint32_t offset,
3004 __in_bcount(length) caddr_t keyp,
3005 __in uint32_t length,
3006 __out uint32_t *lengthp);
3008 __checkReturn efx_rc_t
3010 __in efx_nic_t *enp,
3011 __in_bcount(buffer_size)
3013 __in size_t buffer_size,
3014 __in uint32_t offset,
3015 __in uint32_t length,
3017 __out uint32_t *deltap);
3019 extern __checkReturn efx_rc_t
3020 efx_lic_create_partition(
3021 __in efx_nic_t *enp,
3022 __in_bcount(buffer_size)
3024 __in size_t buffer_size);
3026 extern __checkReturn efx_rc_t
3027 efx_lic_finish_partition(
3028 __in efx_nic_t *enp,
3029 __in_bcount(buffer_size)
3031 __in size_t buffer_size);
3033 #endif /* EFSYS_OPT_LICENSING */
3037 #if EFSYS_OPT_TUNNEL
3039 extern __checkReturn efx_rc_t
3041 __in efx_nic_t *enp);
3045 __in efx_nic_t *enp);
3048 * For overlay network encapsulation using UDP, the firmware needs to know
3049 * the configured UDP port for the overlay so it can decode encapsulated
3051 * The UDP port/protocol list is global.
3054 extern __checkReturn efx_rc_t
3055 efx_tunnel_config_udp_add(
3056 __in efx_nic_t *enp,
3057 __in uint16_t port /* host/cpu-endian */,
3058 __in efx_tunnel_protocol_t protocol);
3060 extern __checkReturn efx_rc_t
3061 efx_tunnel_config_udp_remove(
3062 __in efx_nic_t *enp,
3063 __in uint16_t port /* host/cpu-endian */,
3064 __in efx_tunnel_protocol_t protocol);
3067 efx_tunnel_config_clear(
3068 __in efx_nic_t *enp);
3071 * Apply tunnel UDP ports configuration to hardware.
3073 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3076 extern __checkReturn efx_rc_t
3077 efx_tunnel_reconfigure(
3078 __in efx_nic_t *enp);
3080 #endif /* EFSYS_OPT_TUNNEL */
3082 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3085 * Firmware subvariant choice options.
3087 * It may be switched to no Tx checksum if attached drivers are either
3088 * preboot or firmware subvariant aware and no VIS are allocated.
3089 * If may be always switched to default explicitly using set request or
3090 * implicitly if unaware driver is attaching. If switching is done when
3091 * a driver is attached, it gets MC_REBOOT event and should recreate its
3094 * See SF-119419-TC DPDK Firmware Driver Interface and
3095 * SF-109306-TC EF10 for Driver Writers for details.
3097 typedef enum efx_nic_fw_subvariant_e {
3098 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3099 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3100 EFX_NIC_FW_SUBVARIANT_NTYPES
3101 } efx_nic_fw_subvariant_t;
3103 extern __checkReturn efx_rc_t
3104 efx_nic_get_fw_subvariant(
3105 __in efx_nic_t *enp,
3106 __out efx_nic_fw_subvariant_t *subvariantp);
3108 extern __checkReturn efx_rc_t
3109 efx_nic_set_fw_subvariant(
3110 __in efx_nic_t *enp,
3111 __in efx_nic_fw_subvariant_t subvariant);
3113 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3119 #endif /* _SYS_EFX_H */