2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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34 #define EFX_EV_QSTAT_INCR(_eep, _stat)
36 #define EFX_EV_PRESENT(_qword) \
37 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
38 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
44 static __checkReturn efx_rc_t
52 static __checkReturn efx_rc_t
55 __in unsigned int index,
56 __in efsys_mem_t *esmp,
67 static __checkReturn efx_rc_t
70 __in unsigned int count);
77 static __checkReturn efx_rc_t
80 __in unsigned int us);
82 #endif /* EFSYS_OPT_SIENA */
85 static const efx_ev_ops_t __efx_ev_siena_ops = {
86 siena_ev_init, /* eevo_init */
87 siena_ev_fini, /* eevo_fini */
88 siena_ev_qcreate, /* eevo_qcreate */
89 siena_ev_qdestroy, /* eevo_qdestroy */
90 siena_ev_qprime, /* eevo_qprime */
91 siena_ev_qpost, /* eevo_qpost */
92 siena_ev_qmoderate, /* eevo_qmoderate */
94 #endif /* EFSYS_OPT_SIENA */
97 __checkReturn efx_rc_t
101 const efx_ev_ops_t *eevop;
104 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
105 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
107 if (enp->en_mod_flags & EFX_MOD_EV) {
112 switch (enp->en_family) {
114 case EFX_FAMILY_SIENA:
115 eevop = &__efx_ev_siena_ops;
117 #endif /* EFSYS_OPT_SIENA */
125 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
127 if ((rc = eevop->eevo_init(enp)) != 0)
130 enp->en_eevop = eevop;
131 enp->en_mod_flags |= EFX_MOD_EV;
138 EFSYS_PROBE1(fail1, efx_rc_t, rc);
140 enp->en_eevop = NULL;
141 enp->en_mod_flags &= ~EFX_MOD_EV;
149 const efx_ev_ops_t *eevop = enp->en_eevop;
151 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
152 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
153 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
154 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
155 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
156 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
158 eevop->eevo_fini(enp);
160 enp->en_eevop = NULL;
161 enp->en_mod_flags &= ~EFX_MOD_EV;
165 __checkReturn efx_rc_t
168 __in unsigned int index,
169 __in efsys_mem_t *esmp,
174 __deref_out efx_evq_t **eepp)
176 const efx_ev_ops_t *eevop = enp->en_eevop;
177 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
181 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
182 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
184 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
186 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
187 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
189 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
200 /* Allocate an EVQ object */
201 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
207 eep->ee_magic = EFX_EVQ_MAGIC;
209 eep->ee_index = index;
210 eep->ee_mask = n - 1;
211 eep->ee_flags = flags;
215 * Set outputs before the queue is created because interrupts may be
216 * raised for events immediately after the queue is created, before the
217 * function call below returns. See bug58606.
219 * The eepp pointer passed in by the client must therefore point to data
220 * shared with the client's event processing context.
225 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
236 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
242 EFSYS_PROBE1(fail1, efx_rc_t, rc);
250 efx_nic_t *enp = eep->ee_enp;
251 const efx_ev_ops_t *eevop = enp->en_eevop;
253 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
255 EFSYS_ASSERT(enp->en_ev_qcount != 0);
258 eevop->eevo_qdestroy(eep);
260 /* Free the EVQ object */
261 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
264 __checkReturn efx_rc_t
267 __in unsigned int count)
269 efx_nic_t *enp = eep->ee_enp;
270 const efx_ev_ops_t *eevop = enp->en_eevop;
273 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
275 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
280 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
288 EFSYS_PROBE1(fail1, efx_rc_t, rc);
292 __checkReturn boolean_t
295 __in unsigned int count)
300 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
302 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
303 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
305 return (EFX_EV_PRESENT(qword));
308 #define EFX_EV_BATCH 8
313 __inout unsigned int *countp,
314 __in const efx_ev_callbacks_t *eecp,
317 efx_qword_t ev[EFX_EV_BATCH];
324 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
325 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
326 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
328 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
329 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
330 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
331 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
332 FSE_AZ_EV_CODE_DRV_GEN_EV);
334 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
335 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
338 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
339 EFSYS_ASSERT(countp != NULL);
340 EFSYS_ASSERT(eecp != NULL);
344 /* Read up until the end of the batch period */
345 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
346 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
347 for (total = 0; total < batch; ++total) {
348 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
350 if (!EFX_EV_PRESENT(ev[total]))
353 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
354 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
355 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
357 offset += sizeof (efx_qword_t);
360 /* Process the batch of events */
361 for (index = 0; index < total; ++index) {
362 boolean_t should_abort;
365 EFX_EV_QSTAT_INCR(eep, EV_ALL);
367 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
369 case FSE_AZ_EV_CODE_RX_EV:
370 should_abort = eep->ee_rx(eep,
371 &(ev[index]), eecp, arg);
373 case FSE_AZ_EV_CODE_TX_EV:
374 should_abort = eep->ee_tx(eep,
375 &(ev[index]), eecp, arg);
377 case FSE_AZ_EV_CODE_DRIVER_EV:
378 should_abort = eep->ee_driver(eep,
379 &(ev[index]), eecp, arg);
381 case FSE_AZ_EV_CODE_DRV_GEN_EV:
382 should_abort = eep->ee_drv_gen(eep,
383 &(ev[index]), eecp, arg);
386 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
387 should_abort = eep->ee_mcdi(eep,
388 &(ev[index]), eecp, arg);
391 case FSE_AZ_EV_CODE_GLOBAL_EV:
392 if (eep->ee_global) {
393 should_abort = eep->ee_global(eep,
394 &(ev[index]), eecp, arg);
397 /* else fallthrough */
399 EFSYS_PROBE3(bad_event,
400 unsigned int, eep->ee_index,
402 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
404 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
406 EFSYS_ASSERT(eecp->eec_exception != NULL);
407 (void) eecp->eec_exception(arg,
408 EFX_EXCEPTION_EV_ERROR, code);
409 should_abort = B_TRUE;
412 /* Ignore subsequent events */
419 * Now that the hardware has most likely moved onto dma'ing
420 * into the next cache line, clear the processed events. Take
421 * care to only clear out events that we've processed
423 EFX_SET_QWORD(ev[0]);
424 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
425 for (index = 0; index < total; ++index) {
426 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
427 offset += sizeof (efx_qword_t);
432 } while (total == batch);
442 efx_nic_t *enp = eep->ee_enp;
443 const efx_ev_ops_t *eevop = enp->en_eevop;
445 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
447 EFSYS_ASSERT(eevop != NULL &&
448 eevop->eevo_qpost != NULL);
450 eevop->eevo_qpost(eep, data);
453 __checkReturn efx_rc_t
454 efx_ev_usecs_to_ticks(
456 __in unsigned int us,
457 __out unsigned int *ticksp)
459 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
462 /* Convert microseconds to a timer tick count */
465 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
466 ticks = 1; /* Never round down to zero */
468 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
474 __checkReturn efx_rc_t
477 __in unsigned int us)
479 efx_nic_t *enp = eep->ee_enp;
480 const efx_ev_ops_t *eevop = enp->en_eevop;
483 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
485 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
486 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
491 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
499 EFSYS_PROBE1(fail1, efx_rc_t, rc);
505 static __checkReturn efx_rc_t
512 * Program the event queue for receive and transmit queue
515 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
516 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
517 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
523 static __checkReturn boolean_t
526 __in efx_qword_t *eqp,
529 __inout uint16_t *flagsp)
531 boolean_t ignore = B_FALSE;
533 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
534 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
535 EFSYS_PROBE(tobe_disc);
537 * Assume this is a unicast address mismatch, unless below
538 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
539 * EV_RX_PAUSE_FRM_ERR is set.
541 (*flagsp) |= EFX_ADDR_MISMATCH;
544 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
545 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
546 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
547 (*flagsp) |= EFX_DISCARD;
551 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
552 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
553 EFSYS_PROBE(crc_err);
554 (*flagsp) &= ~EFX_ADDR_MISMATCH;
555 (*flagsp) |= EFX_DISCARD;
558 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
559 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
560 EFSYS_PROBE(pause_frm_err);
561 (*flagsp) &= ~EFX_ADDR_MISMATCH;
562 (*flagsp) |= EFX_DISCARD;
565 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
566 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
567 EFSYS_PROBE(owner_id_err);
568 (*flagsp) |= EFX_DISCARD;
571 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
572 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
573 EFSYS_PROBE(ipv4_err);
574 (*flagsp) &= ~EFX_CKSUM_IPV4;
577 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
578 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
579 EFSYS_PROBE(udp_chk_err);
580 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
583 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
584 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
587 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
588 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
591 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
597 static __checkReturn boolean_t
600 __in efx_qword_t *eqp,
601 __in const efx_ev_callbacks_t *eecp,
612 boolean_t should_abort;
614 EFX_EV_QSTAT_INCR(eep, EV_RX);
616 /* Basic packet information */
617 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
618 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
619 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
620 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
622 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
624 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
627 * If packet is marked as OK and packet type is TCP/IP or
628 * UDP/IP or other IP, then we can rely on the hardware checksums.
631 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
632 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
634 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
635 flags |= EFX_PKT_IPV6;
637 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
638 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
642 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
643 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
645 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
646 flags |= EFX_PKT_IPV6;
648 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
649 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
653 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
655 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
656 flags = EFX_PKT_IPV6;
658 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
659 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
663 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
664 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
669 EFSYS_ASSERT(B_FALSE);
674 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
676 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
678 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
679 uint32_t, size, uint16_t, flags);
685 /* If we're not discarding the packet then it is ok */
686 if (~flags & EFX_DISCARD)
687 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
689 /* Detect multicast packets that didn't match the filter */
690 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
691 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
693 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
694 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
696 EFSYS_PROBE(mcast_mismatch);
697 flags |= EFX_ADDR_MISMATCH;
700 flags |= EFX_PKT_UNICAST;
704 * The packet parser in Siena can abort parsing packets under
705 * certain error conditions, setting the PKT_NOT_PARSED bit
706 * (which clears PKT_OK). If this is set, then don't trust
707 * the PKT_TYPE field.
712 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
714 flags |= EFX_CHECK_VLAN;
717 if (~flags & EFX_CHECK_VLAN) {
720 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
721 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
722 flags |= EFX_PKT_VLAN_TAGGED;
725 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
726 uint32_t, size, uint16_t, flags);
728 EFSYS_ASSERT(eecp->eec_rx != NULL);
729 should_abort = eecp->eec_rx(arg, label, id, size, flags);
731 return (should_abort);
734 static __checkReturn boolean_t
737 __in efx_qword_t *eqp,
738 __in const efx_ev_callbacks_t *eecp,
743 boolean_t should_abort;
745 EFX_EV_QSTAT_INCR(eep, EV_TX);
747 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
748 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
749 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
750 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
752 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
753 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
755 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
757 EFSYS_ASSERT(eecp->eec_tx != NULL);
758 should_abort = eecp->eec_tx(arg, label, id);
760 return (should_abort);
763 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
764 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
765 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
766 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
768 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
769 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
771 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
772 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
774 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
775 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
777 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
781 static __checkReturn boolean_t
784 __in efx_qword_t *eqp,
785 __in const efx_ev_callbacks_t *eecp,
788 _NOTE(ARGUNUSED(eqp, eecp, arg))
790 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
795 static __checkReturn boolean_t
798 __in efx_qword_t *eqp,
799 __in const efx_ev_callbacks_t *eecp,
802 boolean_t should_abort;
804 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
805 should_abort = B_FALSE;
807 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
808 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
811 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
813 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
815 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
817 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
818 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
822 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
826 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
827 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
829 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
830 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
833 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
835 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
837 should_abort = eecp->eec_rxq_flush_failed(arg,
840 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
842 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
844 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
849 case FSE_AZ_EVQ_INIT_DONE_EV:
850 EFSYS_ASSERT(eecp->eec_initialized != NULL);
851 should_abort = eecp->eec_initialized(arg);
855 case FSE_AZ_EVQ_NOT_EN_EV:
856 EFSYS_PROBE(evq_not_en);
859 case FSE_AZ_SRM_UPD_DONE_EV: {
862 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
864 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
866 EFSYS_ASSERT(eecp->eec_sram != NULL);
867 should_abort = eecp->eec_sram(arg, code);
871 case FSE_AZ_WAKE_UP_EV: {
874 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
876 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
877 should_abort = eecp->eec_wake_up(arg, id);
881 case FSE_AZ_TX_PKT_NON_TCP_UDP:
882 EFSYS_PROBE(tx_pkt_non_tcp_udp);
885 case FSE_AZ_TIMER_EV: {
888 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
890 EFSYS_ASSERT(eecp->eec_timer != NULL);
891 should_abort = eecp->eec_timer(arg, id);
895 case FSE_AZ_RX_DSC_ERROR_EV:
896 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
898 EFSYS_PROBE(rx_dsc_error);
900 EFSYS_ASSERT(eecp->eec_exception != NULL);
901 should_abort = eecp->eec_exception(arg,
902 EFX_EXCEPTION_RX_DSC_ERROR, 0);
906 case FSE_AZ_TX_DSC_ERROR_EV:
907 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
909 EFSYS_PROBE(tx_dsc_error);
911 EFSYS_ASSERT(eecp->eec_exception != NULL);
912 should_abort = eecp->eec_exception(arg,
913 EFX_EXCEPTION_TX_DSC_ERROR, 0);
921 return (should_abort);
924 static __checkReturn boolean_t
927 __in efx_qword_t *eqp,
928 __in const efx_ev_callbacks_t *eecp,
932 boolean_t should_abort;
934 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
936 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
937 if (data >= ((uint32_t)1 << 16)) {
938 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
939 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
940 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
944 EFSYS_ASSERT(eecp->eec_software != NULL);
945 should_abort = eecp->eec_software(arg, (uint16_t)data);
947 return (should_abort);
952 static __checkReturn boolean_t
955 __in efx_qword_t *eqp,
956 __in const efx_ev_callbacks_t *eecp,
959 efx_nic_t *enp = eep->ee_enp;
961 boolean_t should_abort = B_FALSE;
963 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
965 if (enp->en_family != EFX_FAMILY_SIENA)
968 EFSYS_ASSERT(eecp->eec_link_change != NULL);
969 EFSYS_ASSERT(eecp->eec_exception != NULL);
971 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
973 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
975 case MCDI_EVENT_CODE_BADSSERT:
976 efx_mcdi_ev_death(enp, EINTR);
979 case MCDI_EVENT_CODE_CMDDONE:
981 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
982 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
983 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
986 case MCDI_EVENT_CODE_LINKCHANGE: {
987 efx_link_mode_t link_mode;
989 siena_phy_link_ev(enp, eqp, &link_mode);
990 should_abort = eecp->eec_link_change(arg, link_mode);
993 case MCDI_EVENT_CODE_SENSOREVT: {
994 should_abort = B_FALSE;
997 case MCDI_EVENT_CODE_SCHEDERR:
998 /* Informational only */
1001 case MCDI_EVENT_CODE_REBOOT:
1002 efx_mcdi_ev_death(enp, EIO);
1005 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1008 case MCDI_EVENT_CODE_FWALERT: {
1009 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1011 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1012 should_abort = eecp->eec_exception(arg,
1013 EFX_EXCEPTION_FWALERT_SRAM,
1014 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1016 should_abort = eecp->eec_exception(arg,
1017 EFX_EXCEPTION_UNKNOWN_FWALERT,
1018 MCDI_EV_FIELD(eqp, DATA));
1023 EFSYS_PROBE1(mc_pcol_error, int, code);
1028 return (should_abort);
1031 #endif /* EFSYS_OPT_MCDI */
1033 static __checkReturn efx_rc_t
1035 __in efx_evq_t *eep,
1036 __in unsigned int count)
1038 efx_nic_t *enp = eep->ee_enp;
1042 rptr = count & eep->ee_mask;
1044 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1046 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1054 __in efx_evq_t *eep,
1057 efx_nic_t *enp = eep->ee_enp;
1061 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1062 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1064 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1065 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1066 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1068 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1071 static __checkReturn efx_rc_t
1073 __in efx_evq_t *eep,
1074 __in unsigned int us)
1076 efx_nic_t *enp = eep->ee_enp;
1077 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1078 unsigned int locked;
1082 if (us > encp->enc_evq_timer_max_us) {
1087 /* If the value is zero then disable the timer */
1089 EFX_POPULATE_DWORD_2(dword,
1090 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1091 FRF_CZ_TC_TIMER_VAL, 0);
1095 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1098 EFSYS_ASSERT(ticks > 0);
1099 EFX_POPULATE_DWORD_2(dword,
1100 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1101 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1104 locked = (eep->ee_index == 0) ? 1 : 0;
1106 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1107 eep->ee_index, &dword, locked);
1114 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1119 static __checkReturn efx_rc_t
1121 __in efx_nic_t *enp,
1122 __in unsigned int index,
1123 __in efsys_mem_t *esmp,
1127 __in uint32_t flags,
1128 __in efx_evq_t *eep)
1130 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1134 boolean_t notify_mode;
1136 _NOTE(ARGUNUSED(esmp))
1138 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1139 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1141 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1145 if (index >= encp->enc_evq_limit) {
1149 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1151 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1153 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1158 /* Set up the handler table */
1159 eep->ee_rx = siena_ev_rx;
1160 eep->ee_tx = siena_ev_tx;
1161 eep->ee_driver = siena_ev_driver;
1162 eep->ee_global = siena_ev_global;
1163 eep->ee_drv_gen = siena_ev_drv_gen;
1165 eep->ee_mcdi = siena_ev_mcdi;
1166 #endif /* EFSYS_OPT_MCDI */
1168 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1169 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1171 /* Set up the new event queue */
1172 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1173 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1174 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1175 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1177 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1178 FRF_AZ_EVQ_BUF_BASE_ID, id);
1180 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1182 /* Set initial interrupt moderation */
1183 siena_ev_qmoderate(eep, us);
1192 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1197 #endif /* EFSYS_OPT_SIENA */
1203 __in efx_evq_t *eep)
1205 efx_nic_t *enp = eep->ee_enp;
1208 /* Purge event queue */
1209 EFX_ZERO_OWORD(oword);
1211 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1212 eep->ee_index, &oword, B_TRUE);
1214 EFX_ZERO_OWORD(oword);
1215 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1220 __in efx_nic_t *enp)
1222 _NOTE(ARGUNUSED(enp))
1225 #endif /* EFSYS_OPT_SIENA */