2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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34 #define EFX_EV_QSTAT_INCR(_eep, _stat)
36 #define EFX_EV_PRESENT(_qword) \
37 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
38 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
44 static __checkReturn efx_rc_t
52 static __checkReturn efx_rc_t
55 __in unsigned int index,
56 __in efsys_mem_t *esmp,
67 static __checkReturn efx_rc_t
70 __in unsigned int count);
77 static __checkReturn efx_rc_t
80 __in unsigned int us);
82 #endif /* EFSYS_OPT_SIENA */
85 static const efx_ev_ops_t __efx_ev_siena_ops = {
86 siena_ev_init, /* eevo_init */
87 siena_ev_fini, /* eevo_fini */
88 siena_ev_qcreate, /* eevo_qcreate */
89 siena_ev_qdestroy, /* eevo_qdestroy */
90 siena_ev_qprime, /* eevo_qprime */
91 siena_ev_qpost, /* eevo_qpost */
92 siena_ev_qmoderate, /* eevo_qmoderate */
94 #endif /* EFSYS_OPT_SIENA */
96 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
97 static const efx_ev_ops_t __efx_ev_ef10_ops = {
98 ef10_ev_init, /* eevo_init */
99 ef10_ev_fini, /* eevo_fini */
100 ef10_ev_qcreate, /* eevo_qcreate */
101 ef10_ev_qdestroy, /* eevo_qdestroy */
102 ef10_ev_qprime, /* eevo_qprime */
103 ef10_ev_qpost, /* eevo_qpost */
104 ef10_ev_qmoderate, /* eevo_qmoderate */
106 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
109 __checkReturn efx_rc_t
113 const efx_ev_ops_t *eevop;
116 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
117 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
119 if (enp->en_mod_flags & EFX_MOD_EV) {
124 switch (enp->en_family) {
126 case EFX_FAMILY_SIENA:
127 eevop = &__efx_ev_siena_ops;
129 #endif /* EFSYS_OPT_SIENA */
131 #if EFSYS_OPT_HUNTINGTON
132 case EFX_FAMILY_HUNTINGTON:
133 eevop = &__efx_ev_ef10_ops;
135 #endif /* EFSYS_OPT_HUNTINGTON */
143 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
145 if ((rc = eevop->eevo_init(enp)) != 0)
148 enp->en_eevop = eevop;
149 enp->en_mod_flags |= EFX_MOD_EV;
156 EFSYS_PROBE1(fail1, efx_rc_t, rc);
158 enp->en_eevop = NULL;
159 enp->en_mod_flags &= ~EFX_MOD_EV;
167 const efx_ev_ops_t *eevop = enp->en_eevop;
169 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
170 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
171 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
172 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
173 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
174 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
176 eevop->eevo_fini(enp);
178 enp->en_eevop = NULL;
179 enp->en_mod_flags &= ~EFX_MOD_EV;
183 __checkReturn efx_rc_t
186 __in unsigned int index,
187 __in efsys_mem_t *esmp,
192 __deref_out efx_evq_t **eepp)
194 const efx_ev_ops_t *eevop = enp->en_eevop;
195 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
199 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
200 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
202 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
204 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
205 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
207 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
218 /* Allocate an EVQ object */
219 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
225 eep->ee_magic = EFX_EVQ_MAGIC;
227 eep->ee_index = index;
228 eep->ee_mask = n - 1;
229 eep->ee_flags = flags;
233 * Set outputs before the queue is created because interrupts may be
234 * raised for events immediately after the queue is created, before the
235 * function call below returns. See bug58606.
237 * The eepp pointer passed in by the client must therefore point to data
238 * shared with the client's event processing context.
243 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
254 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
260 EFSYS_PROBE1(fail1, efx_rc_t, rc);
268 efx_nic_t *enp = eep->ee_enp;
269 const efx_ev_ops_t *eevop = enp->en_eevop;
271 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
273 EFSYS_ASSERT(enp->en_ev_qcount != 0);
276 eevop->eevo_qdestroy(eep);
278 /* Free the EVQ object */
279 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
282 __checkReturn efx_rc_t
285 __in unsigned int count)
287 efx_nic_t *enp = eep->ee_enp;
288 const efx_ev_ops_t *eevop = enp->en_eevop;
291 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
293 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
298 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
306 EFSYS_PROBE1(fail1, efx_rc_t, rc);
310 __checkReturn boolean_t
313 __in unsigned int count)
318 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
320 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
321 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
323 return (EFX_EV_PRESENT(qword));
326 #define EFX_EV_BATCH 8
331 __inout unsigned int *countp,
332 __in const efx_ev_callbacks_t *eecp,
335 efx_qword_t ev[EFX_EV_BATCH];
342 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
343 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
344 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
346 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
347 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
348 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
349 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
350 FSE_AZ_EV_CODE_DRV_GEN_EV);
352 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
353 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
356 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
357 EFSYS_ASSERT(countp != NULL);
358 EFSYS_ASSERT(eecp != NULL);
362 /* Read up until the end of the batch period */
363 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
364 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
365 for (total = 0; total < batch; ++total) {
366 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
368 if (!EFX_EV_PRESENT(ev[total]))
371 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
372 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
373 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
375 offset += sizeof (efx_qword_t);
378 /* Process the batch of events */
379 for (index = 0; index < total; ++index) {
380 boolean_t should_abort;
383 EFX_EV_QSTAT_INCR(eep, EV_ALL);
385 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
387 case FSE_AZ_EV_CODE_RX_EV:
388 should_abort = eep->ee_rx(eep,
389 &(ev[index]), eecp, arg);
391 case FSE_AZ_EV_CODE_TX_EV:
392 should_abort = eep->ee_tx(eep,
393 &(ev[index]), eecp, arg);
395 case FSE_AZ_EV_CODE_DRIVER_EV:
396 should_abort = eep->ee_driver(eep,
397 &(ev[index]), eecp, arg);
399 case FSE_AZ_EV_CODE_DRV_GEN_EV:
400 should_abort = eep->ee_drv_gen(eep,
401 &(ev[index]), eecp, arg);
404 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
405 should_abort = eep->ee_mcdi(eep,
406 &(ev[index]), eecp, arg);
409 case FSE_AZ_EV_CODE_GLOBAL_EV:
410 if (eep->ee_global) {
411 should_abort = eep->ee_global(eep,
412 &(ev[index]), eecp, arg);
415 /* else fallthrough */
417 EFSYS_PROBE3(bad_event,
418 unsigned int, eep->ee_index,
420 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
422 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
424 EFSYS_ASSERT(eecp->eec_exception != NULL);
425 (void) eecp->eec_exception(arg,
426 EFX_EXCEPTION_EV_ERROR, code);
427 should_abort = B_TRUE;
430 /* Ignore subsequent events */
437 * Now that the hardware has most likely moved onto dma'ing
438 * into the next cache line, clear the processed events. Take
439 * care to only clear out events that we've processed
441 EFX_SET_QWORD(ev[0]);
442 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
443 for (index = 0; index < total; ++index) {
444 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
445 offset += sizeof (efx_qword_t);
450 } while (total == batch);
460 efx_nic_t *enp = eep->ee_enp;
461 const efx_ev_ops_t *eevop = enp->en_eevop;
463 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
465 EFSYS_ASSERT(eevop != NULL &&
466 eevop->eevo_qpost != NULL);
468 eevop->eevo_qpost(eep, data);
471 __checkReturn efx_rc_t
472 efx_ev_usecs_to_ticks(
474 __in unsigned int us,
475 __out unsigned int *ticksp)
477 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
480 /* Convert microseconds to a timer tick count */
483 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
484 ticks = 1; /* Never round down to zero */
486 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
492 __checkReturn efx_rc_t
495 __in unsigned int us)
497 efx_nic_t *enp = eep->ee_enp;
498 const efx_ev_ops_t *eevop = enp->en_eevop;
501 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
503 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
504 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
509 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
517 EFSYS_PROBE1(fail1, efx_rc_t, rc);
523 static __checkReturn efx_rc_t
530 * Program the event queue for receive and transmit queue
533 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
534 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
535 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
541 static __checkReturn boolean_t
544 __in efx_qword_t *eqp,
547 __inout uint16_t *flagsp)
549 boolean_t ignore = B_FALSE;
551 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
552 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
553 EFSYS_PROBE(tobe_disc);
555 * Assume this is a unicast address mismatch, unless below
556 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
557 * EV_RX_PAUSE_FRM_ERR is set.
559 (*flagsp) |= EFX_ADDR_MISMATCH;
562 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
563 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
564 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
565 (*flagsp) |= EFX_DISCARD;
569 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
570 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
571 EFSYS_PROBE(crc_err);
572 (*flagsp) &= ~EFX_ADDR_MISMATCH;
573 (*flagsp) |= EFX_DISCARD;
576 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
577 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
578 EFSYS_PROBE(pause_frm_err);
579 (*flagsp) &= ~EFX_ADDR_MISMATCH;
580 (*flagsp) |= EFX_DISCARD;
583 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
584 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
585 EFSYS_PROBE(owner_id_err);
586 (*flagsp) |= EFX_DISCARD;
589 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
590 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
591 EFSYS_PROBE(ipv4_err);
592 (*flagsp) &= ~EFX_CKSUM_IPV4;
595 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
596 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
597 EFSYS_PROBE(udp_chk_err);
598 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
601 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
602 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
605 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
606 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
609 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
615 static __checkReturn boolean_t
618 __in efx_qword_t *eqp,
619 __in const efx_ev_callbacks_t *eecp,
630 boolean_t should_abort;
632 EFX_EV_QSTAT_INCR(eep, EV_RX);
634 /* Basic packet information */
635 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
636 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
637 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
638 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
640 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
642 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
645 * If packet is marked as OK and packet type is TCP/IP or
646 * UDP/IP or other IP, then we can rely on the hardware checksums.
649 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
650 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
652 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
653 flags |= EFX_PKT_IPV6;
655 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
656 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
660 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
661 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
663 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
664 flags |= EFX_PKT_IPV6;
666 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
667 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
671 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
673 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
674 flags = EFX_PKT_IPV6;
676 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
677 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
681 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
682 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
687 EFSYS_ASSERT(B_FALSE);
692 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
694 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
696 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
697 uint32_t, size, uint16_t, flags);
703 /* If we're not discarding the packet then it is ok */
704 if (~flags & EFX_DISCARD)
705 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
707 /* Detect multicast packets that didn't match the filter */
708 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
709 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
711 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
712 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
714 EFSYS_PROBE(mcast_mismatch);
715 flags |= EFX_ADDR_MISMATCH;
718 flags |= EFX_PKT_UNICAST;
722 * The packet parser in Siena can abort parsing packets under
723 * certain error conditions, setting the PKT_NOT_PARSED bit
724 * (which clears PKT_OK). If this is set, then don't trust
725 * the PKT_TYPE field.
730 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
732 flags |= EFX_CHECK_VLAN;
735 if (~flags & EFX_CHECK_VLAN) {
738 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
739 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
740 flags |= EFX_PKT_VLAN_TAGGED;
743 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
744 uint32_t, size, uint16_t, flags);
746 EFSYS_ASSERT(eecp->eec_rx != NULL);
747 should_abort = eecp->eec_rx(arg, label, id, size, flags);
749 return (should_abort);
752 static __checkReturn boolean_t
755 __in efx_qword_t *eqp,
756 __in const efx_ev_callbacks_t *eecp,
761 boolean_t should_abort;
763 EFX_EV_QSTAT_INCR(eep, EV_TX);
765 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
766 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
767 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
768 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
770 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
771 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
773 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
775 EFSYS_ASSERT(eecp->eec_tx != NULL);
776 should_abort = eecp->eec_tx(arg, label, id);
778 return (should_abort);
781 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
782 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
783 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
784 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
786 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
787 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
789 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
790 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
792 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
793 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
795 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
799 static __checkReturn boolean_t
802 __in efx_qword_t *eqp,
803 __in const efx_ev_callbacks_t *eecp,
806 _NOTE(ARGUNUSED(eqp, eecp, arg))
808 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
813 static __checkReturn boolean_t
816 __in efx_qword_t *eqp,
817 __in const efx_ev_callbacks_t *eecp,
820 boolean_t should_abort;
822 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
823 should_abort = B_FALSE;
825 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
826 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
829 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
831 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
833 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
835 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
836 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
840 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
844 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
845 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
847 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
848 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
851 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
853 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
855 should_abort = eecp->eec_rxq_flush_failed(arg,
858 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
860 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
862 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
867 case FSE_AZ_EVQ_INIT_DONE_EV:
868 EFSYS_ASSERT(eecp->eec_initialized != NULL);
869 should_abort = eecp->eec_initialized(arg);
873 case FSE_AZ_EVQ_NOT_EN_EV:
874 EFSYS_PROBE(evq_not_en);
877 case FSE_AZ_SRM_UPD_DONE_EV: {
880 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
882 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
884 EFSYS_ASSERT(eecp->eec_sram != NULL);
885 should_abort = eecp->eec_sram(arg, code);
889 case FSE_AZ_WAKE_UP_EV: {
892 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
894 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
895 should_abort = eecp->eec_wake_up(arg, id);
899 case FSE_AZ_TX_PKT_NON_TCP_UDP:
900 EFSYS_PROBE(tx_pkt_non_tcp_udp);
903 case FSE_AZ_TIMER_EV: {
906 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
908 EFSYS_ASSERT(eecp->eec_timer != NULL);
909 should_abort = eecp->eec_timer(arg, id);
913 case FSE_AZ_RX_DSC_ERROR_EV:
914 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
916 EFSYS_PROBE(rx_dsc_error);
918 EFSYS_ASSERT(eecp->eec_exception != NULL);
919 should_abort = eecp->eec_exception(arg,
920 EFX_EXCEPTION_RX_DSC_ERROR, 0);
924 case FSE_AZ_TX_DSC_ERROR_EV:
925 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
927 EFSYS_PROBE(tx_dsc_error);
929 EFSYS_ASSERT(eecp->eec_exception != NULL);
930 should_abort = eecp->eec_exception(arg,
931 EFX_EXCEPTION_TX_DSC_ERROR, 0);
939 return (should_abort);
942 static __checkReturn boolean_t
945 __in efx_qword_t *eqp,
946 __in const efx_ev_callbacks_t *eecp,
950 boolean_t should_abort;
952 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
954 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
955 if (data >= ((uint32_t)1 << 16)) {
956 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
957 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
958 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
962 EFSYS_ASSERT(eecp->eec_software != NULL);
963 should_abort = eecp->eec_software(arg, (uint16_t)data);
965 return (should_abort);
970 static __checkReturn boolean_t
973 __in efx_qword_t *eqp,
974 __in const efx_ev_callbacks_t *eecp,
977 efx_nic_t *enp = eep->ee_enp;
979 boolean_t should_abort = B_FALSE;
981 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
983 if (enp->en_family != EFX_FAMILY_SIENA)
986 EFSYS_ASSERT(eecp->eec_link_change != NULL);
987 EFSYS_ASSERT(eecp->eec_exception != NULL);
989 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
991 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
993 case MCDI_EVENT_CODE_BADSSERT:
994 efx_mcdi_ev_death(enp, EINTR);
997 case MCDI_EVENT_CODE_CMDDONE:
999 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1000 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1001 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1004 case MCDI_EVENT_CODE_LINKCHANGE: {
1005 efx_link_mode_t link_mode;
1007 siena_phy_link_ev(enp, eqp, &link_mode);
1008 should_abort = eecp->eec_link_change(arg, link_mode);
1011 case MCDI_EVENT_CODE_SENSOREVT: {
1012 should_abort = B_FALSE;
1015 case MCDI_EVENT_CODE_SCHEDERR:
1016 /* Informational only */
1019 case MCDI_EVENT_CODE_REBOOT:
1020 efx_mcdi_ev_death(enp, EIO);
1023 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1026 case MCDI_EVENT_CODE_FWALERT: {
1027 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1029 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1030 should_abort = eecp->eec_exception(arg,
1031 EFX_EXCEPTION_FWALERT_SRAM,
1032 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1034 should_abort = eecp->eec_exception(arg,
1035 EFX_EXCEPTION_UNKNOWN_FWALERT,
1036 MCDI_EV_FIELD(eqp, DATA));
1041 EFSYS_PROBE1(mc_pcol_error, int, code);
1046 return (should_abort);
1049 #endif /* EFSYS_OPT_MCDI */
1051 static __checkReturn efx_rc_t
1053 __in efx_evq_t *eep,
1054 __in unsigned int count)
1056 efx_nic_t *enp = eep->ee_enp;
1060 rptr = count & eep->ee_mask;
1062 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1064 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1072 __in efx_evq_t *eep,
1075 efx_nic_t *enp = eep->ee_enp;
1079 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1080 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1082 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1083 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1084 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1086 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1089 static __checkReturn efx_rc_t
1091 __in efx_evq_t *eep,
1092 __in unsigned int us)
1094 efx_nic_t *enp = eep->ee_enp;
1095 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1096 unsigned int locked;
1100 if (us > encp->enc_evq_timer_max_us) {
1105 /* If the value is zero then disable the timer */
1107 EFX_POPULATE_DWORD_2(dword,
1108 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1109 FRF_CZ_TC_TIMER_VAL, 0);
1113 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1116 EFSYS_ASSERT(ticks > 0);
1117 EFX_POPULATE_DWORD_2(dword,
1118 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1119 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1122 locked = (eep->ee_index == 0) ? 1 : 0;
1124 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1125 eep->ee_index, &dword, locked);
1132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1137 static __checkReturn efx_rc_t
1139 __in efx_nic_t *enp,
1140 __in unsigned int index,
1141 __in efsys_mem_t *esmp,
1145 __in uint32_t flags,
1146 __in efx_evq_t *eep)
1148 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1152 boolean_t notify_mode;
1154 _NOTE(ARGUNUSED(esmp))
1156 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1157 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1159 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1163 if (index >= encp->enc_evq_limit) {
1167 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1169 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1171 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1176 /* Set up the handler table */
1177 eep->ee_rx = siena_ev_rx;
1178 eep->ee_tx = siena_ev_tx;
1179 eep->ee_driver = siena_ev_driver;
1180 eep->ee_global = siena_ev_global;
1181 eep->ee_drv_gen = siena_ev_drv_gen;
1183 eep->ee_mcdi = siena_ev_mcdi;
1184 #endif /* EFSYS_OPT_MCDI */
1186 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1187 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1189 /* Set up the new event queue */
1190 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1191 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1192 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1193 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1195 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1196 FRF_AZ_EVQ_BUF_BASE_ID, id);
1198 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1200 /* Set initial interrupt moderation */
1201 siena_ev_qmoderate(eep, us);
1210 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1215 #endif /* EFSYS_OPT_SIENA */
1221 __in efx_evq_t *eep)
1223 efx_nic_t *enp = eep->ee_enp;
1226 /* Purge event queue */
1227 EFX_ZERO_OWORD(oword);
1229 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1230 eep->ee_index, &oword, B_TRUE);
1232 EFX_ZERO_OWORD(oword);
1233 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1238 __in efx_nic_t *enp)
1240 _NOTE(ARGUNUSED(enp))
1243 #endif /* EFSYS_OPT_SIENA */