1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
14 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
16 (_eep)->ee_stat[_stat]++; \
17 _NOTE(CONSTANTCONDITION) \
20 #define EFX_EV_QSTAT_INCR(_eep, _stat)
23 #define EFX_EV_PRESENT(_qword) \
24 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
25 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
31 static __checkReturn efx_rc_t
39 static __checkReturn efx_rc_t
42 __in unsigned int index,
43 __in efsys_mem_t *esmp,
54 static __checkReturn efx_rc_t
57 __in unsigned int count);
64 static __checkReturn efx_rc_t
67 __in unsigned int us);
71 siena_ev_qstats_update(
73 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
77 #endif /* EFSYS_OPT_SIENA */
80 static const efx_ev_ops_t __efx_ev_siena_ops = {
81 siena_ev_init, /* eevo_init */
82 siena_ev_fini, /* eevo_fini */
83 siena_ev_qcreate, /* eevo_qcreate */
84 siena_ev_qdestroy, /* eevo_qdestroy */
85 siena_ev_qprime, /* eevo_qprime */
86 siena_ev_qpost, /* eevo_qpost */
87 siena_ev_qmoderate, /* eevo_qmoderate */
89 siena_ev_qstats_update, /* eevo_qstats_update */
92 #endif /* EFSYS_OPT_SIENA */
95 static const efx_ev_ops_t __efx_ev_ef10_ops = {
96 ef10_ev_init, /* eevo_init */
97 ef10_ev_fini, /* eevo_fini */
98 ef10_ev_qcreate, /* eevo_qcreate */
99 ef10_ev_qdestroy, /* eevo_qdestroy */
100 ef10_ev_qprime, /* eevo_qprime */
101 ef10_ev_qpost, /* eevo_qpost */
102 ef10_ev_qmoderate, /* eevo_qmoderate */
104 ef10_ev_qstats_update, /* eevo_qstats_update */
107 #endif /* EFX_OPTS_EF10() */
110 __checkReturn efx_rc_t
114 const efx_ev_ops_t *eevop;
117 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
118 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
120 if (enp->en_mod_flags & EFX_MOD_EV) {
125 switch (enp->en_family) {
127 case EFX_FAMILY_SIENA:
128 eevop = &__efx_ev_siena_ops;
130 #endif /* EFSYS_OPT_SIENA */
132 #if EFSYS_OPT_HUNTINGTON
133 case EFX_FAMILY_HUNTINGTON:
134 eevop = &__efx_ev_ef10_ops;
136 #endif /* EFSYS_OPT_HUNTINGTON */
138 #if EFSYS_OPT_MEDFORD
139 case EFX_FAMILY_MEDFORD:
140 eevop = &__efx_ev_ef10_ops;
142 #endif /* EFSYS_OPT_MEDFORD */
144 #if EFSYS_OPT_MEDFORD2
145 case EFX_FAMILY_MEDFORD2:
146 eevop = &__efx_ev_ef10_ops;
148 #endif /* EFSYS_OPT_MEDFORD2 */
156 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
158 if ((rc = eevop->eevo_init(enp)) != 0)
161 enp->en_eevop = eevop;
162 enp->en_mod_flags |= EFX_MOD_EV;
169 EFSYS_PROBE1(fail1, efx_rc_t, rc);
171 enp->en_eevop = NULL;
172 enp->en_mod_flags &= ~EFX_MOD_EV;
178 __in const efx_nic_t *enp,
179 __in unsigned int ndescs)
181 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
183 return (ndescs * encp->enc_ev_desc_size);
186 __checkReturn unsigned int
188 __in const efx_nic_t *enp,
189 __in unsigned int ndescs)
191 return (EFX_DIV_ROUND_UP(efx_evq_size(enp, ndescs), EFX_BUF_SIZE));
198 const efx_ev_ops_t *eevop = enp->en_eevop;
200 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
201 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
202 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
203 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
204 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
205 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
207 eevop->eevo_fini(enp);
209 enp->en_eevop = NULL;
210 enp->en_mod_flags &= ~EFX_MOD_EV;
214 __checkReturn efx_rc_t
217 __in unsigned int index,
218 __in efsys_mem_t *esmp,
223 __deref_out efx_evq_t **eepp)
225 const efx_ev_ops_t *eevop = enp->en_eevop;
227 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
230 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
231 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
233 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
234 enp->en_nic_cfg.enc_evq_limit);
236 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
237 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
239 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
250 EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
251 EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
254 ndescs < encp->enc_evq_min_nevs ||
255 ndescs > encp->enc_evq_max_nevs) {
260 /* Allocate an EVQ object */
261 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
267 eep->ee_magic = EFX_EVQ_MAGIC;
269 eep->ee_index = index;
270 eep->ee_mask = ndescs - 1;
271 eep->ee_flags = flags;
275 * Set outputs before the queue is created because interrupts may be
276 * raised for events immediately after the queue is created, before the
277 * function call below returns. See bug58606.
279 * The eepp pointer passed in by the client must therefore point to data
280 * shared with the client's event processing context.
285 if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
296 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
304 EFSYS_PROBE1(fail1, efx_rc_t, rc);
312 efx_nic_t *enp = eep->ee_enp;
313 const efx_ev_ops_t *eevop = enp->en_eevop;
315 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
317 EFSYS_ASSERT(enp->en_ev_qcount != 0);
320 eevop->eevo_qdestroy(eep);
322 /* Free the EVQ object */
323 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
326 __checkReturn efx_rc_t
329 __in unsigned int count)
331 efx_nic_t *enp = eep->ee_enp;
332 const efx_ev_ops_t *eevop = enp->en_eevop;
335 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
337 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
342 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
350 EFSYS_PROBE1(fail1, efx_rc_t, rc);
354 __checkReturn boolean_t
357 __in unsigned int count)
362 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
364 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
365 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
367 return (EFX_EV_PRESENT(qword));
370 #if EFSYS_OPT_EV_PREFETCH
375 __in unsigned int count)
379 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
381 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
382 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
385 #endif /* EFSYS_OPT_EV_PREFETCH */
387 #define EFX_EV_BATCH 8
392 __inout unsigned int *countp,
393 __in const efx_ev_callbacks_t *eecp,
396 efx_qword_t ev[EFX_EV_BATCH];
403 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
404 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
405 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
407 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
408 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
409 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
410 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
411 FSE_AZ_EV_CODE_DRV_GEN_EV);
413 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
414 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
417 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
418 EFSYS_ASSERT(countp != NULL);
419 EFSYS_ASSERT(eecp != NULL);
423 /* Read up until the end of the batch period */
424 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
425 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
426 for (total = 0; total < batch; ++total) {
427 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
429 if (!EFX_EV_PRESENT(ev[total]))
432 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
433 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
434 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
436 offset += sizeof (efx_qword_t);
439 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
441 * Prefetch the next batch when we get within PREFETCH_PERIOD
442 * of a completed batch. If the batch is smaller, then prefetch
445 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
446 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
447 #endif /* EFSYS_OPT_EV_PREFETCH */
449 /* Process the batch of events */
450 for (index = 0; index < total; ++index) {
451 boolean_t should_abort;
454 #if EFSYS_OPT_EV_PREFETCH
455 /* Prefetch if we've now reached the batch period */
456 if (total == batch &&
457 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
458 offset = (count + batch) & eep->ee_mask;
459 offset *= sizeof (efx_qword_t);
461 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
463 #endif /* EFSYS_OPT_EV_PREFETCH */
465 EFX_EV_QSTAT_INCR(eep, EV_ALL);
467 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
469 case FSE_AZ_EV_CODE_RX_EV:
470 should_abort = eep->ee_rx(eep,
471 &(ev[index]), eecp, arg);
473 case FSE_AZ_EV_CODE_TX_EV:
474 should_abort = eep->ee_tx(eep,
475 &(ev[index]), eecp, arg);
477 case FSE_AZ_EV_CODE_DRIVER_EV:
478 should_abort = eep->ee_driver(eep,
479 &(ev[index]), eecp, arg);
481 case FSE_AZ_EV_CODE_DRV_GEN_EV:
482 should_abort = eep->ee_drv_gen(eep,
483 &(ev[index]), eecp, arg);
486 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
487 should_abort = eep->ee_mcdi(eep,
488 &(ev[index]), eecp, arg);
491 case FSE_AZ_EV_CODE_GLOBAL_EV:
492 if (eep->ee_global) {
493 should_abort = eep->ee_global(eep,
494 &(ev[index]), eecp, arg);
497 /* else fallthrough */
499 EFSYS_PROBE3(bad_event,
500 unsigned int, eep->ee_index,
502 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
504 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
506 EFSYS_ASSERT(eecp->eec_exception != NULL);
507 (void) eecp->eec_exception(arg,
508 EFX_EXCEPTION_EV_ERROR, code);
509 should_abort = B_TRUE;
512 /* Ignore subsequent events */
516 * Poison batch to ensure the outer
517 * loop is broken out of.
519 EFSYS_ASSERT(batch <= EFX_EV_BATCH);
520 batch += (EFX_EV_BATCH << 1);
521 EFSYS_ASSERT(total != batch);
527 * Now that the hardware has most likely moved onto dma'ing
528 * into the next cache line, clear the processed events. Take
529 * care to only clear out events that we've processed
531 EFX_SET_QWORD(ev[0]);
532 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
533 for (index = 0; index < total; ++index) {
534 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
535 offset += sizeof (efx_qword_t);
540 } while (total == batch);
550 efx_nic_t *enp = eep->ee_enp;
551 const efx_ev_ops_t *eevop = enp->en_eevop;
553 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
555 EFSYS_ASSERT(eevop != NULL &&
556 eevop->eevo_qpost != NULL);
558 eevop->eevo_qpost(eep, data);
561 __checkReturn efx_rc_t
562 efx_ev_usecs_to_ticks(
564 __in unsigned int us,
565 __out unsigned int *ticksp)
567 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
571 if (encp->enc_evq_timer_quantum_ns == 0) {
576 /* Convert microseconds to a timer tick count */
579 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
580 ticks = 1; /* Never round down to zero */
582 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
588 EFSYS_PROBE1(fail1, efx_rc_t, rc);
592 __checkReturn efx_rc_t
595 __in unsigned int us)
597 efx_nic_t *enp = eep->ee_enp;
598 const efx_ev_ops_t *eevop = enp->en_eevop;
601 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
603 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
604 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
609 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
617 EFSYS_PROBE1(fail1, efx_rc_t, rc);
623 efx_ev_qstats_update(
625 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
627 { efx_nic_t *enp = eep->ee_enp;
628 const efx_ev_ops_t *eevop = enp->en_eevop;
630 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
632 eevop->eevo_qstats_update(eep, stat);
635 #endif /* EFSYS_OPT_QSTATS */
639 static __checkReturn efx_rc_t
646 * Program the event queue for receive and transmit queue
649 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
650 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
651 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
657 static __checkReturn boolean_t
660 __in efx_qword_t *eqp,
663 __inout uint16_t *flagsp)
665 boolean_t ignore = B_FALSE;
667 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
668 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
669 EFSYS_PROBE(tobe_disc);
671 * Assume this is a unicast address mismatch, unless below
672 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
673 * EV_RX_PAUSE_FRM_ERR is set.
675 (*flagsp) |= EFX_ADDR_MISMATCH;
678 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
679 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
680 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
681 (*flagsp) |= EFX_DISCARD;
683 #if EFSYS_OPT_RX_SCATTER
685 * Lookout for payload queue ran dry errors and ignore them.
687 * Sadly for the header/data split cases, the descriptor
688 * pointer in this event refers to the header queue and
689 * therefore cannot be easily detected as duplicate.
690 * So we drop these and rely on the receive processing seeing
691 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
692 * the partially received packet.
694 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
695 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
696 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
698 #endif /* EFSYS_OPT_RX_SCATTER */
701 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
702 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
703 EFSYS_PROBE(crc_err);
704 (*flagsp) &= ~EFX_ADDR_MISMATCH;
705 (*flagsp) |= EFX_DISCARD;
708 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
709 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
710 EFSYS_PROBE(pause_frm_err);
711 (*flagsp) &= ~EFX_ADDR_MISMATCH;
712 (*flagsp) |= EFX_DISCARD;
715 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
716 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
717 EFSYS_PROBE(owner_id_err);
718 (*flagsp) |= EFX_DISCARD;
721 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
722 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
723 EFSYS_PROBE(ipv4_err);
724 (*flagsp) &= ~EFX_CKSUM_IPV4;
727 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
728 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
729 EFSYS_PROBE(udp_chk_err);
730 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
733 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
734 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
737 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
738 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
741 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
747 static __checkReturn boolean_t
750 __in efx_qword_t *eqp,
751 __in const efx_ev_callbacks_t *eecp,
758 #if EFSYS_OPT_RX_SCATTER
760 boolean_t jumbo_cont;
761 #endif /* EFSYS_OPT_RX_SCATTER */
766 boolean_t should_abort;
768 EFX_EV_QSTAT_INCR(eep, EV_RX);
770 /* Basic packet information */
771 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
772 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
773 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
774 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
776 #if EFSYS_OPT_RX_SCATTER
777 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
778 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
779 #endif /* EFSYS_OPT_RX_SCATTER */
781 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
783 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
786 * If packet is marked as OK and packet type is TCP/IP or
787 * UDP/IP or other IP, then we can rely on the hardware checksums.
790 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
791 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
793 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
794 flags |= EFX_PKT_IPV6;
796 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
797 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
801 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
802 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
804 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
805 flags |= EFX_PKT_IPV6;
807 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
808 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
812 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
814 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
815 flags = EFX_PKT_IPV6;
817 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
818 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
822 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
823 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
828 EFSYS_ASSERT(B_FALSE);
833 #if EFSYS_OPT_RX_SCATTER
834 /* Report scatter and header/lookahead split buffer flags */
836 flags |= EFX_PKT_START;
838 flags |= EFX_PKT_CONT;
839 #endif /* EFSYS_OPT_RX_SCATTER */
841 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
843 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
845 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
846 uint32_t, size, uint16_t, flags);
852 /* If we're not discarding the packet then it is ok */
853 if (~flags & EFX_DISCARD)
854 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
856 /* Detect multicast packets that didn't match the filter */
857 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
858 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
860 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
861 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
863 EFSYS_PROBE(mcast_mismatch);
864 flags |= EFX_ADDR_MISMATCH;
867 flags |= EFX_PKT_UNICAST;
871 * The packet parser in Siena can abort parsing packets under
872 * certain error conditions, setting the PKT_NOT_PARSED bit
873 * (which clears PKT_OK). If this is set, then don't trust
874 * the PKT_TYPE field.
879 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
881 flags |= EFX_CHECK_VLAN;
884 if (~flags & EFX_CHECK_VLAN) {
887 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
888 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
889 flags |= EFX_PKT_VLAN_TAGGED;
892 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
893 uint32_t, size, uint16_t, flags);
895 EFSYS_ASSERT(eecp->eec_rx != NULL);
896 should_abort = eecp->eec_rx(arg, label, id, size, flags);
898 return (should_abort);
901 static __checkReturn boolean_t
904 __in efx_qword_t *eqp,
905 __in const efx_ev_callbacks_t *eecp,
910 boolean_t should_abort;
912 EFX_EV_QSTAT_INCR(eep, EV_TX);
914 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
915 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
916 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
917 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
919 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
920 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
922 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
924 EFSYS_ASSERT(eecp->eec_tx != NULL);
925 should_abort = eecp->eec_tx(arg, label, id);
927 return (should_abort);
930 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
931 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
932 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
933 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
935 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
936 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
938 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
939 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
941 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
942 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
944 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
948 static __checkReturn boolean_t
951 __in efx_qword_t *eqp,
952 __in const efx_ev_callbacks_t *eecp,
955 _NOTE(ARGUNUSED(eqp, eecp, arg))
957 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
962 static __checkReturn boolean_t
965 __in efx_qword_t *eqp,
966 __in const efx_ev_callbacks_t *eecp,
969 boolean_t should_abort;
971 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
972 should_abort = B_FALSE;
974 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
975 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
978 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
980 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
982 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
984 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
985 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
989 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
993 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
994 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
996 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
997 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
1000 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
1002 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
1004 should_abort = eecp->eec_rxq_flush_failed(arg,
1007 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1009 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1011 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1016 case FSE_AZ_EVQ_INIT_DONE_EV:
1017 EFSYS_ASSERT(eecp->eec_initialized != NULL);
1018 should_abort = eecp->eec_initialized(arg);
1022 case FSE_AZ_EVQ_NOT_EN_EV:
1023 EFSYS_PROBE(evq_not_en);
1026 case FSE_AZ_SRM_UPD_DONE_EV: {
1029 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
1031 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1033 EFSYS_ASSERT(eecp->eec_sram != NULL);
1034 should_abort = eecp->eec_sram(arg, code);
1038 case FSE_AZ_WAKE_UP_EV: {
1041 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1043 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1044 should_abort = eecp->eec_wake_up(arg, id);
1048 case FSE_AZ_TX_PKT_NON_TCP_UDP:
1049 EFSYS_PROBE(tx_pkt_non_tcp_udp);
1052 case FSE_AZ_TIMER_EV: {
1055 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1057 EFSYS_ASSERT(eecp->eec_timer != NULL);
1058 should_abort = eecp->eec_timer(arg, id);
1062 case FSE_AZ_RX_DSC_ERROR_EV:
1063 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1065 EFSYS_PROBE(rx_dsc_error);
1067 EFSYS_ASSERT(eecp->eec_exception != NULL);
1068 should_abort = eecp->eec_exception(arg,
1069 EFX_EXCEPTION_RX_DSC_ERROR, 0);
1073 case FSE_AZ_TX_DSC_ERROR_EV:
1074 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1076 EFSYS_PROBE(tx_dsc_error);
1078 EFSYS_ASSERT(eecp->eec_exception != NULL);
1079 should_abort = eecp->eec_exception(arg,
1080 EFX_EXCEPTION_TX_DSC_ERROR, 0);
1088 return (should_abort);
1091 static __checkReturn boolean_t
1093 __in efx_evq_t *eep,
1094 __in efx_qword_t *eqp,
1095 __in const efx_ev_callbacks_t *eecp,
1099 boolean_t should_abort;
1101 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1103 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1104 if (data >= ((uint32_t)1 << 16)) {
1105 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1106 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1107 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1111 EFSYS_ASSERT(eecp->eec_software != NULL);
1112 should_abort = eecp->eec_software(arg, (uint16_t)data);
1114 return (should_abort);
1119 static __checkReturn boolean_t
1121 __in efx_evq_t *eep,
1122 __in efx_qword_t *eqp,
1123 __in const efx_ev_callbacks_t *eecp,
1126 efx_nic_t *enp = eep->ee_enp;
1128 boolean_t should_abort = B_FALSE;
1130 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1132 if (enp->en_family != EFX_FAMILY_SIENA)
1135 EFSYS_ASSERT(eecp->eec_link_change != NULL);
1136 EFSYS_ASSERT(eecp->eec_exception != NULL);
1137 #if EFSYS_OPT_MON_STATS
1138 EFSYS_ASSERT(eecp->eec_monitor != NULL);
1141 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1143 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1145 case MCDI_EVENT_CODE_BADSSERT:
1146 efx_mcdi_ev_death(enp, EINTR);
1149 case MCDI_EVENT_CODE_CMDDONE:
1150 efx_mcdi_ev_cpl(enp,
1151 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1152 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1153 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1156 case MCDI_EVENT_CODE_LINKCHANGE: {
1157 efx_link_mode_t link_mode;
1159 siena_phy_link_ev(enp, eqp, &link_mode);
1160 should_abort = eecp->eec_link_change(arg, link_mode);
1163 case MCDI_EVENT_CODE_SENSOREVT: {
1164 #if EFSYS_OPT_MON_STATS
1166 efx_mon_stat_value_t value;
1169 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1170 should_abort = eecp->eec_monitor(arg, id, value);
1171 else if (rc == ENOTSUP) {
1172 should_abort = eecp->eec_exception(arg,
1173 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1174 MCDI_EV_FIELD(eqp, DATA));
1176 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1178 should_abort = B_FALSE;
1182 case MCDI_EVENT_CODE_SCHEDERR:
1183 /* Informational only */
1186 case MCDI_EVENT_CODE_REBOOT:
1187 efx_mcdi_ev_death(enp, EIO);
1190 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1191 #if EFSYS_OPT_MAC_STATS
1192 if (eecp->eec_mac_stats != NULL) {
1193 eecp->eec_mac_stats(arg,
1194 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1199 case MCDI_EVENT_CODE_FWALERT: {
1200 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1202 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1203 should_abort = eecp->eec_exception(arg,
1204 EFX_EXCEPTION_FWALERT_SRAM,
1205 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1207 should_abort = eecp->eec_exception(arg,
1208 EFX_EXCEPTION_UNKNOWN_FWALERT,
1209 MCDI_EV_FIELD(eqp, DATA));
1214 EFSYS_PROBE1(mc_pcol_error, int, code);
1219 return (should_abort);
1222 #endif /* EFSYS_OPT_MCDI */
1224 static __checkReturn efx_rc_t
1226 __in efx_evq_t *eep,
1227 __in unsigned int count)
1229 efx_nic_t *enp = eep->ee_enp;
1233 rptr = count & eep->ee_mask;
1235 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1237 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1245 __in efx_evq_t *eep,
1248 efx_nic_t *enp = eep->ee_enp;
1252 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1253 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1255 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1256 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1257 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1259 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1262 static __checkReturn efx_rc_t
1264 __in efx_evq_t *eep,
1265 __in unsigned int us)
1267 efx_nic_t *enp = eep->ee_enp;
1268 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1269 unsigned int locked;
1273 if (us > encp->enc_evq_timer_max_us) {
1278 /* If the value is zero then disable the timer */
1280 EFX_POPULATE_DWORD_2(dword,
1281 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1282 FRF_CZ_TC_TIMER_VAL, 0);
1286 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1289 EFSYS_ASSERT(ticks > 0);
1290 EFX_POPULATE_DWORD_2(dword,
1291 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1292 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1295 locked = (eep->ee_index == 0) ? 1 : 0;
1297 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1298 eep->ee_index, &dword, locked);
1305 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1310 static __checkReturn efx_rc_t
1312 __in efx_nic_t *enp,
1313 __in unsigned int index,
1314 __in efsys_mem_t *esmp,
1318 __in uint32_t flags,
1319 __in efx_evq_t *eep)
1321 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1325 boolean_t notify_mode;
1327 _NOTE(ARGUNUSED(esmp))
1329 if (index >= encp->enc_evq_limit) {
1333 #if EFSYS_OPT_RX_SCALE
1334 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1335 index >= EFX_MAXRSS_LEGACY) {
1341 (1U << size) <= encp->enc_evq_max_nevs / encp->enc_evq_min_nevs;
1343 if ((1U << size) == (uint32_t)ndescs / encp->enc_evq_min_nevs)
1345 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1350 /* Set up the handler table */
1351 eep->ee_rx = siena_ev_rx;
1352 eep->ee_tx = siena_ev_tx;
1353 eep->ee_driver = siena_ev_driver;
1354 eep->ee_global = siena_ev_global;
1355 eep->ee_drv_gen = siena_ev_drv_gen;
1357 eep->ee_mcdi = siena_ev_mcdi;
1358 #endif /* EFSYS_OPT_MCDI */
1360 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1361 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1363 /* Set up the new event queue */
1364 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1365 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1366 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1367 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1369 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1370 FRF_AZ_EVQ_BUF_BASE_ID, id);
1372 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1374 /* Set initial interrupt moderation */
1375 siena_ev_qmoderate(eep, us);
1381 #if EFSYS_OPT_RX_SCALE
1386 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1391 #endif /* EFSYS_OPT_SIENA */
1393 #if EFSYS_OPT_QSTATS
1395 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock ac223f7134058b4f */
1396 static const char * const __efx_ev_qstat_name[] = {
1403 "rx_buf_owner_id_err",
1404 "rx_ipv4_hdr_chksum_err",
1405 "rx_tcp_udp_chksum_err",
1409 "rx_mcast_hash_match",
1426 "driver_srm_upd_done",
1427 "driver_tx_descq_fls_done",
1428 "driver_rx_descq_fls_done",
1429 "driver_rx_descq_fls_failed",
1430 "driver_rx_dsc_error",
1431 "driver_tx_dsc_error",
1434 "rx_parse_incomplete",
1436 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1440 __in efx_nic_t *enp,
1441 __in unsigned int id)
1443 _NOTE(ARGUNUSED(enp))
1445 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1446 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1448 return (__efx_ev_qstat_name[id]);
1450 #endif /* EFSYS_OPT_NAMES */
1451 #endif /* EFSYS_OPT_QSTATS */
1455 #if EFSYS_OPT_QSTATS
1457 siena_ev_qstats_update(
1458 __in efx_evq_t *eep,
1459 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1463 for (id = 0; id < EV_NQSTATS; id++) {
1464 efsys_stat_t *essp = &stat[id];
1466 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1467 eep->ee_stat[id] = 0;
1470 #endif /* EFSYS_OPT_QSTATS */
1474 __in efx_evq_t *eep)
1476 efx_nic_t *enp = eep->ee_enp;
1479 /* Purge event queue */
1480 EFX_ZERO_OWORD(oword);
1482 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1483 eep->ee_index, &oword, B_TRUE);
1485 EFX_ZERO_OWORD(oword);
1486 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1491 __in efx_nic_t *enp)
1493 _NOTE(ARGUNUSED(enp))
1496 #endif /* EFSYS_OPT_SIENA */