2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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35 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
37 (_eep)->ee_stat[_stat]++; \
38 _NOTE(CONSTANTCONDITION) \
41 #define EFX_EV_QSTAT_INCR(_eep, _stat)
44 #define EFX_EV_PRESENT(_qword) \
45 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
46 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
52 static __checkReturn efx_rc_t
60 static __checkReturn efx_rc_t
63 __in unsigned int index,
64 __in efsys_mem_t *esmp,
75 static __checkReturn efx_rc_t
78 __in unsigned int count);
85 static __checkReturn efx_rc_t
88 __in unsigned int us);
92 siena_ev_qstats_update(
94 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
98 #endif /* EFSYS_OPT_SIENA */
101 static const efx_ev_ops_t __efx_ev_siena_ops = {
102 siena_ev_init, /* eevo_init */
103 siena_ev_fini, /* eevo_fini */
104 siena_ev_qcreate, /* eevo_qcreate */
105 siena_ev_qdestroy, /* eevo_qdestroy */
106 siena_ev_qprime, /* eevo_qprime */
107 siena_ev_qpost, /* eevo_qpost */
108 siena_ev_qmoderate, /* eevo_qmoderate */
110 siena_ev_qstats_update, /* eevo_qstats_update */
113 #endif /* EFSYS_OPT_SIENA */
115 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
116 static const efx_ev_ops_t __efx_ev_ef10_ops = {
117 ef10_ev_init, /* eevo_init */
118 ef10_ev_fini, /* eevo_fini */
119 ef10_ev_qcreate, /* eevo_qcreate */
120 ef10_ev_qdestroy, /* eevo_qdestroy */
121 ef10_ev_qprime, /* eevo_qprime */
122 ef10_ev_qpost, /* eevo_qpost */
123 ef10_ev_qmoderate, /* eevo_qmoderate */
125 ef10_ev_qstats_update, /* eevo_qstats_update */
128 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
131 __checkReturn efx_rc_t
135 const efx_ev_ops_t *eevop;
138 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
139 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
141 if (enp->en_mod_flags & EFX_MOD_EV) {
146 switch (enp->en_family) {
148 case EFX_FAMILY_SIENA:
149 eevop = &__efx_ev_siena_ops;
151 #endif /* EFSYS_OPT_SIENA */
153 #if EFSYS_OPT_HUNTINGTON
154 case EFX_FAMILY_HUNTINGTON:
155 eevop = &__efx_ev_ef10_ops;
157 #endif /* EFSYS_OPT_HUNTINGTON */
159 #if EFSYS_OPT_MEDFORD
160 case EFX_FAMILY_MEDFORD:
161 eevop = &__efx_ev_ef10_ops;
163 #endif /* EFSYS_OPT_MEDFORD */
171 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
173 if ((rc = eevop->eevo_init(enp)) != 0)
176 enp->en_eevop = eevop;
177 enp->en_mod_flags |= EFX_MOD_EV;
184 EFSYS_PROBE1(fail1, efx_rc_t, rc);
186 enp->en_eevop = NULL;
187 enp->en_mod_flags &= ~EFX_MOD_EV;
195 const efx_ev_ops_t *eevop = enp->en_eevop;
197 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
198 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
199 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
200 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
201 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
202 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
204 eevop->eevo_fini(enp);
206 enp->en_eevop = NULL;
207 enp->en_mod_flags &= ~EFX_MOD_EV;
211 __checkReturn efx_rc_t
214 __in unsigned int index,
215 __in efsys_mem_t *esmp,
220 __deref_out efx_evq_t **eepp)
222 const efx_ev_ops_t *eevop = enp->en_eevop;
223 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
227 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
228 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
230 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
232 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
233 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
235 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
246 /* Allocate an EVQ object */
247 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
253 eep->ee_magic = EFX_EVQ_MAGIC;
255 eep->ee_index = index;
256 eep->ee_mask = n - 1;
257 eep->ee_flags = flags;
261 * Set outputs before the queue is created because interrupts may be
262 * raised for events immediately after the queue is created, before the
263 * function call below returns. See bug58606.
265 * The eepp pointer passed in by the client must therefore point to data
266 * shared with the client's event processing context.
271 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
282 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
288 EFSYS_PROBE1(fail1, efx_rc_t, rc);
296 efx_nic_t *enp = eep->ee_enp;
297 const efx_ev_ops_t *eevop = enp->en_eevop;
299 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
301 EFSYS_ASSERT(enp->en_ev_qcount != 0);
304 eevop->eevo_qdestroy(eep);
306 /* Free the EVQ object */
307 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
310 __checkReturn efx_rc_t
313 __in unsigned int count)
315 efx_nic_t *enp = eep->ee_enp;
316 const efx_ev_ops_t *eevop = enp->en_eevop;
319 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
321 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
326 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
334 EFSYS_PROBE1(fail1, efx_rc_t, rc);
338 __checkReturn boolean_t
341 __in unsigned int count)
346 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
348 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
349 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
351 return (EFX_EV_PRESENT(qword));
354 #if EFSYS_OPT_EV_PREFETCH
359 __in unsigned int count)
363 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
365 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
366 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
369 #endif /* EFSYS_OPT_EV_PREFETCH */
371 #define EFX_EV_BATCH 8
376 __inout unsigned int *countp,
377 __in const efx_ev_callbacks_t *eecp,
380 efx_qword_t ev[EFX_EV_BATCH];
387 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
388 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
389 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
391 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
392 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
393 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
394 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
395 FSE_AZ_EV_CODE_DRV_GEN_EV);
397 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
398 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
401 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
402 EFSYS_ASSERT(countp != NULL);
403 EFSYS_ASSERT(eecp != NULL);
407 /* Read up until the end of the batch period */
408 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
409 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
410 for (total = 0; total < batch; ++total) {
411 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
413 if (!EFX_EV_PRESENT(ev[total]))
416 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
417 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
418 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
420 offset += sizeof (efx_qword_t);
423 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
425 * Prefetch the next batch when we get within PREFETCH_PERIOD
426 * of a completed batch. If the batch is smaller, then prefetch
429 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
430 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
431 #endif /* EFSYS_OPT_EV_PREFETCH */
433 /* Process the batch of events */
434 for (index = 0; index < total; ++index) {
435 boolean_t should_abort;
438 #if EFSYS_OPT_EV_PREFETCH
439 /* Prefetch if we've now reached the batch period */
440 if (total == batch &&
441 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
442 offset = (count + batch) & eep->ee_mask;
443 offset *= sizeof (efx_qword_t);
445 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
447 #endif /* EFSYS_OPT_EV_PREFETCH */
449 EFX_EV_QSTAT_INCR(eep, EV_ALL);
451 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
453 case FSE_AZ_EV_CODE_RX_EV:
454 should_abort = eep->ee_rx(eep,
455 &(ev[index]), eecp, arg);
457 case FSE_AZ_EV_CODE_TX_EV:
458 should_abort = eep->ee_tx(eep,
459 &(ev[index]), eecp, arg);
461 case FSE_AZ_EV_CODE_DRIVER_EV:
462 should_abort = eep->ee_driver(eep,
463 &(ev[index]), eecp, arg);
465 case FSE_AZ_EV_CODE_DRV_GEN_EV:
466 should_abort = eep->ee_drv_gen(eep,
467 &(ev[index]), eecp, arg);
470 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
471 should_abort = eep->ee_mcdi(eep,
472 &(ev[index]), eecp, arg);
475 case FSE_AZ_EV_CODE_GLOBAL_EV:
476 if (eep->ee_global) {
477 should_abort = eep->ee_global(eep,
478 &(ev[index]), eecp, arg);
481 /* else fallthrough */
483 EFSYS_PROBE3(bad_event,
484 unsigned int, eep->ee_index,
486 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
488 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
490 EFSYS_ASSERT(eecp->eec_exception != NULL);
491 (void) eecp->eec_exception(arg,
492 EFX_EXCEPTION_EV_ERROR, code);
493 should_abort = B_TRUE;
496 /* Ignore subsequent events */
503 * Now that the hardware has most likely moved onto dma'ing
504 * into the next cache line, clear the processed events. Take
505 * care to only clear out events that we've processed
507 EFX_SET_QWORD(ev[0]);
508 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
509 for (index = 0; index < total; ++index) {
510 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
511 offset += sizeof (efx_qword_t);
516 } while (total == batch);
526 efx_nic_t *enp = eep->ee_enp;
527 const efx_ev_ops_t *eevop = enp->en_eevop;
529 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
531 EFSYS_ASSERT(eevop != NULL &&
532 eevop->eevo_qpost != NULL);
534 eevop->eevo_qpost(eep, data);
537 __checkReturn efx_rc_t
538 efx_ev_usecs_to_ticks(
540 __in unsigned int us,
541 __out unsigned int *ticksp)
543 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
546 /* Convert microseconds to a timer tick count */
549 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
550 ticks = 1; /* Never round down to zero */
552 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
558 __checkReturn efx_rc_t
561 __in unsigned int us)
563 efx_nic_t *enp = eep->ee_enp;
564 const efx_ev_ops_t *eevop = enp->en_eevop;
567 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
569 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
570 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
575 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
583 EFSYS_PROBE1(fail1, efx_rc_t, rc);
589 efx_ev_qstats_update(
591 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
593 { efx_nic_t *enp = eep->ee_enp;
594 const efx_ev_ops_t *eevop = enp->en_eevop;
596 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
598 eevop->eevo_qstats_update(eep, stat);
601 #endif /* EFSYS_OPT_QSTATS */
605 static __checkReturn efx_rc_t
612 * Program the event queue for receive and transmit queue
615 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
616 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
617 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
623 static __checkReturn boolean_t
626 __in efx_qword_t *eqp,
629 __inout uint16_t *flagsp)
631 boolean_t ignore = B_FALSE;
633 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
634 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
635 EFSYS_PROBE(tobe_disc);
637 * Assume this is a unicast address mismatch, unless below
638 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
639 * EV_RX_PAUSE_FRM_ERR is set.
641 (*flagsp) |= EFX_ADDR_MISMATCH;
644 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
645 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
646 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
647 (*flagsp) |= EFX_DISCARD;
649 #if EFSYS_OPT_RX_SCATTER
651 * Lookout for payload queue ran dry errors and ignore them.
653 * Sadly for the header/data split cases, the descriptor
654 * pointer in this event refers to the header queue and
655 * therefore cannot be easily detected as duplicate.
656 * So we drop these and rely on the receive processing seeing
657 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
658 * the partially received packet.
660 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
661 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
662 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
664 #endif /* EFSYS_OPT_RX_SCATTER */
667 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
668 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
669 EFSYS_PROBE(crc_err);
670 (*flagsp) &= ~EFX_ADDR_MISMATCH;
671 (*flagsp) |= EFX_DISCARD;
674 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
675 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
676 EFSYS_PROBE(pause_frm_err);
677 (*flagsp) &= ~EFX_ADDR_MISMATCH;
678 (*flagsp) |= EFX_DISCARD;
681 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
682 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
683 EFSYS_PROBE(owner_id_err);
684 (*flagsp) |= EFX_DISCARD;
687 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
688 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
689 EFSYS_PROBE(ipv4_err);
690 (*flagsp) &= ~EFX_CKSUM_IPV4;
693 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
694 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
695 EFSYS_PROBE(udp_chk_err);
696 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
699 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
700 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
703 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
704 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
707 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
713 static __checkReturn boolean_t
716 __in efx_qword_t *eqp,
717 __in const efx_ev_callbacks_t *eecp,
724 #if EFSYS_OPT_RX_SCATTER
726 boolean_t jumbo_cont;
727 #endif /* EFSYS_OPT_RX_SCATTER */
732 boolean_t should_abort;
734 EFX_EV_QSTAT_INCR(eep, EV_RX);
736 /* Basic packet information */
737 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
738 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
739 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
740 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
742 #if EFSYS_OPT_RX_SCATTER
743 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
744 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
745 #endif /* EFSYS_OPT_RX_SCATTER */
747 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
749 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
752 * If packet is marked as OK and packet type is TCP/IP or
753 * UDP/IP or other IP, then we can rely on the hardware checksums.
756 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
757 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
759 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
760 flags |= EFX_PKT_IPV6;
762 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
763 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
767 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
768 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
770 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
771 flags |= EFX_PKT_IPV6;
773 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
774 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
778 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
780 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
781 flags = EFX_PKT_IPV6;
783 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
784 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
788 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
789 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
794 EFSYS_ASSERT(B_FALSE);
799 #if EFSYS_OPT_RX_SCATTER
800 /* Report scatter and header/lookahead split buffer flags */
802 flags |= EFX_PKT_START;
804 flags |= EFX_PKT_CONT;
805 #endif /* EFSYS_OPT_RX_SCATTER */
807 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
809 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
811 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
812 uint32_t, size, uint16_t, flags);
818 /* If we're not discarding the packet then it is ok */
819 if (~flags & EFX_DISCARD)
820 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
822 /* Detect multicast packets that didn't match the filter */
823 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
824 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
826 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
827 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
829 EFSYS_PROBE(mcast_mismatch);
830 flags |= EFX_ADDR_MISMATCH;
833 flags |= EFX_PKT_UNICAST;
837 * The packet parser in Siena can abort parsing packets under
838 * certain error conditions, setting the PKT_NOT_PARSED bit
839 * (which clears PKT_OK). If this is set, then don't trust
840 * the PKT_TYPE field.
845 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
847 flags |= EFX_CHECK_VLAN;
850 if (~flags & EFX_CHECK_VLAN) {
853 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
854 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
855 flags |= EFX_PKT_VLAN_TAGGED;
858 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
859 uint32_t, size, uint16_t, flags);
861 EFSYS_ASSERT(eecp->eec_rx != NULL);
862 should_abort = eecp->eec_rx(arg, label, id, size, flags);
864 return (should_abort);
867 static __checkReturn boolean_t
870 __in efx_qword_t *eqp,
871 __in const efx_ev_callbacks_t *eecp,
876 boolean_t should_abort;
878 EFX_EV_QSTAT_INCR(eep, EV_TX);
880 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
881 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
882 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
883 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
885 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
886 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
888 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
890 EFSYS_ASSERT(eecp->eec_tx != NULL);
891 should_abort = eecp->eec_tx(arg, label, id);
893 return (should_abort);
896 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
897 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
898 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
899 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
901 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
902 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
904 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
905 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
907 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
908 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
910 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
914 static __checkReturn boolean_t
917 __in efx_qword_t *eqp,
918 __in const efx_ev_callbacks_t *eecp,
921 _NOTE(ARGUNUSED(eqp, eecp, arg))
923 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
928 static __checkReturn boolean_t
931 __in efx_qword_t *eqp,
932 __in const efx_ev_callbacks_t *eecp,
935 boolean_t should_abort;
937 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
938 should_abort = B_FALSE;
940 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
941 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
944 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
946 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
948 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
950 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
951 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
955 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
959 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
960 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
962 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
963 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
966 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
968 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
970 should_abort = eecp->eec_rxq_flush_failed(arg,
973 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
975 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
977 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
982 case FSE_AZ_EVQ_INIT_DONE_EV:
983 EFSYS_ASSERT(eecp->eec_initialized != NULL);
984 should_abort = eecp->eec_initialized(arg);
988 case FSE_AZ_EVQ_NOT_EN_EV:
989 EFSYS_PROBE(evq_not_en);
992 case FSE_AZ_SRM_UPD_DONE_EV: {
995 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
997 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
999 EFSYS_ASSERT(eecp->eec_sram != NULL);
1000 should_abort = eecp->eec_sram(arg, code);
1004 case FSE_AZ_WAKE_UP_EV: {
1007 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1009 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1010 should_abort = eecp->eec_wake_up(arg, id);
1014 case FSE_AZ_TX_PKT_NON_TCP_UDP:
1015 EFSYS_PROBE(tx_pkt_non_tcp_udp);
1018 case FSE_AZ_TIMER_EV: {
1021 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1023 EFSYS_ASSERT(eecp->eec_timer != NULL);
1024 should_abort = eecp->eec_timer(arg, id);
1028 case FSE_AZ_RX_DSC_ERROR_EV:
1029 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1031 EFSYS_PROBE(rx_dsc_error);
1033 EFSYS_ASSERT(eecp->eec_exception != NULL);
1034 should_abort = eecp->eec_exception(arg,
1035 EFX_EXCEPTION_RX_DSC_ERROR, 0);
1039 case FSE_AZ_TX_DSC_ERROR_EV:
1040 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1042 EFSYS_PROBE(tx_dsc_error);
1044 EFSYS_ASSERT(eecp->eec_exception != NULL);
1045 should_abort = eecp->eec_exception(arg,
1046 EFX_EXCEPTION_TX_DSC_ERROR, 0);
1054 return (should_abort);
1057 static __checkReturn boolean_t
1059 __in efx_evq_t *eep,
1060 __in efx_qword_t *eqp,
1061 __in const efx_ev_callbacks_t *eecp,
1065 boolean_t should_abort;
1067 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1069 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1070 if (data >= ((uint32_t)1 << 16)) {
1071 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1072 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1073 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1077 EFSYS_ASSERT(eecp->eec_software != NULL);
1078 should_abort = eecp->eec_software(arg, (uint16_t)data);
1080 return (should_abort);
1085 static __checkReturn boolean_t
1087 __in efx_evq_t *eep,
1088 __in efx_qword_t *eqp,
1089 __in const efx_ev_callbacks_t *eecp,
1092 efx_nic_t *enp = eep->ee_enp;
1094 boolean_t should_abort = B_FALSE;
1096 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1098 if (enp->en_family != EFX_FAMILY_SIENA)
1101 EFSYS_ASSERT(eecp->eec_link_change != NULL);
1102 EFSYS_ASSERT(eecp->eec_exception != NULL);
1104 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1106 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1108 case MCDI_EVENT_CODE_BADSSERT:
1109 efx_mcdi_ev_death(enp, EINTR);
1112 case MCDI_EVENT_CODE_CMDDONE:
1113 efx_mcdi_ev_cpl(enp,
1114 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1115 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1116 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1119 case MCDI_EVENT_CODE_LINKCHANGE: {
1120 efx_link_mode_t link_mode;
1122 siena_phy_link_ev(enp, eqp, &link_mode);
1123 should_abort = eecp->eec_link_change(arg, link_mode);
1126 case MCDI_EVENT_CODE_SENSOREVT: {
1127 should_abort = B_FALSE;
1130 case MCDI_EVENT_CODE_SCHEDERR:
1131 /* Informational only */
1134 case MCDI_EVENT_CODE_REBOOT:
1135 efx_mcdi_ev_death(enp, EIO);
1138 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1139 #if EFSYS_OPT_MAC_STATS
1140 if (eecp->eec_mac_stats != NULL) {
1141 eecp->eec_mac_stats(arg,
1142 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1147 case MCDI_EVENT_CODE_FWALERT: {
1148 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1150 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1151 should_abort = eecp->eec_exception(arg,
1152 EFX_EXCEPTION_FWALERT_SRAM,
1153 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1155 should_abort = eecp->eec_exception(arg,
1156 EFX_EXCEPTION_UNKNOWN_FWALERT,
1157 MCDI_EV_FIELD(eqp, DATA));
1162 EFSYS_PROBE1(mc_pcol_error, int, code);
1167 return (should_abort);
1170 #endif /* EFSYS_OPT_MCDI */
1172 static __checkReturn efx_rc_t
1174 __in efx_evq_t *eep,
1175 __in unsigned int count)
1177 efx_nic_t *enp = eep->ee_enp;
1181 rptr = count & eep->ee_mask;
1183 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1185 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1193 __in efx_evq_t *eep,
1196 efx_nic_t *enp = eep->ee_enp;
1200 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1201 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1203 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1204 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1205 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1207 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1210 static __checkReturn efx_rc_t
1212 __in efx_evq_t *eep,
1213 __in unsigned int us)
1215 efx_nic_t *enp = eep->ee_enp;
1216 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1217 unsigned int locked;
1221 if (us > encp->enc_evq_timer_max_us) {
1226 /* If the value is zero then disable the timer */
1228 EFX_POPULATE_DWORD_2(dword,
1229 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1230 FRF_CZ_TC_TIMER_VAL, 0);
1234 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1237 EFSYS_ASSERT(ticks > 0);
1238 EFX_POPULATE_DWORD_2(dword,
1239 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1240 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1243 locked = (eep->ee_index == 0) ? 1 : 0;
1245 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1246 eep->ee_index, &dword, locked);
1253 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1258 static __checkReturn efx_rc_t
1260 __in efx_nic_t *enp,
1261 __in unsigned int index,
1262 __in efsys_mem_t *esmp,
1266 __in uint32_t flags,
1267 __in efx_evq_t *eep)
1269 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1273 boolean_t notify_mode;
1275 _NOTE(ARGUNUSED(esmp))
1277 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1278 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1280 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1284 if (index >= encp->enc_evq_limit) {
1288 #if EFSYS_OPT_RX_SCALE
1289 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1290 index >= EFX_MAXRSS_LEGACY) {
1295 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1297 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1299 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1304 /* Set up the handler table */
1305 eep->ee_rx = siena_ev_rx;
1306 eep->ee_tx = siena_ev_tx;
1307 eep->ee_driver = siena_ev_driver;
1308 eep->ee_global = siena_ev_global;
1309 eep->ee_drv_gen = siena_ev_drv_gen;
1311 eep->ee_mcdi = siena_ev_mcdi;
1312 #endif /* EFSYS_OPT_MCDI */
1314 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1315 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1317 /* Set up the new event queue */
1318 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1319 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1320 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1321 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1323 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1324 FRF_AZ_EVQ_BUF_BASE_ID, id);
1326 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1328 /* Set initial interrupt moderation */
1329 siena_ev_qmoderate(eep, us);
1335 #if EFSYS_OPT_RX_SCALE
1342 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1347 #endif /* EFSYS_OPT_SIENA */
1349 #if EFSYS_OPT_QSTATS
1351 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1352 static const char * const __efx_ev_qstat_name[] = {
1359 "rx_buf_owner_id_err",
1360 "rx_ipv4_hdr_chksum_err",
1361 "rx_tcp_udp_chksum_err",
1365 "rx_mcast_hash_match",
1382 "driver_srm_upd_done",
1383 "driver_tx_descq_fls_done",
1384 "driver_rx_descq_fls_done",
1385 "driver_rx_descq_fls_failed",
1386 "driver_rx_dsc_error",
1387 "driver_tx_dsc_error",
1391 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1395 __in efx_nic_t *enp,
1396 __in unsigned int id)
1398 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1399 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1401 return (__efx_ev_qstat_name[id]);
1403 #endif /* EFSYS_OPT_NAMES */
1404 #endif /* EFSYS_OPT_QSTATS */
1408 #if EFSYS_OPT_QSTATS
1410 siena_ev_qstats_update(
1411 __in efx_evq_t *eep,
1412 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1416 for (id = 0; id < EV_NQSTATS; id++) {
1417 efsys_stat_t *essp = &stat[id];
1419 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1420 eep->ee_stat[id] = 0;
1423 #endif /* EFSYS_OPT_QSTATS */
1427 __in efx_evq_t *eep)
1429 efx_nic_t *enp = eep->ee_enp;
1432 /* Purge event queue */
1433 EFX_ZERO_OWORD(oword);
1435 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1436 eep->ee_index, &oword, B_TRUE);
1438 EFX_ZERO_OWORD(oword);
1439 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1444 __in efx_nic_t *enp)
1446 _NOTE(ARGUNUSED(enp))
1449 #endif /* EFSYS_OPT_SIENA */