2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
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11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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35 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
37 (_eep)->ee_stat[_stat]++; \
38 _NOTE(CONSTANTCONDITION) \
41 #define EFX_EV_QSTAT_INCR(_eep, _stat)
44 #define EFX_EV_PRESENT(_qword) \
45 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
46 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
52 static __checkReturn efx_rc_t
60 static __checkReturn efx_rc_t
63 __in unsigned int index,
64 __in efsys_mem_t *esmp,
75 static __checkReturn efx_rc_t
78 __in unsigned int count);
85 static __checkReturn efx_rc_t
88 __in unsigned int us);
92 siena_ev_qstats_update(
94 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
98 #endif /* EFSYS_OPT_SIENA */
101 static const efx_ev_ops_t __efx_ev_siena_ops = {
102 siena_ev_init, /* eevo_init */
103 siena_ev_fini, /* eevo_fini */
104 siena_ev_qcreate, /* eevo_qcreate */
105 siena_ev_qdestroy, /* eevo_qdestroy */
106 siena_ev_qprime, /* eevo_qprime */
107 siena_ev_qpost, /* eevo_qpost */
108 siena_ev_qmoderate, /* eevo_qmoderate */
110 siena_ev_qstats_update, /* eevo_qstats_update */
113 #endif /* EFSYS_OPT_SIENA */
115 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
116 static const efx_ev_ops_t __efx_ev_ef10_ops = {
117 ef10_ev_init, /* eevo_init */
118 ef10_ev_fini, /* eevo_fini */
119 ef10_ev_qcreate, /* eevo_qcreate */
120 ef10_ev_qdestroy, /* eevo_qdestroy */
121 ef10_ev_qprime, /* eevo_qprime */
122 ef10_ev_qpost, /* eevo_qpost */
123 ef10_ev_qmoderate, /* eevo_qmoderate */
125 ef10_ev_qstats_update, /* eevo_qstats_update */
128 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
131 __checkReturn efx_rc_t
135 const efx_ev_ops_t *eevop;
138 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
139 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
141 if (enp->en_mod_flags & EFX_MOD_EV) {
146 switch (enp->en_family) {
148 case EFX_FAMILY_SIENA:
149 eevop = &__efx_ev_siena_ops;
151 #endif /* EFSYS_OPT_SIENA */
153 #if EFSYS_OPT_HUNTINGTON
154 case EFX_FAMILY_HUNTINGTON:
155 eevop = &__efx_ev_ef10_ops;
157 #endif /* EFSYS_OPT_HUNTINGTON */
159 #if EFSYS_OPT_MEDFORD
160 case EFX_FAMILY_MEDFORD:
161 eevop = &__efx_ev_ef10_ops;
163 #endif /* EFSYS_OPT_MEDFORD */
171 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
173 if ((rc = eevop->eevo_init(enp)) != 0)
176 enp->en_eevop = eevop;
177 enp->en_mod_flags |= EFX_MOD_EV;
184 EFSYS_PROBE1(fail1, efx_rc_t, rc);
186 enp->en_eevop = NULL;
187 enp->en_mod_flags &= ~EFX_MOD_EV;
195 const efx_ev_ops_t *eevop = enp->en_eevop;
197 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
198 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
199 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
200 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
201 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
202 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
204 eevop->eevo_fini(enp);
206 enp->en_eevop = NULL;
207 enp->en_mod_flags &= ~EFX_MOD_EV;
211 __checkReturn efx_rc_t
214 __in unsigned int index,
215 __in efsys_mem_t *esmp,
220 __deref_out efx_evq_t **eepp)
222 const efx_ev_ops_t *eevop = enp->en_eevop;
223 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
227 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
228 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
230 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
232 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
233 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
235 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
246 /* Allocate an EVQ object */
247 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
253 eep->ee_magic = EFX_EVQ_MAGIC;
255 eep->ee_index = index;
256 eep->ee_mask = n - 1;
257 eep->ee_flags = flags;
261 * Set outputs before the queue is created because interrupts may be
262 * raised for events immediately after the queue is created, before the
263 * function call below returns. See bug58606.
265 * The eepp pointer passed in by the client must therefore point to data
266 * shared with the client's event processing context.
271 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
282 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
288 EFSYS_PROBE1(fail1, efx_rc_t, rc);
296 efx_nic_t *enp = eep->ee_enp;
297 const efx_ev_ops_t *eevop = enp->en_eevop;
299 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
301 EFSYS_ASSERT(enp->en_ev_qcount != 0);
304 eevop->eevo_qdestroy(eep);
306 /* Free the EVQ object */
307 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
310 __checkReturn efx_rc_t
313 __in unsigned int count)
315 efx_nic_t *enp = eep->ee_enp;
316 const efx_ev_ops_t *eevop = enp->en_eevop;
319 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
321 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
326 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
334 EFSYS_PROBE1(fail1, efx_rc_t, rc);
338 __checkReturn boolean_t
341 __in unsigned int count)
346 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
348 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
349 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
351 return (EFX_EV_PRESENT(qword));
354 #if EFSYS_OPT_EV_PREFETCH
359 __in unsigned int count)
363 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
365 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
366 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
369 #endif /* EFSYS_OPT_EV_PREFETCH */
371 #define EFX_EV_BATCH 8
376 __inout unsigned int *countp,
377 __in const efx_ev_callbacks_t *eecp,
380 efx_qword_t ev[EFX_EV_BATCH];
387 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
388 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
389 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
391 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
392 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
393 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
394 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
395 FSE_AZ_EV_CODE_DRV_GEN_EV);
397 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
398 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
401 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
402 EFSYS_ASSERT(countp != NULL);
403 EFSYS_ASSERT(eecp != NULL);
407 /* Read up until the end of the batch period */
408 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
409 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
410 for (total = 0; total < batch; ++total) {
411 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
413 if (!EFX_EV_PRESENT(ev[total]))
416 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
417 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
418 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
420 offset += sizeof (efx_qword_t);
423 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
425 * Prefetch the next batch when we get within PREFETCH_PERIOD
426 * of a completed batch. If the batch is smaller, then prefetch
429 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
430 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
431 #endif /* EFSYS_OPT_EV_PREFETCH */
433 /* Process the batch of events */
434 for (index = 0; index < total; ++index) {
435 boolean_t should_abort;
438 #if EFSYS_OPT_EV_PREFETCH
439 /* Prefetch if we've now reached the batch period */
440 if (total == batch &&
441 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
442 offset = (count + batch) & eep->ee_mask;
443 offset *= sizeof (efx_qword_t);
445 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
447 #endif /* EFSYS_OPT_EV_PREFETCH */
449 EFX_EV_QSTAT_INCR(eep, EV_ALL);
451 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
453 case FSE_AZ_EV_CODE_RX_EV:
454 should_abort = eep->ee_rx(eep,
455 &(ev[index]), eecp, arg);
457 case FSE_AZ_EV_CODE_TX_EV:
458 should_abort = eep->ee_tx(eep,
459 &(ev[index]), eecp, arg);
461 case FSE_AZ_EV_CODE_DRIVER_EV:
462 should_abort = eep->ee_driver(eep,
463 &(ev[index]), eecp, arg);
465 case FSE_AZ_EV_CODE_DRV_GEN_EV:
466 should_abort = eep->ee_drv_gen(eep,
467 &(ev[index]), eecp, arg);
470 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
471 should_abort = eep->ee_mcdi(eep,
472 &(ev[index]), eecp, arg);
475 case FSE_AZ_EV_CODE_GLOBAL_EV:
476 if (eep->ee_global) {
477 should_abort = eep->ee_global(eep,
478 &(ev[index]), eecp, arg);
481 /* else fallthrough */
483 EFSYS_PROBE3(bad_event,
484 unsigned int, eep->ee_index,
486 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
488 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
490 EFSYS_ASSERT(eecp->eec_exception != NULL);
491 (void) eecp->eec_exception(arg,
492 EFX_EXCEPTION_EV_ERROR, code);
493 should_abort = B_TRUE;
496 /* Ignore subsequent events */
503 * Now that the hardware has most likely moved onto dma'ing
504 * into the next cache line, clear the processed events. Take
505 * care to only clear out events that we've processed
507 EFX_SET_QWORD(ev[0]);
508 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
509 for (index = 0; index < total; ++index) {
510 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
511 offset += sizeof (efx_qword_t);
516 } while (total == batch);
526 efx_nic_t *enp = eep->ee_enp;
527 const efx_ev_ops_t *eevop = enp->en_eevop;
529 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
531 EFSYS_ASSERT(eevop != NULL &&
532 eevop->eevo_qpost != NULL);
534 eevop->eevo_qpost(eep, data);
537 __checkReturn efx_rc_t
538 efx_ev_usecs_to_ticks(
540 __in unsigned int us,
541 __out unsigned int *ticksp)
543 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
546 /* Convert microseconds to a timer tick count */
549 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
550 ticks = 1; /* Never round down to zero */
552 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
558 __checkReturn efx_rc_t
561 __in unsigned int us)
563 efx_nic_t *enp = eep->ee_enp;
564 const efx_ev_ops_t *eevop = enp->en_eevop;
567 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
569 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
570 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
575 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
583 EFSYS_PROBE1(fail1, efx_rc_t, rc);
589 efx_ev_qstats_update(
591 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
593 { efx_nic_t *enp = eep->ee_enp;
594 const efx_ev_ops_t *eevop = enp->en_eevop;
596 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
598 eevop->eevo_qstats_update(eep, stat);
601 #endif /* EFSYS_OPT_QSTATS */
605 static __checkReturn efx_rc_t
612 * Program the event queue for receive and transmit queue
615 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
616 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
617 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
623 static __checkReturn boolean_t
626 __in efx_qword_t *eqp,
629 __inout uint16_t *flagsp)
631 boolean_t ignore = B_FALSE;
633 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
634 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
635 EFSYS_PROBE(tobe_disc);
637 * Assume this is a unicast address mismatch, unless below
638 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
639 * EV_RX_PAUSE_FRM_ERR is set.
641 (*flagsp) |= EFX_ADDR_MISMATCH;
644 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
645 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
646 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
647 (*flagsp) |= EFX_DISCARD;
651 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
652 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
653 EFSYS_PROBE(crc_err);
654 (*flagsp) &= ~EFX_ADDR_MISMATCH;
655 (*flagsp) |= EFX_DISCARD;
658 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
659 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
660 EFSYS_PROBE(pause_frm_err);
661 (*flagsp) &= ~EFX_ADDR_MISMATCH;
662 (*flagsp) |= EFX_DISCARD;
665 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
666 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
667 EFSYS_PROBE(owner_id_err);
668 (*flagsp) |= EFX_DISCARD;
671 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
672 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
673 EFSYS_PROBE(ipv4_err);
674 (*flagsp) &= ~EFX_CKSUM_IPV4;
677 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
678 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
679 EFSYS_PROBE(udp_chk_err);
680 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
683 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
684 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
687 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
688 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
691 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
697 static __checkReturn boolean_t
700 __in efx_qword_t *eqp,
701 __in const efx_ev_callbacks_t *eecp,
712 boolean_t should_abort;
714 EFX_EV_QSTAT_INCR(eep, EV_RX);
716 /* Basic packet information */
717 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
718 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
719 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
720 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
722 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
724 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
727 * If packet is marked as OK and packet type is TCP/IP or
728 * UDP/IP or other IP, then we can rely on the hardware checksums.
731 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
732 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
734 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
735 flags |= EFX_PKT_IPV6;
737 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
738 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
742 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
743 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
745 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
746 flags |= EFX_PKT_IPV6;
748 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
749 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
753 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
755 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
756 flags = EFX_PKT_IPV6;
758 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
759 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
763 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
764 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
769 EFSYS_ASSERT(B_FALSE);
774 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
776 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
778 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
779 uint32_t, size, uint16_t, flags);
785 /* If we're not discarding the packet then it is ok */
786 if (~flags & EFX_DISCARD)
787 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
789 /* Detect multicast packets that didn't match the filter */
790 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
791 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
793 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
794 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
796 EFSYS_PROBE(mcast_mismatch);
797 flags |= EFX_ADDR_MISMATCH;
800 flags |= EFX_PKT_UNICAST;
804 * The packet parser in Siena can abort parsing packets under
805 * certain error conditions, setting the PKT_NOT_PARSED bit
806 * (which clears PKT_OK). If this is set, then don't trust
807 * the PKT_TYPE field.
812 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
814 flags |= EFX_CHECK_VLAN;
817 if (~flags & EFX_CHECK_VLAN) {
820 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
821 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
822 flags |= EFX_PKT_VLAN_TAGGED;
825 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
826 uint32_t, size, uint16_t, flags);
828 EFSYS_ASSERT(eecp->eec_rx != NULL);
829 should_abort = eecp->eec_rx(arg, label, id, size, flags);
831 return (should_abort);
834 static __checkReturn boolean_t
837 __in efx_qword_t *eqp,
838 __in const efx_ev_callbacks_t *eecp,
843 boolean_t should_abort;
845 EFX_EV_QSTAT_INCR(eep, EV_TX);
847 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
848 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
849 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
850 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
852 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
853 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
855 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
857 EFSYS_ASSERT(eecp->eec_tx != NULL);
858 should_abort = eecp->eec_tx(arg, label, id);
860 return (should_abort);
863 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
864 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
865 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
866 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
868 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
869 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
871 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
872 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
874 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
875 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
877 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
881 static __checkReturn boolean_t
884 __in efx_qword_t *eqp,
885 __in const efx_ev_callbacks_t *eecp,
888 _NOTE(ARGUNUSED(eqp, eecp, arg))
890 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
895 static __checkReturn boolean_t
898 __in efx_qword_t *eqp,
899 __in const efx_ev_callbacks_t *eecp,
902 boolean_t should_abort;
904 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
905 should_abort = B_FALSE;
907 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
908 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
911 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
913 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
915 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
917 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
918 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
922 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
926 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
927 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
929 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
930 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
933 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
935 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
937 should_abort = eecp->eec_rxq_flush_failed(arg,
940 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
942 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
944 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
949 case FSE_AZ_EVQ_INIT_DONE_EV:
950 EFSYS_ASSERT(eecp->eec_initialized != NULL);
951 should_abort = eecp->eec_initialized(arg);
955 case FSE_AZ_EVQ_NOT_EN_EV:
956 EFSYS_PROBE(evq_not_en);
959 case FSE_AZ_SRM_UPD_DONE_EV: {
962 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
964 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
966 EFSYS_ASSERT(eecp->eec_sram != NULL);
967 should_abort = eecp->eec_sram(arg, code);
971 case FSE_AZ_WAKE_UP_EV: {
974 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
976 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
977 should_abort = eecp->eec_wake_up(arg, id);
981 case FSE_AZ_TX_PKT_NON_TCP_UDP:
982 EFSYS_PROBE(tx_pkt_non_tcp_udp);
985 case FSE_AZ_TIMER_EV: {
988 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
990 EFSYS_ASSERT(eecp->eec_timer != NULL);
991 should_abort = eecp->eec_timer(arg, id);
995 case FSE_AZ_RX_DSC_ERROR_EV:
996 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
998 EFSYS_PROBE(rx_dsc_error);
1000 EFSYS_ASSERT(eecp->eec_exception != NULL);
1001 should_abort = eecp->eec_exception(arg,
1002 EFX_EXCEPTION_RX_DSC_ERROR, 0);
1006 case FSE_AZ_TX_DSC_ERROR_EV:
1007 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1009 EFSYS_PROBE(tx_dsc_error);
1011 EFSYS_ASSERT(eecp->eec_exception != NULL);
1012 should_abort = eecp->eec_exception(arg,
1013 EFX_EXCEPTION_TX_DSC_ERROR, 0);
1021 return (should_abort);
1024 static __checkReturn boolean_t
1026 __in efx_evq_t *eep,
1027 __in efx_qword_t *eqp,
1028 __in const efx_ev_callbacks_t *eecp,
1032 boolean_t should_abort;
1034 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1036 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1037 if (data >= ((uint32_t)1 << 16)) {
1038 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1039 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1040 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1044 EFSYS_ASSERT(eecp->eec_software != NULL);
1045 should_abort = eecp->eec_software(arg, (uint16_t)data);
1047 return (should_abort);
1052 static __checkReturn boolean_t
1054 __in efx_evq_t *eep,
1055 __in efx_qword_t *eqp,
1056 __in const efx_ev_callbacks_t *eecp,
1059 efx_nic_t *enp = eep->ee_enp;
1061 boolean_t should_abort = B_FALSE;
1063 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1065 if (enp->en_family != EFX_FAMILY_SIENA)
1068 EFSYS_ASSERT(eecp->eec_link_change != NULL);
1069 EFSYS_ASSERT(eecp->eec_exception != NULL);
1071 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1073 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1075 case MCDI_EVENT_CODE_BADSSERT:
1076 efx_mcdi_ev_death(enp, EINTR);
1079 case MCDI_EVENT_CODE_CMDDONE:
1080 efx_mcdi_ev_cpl(enp,
1081 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1082 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1083 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1086 case MCDI_EVENT_CODE_LINKCHANGE: {
1087 efx_link_mode_t link_mode;
1089 siena_phy_link_ev(enp, eqp, &link_mode);
1090 should_abort = eecp->eec_link_change(arg, link_mode);
1093 case MCDI_EVENT_CODE_SENSOREVT: {
1094 should_abort = B_FALSE;
1097 case MCDI_EVENT_CODE_SCHEDERR:
1098 /* Informational only */
1101 case MCDI_EVENT_CODE_REBOOT:
1102 efx_mcdi_ev_death(enp, EIO);
1105 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1106 #if EFSYS_OPT_MAC_STATS
1107 if (eecp->eec_mac_stats != NULL) {
1108 eecp->eec_mac_stats(arg,
1109 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1114 case MCDI_EVENT_CODE_FWALERT: {
1115 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1117 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1118 should_abort = eecp->eec_exception(arg,
1119 EFX_EXCEPTION_FWALERT_SRAM,
1120 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1122 should_abort = eecp->eec_exception(arg,
1123 EFX_EXCEPTION_UNKNOWN_FWALERT,
1124 MCDI_EV_FIELD(eqp, DATA));
1129 EFSYS_PROBE1(mc_pcol_error, int, code);
1134 return (should_abort);
1137 #endif /* EFSYS_OPT_MCDI */
1139 static __checkReturn efx_rc_t
1141 __in efx_evq_t *eep,
1142 __in unsigned int count)
1144 efx_nic_t *enp = eep->ee_enp;
1148 rptr = count & eep->ee_mask;
1150 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1152 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1160 __in efx_evq_t *eep,
1163 efx_nic_t *enp = eep->ee_enp;
1167 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1168 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1170 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1171 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1172 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1174 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1177 static __checkReturn efx_rc_t
1179 __in efx_evq_t *eep,
1180 __in unsigned int us)
1182 efx_nic_t *enp = eep->ee_enp;
1183 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1184 unsigned int locked;
1188 if (us > encp->enc_evq_timer_max_us) {
1193 /* If the value is zero then disable the timer */
1195 EFX_POPULATE_DWORD_2(dword,
1196 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1197 FRF_CZ_TC_TIMER_VAL, 0);
1201 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1204 EFSYS_ASSERT(ticks > 0);
1205 EFX_POPULATE_DWORD_2(dword,
1206 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1207 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1210 locked = (eep->ee_index == 0) ? 1 : 0;
1212 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1213 eep->ee_index, &dword, locked);
1220 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1225 static __checkReturn efx_rc_t
1227 __in efx_nic_t *enp,
1228 __in unsigned int index,
1229 __in efsys_mem_t *esmp,
1233 __in uint32_t flags,
1234 __in efx_evq_t *eep)
1236 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1240 boolean_t notify_mode;
1242 _NOTE(ARGUNUSED(esmp))
1244 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1245 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1247 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1251 if (index >= encp->enc_evq_limit) {
1255 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1257 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1259 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1264 /* Set up the handler table */
1265 eep->ee_rx = siena_ev_rx;
1266 eep->ee_tx = siena_ev_tx;
1267 eep->ee_driver = siena_ev_driver;
1268 eep->ee_global = siena_ev_global;
1269 eep->ee_drv_gen = siena_ev_drv_gen;
1271 eep->ee_mcdi = siena_ev_mcdi;
1272 #endif /* EFSYS_OPT_MCDI */
1274 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1275 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1277 /* Set up the new event queue */
1278 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1279 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1280 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1281 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1283 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1284 FRF_AZ_EVQ_BUF_BASE_ID, id);
1286 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1288 /* Set initial interrupt moderation */
1289 siena_ev_qmoderate(eep, us);
1298 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1303 #endif /* EFSYS_OPT_SIENA */
1305 #if EFSYS_OPT_QSTATS
1307 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1308 static const char * const __efx_ev_qstat_name[] = {
1315 "rx_buf_owner_id_err",
1316 "rx_ipv4_hdr_chksum_err",
1317 "rx_tcp_udp_chksum_err",
1321 "rx_mcast_hash_match",
1338 "driver_srm_upd_done",
1339 "driver_tx_descq_fls_done",
1340 "driver_rx_descq_fls_done",
1341 "driver_rx_descq_fls_failed",
1342 "driver_rx_dsc_error",
1343 "driver_tx_dsc_error",
1347 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1351 __in efx_nic_t *enp,
1352 __in unsigned int id)
1354 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1355 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1357 return (__efx_ev_qstat_name[id]);
1359 #endif /* EFSYS_OPT_NAMES */
1360 #endif /* EFSYS_OPT_QSTATS */
1364 #if EFSYS_OPT_QSTATS
1366 siena_ev_qstats_update(
1367 __in efx_evq_t *eep,
1368 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1372 for (id = 0; id < EV_NQSTATS; id++) {
1373 efsys_stat_t *essp = &stat[id];
1375 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1376 eep->ee_stat[id] = 0;
1379 #endif /* EFSYS_OPT_QSTATS */
1383 __in efx_evq_t *eep)
1385 efx_nic_t *enp = eep->ee_enp;
1388 /* Purge event queue */
1389 EFX_ZERO_OWORD(oword);
1391 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1392 eep->ee_index, &oword, B_TRUE);
1394 EFX_ZERO_OWORD(oword);
1395 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1400 __in efx_nic_t *enp)
1402 _NOTE(ARGUNUSED(enp))
1405 #endif /* EFSYS_OPT_SIENA */