2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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35 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
37 (_eep)->ee_stat[_stat]++; \
38 _NOTE(CONSTANTCONDITION) \
41 #define EFX_EV_QSTAT_INCR(_eep, _stat)
44 #define EFX_EV_PRESENT(_qword) \
45 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
46 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
52 static __checkReturn efx_rc_t
60 static __checkReturn efx_rc_t
63 __in unsigned int index,
64 __in efsys_mem_t *esmp,
75 static __checkReturn efx_rc_t
78 __in unsigned int count);
85 static __checkReturn efx_rc_t
88 __in unsigned int us);
92 siena_ev_qstats_update(
94 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
98 #endif /* EFSYS_OPT_SIENA */
101 static const efx_ev_ops_t __efx_ev_siena_ops = {
102 siena_ev_init, /* eevo_init */
103 siena_ev_fini, /* eevo_fini */
104 siena_ev_qcreate, /* eevo_qcreate */
105 siena_ev_qdestroy, /* eevo_qdestroy */
106 siena_ev_qprime, /* eevo_qprime */
107 siena_ev_qpost, /* eevo_qpost */
108 siena_ev_qmoderate, /* eevo_qmoderate */
110 siena_ev_qstats_update, /* eevo_qstats_update */
113 #endif /* EFSYS_OPT_SIENA */
115 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
116 static const efx_ev_ops_t __efx_ev_ef10_ops = {
117 ef10_ev_init, /* eevo_init */
118 ef10_ev_fini, /* eevo_fini */
119 ef10_ev_qcreate, /* eevo_qcreate */
120 ef10_ev_qdestroy, /* eevo_qdestroy */
121 ef10_ev_qprime, /* eevo_qprime */
122 ef10_ev_qpost, /* eevo_qpost */
123 ef10_ev_qmoderate, /* eevo_qmoderate */
125 ef10_ev_qstats_update, /* eevo_qstats_update */
128 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
131 __checkReturn efx_rc_t
135 const efx_ev_ops_t *eevop;
138 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
139 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
141 if (enp->en_mod_flags & EFX_MOD_EV) {
146 switch (enp->en_family) {
148 case EFX_FAMILY_SIENA:
149 eevop = &__efx_ev_siena_ops;
151 #endif /* EFSYS_OPT_SIENA */
153 #if EFSYS_OPT_HUNTINGTON
154 case EFX_FAMILY_HUNTINGTON:
155 eevop = &__efx_ev_ef10_ops;
157 #endif /* EFSYS_OPT_HUNTINGTON */
159 #if EFSYS_OPT_MEDFORD
160 case EFX_FAMILY_MEDFORD:
161 eevop = &__efx_ev_ef10_ops;
163 #endif /* EFSYS_OPT_MEDFORD */
171 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
173 if ((rc = eevop->eevo_init(enp)) != 0)
176 enp->en_eevop = eevop;
177 enp->en_mod_flags |= EFX_MOD_EV;
184 EFSYS_PROBE1(fail1, efx_rc_t, rc);
186 enp->en_eevop = NULL;
187 enp->en_mod_flags &= ~EFX_MOD_EV;
195 const efx_ev_ops_t *eevop = enp->en_eevop;
197 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
198 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
199 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
200 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
201 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
202 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
204 eevop->eevo_fini(enp);
206 enp->en_eevop = NULL;
207 enp->en_mod_flags &= ~EFX_MOD_EV;
211 __checkReturn efx_rc_t
214 __in unsigned int index,
215 __in efsys_mem_t *esmp,
220 __deref_out efx_evq_t **eepp)
222 const efx_ev_ops_t *eevop = enp->en_eevop;
223 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
227 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
228 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
230 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
232 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
233 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
235 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
246 /* Allocate an EVQ object */
247 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
253 eep->ee_magic = EFX_EVQ_MAGIC;
255 eep->ee_index = index;
256 eep->ee_mask = n - 1;
257 eep->ee_flags = flags;
261 * Set outputs before the queue is created because interrupts may be
262 * raised for events immediately after the queue is created, before the
263 * function call below returns. See bug58606.
265 * The eepp pointer passed in by the client must therefore point to data
266 * shared with the client's event processing context.
271 if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
282 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
288 EFSYS_PROBE1(fail1, efx_rc_t, rc);
296 efx_nic_t *enp = eep->ee_enp;
297 const efx_ev_ops_t *eevop = enp->en_eevop;
299 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
301 EFSYS_ASSERT(enp->en_ev_qcount != 0);
304 eevop->eevo_qdestroy(eep);
306 /* Free the EVQ object */
307 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
310 __checkReturn efx_rc_t
313 __in unsigned int count)
315 efx_nic_t *enp = eep->ee_enp;
316 const efx_ev_ops_t *eevop = enp->en_eevop;
319 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
321 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
326 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
334 EFSYS_PROBE1(fail1, efx_rc_t, rc);
338 __checkReturn boolean_t
341 __in unsigned int count)
346 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
348 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
349 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
351 return (EFX_EV_PRESENT(qword));
354 #define EFX_EV_BATCH 8
359 __inout unsigned int *countp,
360 __in const efx_ev_callbacks_t *eecp,
363 efx_qword_t ev[EFX_EV_BATCH];
370 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
371 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
372 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
374 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
375 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
376 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
377 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
378 FSE_AZ_EV_CODE_DRV_GEN_EV);
380 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
381 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
384 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
385 EFSYS_ASSERT(countp != NULL);
386 EFSYS_ASSERT(eecp != NULL);
390 /* Read up until the end of the batch period */
391 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
392 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
393 for (total = 0; total < batch; ++total) {
394 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
396 if (!EFX_EV_PRESENT(ev[total]))
399 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
400 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
401 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
403 offset += sizeof (efx_qword_t);
406 /* Process the batch of events */
407 for (index = 0; index < total; ++index) {
408 boolean_t should_abort;
411 EFX_EV_QSTAT_INCR(eep, EV_ALL);
413 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
415 case FSE_AZ_EV_CODE_RX_EV:
416 should_abort = eep->ee_rx(eep,
417 &(ev[index]), eecp, arg);
419 case FSE_AZ_EV_CODE_TX_EV:
420 should_abort = eep->ee_tx(eep,
421 &(ev[index]), eecp, arg);
423 case FSE_AZ_EV_CODE_DRIVER_EV:
424 should_abort = eep->ee_driver(eep,
425 &(ev[index]), eecp, arg);
427 case FSE_AZ_EV_CODE_DRV_GEN_EV:
428 should_abort = eep->ee_drv_gen(eep,
429 &(ev[index]), eecp, arg);
432 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
433 should_abort = eep->ee_mcdi(eep,
434 &(ev[index]), eecp, arg);
437 case FSE_AZ_EV_CODE_GLOBAL_EV:
438 if (eep->ee_global) {
439 should_abort = eep->ee_global(eep,
440 &(ev[index]), eecp, arg);
443 /* else fallthrough */
445 EFSYS_PROBE3(bad_event,
446 unsigned int, eep->ee_index,
448 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
450 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
452 EFSYS_ASSERT(eecp->eec_exception != NULL);
453 (void) eecp->eec_exception(arg,
454 EFX_EXCEPTION_EV_ERROR, code);
455 should_abort = B_TRUE;
458 /* Ignore subsequent events */
465 * Now that the hardware has most likely moved onto dma'ing
466 * into the next cache line, clear the processed events. Take
467 * care to only clear out events that we've processed
469 EFX_SET_QWORD(ev[0]);
470 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
471 for (index = 0; index < total; ++index) {
472 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
473 offset += sizeof (efx_qword_t);
478 } while (total == batch);
488 efx_nic_t *enp = eep->ee_enp;
489 const efx_ev_ops_t *eevop = enp->en_eevop;
491 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
493 EFSYS_ASSERT(eevop != NULL &&
494 eevop->eevo_qpost != NULL);
496 eevop->eevo_qpost(eep, data);
499 __checkReturn efx_rc_t
500 efx_ev_usecs_to_ticks(
502 __in unsigned int us,
503 __out unsigned int *ticksp)
505 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
508 /* Convert microseconds to a timer tick count */
511 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
512 ticks = 1; /* Never round down to zero */
514 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
520 __checkReturn efx_rc_t
523 __in unsigned int us)
525 efx_nic_t *enp = eep->ee_enp;
526 const efx_ev_ops_t *eevop = enp->en_eevop;
529 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
531 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
532 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
537 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
545 EFSYS_PROBE1(fail1, efx_rc_t, rc);
551 efx_ev_qstats_update(
553 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
555 { efx_nic_t *enp = eep->ee_enp;
556 const efx_ev_ops_t *eevop = enp->en_eevop;
558 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
560 eevop->eevo_qstats_update(eep, stat);
563 #endif /* EFSYS_OPT_QSTATS */
567 static __checkReturn efx_rc_t
574 * Program the event queue for receive and transmit queue
577 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
578 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
579 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
585 static __checkReturn boolean_t
588 __in efx_qword_t *eqp,
591 __inout uint16_t *flagsp)
593 boolean_t ignore = B_FALSE;
595 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
596 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
597 EFSYS_PROBE(tobe_disc);
599 * Assume this is a unicast address mismatch, unless below
600 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
601 * EV_RX_PAUSE_FRM_ERR is set.
603 (*flagsp) |= EFX_ADDR_MISMATCH;
606 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
607 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
608 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
609 (*flagsp) |= EFX_DISCARD;
613 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
614 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
615 EFSYS_PROBE(crc_err);
616 (*flagsp) &= ~EFX_ADDR_MISMATCH;
617 (*flagsp) |= EFX_DISCARD;
620 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
621 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
622 EFSYS_PROBE(pause_frm_err);
623 (*flagsp) &= ~EFX_ADDR_MISMATCH;
624 (*flagsp) |= EFX_DISCARD;
627 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
628 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
629 EFSYS_PROBE(owner_id_err);
630 (*flagsp) |= EFX_DISCARD;
633 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
634 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
635 EFSYS_PROBE(ipv4_err);
636 (*flagsp) &= ~EFX_CKSUM_IPV4;
639 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
640 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
641 EFSYS_PROBE(udp_chk_err);
642 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
645 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
646 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
649 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
650 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
653 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
659 static __checkReturn boolean_t
662 __in efx_qword_t *eqp,
663 __in const efx_ev_callbacks_t *eecp,
674 boolean_t should_abort;
676 EFX_EV_QSTAT_INCR(eep, EV_RX);
678 /* Basic packet information */
679 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
680 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
681 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
682 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
684 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
686 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
689 * If packet is marked as OK and packet type is TCP/IP or
690 * UDP/IP or other IP, then we can rely on the hardware checksums.
693 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
694 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
696 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
697 flags |= EFX_PKT_IPV6;
699 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
700 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
704 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
705 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
707 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
708 flags |= EFX_PKT_IPV6;
710 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
711 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
715 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
717 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
718 flags = EFX_PKT_IPV6;
720 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
721 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
725 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
726 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
731 EFSYS_ASSERT(B_FALSE);
736 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
738 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
740 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
741 uint32_t, size, uint16_t, flags);
747 /* If we're not discarding the packet then it is ok */
748 if (~flags & EFX_DISCARD)
749 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
751 /* Detect multicast packets that didn't match the filter */
752 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
753 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
755 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
756 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
758 EFSYS_PROBE(mcast_mismatch);
759 flags |= EFX_ADDR_MISMATCH;
762 flags |= EFX_PKT_UNICAST;
766 * The packet parser in Siena can abort parsing packets under
767 * certain error conditions, setting the PKT_NOT_PARSED bit
768 * (which clears PKT_OK). If this is set, then don't trust
769 * the PKT_TYPE field.
774 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
776 flags |= EFX_CHECK_VLAN;
779 if (~flags & EFX_CHECK_VLAN) {
782 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
783 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
784 flags |= EFX_PKT_VLAN_TAGGED;
787 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
788 uint32_t, size, uint16_t, flags);
790 EFSYS_ASSERT(eecp->eec_rx != NULL);
791 should_abort = eecp->eec_rx(arg, label, id, size, flags);
793 return (should_abort);
796 static __checkReturn boolean_t
799 __in efx_qword_t *eqp,
800 __in const efx_ev_callbacks_t *eecp,
805 boolean_t should_abort;
807 EFX_EV_QSTAT_INCR(eep, EV_TX);
809 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
810 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
811 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
812 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
814 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
815 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
817 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
819 EFSYS_ASSERT(eecp->eec_tx != NULL);
820 should_abort = eecp->eec_tx(arg, label, id);
822 return (should_abort);
825 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
826 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
827 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
828 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
830 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
831 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
833 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
834 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
836 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
837 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
839 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
843 static __checkReturn boolean_t
846 __in efx_qword_t *eqp,
847 __in const efx_ev_callbacks_t *eecp,
850 _NOTE(ARGUNUSED(eqp, eecp, arg))
852 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
857 static __checkReturn boolean_t
860 __in efx_qword_t *eqp,
861 __in const efx_ev_callbacks_t *eecp,
864 boolean_t should_abort;
866 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
867 should_abort = B_FALSE;
869 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
870 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
873 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
875 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
877 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
879 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
880 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
884 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
888 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
889 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
891 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
892 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
895 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
897 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
899 should_abort = eecp->eec_rxq_flush_failed(arg,
902 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
904 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
906 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
911 case FSE_AZ_EVQ_INIT_DONE_EV:
912 EFSYS_ASSERT(eecp->eec_initialized != NULL);
913 should_abort = eecp->eec_initialized(arg);
917 case FSE_AZ_EVQ_NOT_EN_EV:
918 EFSYS_PROBE(evq_not_en);
921 case FSE_AZ_SRM_UPD_DONE_EV: {
924 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
926 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
928 EFSYS_ASSERT(eecp->eec_sram != NULL);
929 should_abort = eecp->eec_sram(arg, code);
933 case FSE_AZ_WAKE_UP_EV: {
936 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
938 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
939 should_abort = eecp->eec_wake_up(arg, id);
943 case FSE_AZ_TX_PKT_NON_TCP_UDP:
944 EFSYS_PROBE(tx_pkt_non_tcp_udp);
947 case FSE_AZ_TIMER_EV: {
950 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
952 EFSYS_ASSERT(eecp->eec_timer != NULL);
953 should_abort = eecp->eec_timer(arg, id);
957 case FSE_AZ_RX_DSC_ERROR_EV:
958 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
960 EFSYS_PROBE(rx_dsc_error);
962 EFSYS_ASSERT(eecp->eec_exception != NULL);
963 should_abort = eecp->eec_exception(arg,
964 EFX_EXCEPTION_RX_DSC_ERROR, 0);
968 case FSE_AZ_TX_DSC_ERROR_EV:
969 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
971 EFSYS_PROBE(tx_dsc_error);
973 EFSYS_ASSERT(eecp->eec_exception != NULL);
974 should_abort = eecp->eec_exception(arg,
975 EFX_EXCEPTION_TX_DSC_ERROR, 0);
983 return (should_abort);
986 static __checkReturn boolean_t
989 __in efx_qword_t *eqp,
990 __in const efx_ev_callbacks_t *eecp,
994 boolean_t should_abort;
996 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
998 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
999 if (data >= ((uint32_t)1 << 16)) {
1000 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1001 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1002 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1006 EFSYS_ASSERT(eecp->eec_software != NULL);
1007 should_abort = eecp->eec_software(arg, (uint16_t)data);
1009 return (should_abort);
1014 static __checkReturn boolean_t
1016 __in efx_evq_t *eep,
1017 __in efx_qword_t *eqp,
1018 __in const efx_ev_callbacks_t *eecp,
1021 efx_nic_t *enp = eep->ee_enp;
1023 boolean_t should_abort = B_FALSE;
1025 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1027 if (enp->en_family != EFX_FAMILY_SIENA)
1030 EFSYS_ASSERT(eecp->eec_link_change != NULL);
1031 EFSYS_ASSERT(eecp->eec_exception != NULL);
1033 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1035 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1037 case MCDI_EVENT_CODE_BADSSERT:
1038 efx_mcdi_ev_death(enp, EINTR);
1041 case MCDI_EVENT_CODE_CMDDONE:
1042 efx_mcdi_ev_cpl(enp,
1043 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1044 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1045 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1048 case MCDI_EVENT_CODE_LINKCHANGE: {
1049 efx_link_mode_t link_mode;
1051 siena_phy_link_ev(enp, eqp, &link_mode);
1052 should_abort = eecp->eec_link_change(arg, link_mode);
1055 case MCDI_EVENT_CODE_SENSOREVT: {
1056 should_abort = B_FALSE;
1059 case MCDI_EVENT_CODE_SCHEDERR:
1060 /* Informational only */
1063 case MCDI_EVENT_CODE_REBOOT:
1064 efx_mcdi_ev_death(enp, EIO);
1067 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1070 case MCDI_EVENT_CODE_FWALERT: {
1071 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1073 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1074 should_abort = eecp->eec_exception(arg,
1075 EFX_EXCEPTION_FWALERT_SRAM,
1076 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1078 should_abort = eecp->eec_exception(arg,
1079 EFX_EXCEPTION_UNKNOWN_FWALERT,
1080 MCDI_EV_FIELD(eqp, DATA));
1085 EFSYS_PROBE1(mc_pcol_error, int, code);
1090 return (should_abort);
1093 #endif /* EFSYS_OPT_MCDI */
1095 static __checkReturn efx_rc_t
1097 __in efx_evq_t *eep,
1098 __in unsigned int count)
1100 efx_nic_t *enp = eep->ee_enp;
1104 rptr = count & eep->ee_mask;
1106 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1108 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1116 __in efx_evq_t *eep,
1119 efx_nic_t *enp = eep->ee_enp;
1123 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1124 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1126 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1127 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1128 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1130 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1133 static __checkReturn efx_rc_t
1135 __in efx_evq_t *eep,
1136 __in unsigned int us)
1138 efx_nic_t *enp = eep->ee_enp;
1139 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1140 unsigned int locked;
1144 if (us > encp->enc_evq_timer_max_us) {
1149 /* If the value is zero then disable the timer */
1151 EFX_POPULATE_DWORD_2(dword,
1152 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1153 FRF_CZ_TC_TIMER_VAL, 0);
1157 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1160 EFSYS_ASSERT(ticks > 0);
1161 EFX_POPULATE_DWORD_2(dword,
1162 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1163 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1166 locked = (eep->ee_index == 0) ? 1 : 0;
1168 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1169 eep->ee_index, &dword, locked);
1176 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1181 static __checkReturn efx_rc_t
1183 __in efx_nic_t *enp,
1184 __in unsigned int index,
1185 __in efsys_mem_t *esmp,
1189 __in uint32_t flags,
1190 __in efx_evq_t *eep)
1192 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1196 boolean_t notify_mode;
1198 _NOTE(ARGUNUSED(esmp))
1200 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1201 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1203 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1207 if (index >= encp->enc_evq_limit) {
1211 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1213 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1215 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1220 /* Set up the handler table */
1221 eep->ee_rx = siena_ev_rx;
1222 eep->ee_tx = siena_ev_tx;
1223 eep->ee_driver = siena_ev_driver;
1224 eep->ee_global = siena_ev_global;
1225 eep->ee_drv_gen = siena_ev_drv_gen;
1227 eep->ee_mcdi = siena_ev_mcdi;
1228 #endif /* EFSYS_OPT_MCDI */
1230 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1231 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1233 /* Set up the new event queue */
1234 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1235 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1236 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1237 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1239 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1240 FRF_AZ_EVQ_BUF_BASE_ID, id);
1242 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1244 /* Set initial interrupt moderation */
1245 siena_ev_qmoderate(eep, us);
1254 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1259 #endif /* EFSYS_OPT_SIENA */
1261 #if EFSYS_OPT_QSTATS
1263 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1264 static const char * const __efx_ev_qstat_name[] = {
1271 "rx_buf_owner_id_err",
1272 "rx_ipv4_hdr_chksum_err",
1273 "rx_tcp_udp_chksum_err",
1277 "rx_mcast_hash_match",
1294 "driver_srm_upd_done",
1295 "driver_tx_descq_fls_done",
1296 "driver_rx_descq_fls_done",
1297 "driver_rx_descq_fls_failed",
1298 "driver_rx_dsc_error",
1299 "driver_tx_dsc_error",
1303 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1307 __in efx_nic_t *enp,
1308 __in unsigned int id)
1310 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1311 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1313 return (__efx_ev_qstat_name[id]);
1315 #endif /* EFSYS_OPT_NAMES */
1316 #endif /* EFSYS_OPT_QSTATS */
1320 #if EFSYS_OPT_QSTATS
1322 siena_ev_qstats_update(
1323 __in efx_evq_t *eep,
1324 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1328 for (id = 0; id < EV_NQSTATS; id++) {
1329 efsys_stat_t *essp = &stat[id];
1331 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1332 eep->ee_stat[id] = 0;
1335 #endif /* EFSYS_OPT_QSTATS */
1339 __in efx_evq_t *eep)
1341 efx_nic_t *enp = eep->ee_enp;
1344 /* Purge event queue */
1345 EFX_ZERO_OWORD(oword);
1347 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1348 eep->ee_index, &oword, B_TRUE);
1350 EFX_ZERO_OWORD(oword);
1351 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1356 __in efx_nic_t *enp)
1358 _NOTE(ARGUNUSED(enp))
1361 #endif /* EFSYS_OPT_SIENA */