1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
14 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
16 (_eep)->ee_stat[_stat]++; \
17 _NOTE(CONSTANTCONDITION) \
20 #define EFX_EV_QSTAT_INCR(_eep, _stat)
23 #define EFX_EV_PRESENT(_qword) \
24 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
25 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
31 static __checkReturn efx_rc_t
39 static __checkReturn efx_rc_t
42 __in unsigned int index,
43 __in efsys_mem_t *esmp,
54 static __checkReturn efx_rc_t
57 __in unsigned int count);
64 static __checkReturn efx_rc_t
67 __in unsigned int us);
71 siena_ev_qstats_update(
73 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
77 #endif /* EFSYS_OPT_SIENA */
80 static const efx_ev_ops_t __efx_ev_siena_ops = {
81 siena_ev_init, /* eevo_init */
82 siena_ev_fini, /* eevo_fini */
83 siena_ev_qcreate, /* eevo_qcreate */
84 siena_ev_qdestroy, /* eevo_qdestroy */
85 siena_ev_qprime, /* eevo_qprime */
86 siena_ev_qpost, /* eevo_qpost */
87 siena_ev_qmoderate, /* eevo_qmoderate */
89 siena_ev_qstats_update, /* eevo_qstats_update */
92 #endif /* EFSYS_OPT_SIENA */
94 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
95 static const efx_ev_ops_t __efx_ev_ef10_ops = {
96 ef10_ev_init, /* eevo_init */
97 ef10_ev_fini, /* eevo_fini */
98 ef10_ev_qcreate, /* eevo_qcreate */
99 ef10_ev_qdestroy, /* eevo_qdestroy */
100 ef10_ev_qprime, /* eevo_qprime */
101 ef10_ev_qpost, /* eevo_qpost */
102 ef10_ev_qmoderate, /* eevo_qmoderate */
104 ef10_ev_qstats_update, /* eevo_qstats_update */
107 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
110 __checkReturn efx_rc_t
114 const efx_ev_ops_t *eevop;
117 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
118 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
120 if (enp->en_mod_flags & EFX_MOD_EV) {
125 switch (enp->en_family) {
127 case EFX_FAMILY_SIENA:
128 eevop = &__efx_ev_siena_ops;
130 #endif /* EFSYS_OPT_SIENA */
132 #if EFSYS_OPT_HUNTINGTON
133 case EFX_FAMILY_HUNTINGTON:
134 eevop = &__efx_ev_ef10_ops;
136 #endif /* EFSYS_OPT_HUNTINGTON */
138 #if EFSYS_OPT_MEDFORD
139 case EFX_FAMILY_MEDFORD:
140 eevop = &__efx_ev_ef10_ops;
142 #endif /* EFSYS_OPT_MEDFORD */
144 #if EFSYS_OPT_MEDFORD2
145 case EFX_FAMILY_MEDFORD2:
146 eevop = &__efx_ev_ef10_ops;
148 #endif /* EFSYS_OPT_MEDFORD2 */
156 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
158 if ((rc = eevop->eevo_init(enp)) != 0)
161 enp->en_eevop = eevop;
162 enp->en_mod_flags |= EFX_MOD_EV;
169 EFSYS_PROBE1(fail1, efx_rc_t, rc);
171 enp->en_eevop = NULL;
172 enp->en_mod_flags &= ~EFX_MOD_EV;
180 const efx_ev_ops_t *eevop = enp->en_eevop;
182 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
183 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
184 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
185 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
186 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
187 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
189 eevop->eevo_fini(enp);
191 enp->en_eevop = NULL;
192 enp->en_mod_flags &= ~EFX_MOD_EV;
196 __checkReturn efx_rc_t
199 __in unsigned int index,
200 __in efsys_mem_t *esmp,
205 __deref_out efx_evq_t **eepp)
207 const efx_ev_ops_t *eevop = enp->en_eevop;
211 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
212 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
214 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
215 enp->en_nic_cfg.enc_evq_limit);
217 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
218 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
220 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
231 /* Allocate an EVQ object */
232 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
238 eep->ee_magic = EFX_EVQ_MAGIC;
240 eep->ee_index = index;
241 eep->ee_mask = ndescs - 1;
242 eep->ee_flags = flags;
246 * Set outputs before the queue is created because interrupts may be
247 * raised for events immediately after the queue is created, before the
248 * function call below returns. See bug58606.
250 * The eepp pointer passed in by the client must therefore point to data
251 * shared with the client's event processing context.
256 if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
267 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
273 EFSYS_PROBE1(fail1, efx_rc_t, rc);
281 efx_nic_t *enp = eep->ee_enp;
282 const efx_ev_ops_t *eevop = enp->en_eevop;
284 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
286 EFSYS_ASSERT(enp->en_ev_qcount != 0);
289 eevop->eevo_qdestroy(eep);
291 /* Free the EVQ object */
292 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
295 __checkReturn efx_rc_t
298 __in unsigned int count)
300 efx_nic_t *enp = eep->ee_enp;
301 const efx_ev_ops_t *eevop = enp->en_eevop;
304 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
306 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
311 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
319 EFSYS_PROBE1(fail1, efx_rc_t, rc);
323 __checkReturn boolean_t
326 __in unsigned int count)
331 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
333 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
334 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
336 return (EFX_EV_PRESENT(qword));
339 #if EFSYS_OPT_EV_PREFETCH
344 __in unsigned int count)
348 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
350 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
351 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
354 #endif /* EFSYS_OPT_EV_PREFETCH */
356 #define EFX_EV_BATCH 8
361 __inout unsigned int *countp,
362 __in const efx_ev_callbacks_t *eecp,
365 efx_qword_t ev[EFX_EV_BATCH];
372 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
373 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
374 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
376 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
377 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
378 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
379 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
380 FSE_AZ_EV_CODE_DRV_GEN_EV);
382 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
383 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
386 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
387 EFSYS_ASSERT(countp != NULL);
388 EFSYS_ASSERT(eecp != NULL);
392 /* Read up until the end of the batch period */
393 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
394 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
395 for (total = 0; total < batch; ++total) {
396 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
398 if (!EFX_EV_PRESENT(ev[total]))
401 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
402 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
403 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
405 offset += sizeof (efx_qword_t);
408 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
410 * Prefetch the next batch when we get within PREFETCH_PERIOD
411 * of a completed batch. If the batch is smaller, then prefetch
414 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
415 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
416 #endif /* EFSYS_OPT_EV_PREFETCH */
418 /* Process the batch of events */
419 for (index = 0; index < total; ++index) {
420 boolean_t should_abort;
423 #if EFSYS_OPT_EV_PREFETCH
424 /* Prefetch if we've now reached the batch period */
425 if (total == batch &&
426 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
427 offset = (count + batch) & eep->ee_mask;
428 offset *= sizeof (efx_qword_t);
430 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
432 #endif /* EFSYS_OPT_EV_PREFETCH */
434 EFX_EV_QSTAT_INCR(eep, EV_ALL);
436 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
438 case FSE_AZ_EV_CODE_RX_EV:
439 should_abort = eep->ee_rx(eep,
440 &(ev[index]), eecp, arg);
442 case FSE_AZ_EV_CODE_TX_EV:
443 should_abort = eep->ee_tx(eep,
444 &(ev[index]), eecp, arg);
446 case FSE_AZ_EV_CODE_DRIVER_EV:
447 should_abort = eep->ee_driver(eep,
448 &(ev[index]), eecp, arg);
450 case FSE_AZ_EV_CODE_DRV_GEN_EV:
451 should_abort = eep->ee_drv_gen(eep,
452 &(ev[index]), eecp, arg);
455 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
456 should_abort = eep->ee_mcdi(eep,
457 &(ev[index]), eecp, arg);
460 case FSE_AZ_EV_CODE_GLOBAL_EV:
461 if (eep->ee_global) {
462 should_abort = eep->ee_global(eep,
463 &(ev[index]), eecp, arg);
466 /* else fallthrough */
468 EFSYS_PROBE3(bad_event,
469 unsigned int, eep->ee_index,
471 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
473 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
475 EFSYS_ASSERT(eecp->eec_exception != NULL);
476 (void) eecp->eec_exception(arg,
477 EFX_EXCEPTION_EV_ERROR, code);
478 should_abort = B_TRUE;
481 /* Ignore subsequent events */
485 * Poison batch to ensure the outer
486 * loop is broken out of.
488 EFSYS_ASSERT(batch <= EFX_EV_BATCH);
489 batch += (EFX_EV_BATCH << 1);
490 EFSYS_ASSERT(total != batch);
496 * Now that the hardware has most likely moved onto dma'ing
497 * into the next cache line, clear the processed events. Take
498 * care to only clear out events that we've processed
500 EFX_SET_QWORD(ev[0]);
501 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
502 for (index = 0; index < total; ++index) {
503 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
504 offset += sizeof (efx_qword_t);
509 } while (total == batch);
519 efx_nic_t *enp = eep->ee_enp;
520 const efx_ev_ops_t *eevop = enp->en_eevop;
522 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
524 EFSYS_ASSERT(eevop != NULL &&
525 eevop->eevo_qpost != NULL);
527 eevop->eevo_qpost(eep, data);
530 __checkReturn efx_rc_t
531 efx_ev_usecs_to_ticks(
533 __in unsigned int us,
534 __out unsigned int *ticksp)
536 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
539 /* Convert microseconds to a timer tick count */
542 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
543 ticks = 1; /* Never round down to zero */
545 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
551 __checkReturn efx_rc_t
554 __in unsigned int us)
556 efx_nic_t *enp = eep->ee_enp;
557 const efx_ev_ops_t *eevop = enp->en_eevop;
560 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
562 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
563 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
568 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
576 EFSYS_PROBE1(fail1, efx_rc_t, rc);
582 efx_ev_qstats_update(
584 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
586 { efx_nic_t *enp = eep->ee_enp;
587 const efx_ev_ops_t *eevop = enp->en_eevop;
589 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
591 eevop->eevo_qstats_update(eep, stat);
594 #endif /* EFSYS_OPT_QSTATS */
598 static __checkReturn efx_rc_t
605 * Program the event queue for receive and transmit queue
608 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
609 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
610 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
616 static __checkReturn boolean_t
619 __in efx_qword_t *eqp,
622 __inout uint16_t *flagsp)
624 boolean_t ignore = B_FALSE;
626 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
627 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
628 EFSYS_PROBE(tobe_disc);
630 * Assume this is a unicast address mismatch, unless below
631 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
632 * EV_RX_PAUSE_FRM_ERR is set.
634 (*flagsp) |= EFX_ADDR_MISMATCH;
637 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
638 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
639 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
640 (*flagsp) |= EFX_DISCARD;
642 #if EFSYS_OPT_RX_SCATTER
644 * Lookout for payload queue ran dry errors and ignore them.
646 * Sadly for the header/data split cases, the descriptor
647 * pointer in this event refers to the header queue and
648 * therefore cannot be easily detected as duplicate.
649 * So we drop these and rely on the receive processing seeing
650 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
651 * the partially received packet.
653 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
654 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
655 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
657 #endif /* EFSYS_OPT_RX_SCATTER */
660 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
661 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
662 EFSYS_PROBE(crc_err);
663 (*flagsp) &= ~EFX_ADDR_MISMATCH;
664 (*flagsp) |= EFX_DISCARD;
667 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
668 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
669 EFSYS_PROBE(pause_frm_err);
670 (*flagsp) &= ~EFX_ADDR_MISMATCH;
671 (*flagsp) |= EFX_DISCARD;
674 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
675 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
676 EFSYS_PROBE(owner_id_err);
677 (*flagsp) |= EFX_DISCARD;
680 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
681 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
682 EFSYS_PROBE(ipv4_err);
683 (*flagsp) &= ~EFX_CKSUM_IPV4;
686 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
687 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
688 EFSYS_PROBE(udp_chk_err);
689 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
692 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
693 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
696 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
697 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
700 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
706 static __checkReturn boolean_t
709 __in efx_qword_t *eqp,
710 __in const efx_ev_callbacks_t *eecp,
717 #if EFSYS_OPT_RX_SCATTER
719 boolean_t jumbo_cont;
720 #endif /* EFSYS_OPT_RX_SCATTER */
725 boolean_t should_abort;
727 EFX_EV_QSTAT_INCR(eep, EV_RX);
729 /* Basic packet information */
730 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
731 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
732 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
733 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
735 #if EFSYS_OPT_RX_SCATTER
736 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
737 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
738 #endif /* EFSYS_OPT_RX_SCATTER */
740 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
742 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
745 * If packet is marked as OK and packet type is TCP/IP or
746 * UDP/IP or other IP, then we can rely on the hardware checksums.
749 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
750 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
752 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
753 flags |= EFX_PKT_IPV6;
755 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
756 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
760 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
761 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
763 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
764 flags |= EFX_PKT_IPV6;
766 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
767 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
771 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
773 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
774 flags = EFX_PKT_IPV6;
776 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
777 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
781 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
782 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
787 EFSYS_ASSERT(B_FALSE);
792 #if EFSYS_OPT_RX_SCATTER
793 /* Report scatter and header/lookahead split buffer flags */
795 flags |= EFX_PKT_START;
797 flags |= EFX_PKT_CONT;
798 #endif /* EFSYS_OPT_RX_SCATTER */
800 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
802 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
804 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
805 uint32_t, size, uint16_t, flags);
811 /* If we're not discarding the packet then it is ok */
812 if (~flags & EFX_DISCARD)
813 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
815 /* Detect multicast packets that didn't match the filter */
816 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
817 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
819 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
820 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
822 EFSYS_PROBE(mcast_mismatch);
823 flags |= EFX_ADDR_MISMATCH;
826 flags |= EFX_PKT_UNICAST;
830 * The packet parser in Siena can abort parsing packets under
831 * certain error conditions, setting the PKT_NOT_PARSED bit
832 * (which clears PKT_OK). If this is set, then don't trust
833 * the PKT_TYPE field.
838 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
840 flags |= EFX_CHECK_VLAN;
843 if (~flags & EFX_CHECK_VLAN) {
846 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
847 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
848 flags |= EFX_PKT_VLAN_TAGGED;
851 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
852 uint32_t, size, uint16_t, flags);
854 EFSYS_ASSERT(eecp->eec_rx != NULL);
855 should_abort = eecp->eec_rx(arg, label, id, size, flags);
857 return (should_abort);
860 static __checkReturn boolean_t
863 __in efx_qword_t *eqp,
864 __in const efx_ev_callbacks_t *eecp,
869 boolean_t should_abort;
871 EFX_EV_QSTAT_INCR(eep, EV_TX);
873 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
874 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
875 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
876 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
878 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
879 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
881 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
883 EFSYS_ASSERT(eecp->eec_tx != NULL);
884 should_abort = eecp->eec_tx(arg, label, id);
886 return (should_abort);
889 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
890 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
891 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
892 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
894 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
895 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
897 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
898 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
900 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
901 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
903 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
907 static __checkReturn boolean_t
910 __in efx_qword_t *eqp,
911 __in const efx_ev_callbacks_t *eecp,
914 _NOTE(ARGUNUSED(eqp, eecp, arg))
916 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
921 static __checkReturn boolean_t
924 __in efx_qword_t *eqp,
925 __in const efx_ev_callbacks_t *eecp,
928 boolean_t should_abort;
930 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
931 should_abort = B_FALSE;
933 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
934 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
937 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
939 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
941 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
943 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
944 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
948 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
952 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
953 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
955 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
956 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
959 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
961 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
963 should_abort = eecp->eec_rxq_flush_failed(arg,
966 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
968 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
970 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
975 case FSE_AZ_EVQ_INIT_DONE_EV:
976 EFSYS_ASSERT(eecp->eec_initialized != NULL);
977 should_abort = eecp->eec_initialized(arg);
981 case FSE_AZ_EVQ_NOT_EN_EV:
982 EFSYS_PROBE(evq_not_en);
985 case FSE_AZ_SRM_UPD_DONE_EV: {
988 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
990 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
992 EFSYS_ASSERT(eecp->eec_sram != NULL);
993 should_abort = eecp->eec_sram(arg, code);
997 case FSE_AZ_WAKE_UP_EV: {
1000 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1002 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1003 should_abort = eecp->eec_wake_up(arg, id);
1007 case FSE_AZ_TX_PKT_NON_TCP_UDP:
1008 EFSYS_PROBE(tx_pkt_non_tcp_udp);
1011 case FSE_AZ_TIMER_EV: {
1014 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1016 EFSYS_ASSERT(eecp->eec_timer != NULL);
1017 should_abort = eecp->eec_timer(arg, id);
1021 case FSE_AZ_RX_DSC_ERROR_EV:
1022 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1024 EFSYS_PROBE(rx_dsc_error);
1026 EFSYS_ASSERT(eecp->eec_exception != NULL);
1027 should_abort = eecp->eec_exception(arg,
1028 EFX_EXCEPTION_RX_DSC_ERROR, 0);
1032 case FSE_AZ_TX_DSC_ERROR_EV:
1033 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1035 EFSYS_PROBE(tx_dsc_error);
1037 EFSYS_ASSERT(eecp->eec_exception != NULL);
1038 should_abort = eecp->eec_exception(arg,
1039 EFX_EXCEPTION_TX_DSC_ERROR, 0);
1047 return (should_abort);
1050 static __checkReturn boolean_t
1052 __in efx_evq_t *eep,
1053 __in efx_qword_t *eqp,
1054 __in const efx_ev_callbacks_t *eecp,
1058 boolean_t should_abort;
1060 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1062 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1063 if (data >= ((uint32_t)1 << 16)) {
1064 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1065 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1066 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1070 EFSYS_ASSERT(eecp->eec_software != NULL);
1071 should_abort = eecp->eec_software(arg, (uint16_t)data);
1073 return (should_abort);
1078 static __checkReturn boolean_t
1080 __in efx_evq_t *eep,
1081 __in efx_qword_t *eqp,
1082 __in const efx_ev_callbacks_t *eecp,
1085 efx_nic_t *enp = eep->ee_enp;
1087 boolean_t should_abort = B_FALSE;
1089 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1091 if (enp->en_family != EFX_FAMILY_SIENA)
1094 EFSYS_ASSERT(eecp->eec_link_change != NULL);
1095 EFSYS_ASSERT(eecp->eec_exception != NULL);
1096 #if EFSYS_OPT_MON_STATS
1097 EFSYS_ASSERT(eecp->eec_monitor != NULL);
1100 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1102 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1104 case MCDI_EVENT_CODE_BADSSERT:
1105 efx_mcdi_ev_death(enp, EINTR);
1108 case MCDI_EVENT_CODE_CMDDONE:
1109 efx_mcdi_ev_cpl(enp,
1110 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1111 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1112 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1115 case MCDI_EVENT_CODE_LINKCHANGE: {
1116 efx_link_mode_t link_mode;
1118 siena_phy_link_ev(enp, eqp, &link_mode);
1119 should_abort = eecp->eec_link_change(arg, link_mode);
1122 case MCDI_EVENT_CODE_SENSOREVT: {
1123 #if EFSYS_OPT_MON_STATS
1125 efx_mon_stat_value_t value;
1128 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1129 should_abort = eecp->eec_monitor(arg, id, value);
1130 else if (rc == ENOTSUP) {
1131 should_abort = eecp->eec_exception(arg,
1132 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1133 MCDI_EV_FIELD(eqp, DATA));
1135 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1137 should_abort = B_FALSE;
1141 case MCDI_EVENT_CODE_SCHEDERR:
1142 /* Informational only */
1145 case MCDI_EVENT_CODE_REBOOT:
1146 efx_mcdi_ev_death(enp, EIO);
1149 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1150 #if EFSYS_OPT_MAC_STATS
1151 if (eecp->eec_mac_stats != NULL) {
1152 eecp->eec_mac_stats(arg,
1153 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1158 case MCDI_EVENT_CODE_FWALERT: {
1159 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1161 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1162 should_abort = eecp->eec_exception(arg,
1163 EFX_EXCEPTION_FWALERT_SRAM,
1164 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1166 should_abort = eecp->eec_exception(arg,
1167 EFX_EXCEPTION_UNKNOWN_FWALERT,
1168 MCDI_EV_FIELD(eqp, DATA));
1173 EFSYS_PROBE1(mc_pcol_error, int, code);
1178 return (should_abort);
1181 #endif /* EFSYS_OPT_MCDI */
1183 static __checkReturn efx_rc_t
1185 __in efx_evq_t *eep,
1186 __in unsigned int count)
1188 efx_nic_t *enp = eep->ee_enp;
1192 rptr = count & eep->ee_mask;
1194 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1196 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1204 __in efx_evq_t *eep,
1207 efx_nic_t *enp = eep->ee_enp;
1211 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1212 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1214 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1215 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1216 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1218 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1221 static __checkReturn efx_rc_t
1223 __in efx_evq_t *eep,
1224 __in unsigned int us)
1226 efx_nic_t *enp = eep->ee_enp;
1227 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1228 unsigned int locked;
1232 if (us > encp->enc_evq_timer_max_us) {
1237 /* If the value is zero then disable the timer */
1239 EFX_POPULATE_DWORD_2(dword,
1240 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1241 FRF_CZ_TC_TIMER_VAL, 0);
1245 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1248 EFSYS_ASSERT(ticks > 0);
1249 EFX_POPULATE_DWORD_2(dword,
1250 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1251 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1254 locked = (eep->ee_index == 0) ? 1 : 0;
1256 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1257 eep->ee_index, &dword, locked);
1264 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1269 static __checkReturn efx_rc_t
1271 __in efx_nic_t *enp,
1272 __in unsigned int index,
1273 __in efsys_mem_t *esmp,
1277 __in uint32_t flags,
1278 __in efx_evq_t *eep)
1280 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1284 boolean_t notify_mode;
1286 _NOTE(ARGUNUSED(esmp))
1288 EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
1289 EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
1291 if (!ISP2(ndescs) ||
1292 (ndescs < encp->enc_evq_min_nevs) ||
1293 (ndescs > encp->enc_evq_max_nevs)) {
1297 if (index >= encp->enc_evq_limit) {
1301 #if EFSYS_OPT_RX_SCALE
1302 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1303 index >= EFX_MAXRSS_LEGACY) {
1309 (1U << size) <= encp->enc_evq_max_nevs / encp->enc_evq_min_nevs;
1311 if ((1U << size) == (uint32_t)ndescs / encp->enc_evq_min_nevs)
1313 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1318 /* Set up the handler table */
1319 eep->ee_rx = siena_ev_rx;
1320 eep->ee_tx = siena_ev_tx;
1321 eep->ee_driver = siena_ev_driver;
1322 eep->ee_global = siena_ev_global;
1323 eep->ee_drv_gen = siena_ev_drv_gen;
1325 eep->ee_mcdi = siena_ev_mcdi;
1326 #endif /* EFSYS_OPT_MCDI */
1328 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1329 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1331 /* Set up the new event queue */
1332 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1333 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1334 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1335 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1337 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1338 FRF_AZ_EVQ_BUF_BASE_ID, id);
1340 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1342 /* Set initial interrupt moderation */
1343 siena_ev_qmoderate(eep, us);
1349 #if EFSYS_OPT_RX_SCALE
1356 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1361 #endif /* EFSYS_OPT_SIENA */
1363 #if EFSYS_OPT_QSTATS
1365 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1366 static const char * const __efx_ev_qstat_name[] = {
1373 "rx_buf_owner_id_err",
1374 "rx_ipv4_hdr_chksum_err",
1375 "rx_tcp_udp_chksum_err",
1379 "rx_mcast_hash_match",
1396 "driver_srm_upd_done",
1397 "driver_tx_descq_fls_done",
1398 "driver_rx_descq_fls_done",
1399 "driver_rx_descq_fls_failed",
1400 "driver_rx_dsc_error",
1401 "driver_tx_dsc_error",
1405 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1409 __in efx_nic_t *enp,
1410 __in unsigned int id)
1412 _NOTE(ARGUNUSED(enp))
1414 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1415 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1417 return (__efx_ev_qstat_name[id]);
1419 #endif /* EFSYS_OPT_NAMES */
1420 #endif /* EFSYS_OPT_QSTATS */
1424 #if EFSYS_OPT_QSTATS
1426 siena_ev_qstats_update(
1427 __in efx_evq_t *eep,
1428 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1432 for (id = 0; id < EV_NQSTATS; id++) {
1433 efsys_stat_t *essp = &stat[id];
1435 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1436 eep->ee_stat[id] = 0;
1439 #endif /* EFSYS_OPT_QSTATS */
1443 __in efx_evq_t *eep)
1445 efx_nic_t *enp = eep->ee_enp;
1448 /* Purge event queue */
1449 EFX_ZERO_OWORD(oword);
1451 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1452 eep->ee_index, &oword, B_TRUE);
1454 EFX_ZERO_OWORD(oword);
1455 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1460 __in efx_nic_t *enp)
1462 _NOTE(ARGUNUSED(enp))
1465 #endif /* EFSYS_OPT_SIENA */