2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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33 #if EFSYS_OPT_MON_MCDI
38 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
40 (_eep)->ee_stat[_stat]++; \
41 _NOTE(CONSTANTCONDITION) \
44 #define EFX_EV_QSTAT_INCR(_eep, _stat)
47 #define EFX_EV_PRESENT(_qword) \
48 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
49 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
55 static __checkReturn efx_rc_t
63 static __checkReturn efx_rc_t
66 __in unsigned int index,
67 __in efsys_mem_t *esmp,
78 static __checkReturn efx_rc_t
81 __in unsigned int count);
88 static __checkReturn efx_rc_t
91 __in unsigned int us);
95 siena_ev_qstats_update(
97 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
101 #endif /* EFSYS_OPT_SIENA */
104 static const efx_ev_ops_t __efx_ev_siena_ops = {
105 siena_ev_init, /* eevo_init */
106 siena_ev_fini, /* eevo_fini */
107 siena_ev_qcreate, /* eevo_qcreate */
108 siena_ev_qdestroy, /* eevo_qdestroy */
109 siena_ev_qprime, /* eevo_qprime */
110 siena_ev_qpost, /* eevo_qpost */
111 siena_ev_qmoderate, /* eevo_qmoderate */
113 siena_ev_qstats_update, /* eevo_qstats_update */
116 #endif /* EFSYS_OPT_SIENA */
118 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
119 static const efx_ev_ops_t __efx_ev_ef10_ops = {
120 ef10_ev_init, /* eevo_init */
121 ef10_ev_fini, /* eevo_fini */
122 ef10_ev_qcreate, /* eevo_qcreate */
123 ef10_ev_qdestroy, /* eevo_qdestroy */
124 ef10_ev_qprime, /* eevo_qprime */
125 ef10_ev_qpost, /* eevo_qpost */
126 ef10_ev_qmoderate, /* eevo_qmoderate */
128 ef10_ev_qstats_update, /* eevo_qstats_update */
131 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
134 __checkReturn efx_rc_t
138 const efx_ev_ops_t *eevop;
141 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
142 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
144 if (enp->en_mod_flags & EFX_MOD_EV) {
149 switch (enp->en_family) {
151 case EFX_FAMILY_SIENA:
152 eevop = &__efx_ev_siena_ops;
154 #endif /* EFSYS_OPT_SIENA */
156 #if EFSYS_OPT_HUNTINGTON
157 case EFX_FAMILY_HUNTINGTON:
158 eevop = &__efx_ev_ef10_ops;
160 #endif /* EFSYS_OPT_HUNTINGTON */
162 #if EFSYS_OPT_MEDFORD
163 case EFX_FAMILY_MEDFORD:
164 eevop = &__efx_ev_ef10_ops;
166 #endif /* EFSYS_OPT_MEDFORD */
174 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
176 if ((rc = eevop->eevo_init(enp)) != 0)
179 enp->en_eevop = eevop;
180 enp->en_mod_flags |= EFX_MOD_EV;
187 EFSYS_PROBE1(fail1, efx_rc_t, rc);
189 enp->en_eevop = NULL;
190 enp->en_mod_flags &= ~EFX_MOD_EV;
198 const efx_ev_ops_t *eevop = enp->en_eevop;
200 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
201 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
202 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
203 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
204 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
205 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
207 eevop->eevo_fini(enp);
209 enp->en_eevop = NULL;
210 enp->en_mod_flags &= ~EFX_MOD_EV;
214 __checkReturn efx_rc_t
217 __in unsigned int index,
218 __in efsys_mem_t *esmp,
223 __deref_out efx_evq_t **eepp)
225 const efx_ev_ops_t *eevop = enp->en_eevop;
226 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
230 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
231 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
233 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
235 switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
236 case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
238 case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
249 /* Allocate an EVQ object */
250 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
256 eep->ee_magic = EFX_EVQ_MAGIC;
258 eep->ee_index = index;
259 eep->ee_mask = ndescs - 1;
260 eep->ee_flags = flags;
264 * Set outputs before the queue is created because interrupts may be
265 * raised for events immediately after the queue is created, before the
266 * function call below returns. See bug58606.
268 * The eepp pointer passed in by the client must therefore point to data
269 * shared with the client's event processing context.
274 if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
285 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
299 efx_nic_t *enp = eep->ee_enp;
300 const efx_ev_ops_t *eevop = enp->en_eevop;
302 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
304 EFSYS_ASSERT(enp->en_ev_qcount != 0);
307 eevop->eevo_qdestroy(eep);
309 /* Free the EVQ object */
310 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
313 __checkReturn efx_rc_t
316 __in unsigned int count)
318 efx_nic_t *enp = eep->ee_enp;
319 const efx_ev_ops_t *eevop = enp->en_eevop;
322 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
324 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
329 if ((rc = eevop->eevo_qprime(eep, count)) != 0)
337 EFSYS_PROBE1(fail1, efx_rc_t, rc);
341 __checkReturn boolean_t
344 __in unsigned int count)
349 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
351 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
352 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
354 return (EFX_EV_PRESENT(qword));
357 #if EFSYS_OPT_EV_PREFETCH
362 __in unsigned int count)
366 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
368 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
369 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
372 #endif /* EFSYS_OPT_EV_PREFETCH */
374 #define EFX_EV_BATCH 8
379 __inout unsigned int *countp,
380 __in const efx_ev_callbacks_t *eecp,
383 efx_qword_t ev[EFX_EV_BATCH];
390 /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
391 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
392 EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
394 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
395 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
396 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
397 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
398 FSE_AZ_EV_CODE_DRV_GEN_EV);
400 EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
401 FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
404 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
405 EFSYS_ASSERT(countp != NULL);
406 EFSYS_ASSERT(eecp != NULL);
410 /* Read up until the end of the batch period */
411 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
412 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
413 for (total = 0; total < batch; ++total) {
414 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
416 if (!EFX_EV_PRESENT(ev[total]))
419 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
420 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
421 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
423 offset += sizeof (efx_qword_t);
426 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
428 * Prefetch the next batch when we get within PREFETCH_PERIOD
429 * of a completed batch. If the batch is smaller, then prefetch
432 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
433 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
434 #endif /* EFSYS_OPT_EV_PREFETCH */
436 /* Process the batch of events */
437 for (index = 0; index < total; ++index) {
438 boolean_t should_abort;
441 #if EFSYS_OPT_EV_PREFETCH
442 /* Prefetch if we've now reached the batch period */
443 if (total == batch &&
444 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
445 offset = (count + batch) & eep->ee_mask;
446 offset *= sizeof (efx_qword_t);
448 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
450 #endif /* EFSYS_OPT_EV_PREFETCH */
452 EFX_EV_QSTAT_INCR(eep, EV_ALL);
454 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
456 case FSE_AZ_EV_CODE_RX_EV:
457 should_abort = eep->ee_rx(eep,
458 &(ev[index]), eecp, arg);
460 case FSE_AZ_EV_CODE_TX_EV:
461 should_abort = eep->ee_tx(eep,
462 &(ev[index]), eecp, arg);
464 case FSE_AZ_EV_CODE_DRIVER_EV:
465 should_abort = eep->ee_driver(eep,
466 &(ev[index]), eecp, arg);
468 case FSE_AZ_EV_CODE_DRV_GEN_EV:
469 should_abort = eep->ee_drv_gen(eep,
470 &(ev[index]), eecp, arg);
473 case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
474 should_abort = eep->ee_mcdi(eep,
475 &(ev[index]), eecp, arg);
478 case FSE_AZ_EV_CODE_GLOBAL_EV:
479 if (eep->ee_global) {
480 should_abort = eep->ee_global(eep,
481 &(ev[index]), eecp, arg);
484 /* else fallthrough */
486 EFSYS_PROBE3(bad_event,
487 unsigned int, eep->ee_index,
489 EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
491 EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
493 EFSYS_ASSERT(eecp->eec_exception != NULL);
494 (void) eecp->eec_exception(arg,
495 EFX_EXCEPTION_EV_ERROR, code);
496 should_abort = B_TRUE;
499 /* Ignore subsequent events */
506 * Now that the hardware has most likely moved onto dma'ing
507 * into the next cache line, clear the processed events. Take
508 * care to only clear out events that we've processed
510 EFX_SET_QWORD(ev[0]);
511 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
512 for (index = 0; index < total; ++index) {
513 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
514 offset += sizeof (efx_qword_t);
519 } while (total == batch);
529 efx_nic_t *enp = eep->ee_enp;
530 const efx_ev_ops_t *eevop = enp->en_eevop;
532 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
534 EFSYS_ASSERT(eevop != NULL &&
535 eevop->eevo_qpost != NULL);
537 eevop->eevo_qpost(eep, data);
540 __checkReturn efx_rc_t
541 efx_ev_usecs_to_ticks(
543 __in unsigned int us,
544 __out unsigned int *ticksp)
546 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
549 /* Convert microseconds to a timer tick count */
552 else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
553 ticks = 1; /* Never round down to zero */
555 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
561 __checkReturn efx_rc_t
564 __in unsigned int us)
566 efx_nic_t *enp = eep->ee_enp;
567 const efx_ev_ops_t *eevop = enp->en_eevop;
570 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
572 if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
573 EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
578 if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
586 EFSYS_PROBE1(fail1, efx_rc_t, rc);
592 efx_ev_qstats_update(
594 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
596 { efx_nic_t *enp = eep->ee_enp;
597 const efx_ev_ops_t *eevop = enp->en_eevop;
599 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
601 eevop->eevo_qstats_update(eep, stat);
604 #endif /* EFSYS_OPT_QSTATS */
608 static __checkReturn efx_rc_t
615 * Program the event queue for receive and transmit queue
618 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
619 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
620 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
626 static __checkReturn boolean_t
629 __in efx_qword_t *eqp,
632 __inout uint16_t *flagsp)
634 boolean_t ignore = B_FALSE;
636 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
637 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
638 EFSYS_PROBE(tobe_disc);
640 * Assume this is a unicast address mismatch, unless below
641 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
642 * EV_RX_PAUSE_FRM_ERR is set.
644 (*flagsp) |= EFX_ADDR_MISMATCH;
647 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
648 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
649 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
650 (*flagsp) |= EFX_DISCARD;
652 #if EFSYS_OPT_RX_SCATTER
654 * Lookout for payload queue ran dry errors and ignore them.
656 * Sadly for the header/data split cases, the descriptor
657 * pointer in this event refers to the header queue and
658 * therefore cannot be easily detected as duplicate.
659 * So we drop these and rely on the receive processing seeing
660 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
661 * the partially received packet.
663 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
664 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
665 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
667 #endif /* EFSYS_OPT_RX_SCATTER */
670 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
671 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
672 EFSYS_PROBE(crc_err);
673 (*flagsp) &= ~EFX_ADDR_MISMATCH;
674 (*flagsp) |= EFX_DISCARD;
677 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
678 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
679 EFSYS_PROBE(pause_frm_err);
680 (*flagsp) &= ~EFX_ADDR_MISMATCH;
681 (*flagsp) |= EFX_DISCARD;
684 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
685 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
686 EFSYS_PROBE(owner_id_err);
687 (*flagsp) |= EFX_DISCARD;
690 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
691 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
692 EFSYS_PROBE(ipv4_err);
693 (*flagsp) &= ~EFX_CKSUM_IPV4;
696 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
697 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
698 EFSYS_PROBE(udp_chk_err);
699 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
702 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
703 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
706 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
707 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
710 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
716 static __checkReturn boolean_t
719 __in efx_qword_t *eqp,
720 __in const efx_ev_callbacks_t *eecp,
727 #if EFSYS_OPT_RX_SCATTER
729 boolean_t jumbo_cont;
730 #endif /* EFSYS_OPT_RX_SCATTER */
735 boolean_t should_abort;
737 EFX_EV_QSTAT_INCR(eep, EV_RX);
739 /* Basic packet information */
740 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
741 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
742 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
743 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
745 #if EFSYS_OPT_RX_SCATTER
746 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
747 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
748 #endif /* EFSYS_OPT_RX_SCATTER */
750 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
752 is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
755 * If packet is marked as OK and packet type is TCP/IP or
756 * UDP/IP or other IP, then we can rely on the hardware checksums.
759 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
760 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
762 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
763 flags |= EFX_PKT_IPV6;
765 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
766 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
770 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
771 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
773 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
774 flags |= EFX_PKT_IPV6;
776 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
777 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
781 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
783 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
784 flags = EFX_PKT_IPV6;
786 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
787 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
791 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
792 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
797 EFSYS_ASSERT(B_FALSE);
802 #if EFSYS_OPT_RX_SCATTER
803 /* Report scatter and header/lookahead split buffer flags */
805 flags |= EFX_PKT_START;
807 flags |= EFX_PKT_CONT;
808 #endif /* EFSYS_OPT_RX_SCATTER */
810 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
812 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
814 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
815 uint32_t, size, uint16_t, flags);
821 /* If we're not discarding the packet then it is ok */
822 if (~flags & EFX_DISCARD)
823 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
825 /* Detect multicast packets that didn't match the filter */
826 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
827 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
829 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
830 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
832 EFSYS_PROBE(mcast_mismatch);
833 flags |= EFX_ADDR_MISMATCH;
836 flags |= EFX_PKT_UNICAST;
840 * The packet parser in Siena can abort parsing packets under
841 * certain error conditions, setting the PKT_NOT_PARSED bit
842 * (which clears PKT_OK). If this is set, then don't trust
843 * the PKT_TYPE field.
848 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
850 flags |= EFX_CHECK_VLAN;
853 if (~flags & EFX_CHECK_VLAN) {
856 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
857 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
858 flags |= EFX_PKT_VLAN_TAGGED;
861 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
862 uint32_t, size, uint16_t, flags);
864 EFSYS_ASSERT(eecp->eec_rx != NULL);
865 should_abort = eecp->eec_rx(arg, label, id, size, flags);
867 return (should_abort);
870 static __checkReturn boolean_t
873 __in efx_qword_t *eqp,
874 __in const efx_ev_callbacks_t *eecp,
879 boolean_t should_abort;
881 EFX_EV_QSTAT_INCR(eep, EV_TX);
883 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
884 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
885 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
886 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
888 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
889 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
891 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
893 EFSYS_ASSERT(eecp->eec_tx != NULL);
894 should_abort = eecp->eec_tx(arg, label, id);
896 return (should_abort);
899 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
900 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
901 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
902 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
904 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
905 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
907 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
908 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
910 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
911 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
913 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
917 static __checkReturn boolean_t
920 __in efx_qword_t *eqp,
921 __in const efx_ev_callbacks_t *eecp,
924 _NOTE(ARGUNUSED(eqp, eecp, arg))
926 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
931 static __checkReturn boolean_t
934 __in efx_qword_t *eqp,
935 __in const efx_ev_callbacks_t *eecp,
938 boolean_t should_abort;
940 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
941 should_abort = B_FALSE;
943 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
944 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
947 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
949 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
951 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
953 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
954 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
958 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
962 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
963 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
965 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
966 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
969 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
971 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
973 should_abort = eecp->eec_rxq_flush_failed(arg,
976 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
978 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
980 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
985 case FSE_AZ_EVQ_INIT_DONE_EV:
986 EFSYS_ASSERT(eecp->eec_initialized != NULL);
987 should_abort = eecp->eec_initialized(arg);
991 case FSE_AZ_EVQ_NOT_EN_EV:
992 EFSYS_PROBE(evq_not_en);
995 case FSE_AZ_SRM_UPD_DONE_EV: {
998 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
1000 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1002 EFSYS_ASSERT(eecp->eec_sram != NULL);
1003 should_abort = eecp->eec_sram(arg, code);
1007 case FSE_AZ_WAKE_UP_EV: {
1010 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1012 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1013 should_abort = eecp->eec_wake_up(arg, id);
1017 case FSE_AZ_TX_PKT_NON_TCP_UDP:
1018 EFSYS_PROBE(tx_pkt_non_tcp_udp);
1021 case FSE_AZ_TIMER_EV: {
1024 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1026 EFSYS_ASSERT(eecp->eec_timer != NULL);
1027 should_abort = eecp->eec_timer(arg, id);
1031 case FSE_AZ_RX_DSC_ERROR_EV:
1032 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1034 EFSYS_PROBE(rx_dsc_error);
1036 EFSYS_ASSERT(eecp->eec_exception != NULL);
1037 should_abort = eecp->eec_exception(arg,
1038 EFX_EXCEPTION_RX_DSC_ERROR, 0);
1042 case FSE_AZ_TX_DSC_ERROR_EV:
1043 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1045 EFSYS_PROBE(tx_dsc_error);
1047 EFSYS_ASSERT(eecp->eec_exception != NULL);
1048 should_abort = eecp->eec_exception(arg,
1049 EFX_EXCEPTION_TX_DSC_ERROR, 0);
1057 return (should_abort);
1060 static __checkReturn boolean_t
1062 __in efx_evq_t *eep,
1063 __in efx_qword_t *eqp,
1064 __in const efx_ev_callbacks_t *eecp,
1068 boolean_t should_abort;
1070 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1072 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1073 if (data >= ((uint32_t)1 << 16)) {
1074 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1075 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1076 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1080 EFSYS_ASSERT(eecp->eec_software != NULL);
1081 should_abort = eecp->eec_software(arg, (uint16_t)data);
1083 return (should_abort);
1088 static __checkReturn boolean_t
1090 __in efx_evq_t *eep,
1091 __in efx_qword_t *eqp,
1092 __in const efx_ev_callbacks_t *eecp,
1095 efx_nic_t *enp = eep->ee_enp;
1097 boolean_t should_abort = B_FALSE;
1099 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1101 if (enp->en_family != EFX_FAMILY_SIENA)
1104 EFSYS_ASSERT(eecp->eec_link_change != NULL);
1105 EFSYS_ASSERT(eecp->eec_exception != NULL);
1106 #if EFSYS_OPT_MON_STATS
1107 EFSYS_ASSERT(eecp->eec_monitor != NULL);
1110 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1112 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1114 case MCDI_EVENT_CODE_BADSSERT:
1115 efx_mcdi_ev_death(enp, EINTR);
1118 case MCDI_EVENT_CODE_CMDDONE:
1119 efx_mcdi_ev_cpl(enp,
1120 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1121 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1122 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1125 case MCDI_EVENT_CODE_LINKCHANGE: {
1126 efx_link_mode_t link_mode;
1128 siena_phy_link_ev(enp, eqp, &link_mode);
1129 should_abort = eecp->eec_link_change(arg, link_mode);
1132 case MCDI_EVENT_CODE_SENSOREVT: {
1133 #if EFSYS_OPT_MON_STATS
1135 efx_mon_stat_value_t value;
1138 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1139 should_abort = eecp->eec_monitor(arg, id, value);
1140 else if (rc == ENOTSUP) {
1141 should_abort = eecp->eec_exception(arg,
1142 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1143 MCDI_EV_FIELD(eqp, DATA));
1145 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
1147 should_abort = B_FALSE;
1151 case MCDI_EVENT_CODE_SCHEDERR:
1152 /* Informational only */
1155 case MCDI_EVENT_CODE_REBOOT:
1156 efx_mcdi_ev_death(enp, EIO);
1159 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1160 #if EFSYS_OPT_MAC_STATS
1161 if (eecp->eec_mac_stats != NULL) {
1162 eecp->eec_mac_stats(arg,
1163 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1168 case MCDI_EVENT_CODE_FWALERT: {
1169 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1171 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1172 should_abort = eecp->eec_exception(arg,
1173 EFX_EXCEPTION_FWALERT_SRAM,
1174 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1176 should_abort = eecp->eec_exception(arg,
1177 EFX_EXCEPTION_UNKNOWN_FWALERT,
1178 MCDI_EV_FIELD(eqp, DATA));
1183 EFSYS_PROBE1(mc_pcol_error, int, code);
1188 return (should_abort);
1191 #endif /* EFSYS_OPT_MCDI */
1193 static __checkReturn efx_rc_t
1195 __in efx_evq_t *eep,
1196 __in unsigned int count)
1198 efx_nic_t *enp = eep->ee_enp;
1202 rptr = count & eep->ee_mask;
1204 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1206 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1214 __in efx_evq_t *eep,
1217 efx_nic_t *enp = eep->ee_enp;
1221 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1222 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1224 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1225 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1226 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1228 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1231 static __checkReturn efx_rc_t
1233 __in efx_evq_t *eep,
1234 __in unsigned int us)
1236 efx_nic_t *enp = eep->ee_enp;
1237 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1238 unsigned int locked;
1242 if (us > encp->enc_evq_timer_max_us) {
1247 /* If the value is zero then disable the timer */
1249 EFX_POPULATE_DWORD_2(dword,
1250 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1251 FRF_CZ_TC_TIMER_VAL, 0);
1255 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1258 EFSYS_ASSERT(ticks > 0);
1259 EFX_POPULATE_DWORD_2(dword,
1260 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1261 FRF_CZ_TC_TIMER_VAL, ticks - 1);
1264 locked = (eep->ee_index == 0) ? 1 : 0;
1266 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1267 eep->ee_index, &dword, locked);
1274 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1279 static __checkReturn efx_rc_t
1281 __in efx_nic_t *enp,
1282 __in unsigned int index,
1283 __in efsys_mem_t *esmp,
1287 __in uint32_t flags,
1288 __in efx_evq_t *eep)
1290 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1294 boolean_t notify_mode;
1296 _NOTE(ARGUNUSED(esmp))
1298 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1299 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1301 if (!ISP2(ndescs) ||
1302 (ndescs < EFX_EVQ_MINNEVS) || (ndescs > EFX_EVQ_MAXNEVS)) {
1306 if (index >= encp->enc_evq_limit) {
1310 #if EFSYS_OPT_RX_SCALE
1311 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1312 index >= EFX_MAXRSS_LEGACY) {
1317 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1319 if ((1 << size) == (int)(ndescs / EFX_EVQ_MINNEVS))
1321 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1326 /* Set up the handler table */
1327 eep->ee_rx = siena_ev_rx;
1328 eep->ee_tx = siena_ev_tx;
1329 eep->ee_driver = siena_ev_driver;
1330 eep->ee_global = siena_ev_global;
1331 eep->ee_drv_gen = siena_ev_drv_gen;
1333 eep->ee_mcdi = siena_ev_mcdi;
1334 #endif /* EFSYS_OPT_MCDI */
1336 notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1337 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1339 /* Set up the new event queue */
1340 EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1341 FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1342 FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1343 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1345 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1346 FRF_AZ_EVQ_BUF_BASE_ID, id);
1348 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1350 /* Set initial interrupt moderation */
1351 siena_ev_qmoderate(eep, us);
1357 #if EFSYS_OPT_RX_SCALE
1364 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1369 #endif /* EFSYS_OPT_SIENA */
1371 #if EFSYS_OPT_QSTATS
1373 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1374 static const char * const __efx_ev_qstat_name[] = {
1381 "rx_buf_owner_id_err",
1382 "rx_ipv4_hdr_chksum_err",
1383 "rx_tcp_udp_chksum_err",
1387 "rx_mcast_hash_match",
1404 "driver_srm_upd_done",
1405 "driver_tx_descq_fls_done",
1406 "driver_rx_descq_fls_done",
1407 "driver_rx_descq_fls_failed",
1408 "driver_rx_dsc_error",
1409 "driver_tx_dsc_error",
1413 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1417 __in efx_nic_t *enp,
1418 __in unsigned int id)
1420 _NOTE(ARGUNUSED(enp))
1422 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1423 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1425 return (__efx_ev_qstat_name[id]);
1427 #endif /* EFSYS_OPT_NAMES */
1428 #endif /* EFSYS_OPT_QSTATS */
1432 #if EFSYS_OPT_QSTATS
1434 siena_ev_qstats_update(
1435 __in efx_evq_t *eep,
1436 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1440 for (id = 0; id < EV_NQSTATS; id++) {
1441 efsys_stat_t *essp = &stat[id];
1443 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1444 eep->ee_stat[id] = 0;
1447 #endif /* EFSYS_OPT_QSTATS */
1451 __in efx_evq_t *eep)
1453 efx_nic_t *enp = eep->ee_enp;
1456 /* Purge event queue */
1457 EFX_ZERO_OWORD(oword);
1459 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1460 eep->ee_index, &oword, B_TRUE);
1462 EFX_ZERO_OWORD(oword);
1463 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1468 __in efx_nic_t *enp)
1470 _NOTE(ARGUNUSED(enp))
1473 #endif /* EFSYS_OPT_SIENA */