drivers/net/sfc/base/efx_ev.c

   1 /*
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include "efx.h"
  32 #include "efx_impl.h"
  33
  34 #if EFSYS_OPT_QSTATS
  35 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
  36         do {                                                            \
  37                 (_eep)->ee_stat[_stat]++;                               \
  38         _NOTE(CONSTANTCONDITION)                                        \
  39         } while (B_FALSE)
  40 #else
  41 #define EFX_EV_QSTAT_INCR(_eep, _stat)
  42 #endif
  43
  44 #define EFX_EV_PRESENT(_qword)                                          \
  45         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  46         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  47
  48
  49
  50 #if EFSYS_OPT_SIENA
  51
  52 static  __checkReturn   efx_rc_t
  53 siena_ev_init(
  54         __in            efx_nic_t *enp);
  55
  56 static                  void
  57 siena_ev_fini(
  58         __in            efx_nic_t *enp);
  59
  60 static  __checkReturn   efx_rc_t
  61 siena_ev_qcreate(
  62         __in            efx_nic_t *enp,
  63         __in            unsigned int index,
  64         __in            efsys_mem_t *esmp,
  65         __in            size_t n,
  66         __in            uint32_t id,
  67         __in            uint32_t us,
  68         __in            uint32_t flags,
  69         __in            efx_evq_t *eep);
  70
  71 static                  void
  72 siena_ev_qdestroy(
  73         __in            efx_evq_t *eep);
  74
  75 static  __checkReturn   efx_rc_t
  76 siena_ev_qprime(
  77         __in            efx_evq_t *eep,
  78         __in            unsigned int count);
  79
  80 static                  void
  81 siena_ev_qpost(
  82         __in    efx_evq_t *eep,
  83         __in    uint16_t data);
  84
  85 static  __checkReturn   efx_rc_t
  86 siena_ev_qmoderate(
  87         __in            efx_evq_t *eep,
  88         __in            unsigned int us);
  89
  90 #if EFSYS_OPT_QSTATS
  91 static                  void
  92 siena_ev_qstats_update(
  93         __in                            efx_evq_t *eep,
  94         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
  95
  96 #endif
  97
  98 #endif /* EFSYS_OPT_SIENA */
  99
 100 #if EFSYS_OPT_SIENA
 101 static const efx_ev_ops_t       __efx_ev_siena_ops = {
 102         siena_ev_init,                          /* eevo_init */
 103         siena_ev_fini,                          /* eevo_fini */
 104         siena_ev_qcreate,                       /* eevo_qcreate */
 105         siena_ev_qdestroy,                      /* eevo_qdestroy */
 106         siena_ev_qprime,                        /* eevo_qprime */
 107         siena_ev_qpost,                         /* eevo_qpost */
 108         siena_ev_qmoderate,                     /* eevo_qmoderate */
 109 #if EFSYS_OPT_QSTATS
 110         siena_ev_qstats_update,                 /* eevo_qstats_update */
 111 #endif
 112 };
 113 #endif /* EFSYS_OPT_SIENA */
 114
 115 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 116 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
 117         ef10_ev_init,                           /* eevo_init */
 118         ef10_ev_fini,                           /* eevo_fini */
 119         ef10_ev_qcreate,                        /* eevo_qcreate */
 120         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 121         ef10_ev_qprime,                         /* eevo_qprime */
 122         ef10_ev_qpost,                          /* eevo_qpost */
 123         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 124 #if EFSYS_OPT_QSTATS
 125         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 126 #endif
 127 };
 128 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 129
 130
 131         __checkReturn   efx_rc_t
 132 efx_ev_init(
 133         __in            efx_nic_t *enp)
 134 {
 135         const efx_ev_ops_t *eevop;
 136         efx_rc_t rc;
 137
 138         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 139         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 140
 141         if (enp->en_mod_flags & EFX_MOD_EV) {
 142                 rc = EINVAL;
 143                 goto fail1;
 144         }
 145
 146         switch (enp->en_family) {
 147 #if EFSYS_OPT_SIENA
 148         case EFX_FAMILY_SIENA:
 149                 eevop = &__efx_ev_siena_ops;
 150                 break;
 151 #endif /* EFSYS_OPT_SIENA */
 152
 153 #if EFSYS_OPT_HUNTINGTON
 154         case EFX_FAMILY_HUNTINGTON:
 155                 eevop = &__efx_ev_ef10_ops;
 156                 break;
 157 #endif /* EFSYS_OPT_HUNTINGTON */
 158
 159 #if EFSYS_OPT_MEDFORD
 160         case EFX_FAMILY_MEDFORD:
 161                 eevop = &__efx_ev_ef10_ops;
 162                 break;
 163 #endif /* EFSYS_OPT_MEDFORD */
 164
 165         default:
 166                 EFSYS_ASSERT(0);
 167                 rc = ENOTSUP;
 168                 goto fail1;
 169         }
 170
 171         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 172
 173         if ((rc = eevop->eevo_init(enp)) != 0)
 174                 goto fail2;
 175
 176         enp->en_eevop = eevop;
 177         enp->en_mod_flags |= EFX_MOD_EV;
 178         return (0);
 179
 180 fail2:
 181         EFSYS_PROBE(fail2);
 182
 183 fail1:
 184         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 185
 186         enp->en_eevop = NULL;
 187         enp->en_mod_flags &= ~EFX_MOD_EV;
 188         return (rc);
 189 }
 190
 191                 void
 192 efx_ev_fini(
 193         __in    efx_nic_t *enp)
 194 {
 195         const efx_ev_ops_t *eevop = enp->en_eevop;
 196
 197         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 198         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 199         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 200         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 201         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 202         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 203
 204         eevop->eevo_fini(enp);
 205
 206         enp->en_eevop = NULL;
 207         enp->en_mod_flags &= ~EFX_MOD_EV;
 208 }
 209
 210
 211         __checkReturn   efx_rc_t
 212 efx_ev_qcreate(
 213         __in            efx_nic_t *enp,
 214         __in            unsigned int index,
 215         __in            efsys_mem_t *esmp,
 216         __in            size_t n,
 217         __in            uint32_t id,
 218         __in            uint32_t us,
 219         __in            uint32_t flags,
 220         __deref_out     efx_evq_t **eepp)
 221 {
 222         const efx_ev_ops_t *eevop = enp->en_eevop;
 223         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 224         efx_evq_t *eep;
 225         efx_rc_t rc;
 226
 227         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 228         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 229
 230         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
 231
 232         switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
 233         case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
 234                 break;
 235         case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
 236                 if (us != 0) {
 237                         rc = EINVAL;
 238                         goto fail1;
 239                 }
 240                 break;
 241         default:
 242                 rc = EINVAL;
 243                 goto fail2;
 244         }
 245
 246         /* Allocate an EVQ object */
 247         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 248         if (eep == NULL) {
 249                 rc = ENOMEM;
 250                 goto fail3;
 251         }
 252
 253         eep->ee_magic = EFX_EVQ_MAGIC;
 254         eep->ee_enp = enp;
 255         eep->ee_index = index;
 256         eep->ee_mask = n - 1;
 257         eep->ee_flags = flags;
 258         eep->ee_esmp = esmp;
 259
 260         /*
 261          * Set outputs before the queue is created because interrupts may be
 262          * raised for events immediately after the queue is created, before the
 263          * function call below returns. See bug58606.
 264          *
 265          * The eepp pointer passed in by the client must therefore point to data
 266          * shared with the client's event processing context.
 267          */
 268         enp->en_ev_qcount++;
 269         *eepp = eep;
 270
 271         if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, flags,
 272             eep)) != 0)
 273                 goto fail4;
 274
 275         return (0);
 276
 277 fail4:
 278         EFSYS_PROBE(fail4);
 279
 280         *eepp = NULL;
 281         enp->en_ev_qcount--;
 282         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 283 fail3:
 284         EFSYS_PROBE(fail3);
 285 fail2:
 286         EFSYS_PROBE(fail2);
 287 fail1:
 288         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 289         return (rc);
 290 }
 291
 292                 void
 293 efx_ev_qdestroy(
 294         __in    efx_evq_t *eep)
 295 {
 296         efx_nic_t *enp = eep->ee_enp;
 297         const efx_ev_ops_t *eevop = enp->en_eevop;
 298
 299         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 300
 301         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 302         --enp->en_ev_qcount;
 303
 304         eevop->eevo_qdestroy(eep);
 305
 306         /* Free the EVQ object */
 307         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 308 }
 309
 310         __checkReturn   efx_rc_t
 311 efx_ev_qprime(
 312         __in            efx_evq_t *eep,
 313         __in            unsigned int count)
 314 {
 315         efx_nic_t *enp = eep->ee_enp;
 316         const efx_ev_ops_t *eevop = enp->en_eevop;
 317         efx_rc_t rc;
 318
 319         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 320
 321         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 322                 rc = EINVAL;
 323                 goto fail1;
 324         }
 325
 326         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 327                 goto fail2;
 328
 329         return (0);
 330
 331 fail2:
 332         EFSYS_PROBE(fail2);
 333 fail1:
 334         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 335         return (rc);
 336 }
 337
 338         __checkReturn   boolean_t
 339 efx_ev_qpending(
 340         __in            efx_evq_t *eep,
 341         __in            unsigned int count)
 342 {
 343         size_t offset;
 344         efx_qword_t qword;
 345
 346         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 347
 348         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 349         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 350
 351         return (EFX_EV_PRESENT(qword));
 352 }
 353
 354 #if EFSYS_OPT_EV_PREFETCH
 355
 356                         void
 357 efx_ev_qprefetch(
 358         __in            efx_evq_t *eep,
 359         __in            unsigned int count)
 360 {
 361         unsigned int offset;
 362
 363         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 364
 365         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 366         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 367 }
 368
 369 #endif  /* EFSYS_OPT_EV_PREFETCH */
 370
 371 #define EFX_EV_BATCH    8
 372
 373                         void
 374 efx_ev_qpoll(
 375         __in            efx_evq_t *eep,
 376         __inout         unsigned int *countp,
 377         __in            const efx_ev_callbacks_t *eecp,
 378         __in_opt        void *arg)
 379 {
 380         efx_qword_t ev[EFX_EV_BATCH];
 381         unsigned int batch;
 382         unsigned int total;
 383         unsigned int count;
 384         unsigned int index;
 385         size_t offset;
 386
 387         /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
 388         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
 389         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
 390
 391         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
 392         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
 393         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
 394         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
 395             FSE_AZ_EV_CODE_DRV_GEN_EV);
 396 #if EFSYS_OPT_MCDI
 397         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
 398             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
 399 #endif
 400
 401         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 402         EFSYS_ASSERT(countp != NULL);
 403         EFSYS_ASSERT(eecp != NULL);
 404
 405         count = *countp;
 406         do {
 407                 /* Read up until the end of the batch period */
 408                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
 409                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 410                 for (total = 0; total < batch; ++total) {
 411                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
 412
 413                         if (!EFX_EV_PRESENT(ev[total]))
 414                                 break;
 415
 416                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
 417                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
 418                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
 419
 420                         offset += sizeof (efx_qword_t);
 421                 }
 422
 423 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
 424                 /*
 425                  * Prefetch the next batch when we get within PREFETCH_PERIOD
 426                  * of a completed batch. If the batch is smaller, then prefetch
 427                  * immediately.
 428                  */
 429                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
 430                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 431 #endif  /* EFSYS_OPT_EV_PREFETCH */
 432
 433                 /* Process the batch of events */
 434                 for (index = 0; index < total; ++index) {
 435                         boolean_t should_abort;
 436                         uint32_t code;
 437
 438 #if EFSYS_OPT_EV_PREFETCH
 439                         /* Prefetch if we've now reached the batch period */
 440                         if (total == batch &&
 441                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
 442                                 offset = (count + batch) & eep->ee_mask;
 443                                 offset *= sizeof (efx_qword_t);
 444
 445                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 446                         }
 447 #endif  /* EFSYS_OPT_EV_PREFETCH */
 448
 449                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
 450
 451                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
 452                         switch (code) {
 453                         case FSE_AZ_EV_CODE_RX_EV:
 454                                 should_abort = eep->ee_rx(eep,
 455                                     &(ev[index]), eecp, arg);
 456                                 break;
 457                         case FSE_AZ_EV_CODE_TX_EV:
 458                                 should_abort = eep->ee_tx(eep,
 459                                     &(ev[index]), eecp, arg);
 460                                 break;
 461                         case FSE_AZ_EV_CODE_DRIVER_EV:
 462                                 should_abort = eep->ee_driver(eep,
 463                                     &(ev[index]), eecp, arg);
 464                                 break;
 465                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
 466                                 should_abort = eep->ee_drv_gen(eep,
 467                                     &(ev[index]), eecp, arg);
 468                                 break;
 469 #if EFSYS_OPT_MCDI
 470                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
 471                                 should_abort = eep->ee_mcdi(eep,
 472                                     &(ev[index]), eecp, arg);
 473                                 break;
 474 #endif
 475                         case FSE_AZ_EV_CODE_GLOBAL_EV:
 476                                 if (eep->ee_global) {
 477                                         should_abort = eep->ee_global(eep,
 478                                             &(ev[index]), eecp, arg);
 479                                         break;
 480                                 }
 481                                 /* else fallthrough */
 482                         default:
 483                                 EFSYS_PROBE3(bad_event,
 484                                     unsigned int, eep->ee_index,
 485                                     uint32_t,
 486                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
 487                                     uint32_t,
 488                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
 489
 490                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 491                                 (void) eecp->eec_exception(arg,
 492                                         EFX_EXCEPTION_EV_ERROR, code);
 493                                 should_abort = B_TRUE;
 494                         }
 495                         if (should_abort) {
 496                                 /* Ignore subsequent events */
 497                                 total = index + 1;
 498                                 break;
 499                         }
 500                 }
 501
 502                 /*
 503                  * Now that the hardware has most likely moved onto dma'ing
 504                  * into the next cache line, clear the processed events. Take
 505                  * care to only clear out events that we've processed
 506                  */
 507                 EFX_SET_QWORD(ev[0]);
 508                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 509                 for (index = 0; index < total; ++index) {
 510                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
 511                         offset += sizeof (efx_qword_t);
 512                 }
 513
 514                 count += total;
 515
 516         } while (total == batch);
 517
 518         *countp = count;
 519 }
 520
 521                         void
 522 efx_ev_qpost(
 523         __in    efx_evq_t *eep,
 524         __in    uint16_t data)
 525 {
 526         efx_nic_t *enp = eep->ee_enp;
 527         const efx_ev_ops_t *eevop = enp->en_eevop;
 528
 529         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 530
 531         EFSYS_ASSERT(eevop != NULL &&
 532             eevop->eevo_qpost != NULL);
 533
 534         eevop->eevo_qpost(eep, data);
 535 }
 536
 537         __checkReturn   efx_rc_t
 538 efx_ev_usecs_to_ticks(
 539         __in            efx_nic_t *enp,
 540         __in            unsigned int us,
 541         __out           unsigned int *ticksp)
 542 {
 543         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 544         unsigned int ticks;
 545
 546         /* Convert microseconds to a timer tick count */
 547         if (us == 0)
 548                 ticks = 0;
 549         else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
 550                 ticks = 1;      /* Never round down to zero */
 551         else
 552                 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
 553
 554         *ticksp = ticks;
 555         return (0);
 556 }
 557
 558         __checkReturn   efx_rc_t
 559 efx_ev_qmoderate(
 560         __in            efx_evq_t *eep,
 561         __in            unsigned int us)
 562 {
 563         efx_nic_t *enp = eep->ee_enp;
 564         const efx_ev_ops_t *eevop = enp->en_eevop;
 565         efx_rc_t rc;
 566
 567         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 568
 569         if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
 570             EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
 571                 rc = EINVAL;
 572                 goto fail1;
 573         }
 574
 575         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 576                 goto fail2;
 577
 578         return (0);
 579
 580 fail2:
 581         EFSYS_PROBE(fail2);
 582 fail1:
 583         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 584         return (rc);
 585 }
 586
 587 #if EFSYS_OPT_QSTATS
 588                                         void
 589 efx_ev_qstats_update(
 590         __in                            efx_evq_t *eep,
 591         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 592
 593 {       efx_nic_t *enp = eep->ee_enp;
 594         const efx_ev_ops_t *eevop = enp->en_eevop;
 595
 596         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 597
 598         eevop->eevo_qstats_update(eep, stat);
 599 }
 600
 601 #endif  /* EFSYS_OPT_QSTATS */
 602
 603 #if EFSYS_OPT_SIENA
 604
 605 static  __checkReturn   efx_rc_t
 606 siena_ev_init(
 607         __in            efx_nic_t *enp)
 608 {
 609         efx_oword_t oword;
 610
 611         /*
 612          * Program the event queue for receive and transmit queue
 613          * flush events.
 614          */
 615         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 616         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 617         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 618
 619         return (0);
 620
 621 }
 622
 623 static  __checkReturn   boolean_t
 624 siena_ev_rx_not_ok(
 625         __in            efx_evq_t *eep,
 626         __in            efx_qword_t *eqp,
 627         __in            uint32_t label,
 628         __in            uint32_t id,
 629         __inout         uint16_t *flagsp)
 630 {
 631         boolean_t ignore = B_FALSE;
 632
 633         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 634                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 635                 EFSYS_PROBE(tobe_disc);
 636                 /*
 637                  * Assume this is a unicast address mismatch, unless below
 638                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 639                  * EV_RX_PAUSE_FRM_ERR is set.
 640                  */
 641                 (*flagsp) |= EFX_ADDR_MISMATCH;
 642         }
 643
 644         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 645                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 646                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 647                 (*flagsp) |= EFX_DISCARD;
 648
 649         }
 650
 651         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 652                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 653                 EFSYS_PROBE(crc_err);
 654                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 655                 (*flagsp) |= EFX_DISCARD;
 656         }
 657
 658         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 659                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 660                 EFSYS_PROBE(pause_frm_err);
 661                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 662                 (*flagsp) |= EFX_DISCARD;
 663         }
 664
 665         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 666                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 667                 EFSYS_PROBE(owner_id_err);
 668                 (*flagsp) |= EFX_DISCARD;
 669         }
 670
 671         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 672                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 673                 EFSYS_PROBE(ipv4_err);
 674                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 675         }
 676
 677         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 678                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 679                 EFSYS_PROBE(udp_chk_err);
 680                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 681         }
 682
 683         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 684                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 685
 686                 /*
 687                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 688                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 689                  * condition.
 690                  */
 691                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 692         }
 693
 694         return (ignore);
 695 }
 696
 697 static  __checkReturn   boolean_t
 698 siena_ev_rx(
 699         __in            efx_evq_t *eep,
 700         __in            efx_qword_t *eqp,
 701         __in            const efx_ev_callbacks_t *eecp,
 702         __in_opt        void *arg)
 703 {
 704         uint32_t id;
 705         uint32_t size;
 706         uint32_t label;
 707         boolean_t ok;
 708         uint32_t hdr_type;
 709         boolean_t is_v6;
 710         uint16_t flags;
 711         boolean_t ignore;
 712         boolean_t should_abort;
 713
 714         EFX_EV_QSTAT_INCR(eep, EV_RX);
 715
 716         /* Basic packet information */
 717         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 718         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 719         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 720         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 721
 722         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 723
 724         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 725
 726         /*
 727          * If packet is marked as OK and packet type is TCP/IP or
 728          * UDP/IP or other IP, then we can rely on the hardware checksums.
 729          */
 730         switch (hdr_type) {
 731         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 732                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 733                 if (is_v6) {
 734                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 735                         flags |= EFX_PKT_IPV6;
 736                 } else {
 737                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 738                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 739                 }
 740                 break;
 741
 742         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 743                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 744                 if (is_v6) {
 745                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 746                         flags |= EFX_PKT_IPV6;
 747                 } else {
 748                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 749                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 750                 }
 751                 break;
 752
 753         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 754                 if (is_v6) {
 755                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 756                         flags = EFX_PKT_IPV6;
 757                 } else {
 758                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 759                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 760                 }
 761                 break;
 762
 763         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 764                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 765                 flags = 0;
 766                 break;
 767
 768         default:
 769                 EFSYS_ASSERT(B_FALSE);
 770                 flags = 0;
 771                 break;
 772         }
 773
 774         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 775         if (!ok) {
 776                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 777                 if (ignore) {
 778                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 779                             uint32_t, size, uint16_t, flags);
 780
 781                         return (B_FALSE);
 782                 }
 783         }
 784
 785         /* If we're not discarding the packet then it is ok */
 786         if (~flags & EFX_DISCARD)
 787                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 788
 789         /* Detect multicast packets that didn't match the filter */
 790         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 791                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 792
 793                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 794                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 795                 } else {
 796                         EFSYS_PROBE(mcast_mismatch);
 797                         flags |= EFX_ADDR_MISMATCH;
 798                 }
 799         } else {
 800                 flags |= EFX_PKT_UNICAST;
 801         }
 802
 803         /*
 804          * The packet parser in Siena can abort parsing packets under
 805          * certain error conditions, setting the PKT_NOT_PARSED bit
 806          * (which clears PKT_OK). If this is set, then don't trust
 807          * the PKT_TYPE field.
 808          */
 809         if (!ok) {
 810                 uint32_t parse_err;
 811
 812                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 813                 if (parse_err != 0)
 814                         flags |= EFX_CHECK_VLAN;
 815         }
 816
 817         if (~flags & EFX_CHECK_VLAN) {
 818                 uint32_t pkt_type;
 819
 820                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 821                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 822                         flags |= EFX_PKT_VLAN_TAGGED;
 823         }
 824
 825         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 826             uint32_t, size, uint16_t, flags);
 827
 828         EFSYS_ASSERT(eecp->eec_rx != NULL);
 829         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 830
 831         return (should_abort);
 832 }
 833
 834 static  __checkReturn   boolean_t
 835 siena_ev_tx(
 836         __in            efx_evq_t *eep,
 837         __in            efx_qword_t *eqp,
 838         __in            const efx_ev_callbacks_t *eecp,
 839         __in_opt        void *arg)
 840 {
 841         uint32_t id;
 842         uint32_t label;
 843         boolean_t should_abort;
 844
 845         EFX_EV_QSTAT_INCR(eep, EV_TX);
 846
 847         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 848             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 849             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 850             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 851
 852                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 853                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 854
 855                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 856
 857                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 858                 should_abort = eecp->eec_tx(arg, label, id);
 859
 860                 return (should_abort);
 861         }
 862
 863         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 864                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 865                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 866                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 867
 868         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 869                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 870
 871         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 872                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 873
 874         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 875                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 876
 877         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 878         return (B_FALSE);
 879 }
 880
 881 static  __checkReturn   boolean_t
 882 siena_ev_global(
 883         __in            efx_evq_t *eep,
 884         __in            efx_qword_t *eqp,
 885         __in            const efx_ev_callbacks_t *eecp,
 886         __in_opt        void *arg)
 887 {
 888         _NOTE(ARGUNUSED(eqp, eecp, arg))
 889
 890         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 891
 892         return (B_FALSE);
 893 }
 894
 895 static  __checkReturn   boolean_t
 896 siena_ev_driver(
 897         __in            efx_evq_t *eep,
 898         __in            efx_qword_t *eqp,
 899         __in            const efx_ev_callbacks_t *eecp,
 900         __in_opt        void *arg)
 901 {
 902         boolean_t should_abort;
 903
 904         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 905         should_abort = B_FALSE;
 906
 907         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 908         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 909                 uint32_t txq_index;
 910
 911                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 912
 913                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 914
 915                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 916
 917                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 918                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 919
 920                 break;
 921         }
 922         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 923                 uint32_t rxq_index;
 924                 uint32_t failed;
 925
 926                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 927                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 928
 929                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 930                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 931
 932                 if (failed) {
 933                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 934
 935                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 936
 937                         should_abort = eecp->eec_rxq_flush_failed(arg,
 938                                                                     rxq_index);
 939                 } else {
 940                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 941
 942                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 943
 944                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
 945                 }
 946
 947                 break;
 948         }
 949         case FSE_AZ_EVQ_INIT_DONE_EV:
 950                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
 951                 should_abort = eecp->eec_initialized(arg);
 952
 953                 break;
 954
 955         case FSE_AZ_EVQ_NOT_EN_EV:
 956                 EFSYS_PROBE(evq_not_en);
 957                 break;
 958
 959         case FSE_AZ_SRM_UPD_DONE_EV: {
 960                 uint32_t code;
 961
 962                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
 963
 964                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 965
 966                 EFSYS_ASSERT(eecp->eec_sram != NULL);
 967                 should_abort = eecp->eec_sram(arg, code);
 968
 969                 break;
 970         }
 971         case FSE_AZ_WAKE_UP_EV: {
 972                 uint32_t id;
 973
 974                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 975
 976                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
 977                 should_abort = eecp->eec_wake_up(arg, id);
 978
 979                 break;
 980         }
 981         case FSE_AZ_TX_PKT_NON_TCP_UDP:
 982                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
 983                 break;
 984
 985         case FSE_AZ_TIMER_EV: {
 986                 uint32_t id;
 987
 988                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 989
 990                 EFSYS_ASSERT(eecp->eec_timer != NULL);
 991                 should_abort = eecp->eec_timer(arg, id);
 992
 993                 break;
 994         }
 995         case FSE_AZ_RX_DSC_ERROR_EV:
 996                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
 997
 998                 EFSYS_PROBE(rx_dsc_error);
 999
1000                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1001                 should_abort = eecp->eec_exception(arg,
1002                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
1003
1004                 break;
1005
1006         case FSE_AZ_TX_DSC_ERROR_EV:
1007                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1008
1009                 EFSYS_PROBE(tx_dsc_error);
1010
1011                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1012                 should_abort = eecp->eec_exception(arg,
1013                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
1014
1015                 break;
1016
1017         default:
1018                 break;
1019         }
1020
1021         return (should_abort);
1022 }
1023
1024 static  __checkReturn   boolean_t
1025 siena_ev_drv_gen(
1026         __in            efx_evq_t *eep,
1027         __in            efx_qword_t *eqp,
1028         __in            const efx_ev_callbacks_t *eecp,
1029         __in_opt        void *arg)
1030 {
1031         uint32_t data;
1032         boolean_t should_abort;
1033
1034         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1035
1036         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1037         if (data >= ((uint32_t)1 << 16)) {
1038                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1039                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1040                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1041                 return (B_TRUE);
1042         }
1043
1044         EFSYS_ASSERT(eecp->eec_software != NULL);
1045         should_abort = eecp->eec_software(arg, (uint16_t)data);
1046
1047         return (should_abort);
1048 }
1049
1050 #if EFSYS_OPT_MCDI
1051
1052 static  __checkReturn   boolean_t
1053 siena_ev_mcdi(
1054         __in            efx_evq_t *eep,
1055         __in            efx_qword_t *eqp,
1056         __in            const efx_ev_callbacks_t *eecp,
1057         __in_opt        void *arg)
1058 {
1059         efx_nic_t *enp = eep->ee_enp;
1060         unsigned int code;
1061         boolean_t should_abort = B_FALSE;
1062
1063         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1064
1065         if (enp->en_family != EFX_FAMILY_SIENA)
1066                 goto out;
1067
1068         EFSYS_ASSERT(eecp->eec_link_change != NULL);
1069         EFSYS_ASSERT(eecp->eec_exception != NULL);
1070
1071         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1072
1073         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1074         switch (code) {
1075         case MCDI_EVENT_CODE_BADSSERT:
1076                 efx_mcdi_ev_death(enp, EINTR);
1077                 break;
1078
1079         case MCDI_EVENT_CODE_CMDDONE:
1080                 efx_mcdi_ev_cpl(enp,
1081                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1082                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1083                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1084                 break;
1085
1086         case MCDI_EVENT_CODE_LINKCHANGE: {
1087                 efx_link_mode_t link_mode;
1088
1089                 siena_phy_link_ev(enp, eqp, &link_mode);
1090                 should_abort = eecp->eec_link_change(arg, link_mode);
1091                 break;
1092         }
1093         case MCDI_EVENT_CODE_SENSOREVT: {
1094                 should_abort = B_FALSE;
1095                 break;
1096         }
1097         case MCDI_EVENT_CODE_SCHEDERR:
1098                 /* Informational only */
1099                 break;
1100
1101         case MCDI_EVENT_CODE_REBOOT:
1102                 efx_mcdi_ev_death(enp, EIO);
1103                 break;
1104
1105         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1106 #if EFSYS_OPT_MAC_STATS
1107                 if (eecp->eec_mac_stats != NULL) {
1108                         eecp->eec_mac_stats(arg,
1109                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1110                 }
1111 #endif
1112                 break;
1113
1114         case MCDI_EVENT_CODE_FWALERT: {
1115                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1116
1117                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1118                         should_abort = eecp->eec_exception(arg,
1119                                 EFX_EXCEPTION_FWALERT_SRAM,
1120                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1121                 else
1122                         should_abort = eecp->eec_exception(arg,
1123                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1124                                 MCDI_EV_FIELD(eqp, DATA));
1125                 break;
1126         }
1127
1128         default:
1129                 EFSYS_PROBE1(mc_pcol_error, int, code);
1130                 break;
1131         }
1132
1133 out:
1134         return (should_abort);
1135 }
1136
1137 #endif  /* EFSYS_OPT_MCDI */
1138
1139 static  __checkReturn   efx_rc_t
1140 siena_ev_qprime(
1141         __in            efx_evq_t *eep,
1142         __in            unsigned int count)
1143 {
1144         efx_nic_t *enp = eep->ee_enp;
1145         uint32_t rptr;
1146         efx_dword_t dword;
1147
1148         rptr = count & eep->ee_mask;
1149
1150         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1151
1152         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1153                             &dword, B_FALSE);
1154
1155         return (0);
1156 }
1157
1158 static          void
1159 siena_ev_qpost(
1160         __in    efx_evq_t *eep,
1161         __in    uint16_t data)
1162 {
1163         efx_nic_t *enp = eep->ee_enp;
1164         efx_qword_t ev;
1165         efx_oword_t oword;
1166
1167         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1168             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1169
1170         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1171             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1172             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1173
1174         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1175 }
1176
1177 static  __checkReturn   efx_rc_t
1178 siena_ev_qmoderate(
1179         __in            efx_evq_t *eep,
1180         __in            unsigned int us)
1181 {
1182         efx_nic_t *enp = eep->ee_enp;
1183         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1184         unsigned int locked;
1185         efx_dword_t dword;
1186         efx_rc_t rc;
1187
1188         if (us > encp->enc_evq_timer_max_us) {
1189                 rc = EINVAL;
1190                 goto fail1;
1191         }
1192
1193         /* If the value is zero then disable the timer */
1194         if (us == 0) {
1195                 EFX_POPULATE_DWORD_2(dword,
1196                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1197                     FRF_CZ_TC_TIMER_VAL, 0);
1198         } else {
1199                 unsigned int ticks;
1200
1201                 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1202                         goto fail2;
1203
1204                 EFSYS_ASSERT(ticks > 0);
1205                 EFX_POPULATE_DWORD_2(dword,
1206                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1207                     FRF_CZ_TC_TIMER_VAL, ticks - 1);
1208         }
1209
1210         locked = (eep->ee_index == 0) ? 1 : 0;
1211
1212         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1213             eep->ee_index, &dword, locked);
1214
1215         return (0);
1216
1217 fail2:
1218         EFSYS_PROBE(fail2);
1219 fail1:
1220         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1221
1222         return (rc);
1223 }
1224
1225 static  __checkReturn   efx_rc_t
1226 siena_ev_qcreate(
1227         __in            efx_nic_t *enp,
1228         __in            unsigned int index,
1229         __in            efsys_mem_t *esmp,
1230         __in            size_t n,
1231         __in            uint32_t id,
1232         __in            uint32_t us,
1233         __in            uint32_t flags,
1234         __in            efx_evq_t *eep)
1235 {
1236         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1237         uint32_t size;
1238         efx_oword_t oword;
1239         efx_rc_t rc;
1240         boolean_t notify_mode;
1241
1242         _NOTE(ARGUNUSED(esmp))
1243
1244         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1245         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1246
1247         if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1248                 rc = EINVAL;
1249                 goto fail1;
1250         }
1251         if (index >= encp->enc_evq_limit) {
1252                 rc = EINVAL;
1253                 goto fail2;
1254         }
1255         for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1256             size++)
1257                 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1258                         break;
1259         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1260                 rc = EINVAL;
1261                 goto fail4;
1262         }
1263
1264         /* Set up the handler table */
1265         eep->ee_rx      = siena_ev_rx;
1266         eep->ee_tx      = siena_ev_tx;
1267         eep->ee_driver  = siena_ev_driver;
1268         eep->ee_global  = siena_ev_global;
1269         eep->ee_drv_gen = siena_ev_drv_gen;
1270 #if EFSYS_OPT_MCDI
1271         eep->ee_mcdi    = siena_ev_mcdi;
1272 #endif  /* EFSYS_OPT_MCDI */
1273
1274         notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1275             EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1276
1277         /* Set up the new event queue */
1278         EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1279             FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1280             FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1281         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1282
1283         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1284             FRF_AZ_EVQ_BUF_BASE_ID, id);
1285
1286         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1287
1288         /* Set initial interrupt moderation */
1289         siena_ev_qmoderate(eep, us);
1290
1291         return (0);
1292
1293 fail4:
1294         EFSYS_PROBE(fail4);
1295 fail2:
1296         EFSYS_PROBE(fail2);
1297 fail1:
1298         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1299
1300         return (rc);
1301 }
1302
1303 #endif /* EFSYS_OPT_SIENA */
1304
1305 #if EFSYS_OPT_QSTATS
1306 #if EFSYS_OPT_NAMES
1307 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1308 static const char * const __efx_ev_qstat_name[] = {
1309         "all",
1310         "rx",
1311         "rx_ok",
1312         "rx_frm_trunc",
1313         "rx_tobe_disc",
1314         "rx_pause_frm_err",
1315         "rx_buf_owner_id_err",
1316         "rx_ipv4_hdr_chksum_err",
1317         "rx_tcp_udp_chksum_err",
1318         "rx_eth_crc_err",
1319         "rx_ip_frag_err",
1320         "rx_mcast_pkt",
1321         "rx_mcast_hash_match",
1322         "rx_tcp_ipv4",
1323         "rx_tcp_ipv6",
1324         "rx_udp_ipv4",
1325         "rx_udp_ipv6",
1326         "rx_other_ipv4",
1327         "rx_other_ipv6",
1328         "rx_non_ip",
1329         "rx_batch",
1330         "tx",
1331         "tx_wq_ff_full",
1332         "tx_pkt_err",
1333         "tx_pkt_too_big",
1334         "tx_unexpected",
1335         "global",
1336         "global_mnt",
1337         "driver",
1338         "driver_srm_upd_done",
1339         "driver_tx_descq_fls_done",
1340         "driver_rx_descq_fls_done",
1341         "driver_rx_descq_fls_failed",
1342         "driver_rx_dsc_error",
1343         "driver_tx_dsc_error",
1344         "drv_gen",
1345         "mcdi_response",
1346 };
1347 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1348
1349                 const char *
1350 efx_ev_qstat_name(
1351         __in    efx_nic_t *enp,
1352         __in    unsigned int id)
1353 {
1354         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1355         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1356
1357         return (__efx_ev_qstat_name[id]);
1358 }
1359 #endif  /* EFSYS_OPT_NAMES */
1360 #endif  /* EFSYS_OPT_QSTATS */
1361
1362 #if EFSYS_OPT_SIENA
1363
1364 #if EFSYS_OPT_QSTATS
1365 static                                  void
1366 siena_ev_qstats_update(
1367         __in                            efx_evq_t *eep,
1368         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1369 {
1370         unsigned int id;
1371
1372         for (id = 0; id < EV_NQSTATS; id++) {
1373                 efsys_stat_t *essp = &stat[id];
1374
1375                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1376                 eep->ee_stat[id] = 0;
1377         }
1378 }
1379 #endif  /* EFSYS_OPT_QSTATS */
1380
1381 static          void
1382 siena_ev_qdestroy(
1383         __in    efx_evq_t *eep)
1384 {
1385         efx_nic_t *enp = eep->ee_enp;
1386         efx_oword_t oword;
1387
1388         /* Purge event queue */
1389         EFX_ZERO_OWORD(oword);
1390
1391         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1392             eep->ee_index, &oword, B_TRUE);
1393
1394         EFX_ZERO_OWORD(oword);
1395         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1396 }
1397
1398 static          void
1399 siena_ev_fini(
1400         __in    efx_nic_t *enp)
1401 {
1402         _NOTE(ARGUNUSED(enp))
1403 }
1404
1405 #endif /* EFSYS_OPT_SIENA */