2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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6 * modification, are permitted provided that the following conditions are met:
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39 static __checkReturn efx_rc_t
47 static __checkReturn efx_rc_t
51 static __checkReturn efx_rc_t
54 __inout efx_filter_spec_t *spec,
55 __in boolean_t may_replace);
57 static __checkReturn efx_rc_t
60 __inout efx_filter_spec_t *spec);
62 static __checkReturn efx_rc_t
63 siena_filter_supported_filters(
66 __out size_t *length);
68 #endif /* EFSYS_OPT_SIENA */
71 static const efx_filter_ops_t __efx_filter_siena_ops = {
72 siena_filter_init, /* efo_init */
73 siena_filter_fini, /* efo_fini */
74 siena_filter_restore, /* efo_restore */
75 siena_filter_add, /* efo_add */
76 siena_filter_delete, /* efo_delete */
77 siena_filter_supported_filters, /* efo_supported_filters */
78 NULL, /* efo_reconfigure */
80 #endif /* EFSYS_OPT_SIENA */
82 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
83 static const efx_filter_ops_t __efx_filter_ef10_ops = {
84 ef10_filter_init, /* efo_init */
85 ef10_filter_fini, /* efo_fini */
86 ef10_filter_restore, /* efo_restore */
87 ef10_filter_add, /* efo_add */
88 ef10_filter_delete, /* efo_delete */
89 ef10_filter_supported_filters, /* efo_supported_filters */
90 ef10_filter_reconfigure, /* efo_reconfigure */
92 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
94 __checkReturn efx_rc_t
97 __inout efx_filter_spec_t *spec)
99 const efx_filter_ops_t *efop = enp->en_efop;
101 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
102 EFSYS_ASSERT3P(spec, !=, NULL);
103 EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
105 return (efop->efo_add(enp, spec, B_FALSE));
108 __checkReturn efx_rc_t
111 __inout efx_filter_spec_t *spec)
113 const efx_filter_ops_t *efop = enp->en_efop;
115 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
116 EFSYS_ASSERT3P(spec, !=, NULL);
117 EFSYS_ASSERT3U(spec->efs_flags, &, EFX_FILTER_FLAG_RX);
119 return (efop->efo_delete(enp, spec));
122 __checkReturn efx_rc_t
128 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
130 if ((rc = enp->en_efop->efo_restore(enp)) != 0)
136 EFSYS_PROBE1(fail1, efx_rc_t, rc);
141 __checkReturn efx_rc_t
145 const efx_filter_ops_t *efop;
148 /* Check that efx_filter_spec_t is 64 bytes. */
149 EFX_STATIC_ASSERT(sizeof (efx_filter_spec_t) == 64);
151 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
152 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
153 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_FILTER));
155 switch (enp->en_family) {
157 case EFX_FAMILY_SIENA:
158 efop = &__efx_filter_siena_ops;
160 #endif /* EFSYS_OPT_SIENA */
162 #if EFSYS_OPT_HUNTINGTON
163 case EFX_FAMILY_HUNTINGTON:
164 efop = &__efx_filter_ef10_ops;
166 #endif /* EFSYS_OPT_HUNTINGTON */
174 if ((rc = efop->efo_init(enp)) != 0)
178 enp->en_mod_flags |= EFX_MOD_FILTER;
184 EFSYS_PROBE1(fail1, efx_rc_t, rc);
187 enp->en_mod_flags &= ~EFX_MOD_FILTER;
195 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
196 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
197 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
199 enp->en_efop->efo_fini(enp);
202 enp->en_mod_flags &= ~EFX_MOD_FILTER;
205 __checkReturn efx_rc_t
206 efx_filter_supported_filters(
208 __out uint32_t *list,
209 __out size_t *length)
213 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
214 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
215 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
216 EFSYS_ASSERT(enp->en_efop->efo_supported_filters != NULL);
218 if ((rc = enp->en_efop->efo_supported_filters(enp, list, length)) != 0)
224 EFSYS_PROBE1(fail1, efx_rc_t, rc);
229 __checkReturn efx_rc_t
230 efx_filter_reconfigure(
232 __in_ecount(6) uint8_t const *mac_addr,
233 __in boolean_t all_unicst,
234 __in boolean_t mulcst,
235 __in boolean_t all_mulcst,
236 __in boolean_t brdcst,
237 __in_ecount(6*count) uint8_t const *addrs,
242 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
243 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
244 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_FILTER);
246 if (enp->en_efop->efo_reconfigure != NULL) {
247 if ((rc = enp->en_efop->efo_reconfigure(enp, mac_addr,
257 EFSYS_PROBE1(fail1, efx_rc_t, rc);
263 efx_filter_spec_init_rx(
264 __out efx_filter_spec_t *spec,
265 __in efx_filter_priority_t priority,
266 __in efx_filter_flags_t flags,
269 EFSYS_ASSERT3P(spec, !=, NULL);
270 EFSYS_ASSERT3P(erp, !=, NULL);
271 EFSYS_ASSERT((flags & ~(EFX_FILTER_FLAG_RX_RSS |
272 EFX_FILTER_FLAG_RX_SCATTER)) == 0);
274 memset(spec, 0, sizeof (*spec));
275 spec->efs_priority = priority;
276 spec->efs_flags = EFX_FILTER_FLAG_RX | flags;
277 spec->efs_rss_context = EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT;
278 spec->efs_dmaq_id = (uint16_t)erp->er_index;
282 efx_filter_spec_init_tx(
283 __out efx_filter_spec_t *spec,
286 EFSYS_ASSERT3P(spec, !=, NULL);
287 EFSYS_ASSERT3P(etp, !=, NULL);
289 memset(spec, 0, sizeof (*spec));
290 spec->efs_priority = EFX_FILTER_PRI_REQUIRED;
291 spec->efs_flags = EFX_FILTER_FLAG_TX;
292 spec->efs_dmaq_id = (uint16_t)etp->et_index;
297 * Specify IPv4 host, transport protocol and port in a filter specification
299 __checkReturn efx_rc_t
300 efx_filter_spec_set_ipv4_local(
301 __inout efx_filter_spec_t *spec,
306 EFSYS_ASSERT3P(spec, !=, NULL);
308 spec->efs_match_flags |=
309 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
310 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
311 spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
312 spec->efs_ip_proto = proto;
313 spec->efs_loc_host.eo_u32[0] = host;
314 spec->efs_loc_port = port;
319 * Specify IPv4 hosts, transport protocol and ports in a filter specification
321 __checkReturn efx_rc_t
322 efx_filter_spec_set_ipv4_full(
323 __inout efx_filter_spec_t *spec,
330 EFSYS_ASSERT3P(spec, !=, NULL);
332 spec->efs_match_flags |=
333 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
334 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
335 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
336 spec->efs_ether_type = EFX_ETHER_TYPE_IPV4;
337 spec->efs_ip_proto = proto;
338 spec->efs_loc_host.eo_u32[0] = lhost;
339 spec->efs_loc_port = lport;
340 spec->efs_rem_host.eo_u32[0] = rhost;
341 spec->efs_rem_port = rport;
346 * Specify local Ethernet address and/or VID in filter specification
348 __checkReturn efx_rc_t
349 efx_filter_spec_set_eth_local(
350 __inout efx_filter_spec_t *spec,
352 __in const uint8_t *addr)
354 EFSYS_ASSERT3P(spec, !=, NULL);
355 EFSYS_ASSERT3P(addr, !=, NULL);
357 if (vid == EFX_FILTER_SPEC_VID_UNSPEC && addr == NULL)
360 if (vid != EFX_FILTER_SPEC_VID_UNSPEC) {
361 spec->efs_match_flags |= EFX_FILTER_MATCH_OUTER_VID;
362 spec->efs_outer_vid = vid;
365 spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC;
366 memcpy(spec->efs_loc_mac, addr, EFX_MAC_ADDR_LEN);
372 * Specify matching otherwise-unmatched unicast in a filter specification
374 __checkReturn efx_rc_t
375 efx_filter_spec_set_uc_def(
376 __inout efx_filter_spec_t *spec)
378 EFSYS_ASSERT3P(spec, !=, NULL);
380 spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC_IG;
385 * Specify matching otherwise-unmatched multicast in a filter specification
387 __checkReturn efx_rc_t
388 efx_filter_spec_set_mc_def(
389 __inout efx_filter_spec_t *spec)
391 EFSYS_ASSERT3P(spec, !=, NULL);
393 spec->efs_match_flags |= EFX_FILTER_MATCH_LOC_MAC_IG;
394 spec->efs_loc_mac[0] = 1;
403 * "Fudge factors" - difference between programmed value and actual depth.
404 * Due to pipelined implementation we need to program H/W with a value that
405 * is larger than the hop limit we want.
407 #define FILTER_CTL_SRCH_FUDGE_WILD 3
408 #define FILTER_CTL_SRCH_FUDGE_FULL 1
411 * Hard maximum hop limit. Hardware will time-out beyond 200-something.
412 * We also need to avoid infinite loops in efx_filter_search() when the
415 #define FILTER_CTL_SRCH_MAX 200
417 static __checkReturn efx_rc_t
418 siena_filter_spec_from_gen_spec(
419 __out siena_filter_spec_t *sf_spec,
420 __in efx_filter_spec_t *gen_spec)
423 boolean_t is_full = B_FALSE;
425 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX)
426 EFSYS_ASSERT3U(gen_spec->efs_flags, ==, EFX_FILTER_FLAG_TX);
428 EFSYS_ASSERT3U(gen_spec->efs_flags, &, EFX_FILTER_FLAG_RX);
430 /* Falconsiena only has one RSS context */
431 if ((gen_spec->efs_flags & EFX_FILTER_FLAG_RX_RSS) &&
432 gen_spec->efs_rss_context != 0) {
437 sf_spec->sfs_flags = gen_spec->efs_flags;
438 sf_spec->sfs_dmaq_id = gen_spec->efs_dmaq_id;
440 switch (gen_spec->efs_match_flags) {
441 case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
442 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
443 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT:
446 case EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
447 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT: {
448 uint32_t rhost, host1, host2;
449 uint16_t rport, port1, port2;
451 if (gen_spec->efs_ether_type != EFX_ETHER_TYPE_IPV4) {
455 if (gen_spec->efs_loc_port == 0 ||
456 (is_full && gen_spec->efs_rem_port == 0)) {
460 switch (gen_spec->efs_ip_proto) {
461 case EFX_IPPROTO_TCP:
462 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
463 sf_spec->sfs_type = (is_full ?
464 EFX_SIENA_FILTER_TX_TCP_FULL :
465 EFX_SIENA_FILTER_TX_TCP_WILD);
467 sf_spec->sfs_type = (is_full ?
468 EFX_SIENA_FILTER_RX_TCP_FULL :
469 EFX_SIENA_FILTER_RX_TCP_WILD);
472 case EFX_IPPROTO_UDP:
473 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
474 sf_spec->sfs_type = (is_full ?
475 EFX_SIENA_FILTER_TX_UDP_FULL :
476 EFX_SIENA_FILTER_TX_UDP_WILD);
478 sf_spec->sfs_type = (is_full ?
479 EFX_SIENA_FILTER_RX_UDP_FULL :
480 EFX_SIENA_FILTER_RX_UDP_WILD);
488 * The filter is constructed in terms of source and destination,
489 * with the odd wrinkle that the ports are swapped in a UDP
490 * wildcard filter. We need to convert from local and remote
491 * addresses (zero for a wildcard).
493 rhost = is_full ? gen_spec->efs_rem_host.eo_u32[0] : 0;
494 rport = is_full ? gen_spec->efs_rem_port : 0;
495 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
496 host1 = gen_spec->efs_loc_host.eo_u32[0];
500 host2 = gen_spec->efs_loc_host.eo_u32[0];
502 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
503 if (sf_spec->sfs_type ==
504 EFX_SIENA_FILTER_TX_UDP_WILD) {
506 port2 = gen_spec->efs_loc_port;
508 port1 = gen_spec->efs_loc_port;
512 if (sf_spec->sfs_type ==
513 EFX_SIENA_FILTER_RX_UDP_WILD) {
514 port1 = gen_spec->efs_loc_port;
518 port2 = gen_spec->efs_loc_port;
521 sf_spec->sfs_dword[0] = (host1 << 16) | port1;
522 sf_spec->sfs_dword[1] = (port2 << 16) | (host1 >> 16);
523 sf_spec->sfs_dword[2] = host2;
527 case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
530 case EFX_FILTER_MATCH_LOC_MAC:
531 if (gen_spec->efs_flags & EFX_FILTER_FLAG_TX) {
532 sf_spec->sfs_type = (is_full ?
533 EFX_SIENA_FILTER_TX_MAC_FULL :
534 EFX_SIENA_FILTER_TX_MAC_WILD);
536 sf_spec->sfs_type = (is_full ?
537 EFX_SIENA_FILTER_RX_MAC_FULL :
538 EFX_SIENA_FILTER_RX_MAC_WILD);
540 sf_spec->sfs_dword[0] = is_full ? gen_spec->efs_outer_vid : 0;
541 sf_spec->sfs_dword[1] =
542 gen_spec->efs_loc_mac[2] << 24 |
543 gen_spec->efs_loc_mac[3] << 16 |
544 gen_spec->efs_loc_mac[4] << 8 |
545 gen_spec->efs_loc_mac[5];
546 sf_spec->sfs_dword[2] =
547 gen_spec->efs_loc_mac[0] << 8 |
548 gen_spec->efs_loc_mac[1];
552 EFSYS_ASSERT(B_FALSE);
568 EFSYS_PROBE1(fail1, efx_rc_t, rc);
574 * The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
575 * key derived from the n-tuple.
578 siena_filter_tbl_hash(
583 /* First 16 rounds */
584 tmp = 0x1fff ^ (uint16_t)(key >> 16);
585 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
586 tmp = tmp ^ tmp >> 9;
589 tmp = tmp ^ tmp << 13 ^ (uint16_t)(key & 0xffff);
590 tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
591 tmp = tmp ^ tmp >> 9;
597 * To allow for hash collisions, filter search continues at these
598 * increments from the first possible entry selected by the hash.
601 siena_filter_tbl_increment(
604 return ((uint16_t)(key * 2 - 1));
607 static __checkReturn boolean_t
608 siena_filter_test_used(
609 __in siena_filter_tbl_t *sftp,
610 __in unsigned int index)
612 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
613 return ((sftp->sft_bitmap[index / 32] & (1 << (index % 32))) != 0);
617 siena_filter_set_used(
618 __in siena_filter_tbl_t *sftp,
619 __in unsigned int index)
621 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
622 sftp->sft_bitmap[index / 32] |= (1 << (index % 32));
627 siena_filter_clear_used(
628 __in siena_filter_tbl_t *sftp,
629 __in unsigned int index)
631 EFSYS_ASSERT3P(sftp->sft_bitmap, !=, NULL);
632 sftp->sft_bitmap[index / 32] &= ~(1 << (index % 32));
635 EFSYS_ASSERT3U(sftp->sft_used, >=, 0);
639 static siena_filter_tbl_id_t
641 __in siena_filter_type_t type)
643 siena_filter_tbl_id_t tbl_id;
646 case EFX_SIENA_FILTER_RX_TCP_FULL:
647 case EFX_SIENA_FILTER_RX_TCP_WILD:
648 case EFX_SIENA_FILTER_RX_UDP_FULL:
649 case EFX_SIENA_FILTER_RX_UDP_WILD:
650 tbl_id = EFX_SIENA_FILTER_TBL_RX_IP;
653 case EFX_SIENA_FILTER_RX_MAC_FULL:
654 case EFX_SIENA_FILTER_RX_MAC_WILD:
655 tbl_id = EFX_SIENA_FILTER_TBL_RX_MAC;
658 case EFX_SIENA_FILTER_TX_TCP_FULL:
659 case EFX_SIENA_FILTER_TX_TCP_WILD:
660 case EFX_SIENA_FILTER_TX_UDP_FULL:
661 case EFX_SIENA_FILTER_TX_UDP_WILD:
662 tbl_id = EFX_SIENA_FILTER_TBL_TX_IP;
665 case EFX_SIENA_FILTER_TX_MAC_FULL:
666 case EFX_SIENA_FILTER_TX_MAC_WILD:
667 tbl_id = EFX_SIENA_FILTER_TBL_TX_MAC;
671 EFSYS_ASSERT(B_FALSE);
672 tbl_id = EFX_SIENA_FILTER_NTBLS;
679 siena_filter_reset_search_depth(
680 __inout siena_filter_t *sfp,
681 __in siena_filter_tbl_id_t tbl_id)
684 case EFX_SIENA_FILTER_TBL_RX_IP:
685 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_FULL] = 0;
686 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_WILD] = 0;
687 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_FULL] = 0;
688 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_WILD] = 0;
691 case EFX_SIENA_FILTER_TBL_RX_MAC:
692 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_FULL] = 0;
693 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_WILD] = 0;
696 case EFX_SIENA_FILTER_TBL_TX_IP:
697 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_FULL] = 0;
698 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_WILD] = 0;
699 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_FULL] = 0;
700 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_WILD] = 0;
703 case EFX_SIENA_FILTER_TBL_TX_MAC:
704 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_FULL] = 0;
705 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_WILD] = 0;
709 EFSYS_ASSERT(B_FALSE);
715 siena_filter_push_rx_limits(
718 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
721 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
723 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_FULL_SRCH_LIMIT,
724 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_FULL] +
725 FILTER_CTL_SRCH_FUDGE_FULL);
726 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TCP_WILD_SRCH_LIMIT,
727 sfp->sf_depth[EFX_SIENA_FILTER_RX_TCP_WILD] +
728 FILTER_CTL_SRCH_FUDGE_WILD);
729 EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_FULL_SRCH_LIMIT,
730 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_FULL] +
731 FILTER_CTL_SRCH_FUDGE_FULL);
732 EFX_SET_OWORD_FIELD(oword, FRF_AZ_UDP_WILD_SRCH_LIMIT,
733 sfp->sf_depth[EFX_SIENA_FILTER_RX_UDP_WILD] +
734 FILTER_CTL_SRCH_FUDGE_WILD);
736 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_MAC].sft_size) {
737 EFX_SET_OWORD_FIELD(oword,
738 FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
739 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_FULL] +
740 FILTER_CTL_SRCH_FUDGE_FULL);
741 EFX_SET_OWORD_FIELD(oword,
742 FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
743 sfp->sf_depth[EFX_SIENA_FILTER_RX_MAC_WILD] +
744 FILTER_CTL_SRCH_FUDGE_WILD);
747 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
751 siena_filter_push_tx_limits(
754 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
757 EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword);
759 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_IP].sft_size != 0) {
760 EFX_SET_OWORD_FIELD(oword,
761 FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE,
762 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_FULL] +
763 FILTER_CTL_SRCH_FUDGE_FULL);
764 EFX_SET_OWORD_FIELD(oword,
765 FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE,
766 sfp->sf_depth[EFX_SIENA_FILTER_TX_TCP_WILD] +
767 FILTER_CTL_SRCH_FUDGE_WILD);
768 EFX_SET_OWORD_FIELD(oword,
769 FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE,
770 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_FULL] +
771 FILTER_CTL_SRCH_FUDGE_FULL);
772 EFX_SET_OWORD_FIELD(oword,
773 FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE,
774 sfp->sf_depth[EFX_SIENA_FILTER_TX_UDP_WILD] +
775 FILTER_CTL_SRCH_FUDGE_WILD);
778 if (sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_MAC].sft_size != 0) {
780 oword, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
781 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_FULL] +
782 FILTER_CTL_SRCH_FUDGE_FULL);
784 oword, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
785 sfp->sf_depth[EFX_SIENA_FILTER_TX_MAC_WILD] +
786 FILTER_CTL_SRCH_FUDGE_WILD);
789 EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword);
792 /* Build a filter entry and return its n-tuple key. */
793 static __checkReturn uint32_t
795 __out efx_oword_t *filter,
796 __in siena_filter_spec_t *spec)
800 uint8_t type = spec->sfs_type;
801 uint32_t flags = spec->sfs_flags;
803 switch (siena_filter_tbl_id(type)) {
804 case EFX_SIENA_FILTER_TBL_RX_IP: {
805 boolean_t is_udp = (type == EFX_SIENA_FILTER_RX_UDP_FULL ||
806 type == EFX_SIENA_FILTER_RX_UDP_WILD);
807 EFX_POPULATE_OWORD_7(*filter,
809 (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
811 (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
812 FRF_AZ_TCP_UDP, is_udp,
813 FRF_AZ_RXQ_ID, spec->sfs_dmaq_id,
814 EFX_DWORD_2, spec->sfs_dword[2],
815 EFX_DWORD_1, spec->sfs_dword[1],
816 EFX_DWORD_0, spec->sfs_dword[0]);
821 case EFX_SIENA_FILTER_TBL_RX_MAC: {
822 boolean_t is_wild = (type == EFX_SIENA_FILTER_RX_MAC_WILD);
823 EFX_POPULATE_OWORD_7(*filter,
825 (flags & EFX_FILTER_FLAG_RX_RSS) ? 1 : 0,
826 FRF_CZ_RMFT_SCATTER_EN,
827 (flags & EFX_FILTER_FLAG_RX_SCATTER) ? 1 : 0,
828 FRF_CZ_RMFT_RXQ_ID, spec->sfs_dmaq_id,
829 FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
830 FRF_CZ_RMFT_DEST_MAC_DW1, spec->sfs_dword[2],
831 FRF_CZ_RMFT_DEST_MAC_DW0, spec->sfs_dword[1],
832 FRF_CZ_RMFT_VLAN_ID, spec->sfs_dword[0]);
837 case EFX_SIENA_FILTER_TBL_TX_IP: {
838 boolean_t is_udp = (type == EFX_SIENA_FILTER_TX_UDP_FULL ||
839 type == EFX_SIENA_FILTER_TX_UDP_WILD);
840 EFX_POPULATE_OWORD_5(*filter,
841 FRF_CZ_TIFT_TCP_UDP, is_udp,
842 FRF_CZ_TIFT_TXQ_ID, spec->sfs_dmaq_id,
843 EFX_DWORD_2, spec->sfs_dword[2],
844 EFX_DWORD_1, spec->sfs_dword[1],
845 EFX_DWORD_0, spec->sfs_dword[0]);
846 dword3 = is_udp | spec->sfs_dmaq_id << 1;
850 case EFX_SIENA_FILTER_TBL_TX_MAC: {
851 boolean_t is_wild = (type == EFX_SIENA_FILTER_TX_MAC_WILD);
852 EFX_POPULATE_OWORD_5(*filter,
853 FRF_CZ_TMFT_TXQ_ID, spec->sfs_dmaq_id,
854 FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
855 FRF_CZ_TMFT_SRC_MAC_DW1, spec->sfs_dword[2],
856 FRF_CZ_TMFT_SRC_MAC_DW0, spec->sfs_dword[1],
857 FRF_CZ_TMFT_VLAN_ID, spec->sfs_dword[0]);
858 dword3 = is_wild | spec->sfs_dmaq_id << 1;
863 EFSYS_ASSERT(B_FALSE);
876 static __checkReturn efx_rc_t
877 siena_filter_push_entry(
878 __inout efx_nic_t *enp,
879 __in siena_filter_type_t type,
881 __in efx_oword_t *eop)
886 case EFX_SIENA_FILTER_RX_TCP_FULL:
887 case EFX_SIENA_FILTER_RX_TCP_WILD:
888 case EFX_SIENA_FILTER_RX_UDP_FULL:
889 case EFX_SIENA_FILTER_RX_UDP_WILD:
890 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_FILTER_TBL0, index,
894 case EFX_SIENA_FILTER_RX_MAC_FULL:
895 case EFX_SIENA_FILTER_RX_MAC_WILD:
896 EFX_BAR_TBL_WRITEO(enp, FR_CZ_RX_MAC_FILTER_TBL0, index,
900 case EFX_SIENA_FILTER_TX_TCP_FULL:
901 case EFX_SIENA_FILTER_TX_TCP_WILD:
902 case EFX_SIENA_FILTER_TX_UDP_FULL:
903 case EFX_SIENA_FILTER_TX_UDP_WILD:
904 EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_FILTER_TBL0, index,
908 case EFX_SIENA_FILTER_TX_MAC_FULL:
909 case EFX_SIENA_FILTER_TX_MAC_WILD:
910 EFX_BAR_TBL_WRITEO(enp, FR_CZ_TX_MAC_FILTER_TBL0, index,
915 EFSYS_ASSERT(B_FALSE);
926 static __checkReturn boolean_t
928 __in const siena_filter_spec_t *left,
929 __in const siena_filter_spec_t *right)
931 siena_filter_tbl_id_t tbl_id;
933 tbl_id = siena_filter_tbl_id(left->sfs_type);
936 if (left->sfs_type != right->sfs_type)
939 if (memcmp(left->sfs_dword, right->sfs_dword,
940 sizeof (left->sfs_dword)))
943 if ((tbl_id == EFX_SIENA_FILTER_TBL_TX_IP ||
944 tbl_id == EFX_SIENA_FILTER_TBL_TX_MAC) &&
945 left->sfs_dmaq_id != right->sfs_dmaq_id)
951 static __checkReturn efx_rc_t
953 __in siena_filter_tbl_t *sftp,
954 __in siena_filter_spec_t *spec,
956 __in boolean_t for_insert,
957 __out int *filter_index,
958 __out unsigned int *depth_required)
960 unsigned int hash, incr, filter_idx, depth;
962 hash = siena_filter_tbl_hash(key);
963 incr = siena_filter_tbl_increment(key);
965 filter_idx = hash & (sftp->sft_size - 1);
970 * Return success if entry is used and matches this spec
971 * or entry is unused and we are trying to insert.
973 if (siena_filter_test_used(sftp, filter_idx) ?
974 siena_filter_equal(spec,
975 &sftp->sft_spec[filter_idx]) :
977 *filter_index = filter_idx;
978 *depth_required = depth;
982 /* Return failure if we reached the maximum search depth */
983 if (depth == FILTER_CTL_SRCH_MAX)
984 return (for_insert ? EBUSY : ENOENT);
986 filter_idx = (filter_idx + incr) & (sftp->sft_size - 1);
992 siena_filter_clear_entry(
994 __in siena_filter_tbl_t *sftp,
999 if (siena_filter_test_used(sftp, index)) {
1000 siena_filter_clear_used(sftp, index);
1002 EFX_ZERO_OWORD(filter);
1003 siena_filter_push_entry(enp,
1004 sftp->sft_spec[index].sfs_type,
1007 memset(&sftp->sft_spec[index],
1008 0, sizeof (sftp->sft_spec[0]));
1013 siena_filter_tbl_clear(
1014 __in efx_nic_t *enp,
1015 __in siena_filter_tbl_id_t tbl_id)
1017 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1018 siena_filter_tbl_t *sftp = &sfp->sf_tbl[tbl_id];
1020 efsys_lock_state_t state;
1022 EFSYS_LOCK(enp->en_eslp, state);
1024 for (index = 0; index < sftp->sft_size; ++index) {
1025 siena_filter_clear_entry(enp, sftp, index);
1028 if (sftp->sft_used == 0)
1029 siena_filter_reset_search_depth(sfp, tbl_id);
1031 EFSYS_UNLOCK(enp->en_eslp, state);
1034 static __checkReturn efx_rc_t
1036 __in efx_nic_t *enp)
1038 siena_filter_t *sfp;
1039 siena_filter_tbl_t *sftp;
1043 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (siena_filter_t), sfp);
1050 enp->en_filter.ef_siena_filter = sfp;
1052 switch (enp->en_family) {
1053 case EFX_FAMILY_SIENA:
1054 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_IP];
1055 sftp->sft_size = FR_AZ_RX_FILTER_TBL0_ROWS;
1057 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_RX_MAC];
1058 sftp->sft_size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
1060 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_IP];
1061 sftp->sft_size = FR_CZ_TX_FILTER_TBL0_ROWS;
1063 sftp = &sfp->sf_tbl[EFX_SIENA_FILTER_TBL_TX_MAC];
1064 sftp->sft_size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
1072 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1073 unsigned int bitmap_size;
1075 sftp = &sfp->sf_tbl[tbl_id];
1076 if (sftp->sft_size == 0)
1079 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1082 (sftp->sft_size + (sizeof (uint32_t) * 8) - 1) / 8;
1084 EFSYS_KMEM_ALLOC(enp->en_esip, bitmap_size, sftp->sft_bitmap);
1085 if (!sftp->sft_bitmap) {
1090 EFSYS_KMEM_ALLOC(enp->en_esip,
1091 sftp->sft_size * sizeof (*sftp->sft_spec),
1093 if (!sftp->sft_spec) {
1097 memset(sftp->sft_spec, 0,
1098 sftp->sft_size * sizeof (*sftp->sft_spec));
1111 siena_filter_fini(enp);
1114 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1120 __in efx_nic_t *enp)
1122 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1123 siena_filter_tbl_id_t tbl_id;
1125 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1126 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
1131 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1132 siena_filter_tbl_t *sftp = &sfp->sf_tbl[tbl_id];
1133 unsigned int bitmap_size;
1135 EFX_STATIC_ASSERT(sizeof (sftp->sft_bitmap[0]) ==
1138 (sftp->sft_size + (sizeof (uint32_t) * 8) - 1) / 8;
1140 if (sftp->sft_bitmap != NULL) {
1141 EFSYS_KMEM_FREE(enp->en_esip, bitmap_size,
1143 sftp->sft_bitmap = NULL;
1146 if (sftp->sft_spec != NULL) {
1147 EFSYS_KMEM_FREE(enp->en_esip, sftp->sft_size *
1148 sizeof (*sftp->sft_spec), sftp->sft_spec);
1149 sftp->sft_spec = NULL;
1153 EFSYS_KMEM_FREE(enp->en_esip, sizeof (siena_filter_t),
1154 enp->en_filter.ef_siena_filter);
1157 /* Restore filter state after a reset */
1158 static __checkReturn efx_rc_t
1159 siena_filter_restore(
1160 __in efx_nic_t *enp)
1162 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1163 siena_filter_tbl_id_t tbl_id;
1164 siena_filter_tbl_t *sftp;
1165 siena_filter_spec_t *spec;
1168 efsys_lock_state_t state;
1172 EFSYS_LOCK(enp->en_eslp, state);
1174 for (tbl_id = 0; tbl_id < EFX_SIENA_FILTER_NTBLS; tbl_id++) {
1175 sftp = &sfp->sf_tbl[tbl_id];
1176 for (filter_idx = 0;
1177 filter_idx < sftp->sft_size;
1179 if (!siena_filter_test_used(sftp, filter_idx))
1182 spec = &sftp->sft_spec[filter_idx];
1183 if ((key = siena_filter_build(&filter, spec)) == 0) {
1187 if ((rc = siena_filter_push_entry(enp,
1188 spec->sfs_type, filter_idx, &filter)) != 0)
1193 siena_filter_push_rx_limits(enp);
1194 siena_filter_push_tx_limits(enp);
1196 EFSYS_UNLOCK(enp->en_eslp, state);
1204 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1206 EFSYS_UNLOCK(enp->en_eslp, state);
1211 static __checkReturn efx_rc_t
1213 __in efx_nic_t *enp,
1214 __inout efx_filter_spec_t *spec,
1215 __in boolean_t may_replace)
1218 siena_filter_spec_t sf_spec;
1219 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1220 siena_filter_tbl_id_t tbl_id;
1221 siena_filter_tbl_t *sftp;
1222 siena_filter_spec_t *saved_sf_spec;
1226 efsys_lock_state_t state;
1230 EFSYS_ASSERT3P(spec, !=, NULL);
1232 if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)
1235 tbl_id = siena_filter_tbl_id(sf_spec.sfs_type);
1236 sftp = &sfp->sf_tbl[tbl_id];
1238 if (sftp->sft_size == 0) {
1243 key = siena_filter_build(&filter, &sf_spec);
1245 EFSYS_LOCK(enp->en_eslp, state);
1247 rc = siena_filter_search(sftp, &sf_spec, key, B_TRUE,
1248 &filter_idx, &depth);
1252 EFSYS_ASSERT3U(filter_idx, <, sftp->sft_size);
1253 saved_sf_spec = &sftp->sft_spec[filter_idx];
1255 if (siena_filter_test_used(sftp, filter_idx)) {
1256 if (may_replace == B_FALSE) {
1261 siena_filter_set_used(sftp, filter_idx);
1262 *saved_sf_spec = sf_spec;
1264 if (sfp->sf_depth[sf_spec.sfs_type] < depth) {
1265 sfp->sf_depth[sf_spec.sfs_type] = depth;
1266 if (tbl_id == EFX_SIENA_FILTER_TBL_TX_IP ||
1267 tbl_id == EFX_SIENA_FILTER_TBL_TX_MAC)
1268 siena_filter_push_tx_limits(enp);
1270 siena_filter_push_rx_limits(enp);
1273 siena_filter_push_entry(enp, sf_spec.sfs_type,
1274 filter_idx, &filter);
1276 EFSYS_UNLOCK(enp->en_eslp, state);
1283 EFSYS_UNLOCK(enp->en_eslp, state);
1290 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1294 static __checkReturn efx_rc_t
1295 siena_filter_delete(
1296 __in efx_nic_t *enp,
1297 __inout efx_filter_spec_t *spec)
1300 siena_filter_spec_t sf_spec;
1301 siena_filter_t *sfp = enp->en_filter.ef_siena_filter;
1302 siena_filter_tbl_id_t tbl_id;
1303 siena_filter_tbl_t *sftp;
1307 efsys_lock_state_t state;
1310 EFSYS_ASSERT3P(spec, !=, NULL);
1312 if ((rc = siena_filter_spec_from_gen_spec(&sf_spec, spec)) != 0)
1315 tbl_id = siena_filter_tbl_id(sf_spec.sfs_type);
1316 sftp = &sfp->sf_tbl[tbl_id];
1318 key = siena_filter_build(&filter, &sf_spec);
1320 EFSYS_LOCK(enp->en_eslp, state);
1322 rc = siena_filter_search(sftp, &sf_spec, key, B_FALSE,
1323 &filter_idx, &depth);
1327 siena_filter_clear_entry(enp, sftp, filter_idx);
1328 if (sftp->sft_used == 0)
1329 siena_filter_reset_search_depth(sfp, tbl_id);
1331 EFSYS_UNLOCK(enp->en_eslp, state);
1335 EFSYS_UNLOCK(enp->en_eslp, state);
1339 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1343 #define MAX_SUPPORTED 4
1345 static __checkReturn efx_rc_t
1346 siena_filter_supported_filters(
1347 __in efx_nic_t *enp,
1348 __out uint32_t *list,
1349 __out size_t *length)
1352 uint32_t rx_matches[MAX_SUPPORTED];
1360 rx_matches[index++] =
1361 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
1362 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
1363 EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT;
1365 rx_matches[index++] =
1366 EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
1367 EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
1369 if (enp->en_features & EFX_FEATURE_MAC_HEADER_FILTERS) {
1370 rx_matches[index++] =
1371 EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC;
1373 rx_matches[index++] = EFX_FILTER_MATCH_LOC_MAC;
1376 EFSYS_ASSERT3U(index, <=, MAX_SUPPORTED);
1379 memcpy(list, rx_matches, *length);
1388 #undef MAX_SUPPORTED
1390 #endif /* EFSYS_OPT_SIENA */
1392 #endif /* EFSYS_OPT_FILTER */