drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #if EFSYS_OPT_MCDI
  14 #include "efx_mcdi.h"
  15 #endif  /* EFSYS_OPT_MCDI */
  16
  17 /* FIXME: Add definition for driver generated software events */
  18 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  19 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  20 #endif
  21
  22
  23 #if EFSYS_OPT_SIENA
  24 #include "siena_impl.h"
  25 #endif  /* EFSYS_OPT_SIENA */
  26
  27 #if EFSYS_OPT_HUNTINGTON
  28 #include "hunt_impl.h"
  29 #endif  /* EFSYS_OPT_HUNTINGTON */
  30
  31 #if EFSYS_OPT_MEDFORD
  32 #include "medford_impl.h"
  33 #endif  /* EFSYS_OPT_MEDFORD */
  34
  35 #if EFSYS_OPT_MEDFORD2
  36 #include "medford2_impl.h"
  37 #endif  /* EFSYS_OPT_MEDFORD2 */
  38
  39 #if EFX_OPTS_EF10()
  40 #include "ef10_impl.h"
  41 #endif  /* EFX_OPTS_EF10() */
  42
  43 #ifdef  __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define EFX_MOD_MCDI            0x00000001
  48 #define EFX_MOD_PROBE           0x00000002
  49 #define EFX_MOD_NVRAM           0x00000004
  50 #define EFX_MOD_VPD             0x00000008
  51 #define EFX_MOD_NIC             0x00000010
  52 #define EFX_MOD_INTR            0x00000020
  53 #define EFX_MOD_EV              0x00000040
  54 #define EFX_MOD_RX              0x00000080
  55 #define EFX_MOD_TX              0x00000100
  56 #define EFX_MOD_PORT            0x00000200
  57 #define EFX_MOD_MON             0x00000400
  58 #define EFX_MOD_FILTER          0x00001000
  59 #define EFX_MOD_LIC             0x00002000
  60 #define EFX_MOD_TUNNEL          0x00004000
  61
  62 #define EFX_RESET_PHY           0x00000001
  63 #define EFX_RESET_RXQ_ERR       0x00000002
  64 #define EFX_RESET_TXQ_ERR       0x00000004
  65 #define EFX_RESET_HW_UNAVAIL    0x00000008
  66
  67 typedef enum efx_mac_type_e {
  68         EFX_MAC_INVALID = 0,
  69         EFX_MAC_SIENA,
  70         EFX_MAC_HUNTINGTON,
  71         EFX_MAC_MEDFORD,
  72         EFX_MAC_MEDFORD2,
  73         EFX_MAC_NTYPES
  74 } efx_mac_type_t;
  75
  76 typedef struct efx_ev_ops_s {
  77         efx_rc_t        (*eevo_init)(efx_nic_t *);
  78         void            (*eevo_fini)(efx_nic_t *);
  79         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  80                                           efsys_mem_t *, size_t, uint32_t,
  81                                           uint32_t, uint32_t, efx_evq_t *);
  82         void            (*eevo_qdestroy)(efx_evq_t *);
  83         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  84         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  85         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  86 #if EFSYS_OPT_QSTATS
  87         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  88 #endif
  89 } efx_ev_ops_t;
  90
  91 typedef struct efx_tx_ops_s {
  92         efx_rc_t        (*etxo_init)(efx_nic_t *);
  93         void            (*etxo_fini)(efx_nic_t *);
  94         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  95                                         unsigned int, unsigned int,
  96                                         efsys_mem_t *, size_t,
  97                                         uint32_t, uint16_t,
  98                                         efx_evq_t *, efx_txq_t *,
  99                                         unsigned int *);
 100         void            (*etxo_qdestroy)(efx_txq_t *);
 101         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 102                                       unsigned int, unsigned int,
 103                                       unsigned int *);
 104         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 105         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 106         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 107         void            (*etxo_qenable)(efx_txq_t *);
 108         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 109         void            (*etxo_qpio_disable)(efx_txq_t *);
 110         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 111                                            size_t);
 112         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 113                                            unsigned int *);
 114         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 115                                       unsigned int, unsigned int,
 116                                       unsigned int *);
 117         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 118                                                 size_t, boolean_t,
 119                                                 efx_desc_t *);
 120         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 121                                                 uint32_t, uint8_t,
 122                                                 efx_desc_t *);
 123         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 124                                                 uint16_t, uint32_t, uint16_t,
 125                                                 efx_desc_t *, int);
 126         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 127                                                 efx_desc_t *);
 128         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 129                                                 efx_desc_t *);
 130 #if EFSYS_OPT_QSTATS
 131         void            (*etxo_qstats_update)(efx_txq_t *,
 132                                               efsys_stat_t *);
 133 #endif
 134 } efx_tx_ops_t;
 135
 136 typedef union efx_rxq_type_data_u {
 137         struct {
 138                 size_t          ed_buf_size;
 139         } ertd_default;
 140 #if EFSYS_OPT_RX_PACKED_STREAM
 141         struct {
 142                 uint32_t        eps_buf_size;
 143         } ertd_packed_stream;
 144 #endif
 145 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 146         struct {
 147                 uint32_t        eessb_bufs_per_desc;
 148                 uint32_t        eessb_max_dma_len;
 149                 uint32_t        eessb_buf_stride;
 150                 uint32_t        eessb_hol_block_timeout;
 151         } ertd_es_super_buffer;
 152 #endif
 153 } efx_rxq_type_data_t;
 154
 155 typedef struct efx_rx_ops_s {
 156         efx_rc_t        (*erxo_init)(efx_nic_t *);
 157         void            (*erxo_fini)(efx_nic_t *);
 158 #if EFSYS_OPT_RX_SCATTER
 159         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 160 #endif
 161 #if EFSYS_OPT_RX_SCALE
 162         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 163                                                     efx_rx_scale_context_type_t,
 164                                                     uint32_t, uint32_t *);
 165         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 166         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 167                                                efx_rx_hash_alg_t,
 168                                                efx_rx_hash_type_t, boolean_t);
 169         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 170                                               uint8_t *, size_t);
 171         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 172                                               unsigned int *, size_t);
 173         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 174                                             uint8_t *);
 175 #endif /* EFSYS_OPT_RX_SCALE */
 176         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 177                                               uint16_t *);
 178         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 179                                       unsigned int, unsigned int,
 180                                       unsigned int);
 181         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 182 #if EFSYS_OPT_RX_PACKED_STREAM
 183         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 184         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 185                                                 uint32_t, uint32_t,
 186                                                 uint16_t *, uint32_t *, uint32_t *);
 187 #endif
 188         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 189         void            (*erxo_qenable)(efx_rxq_t *);
 190         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 191                                         unsigned int, efx_rxq_type_t,
 192                                         const efx_rxq_type_data_t *,
 193                                         efsys_mem_t *, size_t, uint32_t,
 194                                         unsigned int,
 195                                         efx_evq_t *, efx_rxq_t *);
 196         void            (*erxo_qdestroy)(efx_rxq_t *);
 197 } efx_rx_ops_t;
 198
 199 typedef struct efx_mac_ops_s {
 200         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 201         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 202         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 203         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 204         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 205         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 206         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 207         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 208                                                       efx_rxq_t *, boolean_t);
 209         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 210 #if EFSYS_OPT_LOOPBACK
 211         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 212                                             efx_loopback_type_t);
 213 #endif  /* EFSYS_OPT_LOOPBACK */
 214 #if EFSYS_OPT_MAC_STATS
 215         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 216         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 217         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 218         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 219                                               uint16_t, boolean_t);
 220         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 221                                             efsys_stat_t *, uint32_t *);
 222 #endif  /* EFSYS_OPT_MAC_STATS */
 223 } efx_mac_ops_t;
 224
 225 typedef struct efx_phy_ops_s {
 226         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 227         efx_rc_t        (*epo_reset)(efx_nic_t *);
 228         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 229         efx_rc_t        (*epo_verify)(efx_nic_t *);
 230         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 231         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 232 #if EFSYS_OPT_PHY_STATS
 233         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 234                                             uint32_t *);
 235 #endif  /* EFSYS_OPT_PHY_STATS */
 236 #if EFSYS_OPT_BIST
 237         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 238         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 239         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 240                                          efx_bist_result_t *, uint32_t *,
 241                                          unsigned long *, size_t);
 242         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 243 #endif  /* EFSYS_OPT_BIST */
 244 } efx_phy_ops_t;
 245
 246 #if EFSYS_OPT_FILTER
 247 typedef struct efx_filter_ops_s {
 248         efx_rc_t        (*efo_init)(efx_nic_t *);
 249         void            (*efo_fini)(efx_nic_t *);
 250         efx_rc_t        (*efo_restore)(efx_nic_t *);
 251         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 252                                    boolean_t may_replace);
 253         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 254         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 255                                    size_t, size_t *);
 256         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 257                                    boolean_t, boolean_t, boolean_t,
 258                                    uint8_t const *, uint32_t);
 259 } efx_filter_ops_t;
 260
 261 extern  __checkReturn   efx_rc_t
 262 efx_filter_reconfigure(
 263         __in                            efx_nic_t *enp,
 264         __in_ecount(6)                  uint8_t const *mac_addr,
 265         __in                            boolean_t all_unicst,
 266         __in                            boolean_t mulcst,
 267         __in                            boolean_t all_mulcst,
 268         __in                            boolean_t brdcst,
 269         __in_ecount(6*count)            uint8_t const *addrs,
 270         __in                            uint32_t count);
 271
 272 #endif /* EFSYS_OPT_FILTER */
 273
 274 #if EFSYS_OPT_TUNNEL
 275 typedef struct efx_tunnel_ops_s {
 276         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 277         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 278 } efx_tunnel_ops_t;
 279 #endif /* EFSYS_OPT_TUNNEL */
 280
 281 typedef struct efx_port_s {
 282         efx_mac_type_t          ep_mac_type;
 283         uint32_t                ep_phy_type;
 284         uint8_t                 ep_port;
 285         uint32_t                ep_mac_pdu;
 286         uint8_t                 ep_mac_addr[6];
 287         efx_link_mode_t         ep_link_mode;
 288         boolean_t               ep_all_unicst;
 289         boolean_t               ep_mulcst;
 290         boolean_t               ep_all_mulcst;
 291         boolean_t               ep_brdcst;
 292         unsigned int            ep_fcntl;
 293         boolean_t               ep_fcntl_autoneg;
 294         efx_oword_t             ep_multicst_hash[2];
 295         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 296                                                     EFX_MAC_MULTICAST_LIST_MAX];
 297         uint32_t                ep_mulcst_addr_count;
 298 #if EFSYS_OPT_LOOPBACK
 299         efx_loopback_type_t     ep_loopback_type;
 300         efx_link_mode_t         ep_loopback_link_mode;
 301 #endif  /* EFSYS_OPT_LOOPBACK */
 302 #if EFSYS_OPT_PHY_FLAGS
 303         uint32_t                ep_phy_flags;
 304 #endif  /* EFSYS_OPT_PHY_FLAGS */
 305 #if EFSYS_OPT_PHY_LED_CONTROL
 306         efx_phy_led_mode_t      ep_phy_led_mode;
 307 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 308         efx_phy_media_type_t    ep_fixed_port_type;
 309         efx_phy_media_type_t    ep_module_type;
 310         uint32_t                ep_adv_cap_mask;
 311         uint32_t                ep_lp_cap_mask;
 312         uint32_t                ep_default_adv_cap_mask;
 313         uint32_t                ep_phy_cap_mask;
 314         boolean_t               ep_mac_drain;
 315 #if EFSYS_OPT_BIST
 316         efx_bist_type_t         ep_current_bist;
 317 #endif
 318         const efx_mac_ops_t     *ep_emop;
 319         const efx_phy_ops_t     *ep_epop;
 320 } efx_port_t;
 321
 322 typedef struct efx_mon_ops_s {
 323 #if EFSYS_OPT_MON_STATS
 324         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 325                                             efx_mon_stat_value_t *);
 326         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 327                                              efx_mon_stat_limits_t *);
 328 #endif  /* EFSYS_OPT_MON_STATS */
 329 } efx_mon_ops_t;
 330
 331 typedef struct efx_mon_s {
 332         efx_mon_type_t          em_type;
 333         const efx_mon_ops_t     *em_emop;
 334 } efx_mon_t;
 335
 336 typedef struct efx_intr_ops_s {
 337         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 338         void            (*eio_enable)(efx_nic_t *);
 339         void            (*eio_disable)(efx_nic_t *);
 340         void            (*eio_disable_unlocked)(efx_nic_t *);
 341         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 342         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 343         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 344                                  boolean_t *);
 345         void            (*eio_fatal)(efx_nic_t *);
 346         void            (*eio_fini)(efx_nic_t *);
 347 } efx_intr_ops_t;
 348
 349 typedef struct efx_intr_s {
 350         const efx_intr_ops_t    *ei_eiop;
 351         efsys_mem_t             *ei_esmp;
 352         efx_intr_type_t         ei_type;
 353         unsigned int            ei_level;
 354 } efx_intr_t;
 355
 356 typedef struct efx_nic_ops_s {
 357         efx_rc_t        (*eno_probe)(efx_nic_t *);
 358         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 359         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 360         efx_rc_t        (*eno_reset)(efx_nic_t *);
 361         efx_rc_t        (*eno_init)(efx_nic_t *);
 362         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 363         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 364                                         uint32_t *, size_t *);
 365         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 366         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 367 #if EFSYS_OPT_DIAG
 368         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 369 #endif  /* EFSYS_OPT_DIAG */
 370         void            (*eno_fini)(efx_nic_t *);
 371         void            (*eno_unprobe)(efx_nic_t *);
 372 } efx_nic_ops_t;
 373
 374 #ifndef EFX_TXQ_LIMIT_TARGET
 375 #define EFX_TXQ_LIMIT_TARGET 259
 376 #endif
 377 #ifndef EFX_RXQ_LIMIT_TARGET
 378 #define EFX_RXQ_LIMIT_TARGET 512
 379 #endif
 380
 381
 382 #if EFSYS_OPT_FILTER
 383
 384 #if EFSYS_OPT_SIENA
 385
 386 typedef struct siena_filter_spec_s {
 387         uint8_t         sfs_type;
 388         uint32_t        sfs_flags;
 389         uint32_t        sfs_dmaq_id;
 390         uint32_t        sfs_dword[3];
 391 } siena_filter_spec_t;
 392
 393 typedef enum siena_filter_type_e {
 394         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 395         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 396         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 397         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 398         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 399         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 400
 401         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 402         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 403         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 404         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 405         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 406         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 407
 408         EFX_SIENA_FILTER_NTYPES
 409 } siena_filter_type_t;
 410
 411 typedef enum siena_filter_tbl_id_e {
 412         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 413         EFX_SIENA_FILTER_TBL_RX_MAC,
 414         EFX_SIENA_FILTER_TBL_TX_IP,
 415         EFX_SIENA_FILTER_TBL_TX_MAC,
 416         EFX_SIENA_FILTER_NTBLS
 417 } siena_filter_tbl_id_t;
 418
 419 typedef struct siena_filter_tbl_s {
 420         int                     sft_size;       /* number of entries */
 421         int                     sft_used;       /* active count */
 422         uint32_t                *sft_bitmap;    /* active bitmap */
 423         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 424 } siena_filter_tbl_t;
 425
 426 typedef struct siena_filter_s {
 427         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 428         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 429 } siena_filter_t;
 430
 431 #endif  /* EFSYS_OPT_SIENA */
 432
 433 typedef struct efx_filter_s {
 434 #if EFSYS_OPT_SIENA
 435         siena_filter_t          *ef_siena_filter;
 436 #endif /* EFSYS_OPT_SIENA */
 437 #if EFX_OPTS_EF10()
 438         ef10_filter_table_t     *ef_ef10_filter_table;
 439 #endif /* EFX_OPTS_EF10() */
 440 } efx_filter_t;
 441
 442 #if EFSYS_OPT_SIENA
 443
 444 extern                  void
 445 siena_filter_tbl_clear(
 446         __in            efx_nic_t *enp,
 447         __in            siena_filter_tbl_id_t tbl);
 448
 449 #endif  /* EFSYS_OPT_SIENA */
 450
 451 #endif  /* EFSYS_OPT_FILTER */
 452
 453 #if EFSYS_OPT_MCDI
 454
 455 #define EFX_TUNNEL_MAXNENTRIES  (16)
 456
 457 #if EFSYS_OPT_TUNNEL
 458
 459 typedef struct efx_tunnel_udp_entry_s {
 460         uint16_t                        etue_port; /* host/cpu-endian */
 461         uint16_t                        etue_protocol;
 462 } efx_tunnel_udp_entry_t;
 463
 464 typedef struct efx_tunnel_cfg_s {
 465         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 466         unsigned int            etc_udp_entries_num;
 467 } efx_tunnel_cfg_t;
 468
 469 #endif /* EFSYS_OPT_TUNNEL */
 470
 471 typedef struct efx_mcdi_ops_s {
 472         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 473         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 474                                         void *, size_t);
 475         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 476         boolean_t       (*emco_poll_response)(efx_nic_t *);
 477         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 478         void            (*emco_fini)(efx_nic_t *);
 479         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 480                                             efx_mcdi_feature_id_t, boolean_t *);
 481         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 482                                             uint32_t *);
 483 } efx_mcdi_ops_t;
 484
 485 typedef struct efx_mcdi_s {
 486         const efx_mcdi_ops_t            *em_emcop;
 487         const efx_mcdi_transport_t      *em_emtp;
 488         efx_mcdi_iface_t                em_emip;
 489 } efx_mcdi_t;
 490
 491 #endif /* EFSYS_OPT_MCDI */
 492
 493 #if EFSYS_OPT_NVRAM
 494
 495 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 496 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 497
 498 typedef struct efx_nvram_ops_s {
 499 #if EFSYS_OPT_DIAG
 500         efx_rc_t        (*envo_test)(efx_nic_t *);
 501 #endif  /* EFSYS_OPT_DIAG */
 502         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 503                                             uint32_t *);
 504         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 505                                             efx_nvram_info_t *);
 506         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 507         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 508                                             unsigned int, caddr_t, size_t);
 509         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 510                                             unsigned int, caddr_t, size_t);
 511         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 512                                             unsigned int, size_t);
 513         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 514                                             unsigned int, caddr_t, size_t);
 515         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 516                                             uint32_t *);
 517         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 518                                             uint32_t *, uint16_t *);
 519         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 520                                             uint16_t *);
 521         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 522                                             caddr_t, size_t);
 523 } efx_nvram_ops_t;
 524 #endif /* EFSYS_OPT_NVRAM */
 525
 526 #if EFSYS_OPT_VPD
 527 typedef struct efx_vpd_ops_s {
 528         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 529         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 530         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 531         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 532         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 533         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 534                                         efx_vpd_value_t *);
 535         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 536                                         efx_vpd_value_t *);
 537         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 538                                         efx_vpd_value_t *, unsigned int *);
 539         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 540         void            (*evpdo_fini)(efx_nic_t *);
 541 } efx_vpd_ops_t;
 542 #endif  /* EFSYS_OPT_VPD */
 543
 544 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 545
 546         __checkReturn           efx_rc_t
 547 efx_mcdi_nvram_partitions(
 548         __in                    efx_nic_t *enp,
 549         __out_bcount(size)      caddr_t data,
 550         __in                    size_t size,
 551         __out                   unsigned int *npartnp);
 552
 553         __checkReturn           efx_rc_t
 554 efx_mcdi_nvram_metadata(
 555         __in                    efx_nic_t *enp,
 556         __in                    uint32_t partn,
 557         __out                   uint32_t *subtypep,
 558         __out_ecount(4)         uint16_t version[4],
 559         __out_bcount_opt(size)  char *descp,
 560         __in                    size_t size);
 561
 562         __checkReturn           efx_rc_t
 563 efx_mcdi_nvram_info(
 564         __in                    efx_nic_t *enp,
 565         __in                    uint32_t partn,
 566         __out                   efx_nvram_info_t *eni);
 567
 568         __checkReturn           efx_rc_t
 569 efx_mcdi_nvram_update_start(
 570         __in                    efx_nic_t *enp,
 571         __in                    uint32_t partn);
 572
 573         __checkReturn           efx_rc_t
 574 efx_mcdi_nvram_read(
 575         __in                    efx_nic_t *enp,
 576         __in                    uint32_t partn,
 577         __in                    uint32_t offset,
 578         __out_bcount(size)      caddr_t data,
 579         __in                    size_t size,
 580         __in                    uint32_t mode);
 581
 582         __checkReturn           efx_rc_t
 583 efx_mcdi_nvram_erase(
 584         __in                    efx_nic_t *enp,
 585         __in                    uint32_t partn,
 586         __in                    uint32_t offset,
 587         __in                    size_t size);
 588
 589         __checkReturn           efx_rc_t
 590 efx_mcdi_nvram_write(
 591         __in                    efx_nic_t *enp,
 592         __in                    uint32_t partn,
 593         __in                    uint32_t offset,
 594         __in_bcount(size)       caddr_t data,
 595         __in                    size_t size);
 596
 597 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 598 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 599
 600         __checkReturn           efx_rc_t
 601 efx_mcdi_nvram_update_finish(
 602         __in                    efx_nic_t *enp,
 603         __in                    uint32_t partn,
 604         __in                    boolean_t reboot,
 605         __in                    uint32_t flags,
 606         __out_opt               uint32_t *verify_resultp);
 607
 608 #if EFSYS_OPT_DIAG
 609
 610         __checkReturn           efx_rc_t
 611 efx_mcdi_nvram_test(
 612         __in                    efx_nic_t *enp,
 613         __in                    uint32_t partn);
 614
 615 #endif  /* EFSYS_OPT_DIAG */
 616
 617 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 618
 619 #if EFSYS_OPT_LICENSING
 620
 621 typedef struct efx_lic_ops_s {
 622         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 623         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 624         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 625         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 626                                       size_t *, uint8_t *);
 627         efx_rc_t        (*elo_find_start)
 628                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 629         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 630                                 uint32_t, uint32_t *);
 631         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 632                                 uint32_t, uint32_t *, uint32_t *);
 633         boolean_t       (*elo_validate_key)(efx_nic_t *,
 634                                 caddr_t, uint32_t);
 635         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 636                                 caddr_t, size_t, uint32_t, uint32_t,
 637                                 caddr_t, size_t, uint32_t *);
 638         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 639                                 caddr_t, size_t, uint32_t,
 640                                 caddr_t, uint32_t, uint32_t *);
 641         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 642                                 caddr_t, size_t, uint32_t,
 643                                 uint32_t, uint32_t, uint32_t *);
 644         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 645                                 caddr_t, size_t);
 646         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 647                                 caddr_t, size_t);
 648 } efx_lic_ops_t;
 649
 650 #endif
 651
 652 #define EFX_DRV_VER_MAX         20
 653
 654 typedef struct efx_drv_cfg_s {
 655         uint32_t                edc_min_vi_count;
 656         uint32_t                edc_max_vi_count;
 657
 658         uint32_t                edc_max_piobuf_count;
 659         uint32_t                edc_pio_alloc_size;
 660 } efx_drv_cfg_t;
 661
 662 struct efx_nic_s {
 663         uint32_t                en_magic;
 664         efx_family_t            en_family;
 665         uint32_t                en_features;
 666         efsys_identifier_t      *en_esip;
 667         efsys_lock_t            *en_eslp;
 668         efsys_bar_t             *en_esbp;
 669         unsigned int            en_mod_flags;
 670         unsigned int            en_reset_flags;
 671         efx_nic_cfg_t           en_nic_cfg;
 672         efx_drv_cfg_t           en_drv_cfg;
 673         efx_port_t              en_port;
 674         efx_mon_t               en_mon;
 675         efx_intr_t              en_intr;
 676         uint32_t                en_ev_qcount;
 677         uint32_t                en_rx_qcount;
 678         uint32_t                en_tx_qcount;
 679         const efx_nic_ops_t     *en_enop;
 680         const efx_ev_ops_t      *en_eevop;
 681         const efx_tx_ops_t      *en_etxop;
 682         const efx_rx_ops_t      *en_erxop;
 683         efx_fw_variant_t        efv;
 684         char                    en_drv_version[EFX_DRV_VER_MAX];
 685 #if EFSYS_OPT_FILTER
 686         efx_filter_t            en_filter;
 687         const efx_filter_ops_t  *en_efop;
 688 #endif  /* EFSYS_OPT_FILTER */
 689 #if EFSYS_OPT_TUNNEL
 690         efx_tunnel_cfg_t        en_tunnel_cfg;
 691         const efx_tunnel_ops_t  *en_etop;
 692 #endif /* EFSYS_OPT_TUNNEL */
 693 #if EFSYS_OPT_MCDI
 694         efx_mcdi_t              en_mcdi;
 695 #endif  /* EFSYS_OPT_MCDI */
 696 #if EFSYS_OPT_NVRAM
 697         uint32_t                en_nvram_partn_locked;
 698         const efx_nvram_ops_t   *en_envop;
 699 #endif  /* EFSYS_OPT_NVRAM */
 700 #if EFSYS_OPT_VPD
 701         const efx_vpd_ops_t     *en_evpdop;
 702 #endif  /* EFSYS_OPT_VPD */
 703 #if EFSYS_OPT_RX_SCALE
 704         efx_rx_hash_support_t           en_hash_support;
 705         efx_rx_scale_context_type_t     en_rss_context_type;
 706         uint32_t                        en_rss_context;
 707 #endif  /* EFSYS_OPT_RX_SCALE */
 708         uint32_t                en_vport_id;
 709 #if EFSYS_OPT_LICENSING
 710         const efx_lic_ops_t     *en_elop;
 711         boolean_t               en_licensing_supported;
 712 #endif
 713         union {
 714 #if EFSYS_OPT_SIENA
 715                 struct {
 716 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 717                         unsigned int            enu_partn_mask;
 718 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 719 #if EFSYS_OPT_VPD
 720                         caddr_t                 enu_svpd;
 721                         size_t                  enu_svpd_length;
 722 #endif  /* EFSYS_OPT_VPD */
 723                         int                     enu_unused;
 724                 } siena;
 725 #endif  /* EFSYS_OPT_SIENA */
 726                 int     enu_unused;
 727         } en_u;
 728 #if EFX_OPTS_EF10()
 729         union en_arch {
 730                 struct {
 731                         int                     ena_vi_base;
 732                         int                     ena_vi_count;
 733                         int                     ena_vi_shift;
 734 #if EFSYS_OPT_VPD
 735                         caddr_t                 ena_svpd;
 736                         size_t                  ena_svpd_length;
 737 #endif  /* EFSYS_OPT_VPD */
 738                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 739                         uint32_t                ena_piobuf_count;
 740                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 741                         uint32_t                ena_pio_write_vi_base;
 742                         /* Memory BAR mapping regions */
 743                         uint32_t                ena_uc_mem_map_offset;
 744                         size_t                  ena_uc_mem_map_size;
 745                         uint32_t                ena_wc_mem_map_offset;
 746                         size_t                  ena_wc_mem_map_size;
 747                 } ef10;
 748         } en_arch;
 749 #endif  /* EFX_OPTS_EF10() */
 750 };
 751
 752 #define EFX_FAMILY_IS_EF10(_enp) \
 753         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 754          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 755          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 756
 757
 758 #define EFX_NIC_MAGIC   0x02121996
 759
 760 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 761     const efx_ev_callbacks_t *, void *);
 762
 763 typedef struct efx_evq_rxq_state_s {
 764         unsigned int                    eers_rx_read_ptr;
 765         unsigned int                    eers_rx_mask;
 766 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 767         unsigned int                    eers_rx_stream_npackets;
 768         boolean_t                       eers_rx_packed_stream;
 769 #endif
 770 #if EFSYS_OPT_RX_PACKED_STREAM
 771         unsigned int                    eers_rx_packed_stream_credits;
 772 #endif
 773 } efx_evq_rxq_state_t;
 774
 775 struct efx_evq_s {
 776         uint32_t                        ee_magic;
 777         uint32_t                        ee_flags;
 778         efx_nic_t                       *ee_enp;
 779         unsigned int                    ee_index;
 780         unsigned int                    ee_mask;
 781         efsys_mem_t                     *ee_esmp;
 782 #if EFSYS_OPT_QSTATS
 783         uint32_t                        ee_stat[EV_NQSTATS];
 784 #endif  /* EFSYS_OPT_QSTATS */
 785
 786         efx_ev_handler_t                ee_rx;
 787         efx_ev_handler_t                ee_tx;
 788         efx_ev_handler_t                ee_driver;
 789         efx_ev_handler_t                ee_global;
 790         efx_ev_handler_t                ee_drv_gen;
 791 #if EFSYS_OPT_MCDI
 792         efx_ev_handler_t                ee_mcdi;
 793 #endif  /* EFSYS_OPT_MCDI */
 794
 795         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 796 };
 797
 798 #define EFX_EVQ_MAGIC   0x08081997
 799
 800 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 801
 802 #if EFSYS_OPT_QSTATS
 803 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
 804         do {                                                            \
 805                 (_eep)->ee_stat[_stat]++;                               \
 806         _NOTE(CONSTANTCONDITION)                                        \
 807         } while (B_FALSE)
 808 #else
 809 #define EFX_EV_QSTAT_INCR(_eep, _stat)
 810 #endif
 811
 812 struct efx_rxq_s {
 813         uint32_t                        er_magic;
 814         efx_nic_t                       *er_enp;
 815         efx_evq_t                       *er_eep;
 816         unsigned int                    er_index;
 817         unsigned int                    er_label;
 818         unsigned int                    er_mask;
 819         size_t                          er_buf_size;
 820         efsys_mem_t                     *er_esmp;
 821         efx_evq_rxq_state_t             *er_ev_qstate;
 822 };
 823
 824 #define EFX_RXQ_MAGIC   0x15022005
 825
 826 struct efx_txq_s {
 827         uint32_t                        et_magic;
 828         efx_nic_t                       *et_enp;
 829         unsigned int                    et_index;
 830         unsigned int                    et_mask;
 831         efsys_mem_t                     *et_esmp;
 832 #if EFSYS_OPT_HUNTINGTON
 833         uint32_t                        et_pio_bufnum;
 834         uint32_t                        et_pio_blknum;
 835         uint32_t                        et_pio_write_offset;
 836         uint32_t                        et_pio_offset;
 837         size_t                          et_pio_size;
 838 #endif
 839 #if EFSYS_OPT_QSTATS
 840         uint32_t                        et_stat[TX_NQSTATS];
 841 #endif  /* EFSYS_OPT_QSTATS */
 842 };
 843
 844 #define EFX_TXQ_MAGIC   0x05092005
 845
 846 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 847         do {                                                            \
 848                 (_dst)[0] = (_src)[0];                                  \
 849                 (_dst)[1] = (_src)[1];                                  \
 850                 (_dst)[2] = (_src)[2];                                  \
 851                 (_dst)[3] = (_src)[3];                                  \
 852                 (_dst)[4] = (_src)[4];                                  \
 853                 (_dst)[5] = (_src)[5];                                  \
 854         _NOTE(CONSTANTCONDITION)                                        \
 855         } while (B_FALSE)
 856
 857 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 858         do {                                                            \
 859                 uint16_t *_d = (uint16_t *)(_dst);                      \
 860                 _d[0] = 0xffff;                                         \
 861                 _d[1] = 0xffff;                                         \
 862                 _d[2] = 0xffff;                                         \
 863         _NOTE(CONSTANTCONDITION)                                        \
 864         } while (B_FALSE)
 865
 866 #if EFSYS_OPT_CHECK_REG
 867 #define EFX_CHECK_REG(_enp, _reg)                                       \
 868         do {                                                            \
 869                 const char *name = #_reg;                               \
 870                 char min = name[4];                                     \
 871                 char max = name[5];                                     \
 872                 char rev;                                               \
 873                                                                         \
 874                 switch ((_enp)->en_family) {                            \
 875                 case EFX_FAMILY_SIENA:                                  \
 876                         rev = 'C';                                      \
 877                         break;                                          \
 878                                                                         \
 879                 case EFX_FAMILY_HUNTINGTON:                             \
 880                         rev = 'D';                                      \
 881                         break;                                          \
 882                                                                         \
 883                 case EFX_FAMILY_MEDFORD:                                \
 884                         rev = 'E';                                      \
 885                         break;                                          \
 886                                                                         \
 887                 case EFX_FAMILY_MEDFORD2:                               \
 888                         rev = 'F';                                      \
 889                         break;                                          \
 890                                                                         \
 891                 default:                                                \
 892                         rev = '?';                                      \
 893                         break;                                          \
 894                 }                                                       \
 895                                                                         \
 896                 EFSYS_ASSERT3S(rev, >=, min);                           \
 897                 EFSYS_ASSERT3S(rev, <=, max);                           \
 898                                                                         \
 899         _NOTE(CONSTANTCONDITION)                                        \
 900         } while (B_FALSE)
 901 #else
 902 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 903         _NOTE(CONSTANTCONDITION)                                        \
 904         } while (B_FALSE)
 905 #endif
 906
 907 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 908         do {                                                            \
 909                 EFX_CHECK_REG((_enp), (_reg));                          \
 910                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 911                     (_edp), (_lock));                                   \
 912                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 913                     uint32_t, _reg ## _OFST,                            \
 914                     uint32_t, (_edp)->ed_u32[0]);                       \
 915         _NOTE(CONSTANTCONDITION)                                        \
 916         } while (B_FALSE)
 917
 918 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 919         do {                                                            \
 920                 EFX_CHECK_REG((_enp), (_reg));                          \
 921                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 922                     uint32_t, _reg ## _OFST,                            \
 923                     uint32_t, (_edp)->ed_u32[0]);                       \
 924                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 925                     (_edp), (_lock));                                   \
 926         _NOTE(CONSTANTCONDITION)                                        \
 927         } while (B_FALSE)
 928
 929 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 930         do {                                                            \
 931                 EFX_CHECK_REG((_enp), (_reg));                          \
 932                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 933                     (_eqp));                                            \
 934                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 935                     uint32_t, _reg ## _OFST,                            \
 936                     uint32_t, (_eqp)->eq_u32[1],                        \
 937                     uint32_t, (_eqp)->eq_u32[0]);                       \
 938         _NOTE(CONSTANTCONDITION)                                        \
 939         } while (B_FALSE)
 940
 941 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 942         do {                                                            \
 943                 EFX_CHECK_REG((_enp), (_reg));                          \
 944                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 945                     uint32_t, _reg ## _OFST,                            \
 946                     uint32_t, (_eqp)->eq_u32[1],                        \
 947                     uint32_t, (_eqp)->eq_u32[0]);                       \
 948                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 949                     (_eqp));                                            \
 950         _NOTE(CONSTANTCONDITION)                                        \
 951         } while (B_FALSE)
 952
 953 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 954         do {                                                            \
 955                 EFX_CHECK_REG((_enp), (_reg));                          \
 956                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 957                     (_eop), B_TRUE);                                    \
 958                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 959                     uint32_t, _reg ## _OFST,                            \
 960                     uint32_t, (_eop)->eo_u32[3],                        \
 961                     uint32_t, (_eop)->eo_u32[2],                        \
 962                     uint32_t, (_eop)->eo_u32[1],                        \
 963                     uint32_t, (_eop)->eo_u32[0]);                       \
 964         _NOTE(CONSTANTCONDITION)                                        \
 965         } while (B_FALSE)
 966
 967 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 968         do {                                                            \
 969                 EFX_CHECK_REG((_enp), (_reg));                          \
 970                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 971                     uint32_t, _reg ## _OFST,                            \
 972                     uint32_t, (_eop)->eo_u32[3],                        \
 973                     uint32_t, (_eop)->eo_u32[2],                        \
 974                     uint32_t, (_eop)->eo_u32[1],                        \
 975                     uint32_t, (_eop)->eo_u32[0]);                       \
 976                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 977                     (_eop), B_TRUE);                                    \
 978         _NOTE(CONSTANTCONDITION)                                        \
 979         } while (B_FALSE)
 980
 981 /*
 982  * Accessors for memory BAR non-VI tables.
 983  *
 984  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
 985  * to ensure the correct runtime VI window size is used on Medford2.
 986  *
 987  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
 988  */
 989
 990 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 991         do {                                                            \
 992                 EFX_CHECK_REG((_enp), (_reg));                          \
 993                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 994                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 995                     (_edp), (_lock));                                   \
 996                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 997                     uint32_t, (_index),                                 \
 998                     uint32_t, _reg ## _OFST,                            \
 999                     uint32_t, (_edp)->ed_u32[0]);                       \
1000         _NOTE(CONSTANTCONDITION)                                        \
1001         } while (B_FALSE)
1002
1003 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1004         do {                                                            \
1005                 EFX_CHECK_REG((_enp), (_reg));                          \
1006                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1007                     uint32_t, (_index),                                 \
1008                     uint32_t, _reg ## _OFST,                            \
1009                     uint32_t, (_edp)->ed_u32[0]);                       \
1010                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1011                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1012                     (_edp), (_lock));                                   \
1013         _NOTE(CONSTANTCONDITION)                                        \
1014         } while (B_FALSE)
1015
1016 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1017         do {                                                            \
1018                 EFX_CHECK_REG((_enp), (_reg));                          \
1019                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1020                     uint32_t, (_index),                                 \
1021                     uint32_t, _reg ## _OFST,                            \
1022                     uint32_t, (_edp)->ed_u32[0]);                       \
1023                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1024                     (_reg ## _OFST +                                    \
1025                     (3 * sizeof (efx_dword_t)) +                        \
1026                     ((_index) * _reg ## _STEP)),                        \
1027                     (_edp), (_lock));                                   \
1028         _NOTE(CONSTANTCONDITION)                                        \
1029         } while (B_FALSE)
1030
1031 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1032         do {                                                            \
1033                 EFX_CHECK_REG((_enp), (_reg));                          \
1034                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1035                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1036                     (_eqp));                                            \
1037                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1038                     uint32_t, (_index),                                 \
1039                     uint32_t, _reg ## _OFST,                            \
1040                     uint32_t, (_eqp)->eq_u32[1],                        \
1041                     uint32_t, (_eqp)->eq_u32[0]);                       \
1042         _NOTE(CONSTANTCONDITION)                                        \
1043         } while (B_FALSE)
1044
1045 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1046         do {                                                            \
1047                 EFX_CHECK_REG((_enp), (_reg));                          \
1048                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1049                     uint32_t, (_index),                                 \
1050                     uint32_t, _reg ## _OFST,                            \
1051                     uint32_t, (_eqp)->eq_u32[1],                        \
1052                     uint32_t, (_eqp)->eq_u32[0]);                       \
1053                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1054                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1055                     (_eqp));                                            \
1056         _NOTE(CONSTANTCONDITION)                                        \
1057         } while (B_FALSE)
1058
1059 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1060         do {                                                            \
1061                 EFX_CHECK_REG((_enp), (_reg));                          \
1062                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1063                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1064                     (_eop), (_lock));                                   \
1065                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1066                     uint32_t, (_index),                                 \
1067                     uint32_t, _reg ## _OFST,                            \
1068                     uint32_t, (_eop)->eo_u32[3],                        \
1069                     uint32_t, (_eop)->eo_u32[2],                        \
1070                     uint32_t, (_eop)->eo_u32[1],                        \
1071                     uint32_t, (_eop)->eo_u32[0]);                       \
1072         _NOTE(CONSTANTCONDITION)                                        \
1073         } while (B_FALSE)
1074
1075 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1076         do {                                                            \
1077                 EFX_CHECK_REG((_enp), (_reg));                          \
1078                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1079                     uint32_t, (_index),                                 \
1080                     uint32_t, _reg ## _OFST,                            \
1081                     uint32_t, (_eop)->eo_u32[3],                        \
1082                     uint32_t, (_eop)->eo_u32[2],                        \
1083                     uint32_t, (_eop)->eo_u32[1],                        \
1084                     uint32_t, (_eop)->eo_u32[0]);                       \
1085                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1086                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1087                     (_eop), (_lock));                                   \
1088         _NOTE(CONSTANTCONDITION)                                        \
1089         } while (B_FALSE)
1090
1091 /*
1092  * Accessors for memory BAR per-VI registers.
1093  *
1094  * The VI window size is 8KB for Medford and all earlier controllers.
1095  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1096  */
1097
1098 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1099         do {                                                            \
1100                 EFX_CHECK_REG((_enp), (_reg));                          \
1101                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1102                     ((_reg ## _OFST) +                                  \
1103                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1104                     (_edp), (_lock));                                   \
1105                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1106                     uint32_t, (_index),                                 \
1107                     uint32_t, _reg ## _OFST,                            \
1108                     uint32_t, (_edp)->ed_u32[0]);                       \
1109         _NOTE(CONSTANTCONDITION)                                        \
1110         } while (B_FALSE)
1111
1112 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1113         do {                                                            \
1114                 EFX_CHECK_REG((_enp), (_reg));                          \
1115                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1116                     uint32_t, (_index),                                 \
1117                     uint32_t, _reg ## _OFST,                            \
1118                     uint32_t, (_edp)->ed_u32[0]);                       \
1119                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1120                     ((_reg ## _OFST) +                                  \
1121                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1122                     (_edp), (_lock));                                   \
1123         _NOTE(CONSTANTCONDITION)                                        \
1124         } while (B_FALSE)
1125
1126 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1127         do {                                                            \
1128                 EFX_CHECK_REG((_enp), (_reg));                          \
1129                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1130                     uint32_t, (_index),                                 \
1131                     uint32_t, _reg ## _OFST,                            \
1132                     uint32_t, (_edp)->ed_u32[0]);                       \
1133                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1134                     ((_reg ## _OFST) +                                  \
1135                     (2 * sizeof (efx_dword_t)) +                        \
1136                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1137                     (_edp), (_lock));                                   \
1138         _NOTE(CONSTANTCONDITION)                                        \
1139         } while (B_FALSE)
1140
1141 /*
1142  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1143  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1144  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1145  * the need for locking in the host, and are the only ones known to be safe to
1146  * use 128-bites write with.
1147  */
1148 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1149         do {                                                            \
1150                 EFX_CHECK_REG((_enp), (_reg));                          \
1151                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1152                     const char *, #_reg,                                \
1153                     uint32_t, (_index),                                 \
1154                     uint32_t, _reg ## _OFST,                            \
1155                     uint32_t, (_eop)->eo_u32[3],                        \
1156                     uint32_t, (_eop)->eo_u32[2],                        \
1157                     uint32_t, (_eop)->eo_u32[1],                        \
1158                     uint32_t, (_eop)->eo_u32[0]);                       \
1159                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1160                     (_reg ## _OFST +                                    \
1161                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1162                     (_eop));                                            \
1163         _NOTE(CONSTANTCONDITION)                                        \
1164         } while (B_FALSE)
1165
1166 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1167         do {                                                            \
1168                 unsigned int _new = (_wptr);                            \
1169                 unsigned int _old = (_owptr);                           \
1170                                                                         \
1171                 if ((_new) >= (_old))                                   \
1172                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1173                             (_old) * sizeof (efx_desc_t),               \
1174                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1175                 else                                                    \
1176                         /*                                              \
1177                          * It is cheaper to sync entire map than sync   \
1178                          * two parts especially when offset/size are    \
1179                          * ignored and entire map is synced in any case.\
1180                          */                                             \
1181                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1182                             0,                                          \
1183                             (_entries) * sizeof (efx_desc_t));          \
1184         _NOTE(CONSTANTCONDITION)                                        \
1185         } while (B_FALSE)
1186
1187 extern  __checkReturn   efx_rc_t
1188 efx_mac_select(
1189         __in            efx_nic_t *enp);
1190
1191 extern  void
1192 efx_mac_multicast_hash_compute(
1193         __in_ecount(6*count)            uint8_t const *addrs,
1194         __in                            int count,
1195         __out                           efx_oword_t *hash_low,
1196         __out                           efx_oword_t *hash_high);
1197
1198 extern  __checkReturn   efx_rc_t
1199 efx_phy_probe(
1200         __in            efx_nic_t *enp);
1201
1202 extern                  void
1203 efx_phy_unprobe(
1204         __in            efx_nic_t *enp);
1205
1206 #if EFSYS_OPT_VPD
1207
1208 /* VPD utility functions */
1209
1210 extern  __checkReturn           efx_rc_t
1211 efx_vpd_hunk_length(
1212         __in_bcount(size)       caddr_t data,
1213         __in                    size_t size,
1214         __out                   size_t *lengthp);
1215
1216 extern  __checkReturn           efx_rc_t
1217 efx_vpd_hunk_verify(
1218         __in_bcount(size)       caddr_t data,
1219         __in                    size_t size,
1220         __out_opt               boolean_t *cksummedp);
1221
1222 extern  __checkReturn           efx_rc_t
1223 efx_vpd_hunk_reinit(
1224         __in_bcount(size)       caddr_t data,
1225         __in                    size_t size,
1226         __in                    boolean_t wantpid);
1227
1228 extern  __checkReturn           efx_rc_t
1229 efx_vpd_hunk_get(
1230         __in_bcount(size)       caddr_t data,
1231         __in                    size_t size,
1232         __in                    efx_vpd_tag_t tag,
1233         __in                    efx_vpd_keyword_t keyword,
1234         __out                   unsigned int *payloadp,
1235         __out                   uint8_t *paylenp);
1236
1237 extern  __checkReturn                   efx_rc_t
1238 efx_vpd_hunk_next(
1239         __in_bcount(size)               caddr_t data,
1240         __in                            size_t size,
1241         __out                           efx_vpd_tag_t *tagp,
1242         __out                           efx_vpd_keyword_t *keyword,
1243         __out_opt                       unsigned int *payloadp,
1244         __out_opt                       uint8_t *paylenp,
1245         __inout                         unsigned int *contp);
1246
1247 extern  __checkReturn           efx_rc_t
1248 efx_vpd_hunk_set(
1249         __in_bcount(size)       caddr_t data,
1250         __in                    size_t size,
1251         __in                    efx_vpd_value_t *evvp);
1252
1253 #endif  /* EFSYS_OPT_VPD */
1254
1255 #if EFSYS_OPT_MCDI
1256
1257 extern  __checkReturn           efx_rc_t
1258 efx_mcdi_set_workaround(
1259         __in                    efx_nic_t *enp,
1260         __in                    uint32_t type,
1261         __in                    boolean_t enabled,
1262         __out_opt               uint32_t *flagsp);
1263
1264 extern  __checkReturn           efx_rc_t
1265 efx_mcdi_get_workarounds(
1266         __in                    efx_nic_t *enp,
1267         __out_opt               uint32_t *implementedp,
1268         __out_opt               uint32_t *enabledp);
1269
1270 #endif /* EFSYS_OPT_MCDI */
1271
1272 #if EFSYS_OPT_MAC_STATS
1273
1274 /*
1275  * Closed range of stats (i.e. the first and the last are included).
1276  * The last must be greater or equal (if the range is one item only) to
1277  * the first.
1278  */
1279 struct efx_mac_stats_range {
1280         efx_mac_stat_t          first;
1281         efx_mac_stat_t          last;
1282 };
1283
1284 extern                                  efx_rc_t
1285 efx_mac_stats_mask_add_ranges(
1286         __inout_bcount(mask_size)       uint32_t *maskp,
1287         __in                            size_t mask_size,
1288         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1289         __in                            unsigned int rng_count);
1290
1291 #endif  /* EFSYS_OPT_MAC_STATS */
1292
1293 #ifdef  __cplusplus
1294 }
1295 #endif
1296
1297 #endif  /* _SYS_EFX_IMPL_H */