2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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31 #ifndef _SYS_EFX_IMPL_H
32 #define _SYS_EFX_IMPL_H
36 #include "efx_regs_ef10.h"
38 /* FIXME: Add definition for driver generated software events */
39 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
40 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
48 #define EFX_MOD_MCDI 0x00000001
49 #define EFX_MOD_PROBE 0x00000002
50 #define EFX_MOD_NVRAM 0x00000004
51 #define EFX_MOD_VPD 0x00000008
52 #define EFX_MOD_NIC 0x00000010
53 #define EFX_MOD_INTR 0x00000020
54 #define EFX_MOD_EV 0x00000040
55 #define EFX_MOD_RX 0x00000080
56 #define EFX_MOD_TX 0x00000100
57 #define EFX_MOD_PORT 0x00000200
58 #define EFX_MOD_MON 0x00000400
59 #define EFX_MOD_FILTER 0x00001000
60 #define EFX_MOD_LIC 0x00002000
62 #define EFX_RESET_PHY 0x00000001
63 #define EFX_RESET_RXQ_ERR 0x00000002
64 #define EFX_RESET_TXQ_ERR 0x00000004
66 typedef enum efx_mac_type_e {
74 typedef struct efx_ev_ops_s {
75 efx_rc_t (*eevo_init)(efx_nic_t *);
76 void (*eevo_fini)(efx_nic_t *);
77 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int,
78 efsys_mem_t *, size_t, uint32_t,
79 uint32_t, uint32_t, efx_evq_t *);
80 void (*eevo_qdestroy)(efx_evq_t *);
81 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int);
82 void (*eevo_qpost)(efx_evq_t *, uint16_t);
83 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int);
86 typedef struct efx_tx_ops_s {
87 efx_rc_t (*etxo_init)(efx_nic_t *);
88 void (*etxo_fini)(efx_nic_t *);
89 efx_rc_t (*etxo_qcreate)(efx_nic_t *,
90 unsigned int, unsigned int,
91 efsys_mem_t *, size_t,
93 efx_evq_t *, efx_txq_t *,
95 void (*etxo_qdestroy)(efx_txq_t *);
96 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
97 unsigned int, unsigned int,
99 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
100 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int);
101 efx_rc_t (*etxo_qflush)(efx_txq_t *);
102 void (*etxo_qenable)(efx_txq_t *);
103 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *);
104 void (*etxo_qpio_disable)(efx_txq_t *);
105 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
107 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
109 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
110 unsigned int, unsigned int,
112 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
115 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
118 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
121 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
125 typedef struct efx_rx_ops_s {
126 efx_rc_t (*erxo_init)(efx_nic_t *);
127 void (*erxo_fini)(efx_nic_t *);
128 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
130 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
131 unsigned int, unsigned int,
133 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
134 efx_rc_t (*erxo_qflush)(efx_rxq_t *);
135 void (*erxo_qenable)(efx_rxq_t *);
136 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
137 unsigned int, efx_rxq_type_t,
138 efsys_mem_t *, size_t, uint32_t,
139 efx_evq_t *, efx_rxq_t *);
140 void (*erxo_qdestroy)(efx_rxq_t *);
143 typedef struct efx_mac_ops_s {
144 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
145 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *);
146 efx_rc_t (*emo_addr_set)(efx_nic_t *);
147 efx_rc_t (*emo_pdu_set)(efx_nic_t *);
148 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *);
149 efx_rc_t (*emo_reconfigure)(efx_nic_t *);
150 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *);
151 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *,
152 efx_rxq_t *, boolean_t);
153 void (*emo_filter_default_rxq_clear)(efx_nic_t *);
156 typedef struct efx_phy_ops_s {
157 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */
158 efx_rc_t (*epo_reset)(efx_nic_t *);
159 efx_rc_t (*epo_reconfigure)(efx_nic_t *);
160 efx_rc_t (*epo_verify)(efx_nic_t *);
161 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *);
165 typedef struct efx_port_s {
166 efx_mac_type_t ep_mac_type;
167 uint32_t ep_phy_type;
170 uint8_t ep_mac_addr[6];
171 efx_link_mode_t ep_link_mode;
172 boolean_t ep_all_unicst;
174 boolean_t ep_all_mulcst;
176 unsigned int ep_fcntl;
177 boolean_t ep_fcntl_autoneg;
178 efx_oword_t ep_multicst_hash[2];
179 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
180 EFX_MAC_MULTICAST_LIST_MAX];
181 uint32_t ep_mulcst_addr_count;
182 efx_phy_media_type_t ep_fixed_port_type;
183 efx_phy_media_type_t ep_module_type;
184 uint32_t ep_adv_cap_mask;
185 uint32_t ep_lp_cap_mask;
186 uint32_t ep_default_adv_cap_mask;
187 uint32_t ep_phy_cap_mask;
188 boolean_t ep_mac_drain;
189 boolean_t ep_mac_stats_pending;
190 const efx_mac_ops_t *ep_emop;
191 const efx_phy_ops_t *ep_epop;
194 typedef struct efx_mon_ops_s {
197 typedef struct efx_mon_s {
198 efx_mon_type_t em_type;
199 const efx_mon_ops_t *em_emop;
202 typedef struct efx_intr_ops_s {
203 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
204 void (*eio_enable)(efx_nic_t *);
205 void (*eio_disable)(efx_nic_t *);
206 void (*eio_disable_unlocked)(efx_nic_t *);
207 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int);
208 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
209 void (*eio_status_message)(efx_nic_t *, unsigned int,
211 void (*eio_fatal)(efx_nic_t *);
212 void (*eio_fini)(efx_nic_t *);
215 typedef struct efx_intr_s {
216 const efx_intr_ops_t *ei_eiop;
217 efsys_mem_t *ei_esmp;
218 efx_intr_type_t ei_type;
219 unsigned int ei_level;
222 typedef struct efx_nic_ops_s {
223 efx_rc_t (*eno_probe)(efx_nic_t *);
224 efx_rc_t (*eno_board_cfg)(efx_nic_t *);
225 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
226 efx_rc_t (*eno_reset)(efx_nic_t *);
227 efx_rc_t (*eno_init)(efx_nic_t *);
228 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
229 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
230 uint32_t *, size_t *);
231 void (*eno_fini)(efx_nic_t *);
232 void (*eno_unprobe)(efx_nic_t *);
235 #ifndef EFX_TXQ_LIMIT_TARGET
236 #define EFX_TXQ_LIMIT_TARGET 259
238 #ifndef EFX_RXQ_LIMIT_TARGET
239 #define EFX_RXQ_LIMIT_TARGET 512
241 #ifndef EFX_TXQ_DC_SIZE
242 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
244 #ifndef EFX_RXQ_DC_SIZE
245 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
248 typedef struct efx_drv_cfg_s {
249 uint32_t edc_min_vi_count;
250 uint32_t edc_max_vi_count;
252 uint32_t edc_max_piobuf_count;
253 uint32_t edc_pio_alloc_size;
258 efx_family_t en_family;
259 uint32_t en_features;
260 efsys_identifier_t *en_esip;
261 efsys_lock_t *en_eslp;
262 efsys_bar_t *en_esbp;
263 unsigned int en_mod_flags;
264 unsigned int en_reset_flags;
265 efx_nic_cfg_t en_nic_cfg;
266 efx_drv_cfg_t en_drv_cfg;
270 uint32_t en_ev_qcount;
271 uint32_t en_rx_qcount;
272 uint32_t en_tx_qcount;
273 const efx_nic_ops_t *en_enop;
274 const efx_ev_ops_t *en_eevop;
275 const efx_tx_ops_t *en_etxop;
276 const efx_rx_ops_t *en_erxop;
277 uint32_t en_vport_id;
284 #define EFX_NIC_MAGIC 0x02121996
286 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
287 const efx_ev_callbacks_t *, void *);
289 typedef struct efx_evq_rxq_state_s {
290 unsigned int eers_rx_read_ptr;
291 unsigned int eers_rx_mask;
292 } efx_evq_rxq_state_t;
297 unsigned int ee_index;
298 unsigned int ee_mask;
299 efsys_mem_t *ee_esmp;
301 efx_ev_handler_t ee_rx;
302 efx_ev_handler_t ee_tx;
303 efx_ev_handler_t ee_driver;
304 efx_ev_handler_t ee_global;
305 efx_ev_handler_t ee_drv_gen;
307 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS];
312 #define EFX_EVQ_MAGIC 0x08081997
314 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
320 unsigned int er_index;
321 unsigned int er_label;
322 unsigned int er_mask;
323 efsys_mem_t *er_esmp;
326 #define EFX_RXQ_MAGIC 0x15022005
331 unsigned int et_index;
332 unsigned int et_mask;
333 efsys_mem_t *et_esmp;
336 #define EFX_TXQ_MAGIC 0x05092005
338 #define EFX_MAC_ADDR_COPY(_dst, _src) \
340 (_dst)[0] = (_src)[0]; \
341 (_dst)[1] = (_src)[1]; \
342 (_dst)[2] = (_src)[2]; \
343 (_dst)[3] = (_src)[3]; \
344 (_dst)[4] = (_src)[4]; \
345 (_dst)[5] = (_src)[5]; \
346 _NOTE(CONSTANTCONDITION) \
349 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \
351 uint16_t *_d = (uint16_t *)(_dst); \
355 _NOTE(CONSTANTCONDITION) \
358 #if EFSYS_OPT_CHECK_REG
359 #define EFX_CHECK_REG(_enp, _reg) \
361 const char *name = #_reg; \
362 char min = name[4]; \
363 char max = name[5]; \
366 switch ((_enp)->en_family) { \
367 case EFX_FAMILY_SIENA: \
371 case EFX_FAMILY_HUNTINGTON: \
375 case EFX_FAMILY_MEDFORD: \
384 EFSYS_ASSERT3S(rev, >=, min); \
385 EFSYS_ASSERT3S(rev, <=, max); \
387 _NOTE(CONSTANTCONDITION) \
390 #define EFX_CHECK_REG(_enp, _reg) do { \
391 _NOTE(CONSTANTCONDITION) \
395 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
397 EFX_CHECK_REG((_enp), (_reg)); \
398 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
400 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
401 uint32_t, _reg ## _OFST, \
402 uint32_t, (_edp)->ed_u32[0]); \
403 _NOTE(CONSTANTCONDITION) \
406 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
408 EFX_CHECK_REG((_enp), (_reg)); \
409 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
410 uint32_t, _reg ## _OFST, \
411 uint32_t, (_edp)->ed_u32[0]); \
412 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
414 _NOTE(CONSTANTCONDITION) \
417 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
419 EFX_CHECK_REG((_enp), (_reg)); \
420 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
422 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
423 uint32_t, _reg ## _OFST, \
424 uint32_t, (_eqp)->eq_u32[1], \
425 uint32_t, (_eqp)->eq_u32[0]); \
426 _NOTE(CONSTANTCONDITION) \
429 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
431 EFX_CHECK_REG((_enp), (_reg)); \
432 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
433 uint32_t, _reg ## _OFST, \
434 uint32_t, (_eqp)->eq_u32[1], \
435 uint32_t, (_eqp)->eq_u32[0]); \
436 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
438 _NOTE(CONSTANTCONDITION) \
441 #define EFX_BAR_READO(_enp, _reg, _eop) \
443 EFX_CHECK_REG((_enp), (_reg)); \
444 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
446 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
447 uint32_t, _reg ## _OFST, \
448 uint32_t, (_eop)->eo_u32[3], \
449 uint32_t, (_eop)->eo_u32[2], \
450 uint32_t, (_eop)->eo_u32[1], \
451 uint32_t, (_eop)->eo_u32[0]); \
452 _NOTE(CONSTANTCONDITION) \
455 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
457 EFX_CHECK_REG((_enp), (_reg)); \
458 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
459 uint32_t, _reg ## _OFST, \
460 uint32_t, (_eop)->eo_u32[3], \
461 uint32_t, (_eop)->eo_u32[2], \
462 uint32_t, (_eop)->eo_u32[1], \
463 uint32_t, (_eop)->eo_u32[0]); \
464 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
466 _NOTE(CONSTANTCONDITION) \
469 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
471 EFX_CHECK_REG((_enp), (_reg)); \
472 EFSYS_BAR_READD((_enp)->en_esbp, \
473 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
475 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
476 uint32_t, (_index), \
477 uint32_t, _reg ## _OFST, \
478 uint32_t, (_edp)->ed_u32[0]); \
479 _NOTE(CONSTANTCONDITION) \
482 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
484 EFX_CHECK_REG((_enp), (_reg)); \
485 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
486 uint32_t, (_index), \
487 uint32_t, _reg ## _OFST, \
488 uint32_t, (_edp)->ed_u32[0]); \
489 EFSYS_BAR_WRITED((_enp)->en_esbp, \
490 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
492 _NOTE(CONSTANTCONDITION) \
495 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock) \
497 EFX_CHECK_REG((_enp), (_reg)); \
498 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
499 uint32_t, (_index), \
500 uint32_t, _reg ## _OFST, \
501 uint32_t, (_edp)->ed_u32[0]); \
502 EFSYS_BAR_WRITED((_enp)->en_esbp, \
504 (2 * sizeof (efx_dword_t)) + \
505 ((_index) * _reg ## _STEP)), \
507 _NOTE(CONSTANTCONDITION) \
510 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
512 EFX_CHECK_REG((_enp), (_reg)); \
513 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
514 uint32_t, (_index), \
515 uint32_t, _reg ## _OFST, \
516 uint32_t, (_edp)->ed_u32[0]); \
517 EFSYS_BAR_WRITED((_enp)->en_esbp, \
519 (3 * sizeof (efx_dword_t)) + \
520 ((_index) * _reg ## _STEP)), \
522 _NOTE(CONSTANTCONDITION) \
525 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
527 EFX_CHECK_REG((_enp), (_reg)); \
528 EFSYS_BAR_READQ((_enp)->en_esbp, \
529 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
531 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
532 uint32_t, (_index), \
533 uint32_t, _reg ## _OFST, \
534 uint32_t, (_eqp)->eq_u32[1], \
535 uint32_t, (_eqp)->eq_u32[0]); \
536 _NOTE(CONSTANTCONDITION) \
539 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
541 EFX_CHECK_REG((_enp), (_reg)); \
542 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
543 uint32_t, (_index), \
544 uint32_t, _reg ## _OFST, \
545 uint32_t, (_eqp)->eq_u32[1], \
546 uint32_t, (_eqp)->eq_u32[0]); \
547 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
548 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
550 _NOTE(CONSTANTCONDITION) \
553 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \
555 EFX_CHECK_REG((_enp), (_reg)); \
556 EFSYS_BAR_READO((_enp)->en_esbp, \
557 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
559 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
560 uint32_t, (_index), \
561 uint32_t, _reg ## _OFST, \
562 uint32_t, (_eop)->eo_u32[3], \
563 uint32_t, (_eop)->eo_u32[2], \
564 uint32_t, (_eop)->eo_u32[1], \
565 uint32_t, (_eop)->eo_u32[0]); \
566 _NOTE(CONSTANTCONDITION) \
569 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \
571 EFX_CHECK_REG((_enp), (_reg)); \
572 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
573 uint32_t, (_index), \
574 uint32_t, _reg ## _OFST, \
575 uint32_t, (_eop)->eo_u32[3], \
576 uint32_t, (_eop)->eo_u32[2], \
577 uint32_t, (_eop)->eo_u32[1], \
578 uint32_t, (_eop)->eo_u32[0]); \
579 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
580 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
582 _NOTE(CONSTANTCONDITION) \
586 * Allow drivers to perform optimised 128-bit doorbell writes.
587 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
588 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
589 * the need for locking in the host, and are the only ones known to be safe to
590 * use 128-bites write with.
592 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \
594 EFX_CHECK_REG((_enp), (_reg)); \
595 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo, \
598 uint32_t, (_index), \
599 uint32_t, _reg ## _OFST, \
600 uint32_t, (_eop)->eo_u32[3], \
601 uint32_t, (_eop)->eo_u32[2], \
602 uint32_t, (_eop)->eo_u32[1], \
603 uint32_t, (_eop)->eo_u32[0]); \
604 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \
605 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
607 _NOTE(CONSTANTCONDITION) \
610 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \
612 unsigned int _new = (_wptr); \
613 unsigned int _old = (_owptr); \
615 if ((_new) >= (_old)) \
616 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
617 (_old) * sizeof (efx_desc_t), \
618 ((_new) - (_old)) * sizeof (efx_desc_t)); \
621 * It is cheaper to sync entire map than sync \
622 * two parts especially when offset/size are \
623 * ignored and entire map is synced in any case.\
625 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \
627 (_entries) * sizeof (efx_desc_t)); \
628 _NOTE(CONSTANTCONDITION) \
631 extern __checkReturn efx_rc_t
633 __in efx_nic_t *enp);
635 extern __checkReturn efx_rc_t
637 __in efx_nic_t *enp);
640 efx_mac_multicast_hash_compute(
641 __in_ecount(6*count) uint8_t const *addrs,
643 __out efx_oword_t *hash_low,
644 __out efx_oword_t *hash_high);
646 extern __checkReturn efx_rc_t
648 __in efx_nic_t *enp);
652 __in efx_nic_t *enp);
658 #endif /* _SYS_EFX_IMPL_H */